drivers/phy/mscc/phy-ocelot-serdes.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * SerDes PHY driver for Microsemi Ocelot
   4  *
   5  * Copyright (c) 2018 Microsemi
   6  *
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/mfd/syscon.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/phy.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/regmap.h>
  18 #include <soc/mscc/ocelot_hsio.h>
  19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
  20
  21 struct serdes_ctrl {
  22         struct regmap           *regs;
  23         struct device           *dev;
  24         struct phy              *phys[SERDES_MAX];
  25 };
  26
  27 struct serdes_macro {
  28         u8                      idx;
  29         /* Not used when in QSGMII or PCIe mode */
  30         int                     port;
  31         struct serdes_ctrl      *ctrl;
  32 };
  33
  34 #define MCB_S1G_CFG_TIMEOUT     50
  35
  36 static int __serdes_write_mcb_s1g(struct regmap *regmap, u8 macro, u32 op)
  37 {
  38         unsigned int regval;
  39
  40         regmap_write(regmap, HSIO_MCB_S1G_ADDR_CFG, op |
  41                      HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(BIT(macro)));
  42
  43         return regmap_read_poll_timeout(regmap, HSIO_MCB_S1G_ADDR_CFG, regval,
  44                                         (regval & op) != op, 100,
  45                                         MCB_S1G_CFG_TIMEOUT * 1000);
  46 }
  47
  48 static int serdes_commit_mcb_s1g(struct regmap *regmap, u8 macro)
  49 {
  50         return __serdes_write_mcb_s1g(regmap, macro,
  51                 HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT);
  52 }
  53
  54 static int serdes_update_mcb_s1g(struct regmap *regmap, u8 macro)
  55 {
  56         return __serdes_write_mcb_s1g(regmap, macro,
  57                 HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT);
  58 }
  59
  60 static int serdes_init_s1g(struct regmap *regmap, u8 serdes)
  61 {
  62         int ret;
  63
  64         ret = serdes_update_mcb_s1g(regmap, serdes);
  65         if (ret)
  66                 return ret;
  67
  68         regmap_update_bits(regmap, HSIO_S1G_COMMON_CFG,
  69                            HSIO_S1G_COMMON_CFG_SYS_RST |
  70                            HSIO_S1G_COMMON_CFG_ENA_LANE |
  71                            HSIO_S1G_COMMON_CFG_ENA_ELOOP |
  72                            HSIO_S1G_COMMON_CFG_ENA_FLOOP,
  73                            HSIO_S1G_COMMON_CFG_ENA_LANE);
  74
  75         regmap_update_bits(regmap, HSIO_S1G_PLL_CFG,
  76                            HSIO_S1G_PLL_CFG_PLL_FSM_ENA |
  77                            HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M,
  78                            HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(200) |
  79                            HSIO_S1G_PLL_CFG_PLL_FSM_ENA);
  80
  81         regmap_update_bits(regmap, HSIO_S1G_MISC_CFG,
  82                            HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA |
  83                            HSIO_S1G_MISC_CFG_LANE_RST,
  84                            HSIO_S1G_MISC_CFG_LANE_RST);
  85
  86         ret = serdes_commit_mcb_s1g(regmap, serdes);
  87         if (ret)
  88                 return ret;
  89
  90         regmap_update_bits(regmap, HSIO_S1G_COMMON_CFG,
  91                            HSIO_S1G_COMMON_CFG_SYS_RST,
  92                            HSIO_S1G_COMMON_CFG_SYS_RST);
  93
  94         regmap_update_bits(regmap, HSIO_S1G_MISC_CFG,
  95                            HSIO_S1G_MISC_CFG_LANE_RST, 0);
  96
  97         ret = serdes_commit_mcb_s1g(regmap, serdes);
  98         if (ret)
  99                 return ret;
 100
 101         return 0;
 102 }
 103
 104 struct serdes_mux {
 105         u8                      idx;
 106         u8                      port;
 107         enum phy_mode           mode;
 108         int                     submode;
 109         u32                     mask;
 110         u32                     mux;
 111 };
 112
 113 #define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) {         \
 114         .idx = _idx,                                            \
 115         .port = _port,                                          \
 116         .mode = _mode,                                          \
 117         .submode = _submode,                                    \
 118         .mask = _mask,                                          \
 119         .mux = _mux,                                            \
 120 }
 121
 122 #define SERDES_MUX_SGMII(i, p, m, c) \
 123         SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_SGMII, m, c)
 124 #define SERDES_MUX_QSGMII(i, p, m, c) \
 125         SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c)
 126
 127 static const struct serdes_mux ocelot_serdes_muxes[] = {
 128         SERDES_MUX_SGMII(SERDES1G(0), 0, 0, 0),
 129         SERDES_MUX_SGMII(SERDES1G(1), 1, HSIO_HW_CFG_DEV1G_5_MODE, 0),
 130         SERDES_MUX_SGMII(SERDES1G(1), 5, HSIO_HW_CFG_QSGMII_ENA |
 131                          HSIO_HW_CFG_DEV1G_5_MODE, HSIO_HW_CFG_DEV1G_5_MODE),
 132         SERDES_MUX_SGMII(SERDES1G(2), 2, HSIO_HW_CFG_DEV1G_4_MODE, 0),
 133         SERDES_MUX_SGMII(SERDES1G(2), 4, HSIO_HW_CFG_QSGMII_ENA |
 134                          HSIO_HW_CFG_DEV1G_4_MODE, HSIO_HW_CFG_DEV1G_4_MODE),
 135         SERDES_MUX_SGMII(SERDES1G(3), 3, HSIO_HW_CFG_DEV1G_6_MODE, 0),
 136         SERDES_MUX_SGMII(SERDES1G(3), 6, HSIO_HW_CFG_QSGMII_ENA |
 137                          HSIO_HW_CFG_DEV1G_6_MODE, HSIO_HW_CFG_DEV1G_6_MODE),
 138         SERDES_MUX_SGMII(SERDES1G(4), 4, HSIO_HW_CFG_QSGMII_ENA |
 139                          HSIO_HW_CFG_DEV1G_4_MODE | HSIO_HW_CFG_DEV1G_9_MODE,
 140                          0),
 141         SERDES_MUX_SGMII(SERDES1G(4), 9, HSIO_HW_CFG_DEV1G_4_MODE |
 142                          HSIO_HW_CFG_DEV1G_9_MODE, HSIO_HW_CFG_DEV1G_4_MODE |
 143                          HSIO_HW_CFG_DEV1G_9_MODE),
 144         SERDES_MUX_SGMII(SERDES1G(5), 5, HSIO_HW_CFG_QSGMII_ENA |
 145                          HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE,
 146                          0),
 147         SERDES_MUX_SGMII(SERDES1G(5), 10, HSIO_HW_CFG_PCIE_ENA |
 148                          HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE,
 149                          HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE),
 150         SERDES_MUX_QSGMII(SERDES6G(0), 4, HSIO_HW_CFG_QSGMII_ENA,
 151                           HSIO_HW_CFG_QSGMII_ENA),
 152         SERDES_MUX_QSGMII(SERDES6G(0), 5, HSIO_HW_CFG_QSGMII_ENA,
 153                           HSIO_HW_CFG_QSGMII_ENA),
 154         SERDES_MUX_QSGMII(SERDES6G(0), 6, HSIO_HW_CFG_QSGMII_ENA,
 155                           HSIO_HW_CFG_QSGMII_ENA),
 156         SERDES_MUX_SGMII(SERDES6G(0), 7, HSIO_HW_CFG_QSGMII_ENA, 0),
 157         SERDES_MUX_QSGMII(SERDES6G(0), 7, HSIO_HW_CFG_QSGMII_ENA,
 158                           HSIO_HW_CFG_QSGMII_ENA),
 159         SERDES_MUX_SGMII(SERDES6G(1), 8, 0, 0),
 160         SERDES_MUX_SGMII(SERDES6G(2), 10, HSIO_HW_CFG_PCIE_ENA |
 161                          HSIO_HW_CFG_DEV2G5_10_MODE, 0),
 162         SERDES_MUX(SERDES6G(2), 10, PHY_MODE_PCIE, 0, HSIO_HW_CFG_PCIE_ENA,
 163                    HSIO_HW_CFG_PCIE_ENA),
 164 };
 165
 166 static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)
 167 {
 168         struct serdes_macro *macro = phy_get_drvdata(phy);
 169         unsigned int i;
 170         int ret;
 171
 172         /* As of now only PHY_MODE_ETHERNET is supported */
 173         if (mode != PHY_MODE_ETHERNET)
 174                 return -EOPNOTSUPP;
 175
 176         for (i = 0; i < ARRAY_SIZE(ocelot_serdes_muxes); i++) {
 177                 if (macro->idx != ocelot_serdes_muxes[i].idx ||
 178                     mode != ocelot_serdes_muxes[i].mode ||
 179                     submode != ocelot_serdes_muxes[i].submode)
 180                         continue;
 181
 182                 if (submode != PHY_INTERFACE_MODE_QSGMII &&
 183                     macro->port != ocelot_serdes_muxes[i].port)
 184                         continue;
 185
 186                 ret = regmap_update_bits(macro->ctrl->regs, HSIO_HW_CFG,
 187                                          ocelot_serdes_muxes[i].mask,
 188                                          ocelot_serdes_muxes[i].mux);
 189                 if (ret)
 190                         return ret;
 191
 192                 if (macro->idx <= SERDES1G_MAX)
 193                         return serdes_init_s1g(macro->ctrl->regs, macro->idx);
 194
 195                 /* SERDES6G and PCIe not supported yet */
 196                 return -EOPNOTSUPP;
 197         }
 198
 199         return -EINVAL;
 200 }
 201
 202 static const struct phy_ops serdes_ops = {
 203         .set_mode       = serdes_set_mode,
 204         .owner          = THIS_MODULE,
 205 };
 206
 207 static struct phy *serdes_simple_xlate(struct device *dev,
 208                                        struct of_phandle_args *args)
 209 {
 210         struct serdes_ctrl *ctrl = dev_get_drvdata(dev);
 211         unsigned int port, idx, i;
 212
 213         if (args->args_count != 2)
 214                 return ERR_PTR(-EINVAL);
 215
 216         port = args->args[0];
 217         idx = args->args[1];
 218
 219         for (i = 0; i < SERDES_MAX; i++) {
 220                 struct serdes_macro *macro = phy_get_drvdata(ctrl->phys[i]);
 221
 222                 if (idx != macro->idx)
 223                         continue;
 224
 225                 /* SERDES6G(0) is the only SerDes capable of QSGMII */
 226                 if (idx != SERDES6G(0) && macro->port >= 0)
 227                         return ERR_PTR(-EBUSY);
 228
 229                 macro->port = port;
 230                 return ctrl->phys[i];
 231         }
 232
 233         return ERR_PTR(-ENODEV);
 234 }
 235
 236 static int serdes_phy_create(struct serdes_ctrl *ctrl, u8 idx, struct phy **phy)
 237 {
 238         struct serdes_macro *macro;
 239
 240         *phy = devm_phy_create(ctrl->dev, NULL, &serdes_ops);
 241         if (IS_ERR(*phy))
 242                 return PTR_ERR(*phy);
 243
 244         macro = devm_kzalloc(ctrl->dev, sizeof(*macro), GFP_KERNEL);
 245         if (!macro)
 246                 return -ENOMEM;
 247
 248         macro->idx = idx;
 249         macro->ctrl = ctrl;
 250         macro->port = -1;
 251
 252         phy_set_drvdata(*phy, macro);
 253
 254         return 0;
 255 }
 256
 257 static int serdes_probe(struct platform_device *pdev)
 258 {
 259         struct phy_provider *provider;
 260         struct serdes_ctrl *ctrl;
 261         unsigned int i;
 262         int ret;
 263
 264         ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
 265         if (!ctrl)
 266                 return -ENOMEM;
 267
 268         ctrl->dev = &pdev->dev;
 269         ctrl->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
 270         if (IS_ERR(ctrl->regs))
 271                 return PTR_ERR(ctrl->regs);
 272
 273         for (i = 0; i < SERDES_MAX; i++) {
 274                 ret = serdes_phy_create(ctrl, i, &ctrl->phys[i]);
 275                 if (ret)
 276                         return ret;
 277         }
 278
 279         dev_set_drvdata(&pdev->dev, ctrl);
 280
 281         provider = devm_of_phy_provider_register(ctrl->dev,
 282                                                  serdes_simple_xlate);
 283
 284         return PTR_ERR_OR_ZERO(provider);
 285 }
 286
 287 static const struct of_device_id serdes_ids[] = {
 288         { .compatible = "mscc,vsc7514-serdes", },
 289         {},
 290 };
 291 MODULE_DEVICE_TABLE(of, serdes_ids);
 292
 293 static struct platform_driver mscc_ocelot_serdes = {
 294         .probe          = serdes_probe,
 295         .driver         = {
 296                 .name   = "mscc,ocelot-serdes",
 297                 .of_match_table = of_match_ptr(serdes_ids),
 298         },
 299 };
 300
 301 module_platform_driver(mscc_ocelot_serdes);
 302
 303 MODULE_AUTHOR("Quentin Schulz <[email protected]>");
 304 MODULE_DESCRIPTION("SerDes driver for Microsemi Ocelot");
 305 MODULE_LICENSE("Dual MIT/GPL");