drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/bitmap.h>
  42 #if defined(CONFIG_X86)
  43 #include <asm/pat.h>
  44 #endif
  45 #include <linux/sched.h>
  46 #include <linux/sched/mm.h>
  47 #include <linux/sched/task.h>
  48 #include <linux/delay.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <rdma/ib_addr.h>
  51 #include <rdma/ib_cache.h>
  52 #include <linux/mlx5/port.h>
  53 #include <linux/mlx5/vport.h>
  54 #include <linux/mlx5/fs.h>
  55 #include <linux/list.h>
  56 #include <rdma/ib_smi.h>
  57 #include <rdma/ib_umem.h>
  58 #include <linux/in.h>
  59 #include <linux/etherdevice.h>
  60 #include "mlx5_ib.h"
  61 #include "ib_rep.h"
  62 #include "cmd.h"
  63 #include "srq.h"
  64 #include <linux/mlx5/fs_helpers.h>
  65 #include <linux/mlx5/accel.h>
  66 #include <rdma/uverbs_std_types.h>
  67 #include <rdma/mlx5_user_ioctl_verbs.h>
  68 #include <rdma/mlx5_user_ioctl_cmds.h>
  69
  70 #define UVERBS_MODULE_NAME mlx5_ib
  71 #include <rdma/uverbs_named_ioctl.h>
  72
  73 #define DRIVER_NAME "mlx5_ib"
  74 #define DRIVER_VERSION "5.0-0"
  75
  76 MODULE_AUTHOR("Eli Cohen <[email protected]>");
  77 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  78 MODULE_LICENSE("Dual BSD/GPL");
  79
  80 static char mlx5_version[] =
  81         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  82         DRIVER_VERSION "\n";
  83
  84 struct mlx5_ib_event_work {
  85         struct work_struct      work;
  86         union {
  87                 struct mlx5_ib_dev            *dev;
  88                 struct mlx5_ib_multiport_info *mpi;
  89         };
  90         bool                    is_slave;
  91         unsigned int            event;
  92         void                    *param;
  93 };
  94
  95 enum {
  96         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  97 };
  98
  99 static struct workqueue_struct *mlx5_ib_event_wq;
 100 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
 101 static LIST_HEAD(mlx5_ib_dev_list);
 102 /*
 103  * This mutex should be held when accessing either of the above lists
 104  */
 105 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
 106
 107 /* We can't use an array for xlt_emergency_page because dma_map_single
 108  * doesn't work on kernel modules memory
 109  */
 110 static unsigned long xlt_emergency_page;
 111 static struct mutex xlt_emergency_page_mutex;
 112
 113 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
 114 {
 115         struct mlx5_ib_dev *dev;
 116
 117         mutex_lock(&mlx5_ib_multiport_mutex);
 118         dev = mpi->ibdev;
 119         mutex_unlock(&mlx5_ib_multiport_mutex);
 120         return dev;
 121 }
 122
 123 static enum rdma_link_layer
 124 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 125 {
 126         switch (port_type_cap) {
 127         case MLX5_CAP_PORT_TYPE_IB:
 128                 return IB_LINK_LAYER_INFINIBAND;
 129         case MLX5_CAP_PORT_TYPE_ETH:
 130                 return IB_LINK_LAYER_ETHERNET;
 131         default:
 132                 return IB_LINK_LAYER_UNSPECIFIED;
 133         }
 134 }
 135
 136 static enum rdma_link_layer
 137 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 138 {
 139         struct mlx5_ib_dev *dev = to_mdev(device);
 140         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 141
 142         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 143 }
 144
 145 static int get_port_state(struct ib_device *ibdev,
 146                           u8 port_num,
 147                           enum ib_port_state *state)
 148 {
 149         struct ib_port_attr attr;
 150         int ret;
 151
 152         memset(&attr, 0, sizeof(attr));
 153         ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 154         if (!ret)
 155                 *state = attr.state;
 156         return ret;
 157 }
 158
 159 static int mlx5_netdev_event(struct notifier_block *this,
 160                              unsigned long event, void *ptr)
 161 {
 162         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 163         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 164         u8 port_num = roce->native_port_num;
 165         struct mlx5_core_dev *mdev;
 166         struct mlx5_ib_dev *ibdev;
 167
 168         ibdev = roce->dev;
 169         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 170         if (!mdev)
 171                 return NOTIFY_DONE;
 172
 173         switch (event) {
 174         case NETDEV_REGISTER:
 175                 write_lock(&roce->netdev_lock);
 176                 if (ibdev->rep) {
 177                         struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
 178                         struct net_device *rep_ndev;
 179
 180                         rep_ndev = mlx5_ib_get_rep_netdev(esw,
 181                                                           ibdev->rep->vport);
 182                         if (rep_ndev == ndev)
 183                                 roce->netdev = ndev;
 184                 } else if (ndev->dev.parent == &mdev->pdev->dev) {
 185                         roce->netdev = ndev;
 186                 }
 187                 write_unlock(&roce->netdev_lock);
 188                 break;
 189
 190         case NETDEV_UNREGISTER:
 191                 write_lock(&roce->netdev_lock);
 192                 if (roce->netdev == ndev)
 193                         roce->netdev = NULL;
 194                 write_unlock(&roce->netdev_lock);
 195                 break;
 196
 197         case NETDEV_CHANGE:
 198         case NETDEV_UP:
 199         case NETDEV_DOWN: {
 200                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 201                 struct net_device *upper = NULL;
 202
 203                 if (lag_ndev) {
 204                         upper = netdev_master_upper_dev_get(lag_ndev);
 205                         dev_put(lag_ndev);
 206                 }
 207
 208                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 209                     && ibdev->ib_active) {
 210                         struct ib_event ibev = { };
 211                         enum ib_port_state port_state;
 212
 213                         if (get_port_state(&ibdev->ib_dev, port_num,
 214                                            &port_state))
 215                                 goto done;
 216
 217                         if (roce->last_port_state == port_state)
 218                                 goto done;
 219
 220                         roce->last_port_state = port_state;
 221                         ibev.device = &ibdev->ib_dev;
 222                         if (port_state == IB_PORT_DOWN)
 223                                 ibev.event = IB_EVENT_PORT_ERR;
 224                         else if (port_state == IB_PORT_ACTIVE)
 225                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 226                         else
 227                                 goto done;
 228
 229                         ibev.element.port_num = port_num;
 230                         ib_dispatch_event(&ibev);
 231                 }
 232                 break;
 233         }
 234
 235         default:
 236                 break;
 237         }
 238 done:
 239         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 240         return NOTIFY_DONE;
 241 }
 242
 243 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 244                                              u8 port_num)
 245 {
 246         struct mlx5_ib_dev *ibdev = to_mdev(device);
 247         struct net_device *ndev;
 248         struct mlx5_core_dev *mdev;
 249
 250         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 251         if (!mdev)
 252                 return NULL;
 253
 254         ndev = mlx5_lag_get_roce_netdev(mdev);
 255         if (ndev)
 256                 goto out;
 257
 258         /* Ensure ndev does not disappear before we invoke dev_hold()
 259          */
 260         read_lock(&ibdev->roce[port_num - 1].netdev_lock);
 261         ndev = ibdev->roce[port_num - 1].netdev;
 262         if (ndev)
 263                 dev_hold(ndev);
 264         read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
 265
 266 out:
 267         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 268         return ndev;
 269 }
 270
 271 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 272                                                    u8 ib_port_num,
 273                                                    u8 *native_port_num)
 274 {
 275         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 276                                                           ib_port_num);
 277         struct mlx5_core_dev *mdev = NULL;
 278         struct mlx5_ib_multiport_info *mpi;
 279         struct mlx5_ib_port *port;
 280
 281         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 282             ll != IB_LINK_LAYER_ETHERNET) {
 283                 if (native_port_num)
 284                         *native_port_num = ib_port_num;
 285                 return ibdev->mdev;
 286         }
 287
 288         if (native_port_num)
 289                 *native_port_num = 1;
 290
 291         port = &ibdev->port[ib_port_num - 1];
 292         if (!port)
 293                 return NULL;
 294
 295         spin_lock(&port->mp.mpi_lock);
 296         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 297         if (mpi && !mpi->unaffiliate) {
 298                 mdev = mpi->mdev;
 299                 /* If it's the master no need to refcount, it'll exist
 300                  * as long as the ib_dev exists.
 301                  */
 302                 if (!mpi->is_master)
 303                         mpi->mdev_refcnt++;
 304         }
 305         spin_unlock(&port->mp.mpi_lock);
 306
 307         return mdev;
 308 }
 309
 310 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 311 {
 312         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 313                                                           port_num);
 314         struct mlx5_ib_multiport_info *mpi;
 315         struct mlx5_ib_port *port;
 316
 317         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 318                 return;
 319
 320         port = &ibdev->port[port_num - 1];
 321
 322         spin_lock(&port->mp.mpi_lock);
 323         mpi = ibdev->port[port_num - 1].mp.mpi;
 324         if (mpi->is_master)
 325                 goto out;
 326
 327         mpi->mdev_refcnt--;
 328         if (mpi->unaffiliate)
 329                 complete(&mpi->unref_comp);
 330 out:
 331         spin_unlock(&port->mp.mpi_lock);
 332 }
 333
 334 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 335                                            u8 *active_width)
 336 {
 337         switch (eth_proto_oper) {
 338         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 339         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 340         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 341         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 342                 *active_width = IB_WIDTH_1X;
 343                 *active_speed = IB_SPEED_SDR;
 344                 break;
 345         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 346         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 347         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 348         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 349         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 350         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 351         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 352                 *active_width = IB_WIDTH_1X;
 353                 *active_speed = IB_SPEED_QDR;
 354                 break;
 355         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 356         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 357         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 358                 *active_width = IB_WIDTH_1X;
 359                 *active_speed = IB_SPEED_EDR;
 360                 break;
 361         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 362         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 363         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 364         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 365                 *active_width = IB_WIDTH_4X;
 366                 *active_speed = IB_SPEED_QDR;
 367                 break;
 368         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 369         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 370         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 371                 *active_width = IB_WIDTH_1X;
 372                 *active_speed = IB_SPEED_HDR;
 373                 break;
 374         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 375                 *active_width = IB_WIDTH_4X;
 376                 *active_speed = IB_SPEED_FDR;
 377                 break;
 378         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 379         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 380         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 381         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 382                 *active_width = IB_WIDTH_4X;
 383                 *active_speed = IB_SPEED_EDR;
 384                 break;
 385         default:
 386                 return -EINVAL;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 393                                         u8 *active_width)
 394 {
 395         switch (eth_proto_oper) {
 396         case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 397         case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 398                 *active_width = IB_WIDTH_1X;
 399                 *active_speed = IB_SPEED_SDR;
 400                 break;
 401         case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 402                 *active_width = IB_WIDTH_1X;
 403                 *active_speed = IB_SPEED_DDR;
 404                 break;
 405         case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 406                 *active_width = IB_WIDTH_1X;
 407                 *active_speed = IB_SPEED_QDR;
 408                 break;
 409         case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 410                 *active_width = IB_WIDTH_4X;
 411                 *active_speed = IB_SPEED_QDR;
 412                 break;
 413         case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 414                 *active_width = IB_WIDTH_1X;
 415                 *active_speed = IB_SPEED_EDR;
 416                 break;
 417         case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 418         case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 419                 *active_width = IB_WIDTH_1X;
 420                 *active_speed = IB_SPEED_HDR;
 421                 break;
 422         case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 423                 *active_width = IB_WIDTH_2X;
 424                 *active_speed = IB_SPEED_HDR;
 425                 break;
 426         case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 427                 *active_width = IB_WIDTH_4X;
 428                 *active_speed = IB_SPEED_HDR;
 429                 break;
 430         default:
 431                 return -EINVAL;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 438                                     u8 *active_width, bool ext)
 439 {
 440         return ext ?
 441                 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 442                                              active_width) :
 443                 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 444                                                 active_width);
 445 }
 446
 447 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 448                                 struct ib_port_attr *props)
 449 {
 450         struct mlx5_ib_dev *dev = to_mdev(device);
 451         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 452         struct mlx5_core_dev *mdev;
 453         struct net_device *ndev, *upper;
 454         enum ib_mtu ndev_ib_mtu;
 455         bool put_mdev = true;
 456         u16 qkey_viol_cntr;
 457         u32 eth_prot_oper;
 458         u8 mdev_port_num;
 459         bool ext;
 460         int err;
 461
 462         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 463         if (!mdev) {
 464                 /* This means the port isn't affiliated yet. Get the
 465                  * info for the master port instead.
 466                  */
 467                 put_mdev = false;
 468                 mdev = dev->mdev;
 469                 mdev_port_num = 1;
 470                 port_num = 1;
 471         }
 472
 473         /* Possible bad flows are checked before filling out props so in case
 474          * of an error it will still be zeroed out.
 475          */
 476         err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 477                                    mdev_port_num);
 478         if (err)
 479                 goto out;
 480         ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
 481         eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 482
 483         props->active_width     = IB_WIDTH_4X;
 484         props->active_speed     = IB_SPEED_QDR;
 485
 486         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 487                                  &props->active_width, ext);
 488
 489         props->port_cap_flags |= IB_PORT_CM_SUP;
 490         props->ip_gids = true;
 491
 492         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 493                                                 roce_address_table_size);
 494         props->max_mtu          = IB_MTU_4096;
 495         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 496         props->pkey_tbl_len     = 1;
 497         props->state            = IB_PORT_DOWN;
 498         props->phys_state       = 3;
 499
 500         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 501         props->qkey_viol_cntr = qkey_viol_cntr;
 502
 503         /* If this is a stub query for an unaffiliated port stop here */
 504         if (!put_mdev)
 505                 goto out;
 506
 507         ndev = mlx5_ib_get_netdev(device, port_num);
 508         if (!ndev)
 509                 goto out;
 510
 511         if (dev->lag_active) {
 512                 rcu_read_lock();
 513                 upper = netdev_master_upper_dev_get_rcu(ndev);
 514                 if (upper) {
 515                         dev_put(ndev);
 516                         ndev = upper;
 517                         dev_hold(ndev);
 518                 }
 519                 rcu_read_unlock();
 520         }
 521
 522         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 523                 props->state      = IB_PORT_ACTIVE;
 524                 props->phys_state = 5;
 525         }
 526
 527         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 528
 529         dev_put(ndev);
 530
 531         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 532 out:
 533         if (put_mdev)
 534                 mlx5_ib_put_native_port_mdev(dev, port_num);
 535         return err;
 536 }
 537
 538 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 539                          unsigned int index, const union ib_gid *gid,
 540                          const struct ib_gid_attr *attr)
 541 {
 542         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 543         u8 roce_version = 0;
 544         u8 roce_l3_type = 0;
 545         bool vlan = false;
 546         u8 mac[ETH_ALEN];
 547         u16 vlan_id = 0;
 548
 549         if (gid) {
 550                 gid_type = attr->gid_type;
 551                 ether_addr_copy(mac, attr->ndev->dev_addr);
 552
 553                 if (is_vlan_dev(attr->ndev)) {
 554                         vlan = true;
 555                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 556                 }
 557         }
 558
 559         switch (gid_type) {
 560         case IB_GID_TYPE_IB:
 561                 roce_version = MLX5_ROCE_VERSION_1;
 562                 break;
 563         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 564                 roce_version = MLX5_ROCE_VERSION_2;
 565                 if (ipv6_addr_v4mapped((void *)gid))
 566                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 567                 else
 568                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 569                 break;
 570
 571         default:
 572                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 573         }
 574
 575         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 576                                       roce_l3_type, gid->raw, mac, vlan,
 577                                       vlan_id, port_num);
 578 }
 579
 580 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 581                            __always_unused void **context)
 582 {
 583         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 584                              attr->index, &attr->gid, attr);
 585 }
 586
 587 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 588                            __always_unused void **context)
 589 {
 590         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 591                              attr->index, NULL, NULL);
 592 }
 593
 594 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
 595                                const struct ib_gid_attr *attr)
 596 {
 597         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 598                 return 0;
 599
 600         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 601 }
 602
 603 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 604 {
 605         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 606                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 607         return 0;
 608 }
 609
 610 enum {
 611         MLX5_VPORT_ACCESS_METHOD_MAD,
 612         MLX5_VPORT_ACCESS_METHOD_HCA,
 613         MLX5_VPORT_ACCESS_METHOD_NIC,
 614 };
 615
 616 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 617 {
 618         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 619                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 620
 621         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 622             IB_LINK_LAYER_ETHERNET)
 623                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 624
 625         return MLX5_VPORT_ACCESS_METHOD_HCA;
 626 }
 627
 628 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 629                             u8 atomic_size_qp,
 630                             struct ib_device_attr *props)
 631 {
 632         u8 tmp;
 633         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 634         u8 atomic_req_8B_endianness_mode =
 635                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 636
 637         /* Check if HW supports 8 bytes standard atomic operations and capable
 638          * of host endianness respond
 639          */
 640         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 641         if (((atomic_operations & tmp) == tmp) &&
 642             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 643             (atomic_req_8B_endianness_mode)) {
 644                 props->atomic_cap = IB_ATOMIC_HCA;
 645         } else {
 646                 props->atomic_cap = IB_ATOMIC_NONE;
 647         }
 648 }
 649
 650 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 651                                struct ib_device_attr *props)
 652 {
 653         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 654
 655         get_atomic_caps(dev, atomic_size_qp, props);
 656 }
 657
 658 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 659                                struct ib_device_attr *props)
 660 {
 661         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 662
 663         get_atomic_caps(dev, atomic_size_qp, props);
 664 }
 665
 666 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 667 {
 668         struct ib_device_attr props = {};
 669
 670         get_atomic_caps_dc(dev, &props);
 671         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 672 }
 673 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 674                                         __be64 *sys_image_guid)
 675 {
 676         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 677         struct mlx5_core_dev *mdev = dev->mdev;
 678         u64 tmp;
 679         int err;
 680
 681         switch (mlx5_get_vport_access_method(ibdev)) {
 682         case MLX5_VPORT_ACCESS_METHOD_MAD:
 683                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 684                                                             sys_image_guid);
 685
 686         case MLX5_VPORT_ACCESS_METHOD_HCA:
 687                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 688                 break;
 689
 690         case MLX5_VPORT_ACCESS_METHOD_NIC:
 691                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 692                 break;
 693
 694         default:
 695                 return -EINVAL;
 696         }
 697
 698         if (!err)
 699                 *sys_image_guid = cpu_to_be64(tmp);
 700
 701         return err;
 702
 703 }
 704
 705 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 706                                 u16 *max_pkeys)
 707 {
 708         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 709         struct mlx5_core_dev *mdev = dev->mdev;
 710
 711         switch (mlx5_get_vport_access_method(ibdev)) {
 712         case MLX5_VPORT_ACCESS_METHOD_MAD:
 713                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 714
 715         case MLX5_VPORT_ACCESS_METHOD_HCA:
 716         case MLX5_VPORT_ACCESS_METHOD_NIC:
 717                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 718                                                 pkey_table_size));
 719                 return 0;
 720
 721         default:
 722                 return -EINVAL;
 723         }
 724 }
 725
 726 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 727                                 u32 *vendor_id)
 728 {
 729         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 730
 731         switch (mlx5_get_vport_access_method(ibdev)) {
 732         case MLX5_VPORT_ACCESS_METHOD_MAD:
 733                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 734
 735         case MLX5_VPORT_ACCESS_METHOD_HCA:
 736         case MLX5_VPORT_ACCESS_METHOD_NIC:
 737                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 738
 739         default:
 740                 return -EINVAL;
 741         }
 742 }
 743
 744 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 745                                 __be64 *node_guid)
 746 {
 747         u64 tmp;
 748         int err;
 749
 750         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 751         case MLX5_VPORT_ACCESS_METHOD_MAD:
 752                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 753
 754         case MLX5_VPORT_ACCESS_METHOD_HCA:
 755                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 756                 break;
 757
 758         case MLX5_VPORT_ACCESS_METHOD_NIC:
 759                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 760                 break;
 761
 762         default:
 763                 return -EINVAL;
 764         }
 765
 766         if (!err)
 767                 *node_guid = cpu_to_be64(tmp);
 768
 769         return err;
 770 }
 771
 772 struct mlx5_reg_node_desc {
 773         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 774 };
 775
 776 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 777 {
 778         struct mlx5_reg_node_desc in;
 779
 780         if (mlx5_use_mad_ifc(dev))
 781                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 782
 783         memset(&in, 0, sizeof(in));
 784
 785         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 786                                     sizeof(struct mlx5_reg_node_desc),
 787                                     MLX5_REG_NODE_DESC, 0, 0);
 788 }
 789
 790 static int mlx5_ib_query_device(struct ib_device *ibdev,
 791                                 struct ib_device_attr *props,
 792                                 struct ib_udata *uhw)
 793 {
 794         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 795         struct mlx5_core_dev *mdev = dev->mdev;
 796         int err = -ENOMEM;
 797         int max_sq_desc;
 798         int max_rq_sg;
 799         int max_sq_sg;
 800         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 801         bool raw_support = !mlx5_core_mp_enabled(mdev);
 802         struct mlx5_ib_query_device_resp resp = {};
 803         size_t resp_len;
 804         u64 max_tso;
 805
 806         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 807         if (uhw->outlen && uhw->outlen < resp_len)
 808                 return -EINVAL;
 809         else
 810                 resp.response_length = resp_len;
 811
 812         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 813                 return -EINVAL;
 814
 815         memset(props, 0, sizeof(*props));
 816         err = mlx5_query_system_image_guid(ibdev,
 817                                            &props->sys_image_guid);
 818         if (err)
 819                 return err;
 820
 821         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 822         if (err)
 823                 return err;
 824
 825         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 826         if (err)
 827                 return err;
 828
 829         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 830                 (fw_rev_min(dev->mdev) << 16) |
 831                 fw_rev_sub(dev->mdev);
 832         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 833                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 834                 IB_DEVICE_SYS_IMAGE_GUID                |
 835                 IB_DEVICE_RC_RNR_NAK_GEN;
 836
 837         if (MLX5_CAP_GEN(mdev, pkv))
 838                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 839         if (MLX5_CAP_GEN(mdev, qkv))
 840                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 841         if (MLX5_CAP_GEN(mdev, apm))
 842                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 843         if (MLX5_CAP_GEN(mdev, xrc))
 844                 props->device_cap_flags |= IB_DEVICE_XRC;
 845         if (MLX5_CAP_GEN(mdev, imaicl)) {
 846                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 847                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 848                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 849                 /* We support 'Gappy' memory registration too */
 850                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 851         }
 852         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 853         if (MLX5_CAP_GEN(mdev, sho)) {
 854                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 855                 /* At this stage no support for signature handover */
 856                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 857                                       IB_PROT_T10DIF_TYPE_2 |
 858                                       IB_PROT_T10DIF_TYPE_3;
 859                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 860                                        IB_GUARD_T10DIF_CSUM;
 861         }
 862         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 863                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 864
 865         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 866                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 867                         /* Legacy bit to support old userspace libraries */
 868                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 869                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 870                 }
 871
 872                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 873                         props->raw_packet_caps |=
 874                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 875
 876                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 877                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 878                         if (max_tso) {
 879                                 resp.tso_caps.max_tso = 1 << max_tso;
 880                                 resp.tso_caps.supported_qpts |=
 881                                         1 << IB_QPT_RAW_PACKET;
 882                                 resp.response_length += sizeof(resp.tso_caps);
 883                         }
 884                 }
 885
 886                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 887                         resp.rss_caps.rx_hash_function =
 888                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 889                         resp.rss_caps.rx_hash_fields_mask =
 890                                                 MLX5_RX_HASH_SRC_IPV4 |
 891                                                 MLX5_RX_HASH_DST_IPV4 |
 892                                                 MLX5_RX_HASH_SRC_IPV6 |
 893                                                 MLX5_RX_HASH_DST_IPV6 |
 894                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 895                                                 MLX5_RX_HASH_DST_PORT_TCP |
 896                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 897                                                 MLX5_RX_HASH_DST_PORT_UDP |
 898                                                 MLX5_RX_HASH_INNER;
 899                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 900                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 901                                 resp.rss_caps.rx_hash_fields_mask |=
 902                                         MLX5_RX_HASH_IPSEC_SPI;
 903                         resp.response_length += sizeof(resp.rss_caps);
 904                 }
 905         } else {
 906                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 907                         resp.response_length += sizeof(resp.tso_caps);
 908                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 909                         resp.response_length += sizeof(resp.rss_caps);
 910         }
 911
 912         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 913                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 914                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 915         }
 916
 917         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 918             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 919             raw_support)
 920                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 921
 922         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 923             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 924                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 925
 926         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 927             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 928             raw_support) {
 929                 /* Legacy bit to support old userspace libraries */
 930                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 931                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 932         }
 933
 934         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 935                 props->max_dm_size =
 936                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 937         }
 938
 939         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 940                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 941
 942         if (MLX5_CAP_GEN(mdev, end_pad))
 943                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 944
 945         props->vendor_part_id      = mdev->pdev->device;
 946         props->hw_ver              = mdev->pdev->revision;
 947
 948         props->max_mr_size         = ~0ull;
 949         props->page_size_cap       = ~(min_page_size - 1);
 950         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 951         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 952         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 953                      sizeof(struct mlx5_wqe_data_seg);
 954         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 955         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 956                      sizeof(struct mlx5_wqe_raddr_seg)) /
 957                 sizeof(struct mlx5_wqe_data_seg);
 958         props->max_send_sge = max_sq_sg;
 959         props->max_recv_sge = max_rq_sg;
 960         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 961         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 962         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 963         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 964         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 965         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 966         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 967         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 968         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 969         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 970         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 971         props->max_srq_sge         = max_rq_sg - 1;
 972         props->max_fast_reg_page_list_len =
 973                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 974         get_atomic_caps_qp(dev, props);
 975         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 976         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 977         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 978         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 979                                            props->max_mcast_grp;
 980         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 981         props->max_ah = INT_MAX;
 982         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 983         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 984
 985 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 986         if (MLX5_CAP_GEN(mdev, pg))
 987                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 988         props->odp_caps = dev->odp_caps;
 989 #endif
 990
 991         if (MLX5_CAP_GEN(mdev, cd))
 992                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 993
 994         if (!mlx5_core_is_pf(mdev))
 995                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 996
 997         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 998             IB_LINK_LAYER_ETHERNET && raw_support) {
 999                 props->rss_caps.max_rwq_indirection_tables =
1000                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1001                 props->rss_caps.max_rwq_indirection_table_size =
1002                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1003                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1004                 props->max_wq_type_rq =
1005                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1006         }
1007
1008         if (MLX5_CAP_GEN(mdev, tag_matching)) {
1009                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1010                 props->tm_caps.max_num_tags =
1011                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1012                 props->tm_caps.flags = IB_TM_CAP_RC;
1013                 props->tm_caps.max_ops =
1014                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1015                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1016         }
1017
1018         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1019                 props->cq_caps.max_cq_moderation_count =
1020                                                 MLX5_MAX_CQ_COUNT;
1021                 props->cq_caps.max_cq_moderation_period =
1022                                                 MLX5_MAX_CQ_PERIOD;
1023         }
1024
1025         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
1026                 resp.response_length += sizeof(resp.cqe_comp_caps);
1027
1028                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1029                         resp.cqe_comp_caps.max_num =
1030                                 MLX5_CAP_GEN(dev->mdev,
1031                                              cqe_compression_max_num);
1032
1033                         resp.cqe_comp_caps.supported_format =
1034                                 MLX5_IB_CQE_RES_FORMAT_HASH |
1035                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
1036
1037                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1038                                 resp.cqe_comp_caps.supported_format |=
1039                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1040                 }
1041         }
1042
1043         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1044             raw_support) {
1045                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1046                     MLX5_CAP_GEN(mdev, qos)) {
1047                         resp.packet_pacing_caps.qp_rate_limit_max =
1048                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1049                         resp.packet_pacing_caps.qp_rate_limit_min =
1050                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1051                         resp.packet_pacing_caps.supported_qpts |=
1052                                 1 << IB_QPT_RAW_PACKET;
1053                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1054                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1055                                 resp.packet_pacing_caps.cap_flags |=
1056                                         MLX5_IB_PP_SUPPORT_BURST;
1057                 }
1058                 resp.response_length += sizeof(resp.packet_pacing_caps);
1059         }
1060
1061         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1062                         uhw->outlen)) {
1063                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1064                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1065                                 MLX5_IB_ALLOW_MPW;
1066
1067                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1068                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1069                                 MLX5_IB_SUPPORT_EMPW;
1070
1071                 resp.response_length +=
1072                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1073         }
1074
1075         if (field_avail(typeof(resp), flags, uhw->outlen)) {
1076                 resp.response_length += sizeof(resp.flags);
1077
1078                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1079                         resp.flags |=
1080                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1081
1082                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1083                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1084                 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1085                         resp.flags |=
1086                                 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1087         }
1088
1089         if (field_avail(typeof(resp), sw_parsing_caps,
1090                         uhw->outlen)) {
1091                 resp.response_length += sizeof(resp.sw_parsing_caps);
1092                 if (MLX5_CAP_ETH(mdev, swp)) {
1093                         resp.sw_parsing_caps.sw_parsing_offloads |=
1094                                 MLX5_IB_SW_PARSING;
1095
1096                         if (MLX5_CAP_ETH(mdev, swp_csum))
1097                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1098                                         MLX5_IB_SW_PARSING_CSUM;
1099
1100                         if (MLX5_CAP_ETH(mdev, swp_lso))
1101                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1102                                         MLX5_IB_SW_PARSING_LSO;
1103
1104                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1105                                 resp.sw_parsing_caps.supported_qpts =
1106                                         BIT(IB_QPT_RAW_PACKET);
1107                 }
1108         }
1109
1110         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1111             raw_support) {
1112                 resp.response_length += sizeof(resp.striding_rq_caps);
1113                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1114                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1115                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1116                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1117                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1118                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1119                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1120                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1121                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1122                         resp.striding_rq_caps.supported_qpts =
1123                                 BIT(IB_QPT_RAW_PACKET);
1124                 }
1125         }
1126
1127         if (field_avail(typeof(resp), tunnel_offloads_caps,
1128                         uhw->outlen)) {
1129                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1130                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1131                         resp.tunnel_offloads_caps |=
1132                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1133                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1134                         resp.tunnel_offloads_caps |=
1135                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1136                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1137                         resp.tunnel_offloads_caps |=
1138                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1139                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1140                     MLX5_FLEX_PROTO_CW_MPLS_GRE)
1141                         resp.tunnel_offloads_caps |=
1142                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1143                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1144                     MLX5_FLEX_PROTO_CW_MPLS_UDP)
1145                         resp.tunnel_offloads_caps |=
1146                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1147         }
1148
1149         if (uhw->outlen) {
1150                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1151
1152                 if (err)
1153                         return err;
1154         }
1155
1156         return 0;
1157 }
1158
1159 enum mlx5_ib_width {
1160         MLX5_IB_WIDTH_1X        = 1 << 0,
1161         MLX5_IB_WIDTH_2X        = 1 << 1,
1162         MLX5_IB_WIDTH_4X        = 1 << 2,
1163         MLX5_IB_WIDTH_8X        = 1 << 3,
1164         MLX5_IB_WIDTH_12X       = 1 << 4
1165 };
1166
1167 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1168                                   u8 *ib_width)
1169 {
1170         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1171
1172         if (active_width & MLX5_IB_WIDTH_1X)
1173                 *ib_width = IB_WIDTH_1X;
1174         else if (active_width & MLX5_IB_WIDTH_2X)
1175                 *ib_width = IB_WIDTH_2X;
1176         else if (active_width & MLX5_IB_WIDTH_4X)
1177                 *ib_width = IB_WIDTH_4X;
1178         else if (active_width & MLX5_IB_WIDTH_8X)
1179                 *ib_width = IB_WIDTH_8X;
1180         else if (active_width & MLX5_IB_WIDTH_12X)
1181                 *ib_width = IB_WIDTH_12X;
1182         else {
1183                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1184                             (int)active_width);
1185                 *ib_width = IB_WIDTH_4X;
1186         }
1187
1188         return;
1189 }
1190
1191 static int mlx5_mtu_to_ib_mtu(int mtu)
1192 {
1193         switch (mtu) {
1194         case 256: return 1;
1195         case 512: return 2;
1196         case 1024: return 3;
1197         case 2048: return 4;
1198         case 4096: return 5;
1199         default:
1200                 pr_warn("invalid mtu\n");
1201                 return -1;
1202         }
1203 }
1204
1205 enum ib_max_vl_num {
1206         __IB_MAX_VL_0           = 1,
1207         __IB_MAX_VL_0_1         = 2,
1208         __IB_MAX_VL_0_3         = 3,
1209         __IB_MAX_VL_0_7         = 4,
1210         __IB_MAX_VL_0_14        = 5,
1211 };
1212
1213 enum mlx5_vl_hw_cap {
1214         MLX5_VL_HW_0    = 1,
1215         MLX5_VL_HW_0_1  = 2,
1216         MLX5_VL_HW_0_2  = 3,
1217         MLX5_VL_HW_0_3  = 4,
1218         MLX5_VL_HW_0_4  = 5,
1219         MLX5_VL_HW_0_5  = 6,
1220         MLX5_VL_HW_0_6  = 7,
1221         MLX5_VL_HW_0_7  = 8,
1222         MLX5_VL_HW_0_14 = 15
1223 };
1224
1225 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1226                                 u8 *max_vl_num)
1227 {
1228         switch (vl_hw_cap) {
1229         case MLX5_VL_HW_0:
1230                 *max_vl_num = __IB_MAX_VL_0;
1231                 break;
1232         case MLX5_VL_HW_0_1:
1233                 *max_vl_num = __IB_MAX_VL_0_1;
1234                 break;
1235         case MLX5_VL_HW_0_3:
1236                 *max_vl_num = __IB_MAX_VL_0_3;
1237                 break;
1238         case MLX5_VL_HW_0_7:
1239                 *max_vl_num = __IB_MAX_VL_0_7;
1240                 break;
1241         case MLX5_VL_HW_0_14:
1242                 *max_vl_num = __IB_MAX_VL_0_14;
1243                 break;
1244
1245         default:
1246                 return -EINVAL;
1247         }
1248
1249         return 0;
1250 }
1251
1252 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1253                                struct ib_port_attr *props)
1254 {
1255         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1256         struct mlx5_core_dev *mdev = dev->mdev;
1257         struct mlx5_hca_vport_context *rep;
1258         u16 max_mtu;
1259         u16 oper_mtu;
1260         int err;
1261         u8 ib_link_width_oper;
1262         u8 vl_hw_cap;
1263
1264         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1265         if (!rep) {
1266                 err = -ENOMEM;
1267                 goto out;
1268         }
1269
1270         /* props being zeroed by the caller, avoid zeroing it here */
1271
1272         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1273         if (err)
1274                 goto out;
1275
1276         props->lid              = rep->lid;
1277         props->lmc              = rep->lmc;
1278         props->sm_lid           = rep->sm_lid;
1279         props->sm_sl            = rep->sm_sl;
1280         props->state            = rep->vport_state;
1281         props->phys_state       = rep->port_physical_state;
1282         props->port_cap_flags   = rep->cap_mask1;
1283         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1284         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1285         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1286         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1287         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1288         props->subnet_timeout   = rep->subnet_timeout;
1289         props->init_type_reply  = rep->init_type_reply;
1290
1291         if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1292                 props->port_cap_flags2 = rep->cap_mask2;
1293
1294         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1295         if (err)
1296                 goto out;
1297
1298         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1299
1300         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1301         if (err)
1302                 goto out;
1303
1304         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1305
1306         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1307
1308         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1309
1310         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1311
1312         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1313         if (err)
1314                 goto out;
1315
1316         err = translate_max_vl_num(ibdev, vl_hw_cap,
1317                                    &props->max_vl_num);
1318 out:
1319         kfree(rep);
1320         return err;
1321 }
1322
1323 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1324                        struct ib_port_attr *props)
1325 {
1326         unsigned int count;
1327         int ret;
1328
1329         switch (mlx5_get_vport_access_method(ibdev)) {
1330         case MLX5_VPORT_ACCESS_METHOD_MAD:
1331                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1332                 break;
1333
1334         case MLX5_VPORT_ACCESS_METHOD_HCA:
1335                 ret = mlx5_query_hca_port(ibdev, port, props);
1336                 break;
1337
1338         case MLX5_VPORT_ACCESS_METHOD_NIC:
1339                 ret = mlx5_query_port_roce(ibdev, port, props);
1340                 break;
1341
1342         default:
1343                 ret = -EINVAL;
1344         }
1345
1346         if (!ret && props) {
1347                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1348                 struct mlx5_core_dev *mdev;
1349                 bool put_mdev = true;
1350
1351                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1352                 if (!mdev) {
1353                         /* If the port isn't affiliated yet query the master.
1354                          * The master and slave will have the same values.
1355                          */
1356                         mdev = dev->mdev;
1357                         port = 1;
1358                         put_mdev = false;
1359                 }
1360                 count = mlx5_core_reserved_gids_count(mdev);
1361                 if (put_mdev)
1362                         mlx5_ib_put_native_port_mdev(dev, port);
1363                 props->gid_tbl_len -= count;
1364         }
1365         return ret;
1366 }
1367
1368 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1369                                   struct ib_port_attr *props)
1370 {
1371         int ret;
1372
1373         /* Only link layer == ethernet is valid for representors */
1374         ret = mlx5_query_port_roce(ibdev, port, props);
1375         if (ret || !props)
1376                 return ret;
1377
1378         /* We don't support GIDS */
1379         props->gid_tbl_len = 0;
1380
1381         return ret;
1382 }
1383
1384 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1385                              union ib_gid *gid)
1386 {
1387         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1388         struct mlx5_core_dev *mdev = dev->mdev;
1389
1390         switch (mlx5_get_vport_access_method(ibdev)) {
1391         case MLX5_VPORT_ACCESS_METHOD_MAD:
1392                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1393
1394         case MLX5_VPORT_ACCESS_METHOD_HCA:
1395                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1396
1397         default:
1398                 return -EINVAL;
1399         }
1400
1401 }
1402
1403 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1404                                    u16 index, u16 *pkey)
1405 {
1406         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1407         struct mlx5_core_dev *mdev;
1408         bool put_mdev = true;
1409         u8 mdev_port_num;
1410         int err;
1411
1412         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1413         if (!mdev) {
1414                 /* The port isn't affiliated yet, get the PKey from the master
1415                  * port. For RoCE the PKey tables will be the same.
1416                  */
1417                 put_mdev = false;
1418                 mdev = dev->mdev;
1419                 mdev_port_num = 1;
1420         }
1421
1422         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1423                                         index, pkey);
1424         if (put_mdev)
1425                 mlx5_ib_put_native_port_mdev(dev, port);
1426
1427         return err;
1428 }
1429
1430 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1431                               u16 *pkey)
1432 {
1433         switch (mlx5_get_vport_access_method(ibdev)) {
1434         case MLX5_VPORT_ACCESS_METHOD_MAD:
1435                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1436
1437         case MLX5_VPORT_ACCESS_METHOD_HCA:
1438         case MLX5_VPORT_ACCESS_METHOD_NIC:
1439                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1440         default:
1441                 return -EINVAL;
1442         }
1443 }
1444
1445 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1446                                  struct ib_device_modify *props)
1447 {
1448         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1449         struct mlx5_reg_node_desc in;
1450         struct mlx5_reg_node_desc out;
1451         int err;
1452
1453         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1454                 return -EOPNOTSUPP;
1455
1456         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1457                 return 0;
1458
1459         /*
1460          * If possible, pass node desc to FW, so it can generate
1461          * a 144 trap.  If cmd fails, just ignore.
1462          */
1463         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1464         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1465                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1466         if (err)
1467                 return err;
1468
1469         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1470
1471         return err;
1472 }
1473
1474 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1475                                 u32 value)
1476 {
1477         struct mlx5_hca_vport_context ctx = {};
1478         struct mlx5_core_dev *mdev;
1479         u8 mdev_port_num;
1480         int err;
1481
1482         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1483         if (!mdev)
1484                 return -ENODEV;
1485
1486         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1487         if (err)
1488                 goto out;
1489
1490         if (~ctx.cap_mask1_perm & mask) {
1491                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1492                              mask, ctx.cap_mask1_perm);
1493                 err = -EINVAL;
1494                 goto out;
1495         }
1496
1497         ctx.cap_mask1 = value;
1498         ctx.cap_mask1_perm = mask;
1499         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1500                                                  0, &ctx);
1501
1502 out:
1503         mlx5_ib_put_native_port_mdev(dev, port_num);
1504
1505         return err;
1506 }
1507
1508 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1509                                struct ib_port_modify *props)
1510 {
1511         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1512         struct ib_port_attr attr;
1513         u32 tmp;
1514         int err;
1515         u32 change_mask;
1516         u32 value;
1517         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1518                       IB_LINK_LAYER_INFINIBAND);
1519
1520         /* CM layer calls ib_modify_port() regardless of the link layer. For
1521          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1522          */
1523         if (!is_ib)
1524                 return 0;
1525
1526         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1527                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1528                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1529                 return set_port_caps_atomic(dev, port, change_mask, value);
1530         }
1531
1532         mutex_lock(&dev->cap_mask_mutex);
1533
1534         err = ib_query_port(ibdev, port, &attr);
1535         if (err)
1536                 goto out;
1537
1538         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1539                 ~props->clr_port_cap_mask;
1540
1541         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1542
1543 out:
1544         mutex_unlock(&dev->cap_mask_mutex);
1545         return err;
1546 }
1547
1548 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1549 {
1550         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1551                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1552 }
1553
1554 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1555 {
1556         /* Large page with non 4k uar support might limit the dynamic size */
1557         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1558                 return MLX5_MIN_DYN_BFREGS;
1559
1560         return MLX5_MAX_DYN_BFREGS;
1561 }
1562
1563 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1564                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1565                              struct mlx5_bfreg_info *bfregi)
1566 {
1567         int uars_per_sys_page;
1568         int bfregs_per_sys_page;
1569         int ref_bfregs = req->total_num_bfregs;
1570
1571         if (req->total_num_bfregs == 0)
1572                 return -EINVAL;
1573
1574         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1575         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1576
1577         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1578                 return -ENOMEM;
1579
1580         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1581         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1582         /* This holds the required static allocation asked by the user */
1583         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1584         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1585                 return -EINVAL;
1586
1587         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1588         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1589         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1590         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1591
1592         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1593                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1594                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1595                     req->total_num_bfregs, bfregi->total_num_bfregs,
1596                     bfregi->num_sys_pages);
1597
1598         return 0;
1599 }
1600
1601 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1602 {
1603         struct mlx5_bfreg_info *bfregi;
1604         int err;
1605         int i;
1606
1607         bfregi = &context->bfregi;
1608         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1609                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1610                 if (err)
1611                         goto error;
1612
1613                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1614         }
1615
1616         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1617                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1618
1619         return 0;
1620
1621 error:
1622         for (--i; i >= 0; i--)
1623                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1624                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1625
1626         return err;
1627 }
1628
1629 static void deallocate_uars(struct mlx5_ib_dev *dev,
1630                             struct mlx5_ib_ucontext *context)
1631 {
1632         struct mlx5_bfreg_info *bfregi;
1633         int i;
1634
1635         bfregi = &context->bfregi;
1636         for (i = 0; i < bfregi->num_sys_pages; i++)
1637                 if (i < bfregi->num_static_sys_pages ||
1638                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1639                         mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1640 }
1641
1642 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1643 {
1644         int err = 0;
1645
1646         mutex_lock(&dev->lb.mutex);
1647         if (td)
1648                 dev->lb.user_td++;
1649         if (qp)
1650                 dev->lb.qps++;
1651
1652         if (dev->lb.user_td == 2 ||
1653             dev->lb.qps == 1) {
1654                 if (!dev->lb.enabled) {
1655                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1656                         dev->lb.enabled = true;
1657                 }
1658         }
1659
1660         mutex_unlock(&dev->lb.mutex);
1661
1662         return err;
1663 }
1664
1665 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1666 {
1667         mutex_lock(&dev->lb.mutex);
1668         if (td)
1669                 dev->lb.user_td--;
1670         if (qp)
1671                 dev->lb.qps--;
1672
1673         if (dev->lb.user_td == 1 &&
1674             dev->lb.qps == 0) {
1675                 if (dev->lb.enabled) {
1676                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1677                         dev->lb.enabled = false;
1678                 }
1679         }
1680
1681         mutex_unlock(&dev->lb.mutex);
1682 }
1683
1684 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1685                                           u16 uid)
1686 {
1687         int err;
1688
1689         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1690                 return 0;
1691
1692         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1693         if (err)
1694                 return err;
1695
1696         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1697             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1698              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1699                 return err;
1700
1701         return mlx5_ib_enable_lb(dev, true, false);
1702 }
1703
1704 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1705                                              u16 uid)
1706 {
1707         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1708                 return;
1709
1710         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1711
1712         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1713             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1714              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1715                 return;
1716
1717         mlx5_ib_disable_lb(dev, true, false);
1718 }
1719
1720 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1721                                                   struct ib_udata *udata)
1722 {
1723         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1724         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1725         struct mlx5_ib_alloc_ucontext_resp resp = {};
1726         struct mlx5_core_dev *mdev = dev->mdev;
1727         struct mlx5_ib_ucontext *context;
1728         struct mlx5_bfreg_info *bfregi;
1729         int ver;
1730         int err;
1731         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1732                                      max_cqe_version);
1733         u32 dump_fill_mkey;
1734         bool lib_uar_4k;
1735
1736         if (!dev->ib_active)
1737                 return ERR_PTR(-EAGAIN);
1738
1739         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1740                 ver = 0;
1741         else if (udata->inlen >= min_req_v2)
1742                 ver = 2;
1743         else
1744                 return ERR_PTR(-EINVAL);
1745
1746         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1747         if (err)
1748                 return ERR_PTR(err);
1749
1750         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1751                 return ERR_PTR(-EOPNOTSUPP);
1752
1753         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1754                 return ERR_PTR(-EOPNOTSUPP);
1755
1756         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1757                                     MLX5_NON_FP_BFREGS_PER_UAR);
1758         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1759                 return ERR_PTR(-EINVAL);
1760
1761         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1762         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1763                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1764         resp.cache_line_size = cache_line_size();
1765         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1766         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1767         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1768         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1769         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1770         resp.cqe_version = min_t(__u8,
1771                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1772                                  req.max_cqe_version);
1773         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1774                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1775         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1776                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1777         resp.response_length = min(offsetof(typeof(resp), response_length) +
1778                                    sizeof(resp.response_length), udata->outlen);
1779
1780         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1781                 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1782                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1783                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1784                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1785                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1786                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1787                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1788                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1789                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1790         }
1791
1792         context = kzalloc(sizeof(*context), GFP_KERNEL);
1793         if (!context)
1794                 return ERR_PTR(-ENOMEM);
1795
1796         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1797         bfregi = &context->bfregi;
1798
1799         /* updates req->total_num_bfregs */
1800         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1801         if (err)
1802                 goto out_ctx;
1803
1804         mutex_init(&bfregi->lock);
1805         bfregi->lib_uar_4k = lib_uar_4k;
1806         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1807                                 GFP_KERNEL);
1808         if (!bfregi->count) {
1809                 err = -ENOMEM;
1810                 goto out_ctx;
1811         }
1812
1813         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1814                                     sizeof(*bfregi->sys_pages),
1815                                     GFP_KERNEL);
1816         if (!bfregi->sys_pages) {
1817                 err = -ENOMEM;
1818                 goto out_count;
1819         }
1820
1821         err = allocate_uars(dev, context);
1822         if (err)
1823                 goto out_sys_pages;
1824
1825 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1826         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1827 #endif
1828
1829         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1830                 err = mlx5_ib_devx_create(dev, true);
1831                 if (err < 0)
1832                         goto out_uars;
1833                 context->devx_uid = err;
1834         }
1835
1836         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1837                                              context->devx_uid);
1838         if (err)
1839                 goto out_devx;
1840
1841         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1842                 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1843                 if (err)
1844                         goto out_mdev;
1845         }
1846
1847         INIT_LIST_HEAD(&context->db_page_list);
1848         mutex_init(&context->db_page_mutex);
1849
1850         resp.tot_bfregs = req.total_num_bfregs;
1851         resp.num_ports = dev->num_ports;
1852
1853         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1854                 resp.response_length += sizeof(resp.cqe_version);
1855
1856         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1857                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1858                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1859                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1860         }
1861
1862         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1863                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1864                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1865                         resp.eth_min_inline++;
1866                 }
1867                 resp.response_length += sizeof(resp.eth_min_inline);
1868         }
1869
1870         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1871                 if (mdev->clock_info)
1872                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1873                 resp.response_length += sizeof(resp.clock_info_versions);
1874         }
1875
1876         /*
1877          * We don't want to expose information from the PCI bar that is located
1878          * after 4096 bytes, so if the arch only supports larger pages, let's
1879          * pretend we don't support reading the HCA's core clock. This is also
1880          * forced by mmap function.
1881          */
1882         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1883                 if (PAGE_SIZE <= 4096) {
1884                         resp.comp_mask |=
1885                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1886                         resp.hca_core_clock_offset =
1887                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1888                 }
1889                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1890         }
1891
1892         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1893                 resp.response_length += sizeof(resp.log_uar_size);
1894
1895         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1896                 resp.response_length += sizeof(resp.num_uars_per_page);
1897
1898         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1899                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1900                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1901         }
1902
1903         if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1904                 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1905                         resp.dump_fill_mkey = dump_fill_mkey;
1906                         resp.comp_mask |=
1907                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1908                 }
1909                 resp.response_length += sizeof(resp.dump_fill_mkey);
1910         }
1911
1912         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1913         if (err)
1914                 goto out_mdev;
1915
1916         bfregi->ver = ver;
1917         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1918         context->cqe_version = resp.cqe_version;
1919         context->lib_caps = req.lib_caps;
1920         print_lib_caps(dev, context->lib_caps);
1921
1922         if (dev->lag_active) {
1923                 u8 port = mlx5_core_native_port_num(dev->mdev);
1924
1925                 atomic_set(&context->tx_port_affinity,
1926                            atomic_add_return(
1927                                    1, &dev->roce[port].tx_port_affinity));
1928         }
1929
1930         return &context->ibucontext;
1931
1932 out_mdev:
1933         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1934 out_devx:
1935         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1936                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1937
1938 out_uars:
1939         deallocate_uars(dev, context);
1940
1941 out_sys_pages:
1942         kfree(bfregi->sys_pages);
1943
1944 out_count:
1945         kfree(bfregi->count);
1946
1947 out_ctx:
1948         kfree(context);
1949
1950         return ERR_PTR(err);
1951 }
1952
1953 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1954 {
1955         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1956         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1957         struct mlx5_bfreg_info *bfregi;
1958
1959 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1960         /* All umem's must be destroyed before destroying the ucontext. */
1961         mutex_lock(&ibcontext->per_mm_list_lock);
1962         WARN_ON(!list_empty(&ibcontext->per_mm_list));
1963         mutex_unlock(&ibcontext->per_mm_list_lock);
1964 #endif
1965
1966         bfregi = &context->bfregi;
1967         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1968
1969         if (context->devx_uid)
1970                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1971
1972         deallocate_uars(dev, context);
1973         kfree(bfregi->sys_pages);
1974         kfree(bfregi->count);
1975         kfree(context);
1976
1977         return 0;
1978 }
1979
1980 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1981                                  int uar_idx)
1982 {
1983         int fw_uars_per_page;
1984
1985         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1986
1987         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1988 }
1989
1990 static int get_command(unsigned long offset)
1991 {
1992         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1993 }
1994
1995 static int get_arg(unsigned long offset)
1996 {
1997         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1998 }
1999
2000 static int get_index(unsigned long offset)
2001 {
2002         return get_arg(offset);
2003 }
2004
2005 /* Index resides in an extra byte to enable larger values than 255 */
2006 static int get_extended_index(unsigned long offset)
2007 {
2008         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2009 }
2010
2011
2012 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2013 {
2014 }
2015
2016 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2017 {
2018         switch (cmd) {
2019         case MLX5_IB_MMAP_WC_PAGE:
2020                 return "WC";
2021         case MLX5_IB_MMAP_REGULAR_PAGE:
2022                 return "best effort WC";
2023         case MLX5_IB_MMAP_NC_PAGE:
2024                 return "NC";
2025         case MLX5_IB_MMAP_DEVICE_MEM:
2026                 return "Device Memory";
2027         default:
2028                 return NULL;
2029         }
2030 }
2031
2032 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2033                                         struct vm_area_struct *vma,
2034                                         struct mlx5_ib_ucontext *context)
2035 {
2036         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2037                 return -EINVAL;
2038
2039         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2040                 return -EOPNOTSUPP;
2041
2042         if (vma->vm_flags & VM_WRITE)
2043                 return -EPERM;
2044
2045         if (!dev->mdev->clock_info_page)
2046                 return -EOPNOTSUPP;
2047
2048         return rdma_user_mmap_page(&context->ibucontext, vma,
2049                                    dev->mdev->clock_info_page, PAGE_SIZE);
2050 }
2051
2052 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2053                     struct vm_area_struct *vma,
2054                     struct mlx5_ib_ucontext *context)
2055 {
2056         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2057         int err;
2058         unsigned long idx;
2059         phys_addr_t pfn;
2060         pgprot_t prot;
2061         u32 bfreg_dyn_idx = 0;
2062         u32 uar_index;
2063         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2064         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2065                                 bfregi->num_static_sys_pages;
2066
2067         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2068                 return -EINVAL;
2069
2070         if (dyn_uar)
2071                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2072         else
2073                 idx = get_index(vma->vm_pgoff);
2074
2075         if (idx >= max_valid_idx) {
2076                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2077                              idx, max_valid_idx);
2078                 return -EINVAL;
2079         }
2080
2081         switch (cmd) {
2082         case MLX5_IB_MMAP_WC_PAGE:
2083         case MLX5_IB_MMAP_ALLOC_WC:
2084 /* Some architectures don't support WC memory */
2085 #if defined(CONFIG_X86)
2086                 if (!pat_enabled())
2087                         return -EPERM;
2088 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2089                         return -EPERM;
2090 #endif
2091         /* fall through */
2092         case MLX5_IB_MMAP_REGULAR_PAGE:
2093                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2094                 prot = pgprot_writecombine(vma->vm_page_prot);
2095                 break;
2096         case MLX5_IB_MMAP_NC_PAGE:
2097                 prot = pgprot_noncached(vma->vm_page_prot);
2098                 break;
2099         default:
2100                 return -EINVAL;
2101         }
2102
2103         if (dyn_uar) {
2104                 int uars_per_page;
2105
2106                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2107                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2108                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2109                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2110                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2111                         return -EINVAL;
2112                 }
2113
2114                 mutex_lock(&bfregi->lock);
2115                 /* Fail if uar already allocated, first bfreg index of each
2116                  * page holds its count.
2117                  */
2118                 if (bfregi->count[bfreg_dyn_idx]) {
2119                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2120                         mutex_unlock(&bfregi->lock);
2121                         return -EINVAL;
2122                 }
2123
2124                 bfregi->count[bfreg_dyn_idx]++;
2125                 mutex_unlock(&bfregi->lock);
2126
2127                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2128                 if (err) {
2129                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2130                         goto free_bfreg;
2131                 }
2132         } else {
2133                 uar_index = bfregi->sys_pages[idx];
2134         }
2135
2136         pfn = uar_index2pfn(dev, uar_index);
2137         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2138
2139         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2140                                 prot);
2141         if (err) {
2142                 mlx5_ib_err(dev,
2143                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2144                             err, mmap_cmd2str(cmd));
2145                 goto err;
2146         }
2147
2148         if (dyn_uar)
2149                 bfregi->sys_pages[idx] = uar_index;
2150         return 0;
2151
2152 err:
2153         if (!dyn_uar)
2154                 return err;
2155
2156         mlx5_cmd_free_uar(dev->mdev, idx);
2157
2158 free_bfreg:
2159         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2160
2161         return err;
2162 }
2163
2164 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2165 {
2166         struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2167         struct mlx5_ib_dev *dev = to_mdev(context->device);
2168         u16 page_idx = get_extended_index(vma->vm_pgoff);
2169         size_t map_size = vma->vm_end - vma->vm_start;
2170         u32 npages = map_size >> PAGE_SHIFT;
2171         phys_addr_t pfn;
2172
2173         if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2174             page_idx + npages)
2175                 return -EINVAL;
2176
2177         pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2178               MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2179               PAGE_SHIFT) +
2180               page_idx;
2181         return rdma_user_mmap_io(context, vma, pfn, map_size,
2182                                  pgprot_writecombine(vma->vm_page_prot));
2183 }
2184
2185 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2186 {
2187         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2188         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2189         unsigned long command;
2190         phys_addr_t pfn;
2191
2192         command = get_command(vma->vm_pgoff);
2193         switch (command) {
2194         case MLX5_IB_MMAP_WC_PAGE:
2195         case MLX5_IB_MMAP_NC_PAGE:
2196         case MLX5_IB_MMAP_REGULAR_PAGE:
2197         case MLX5_IB_MMAP_ALLOC_WC:
2198                 return uar_mmap(dev, command, vma, context);
2199
2200         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2201                 return -ENOSYS;
2202
2203         case MLX5_IB_MMAP_CORE_CLOCK:
2204                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2205                         return -EINVAL;
2206
2207                 if (vma->vm_flags & VM_WRITE)
2208                         return -EPERM;
2209
2210                 /* Don't expose to user-space information it shouldn't have */
2211                 if (PAGE_SIZE > 4096)
2212                         return -EOPNOTSUPP;
2213
2214                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2215                 pfn = (dev->mdev->iseg_base +
2216                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2217                         PAGE_SHIFT;
2218                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2219                                        PAGE_SIZE, vma->vm_page_prot))
2220                         return -EAGAIN;
2221                 break;
2222         case MLX5_IB_MMAP_CLOCK_INFO:
2223                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2224
2225         case MLX5_IB_MMAP_DEVICE_MEM:
2226                 return dm_mmap(ibcontext, vma);
2227
2228         default:
2229                 return -EINVAL;
2230         }
2231
2232         return 0;
2233 }
2234
2235 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2236                                struct ib_ucontext *context,
2237                                struct ib_dm_alloc_attr *attr,
2238                                struct uverbs_attr_bundle *attrs)
2239 {
2240         u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2241         struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2242         phys_addr_t memic_addr;
2243         struct mlx5_ib_dm *dm;
2244         u64 start_offset;
2245         u32 page_idx;
2246         int err;
2247
2248         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2249         if (!dm)
2250                 return ERR_PTR(-ENOMEM);
2251
2252         mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2253                     attr->length, act_size, attr->alignment);
2254
2255         err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2256                                    act_size, attr->alignment);
2257         if (err)
2258                 goto err_free;
2259
2260         start_offset = memic_addr & ~PAGE_MASK;
2261         page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2262                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2263                     PAGE_SHIFT;
2264
2265         err = uverbs_copy_to(attrs,
2266                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2267                              &start_offset, sizeof(start_offset));
2268         if (err)
2269                 goto err_dealloc;
2270
2271         err = uverbs_copy_to(attrs,
2272                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2273                              &page_idx, sizeof(page_idx));
2274         if (err)
2275                 goto err_dealloc;
2276
2277         bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2278                    DIV_ROUND_UP(act_size, PAGE_SIZE));
2279
2280         dm->dev_addr = memic_addr;
2281
2282         return &dm->ibdm;
2283
2284 err_dealloc:
2285         mlx5_cmd_dealloc_memic(memic, memic_addr,
2286                                act_size);
2287 err_free:
2288         kfree(dm);
2289         return ERR_PTR(err);
2290 }
2291
2292 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2293 {
2294         struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2295         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2296         u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2297         u32 page_idx;
2298         int ret;
2299
2300         ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2301         if (ret)
2302                 return ret;
2303
2304         page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2305                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2306                     PAGE_SHIFT;
2307         bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2308                      page_idx,
2309                      DIV_ROUND_UP(act_size, PAGE_SIZE));
2310
2311         kfree(dm);
2312
2313         return 0;
2314 }
2315
2316 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2317                                       struct ib_ucontext *context,
2318                                       struct ib_udata *udata)
2319 {
2320         struct mlx5_ib_alloc_pd_resp resp;
2321         struct mlx5_ib_pd *pd;
2322         int err;
2323         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2324         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)]   = {};
2325         u16 uid = 0;
2326
2327         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2328         if (!pd)
2329                 return ERR_PTR(-ENOMEM);
2330
2331         uid = context ? to_mucontext(context)->devx_uid : 0;
2332         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2333         MLX5_SET(alloc_pd_in, in, uid, uid);
2334         err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2335                             out, sizeof(out));
2336         if (err) {
2337                 kfree(pd);
2338                 return ERR_PTR(err);
2339         }
2340
2341         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2342         pd->uid = uid;
2343         if (context) {
2344                 resp.pdn = pd->pdn;
2345                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2346                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2347                         kfree(pd);
2348                         return ERR_PTR(-EFAULT);
2349                 }
2350         }
2351
2352         return &pd->ibpd;
2353 }
2354
2355 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2356 {
2357         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2358         struct mlx5_ib_pd *mpd = to_mpd(pd);
2359
2360         mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2361         kfree(mpd);
2362
2363         return 0;
2364 }
2365
2366 enum {
2367         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2368         MATCH_CRITERIA_ENABLE_MISC_BIT,
2369         MATCH_CRITERIA_ENABLE_INNER_BIT,
2370         MATCH_CRITERIA_ENABLE_MISC2_BIT
2371 };
2372
2373 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2374         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2375                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2376
2377 static u8 get_match_criteria_enable(u32 *match_criteria)
2378 {
2379         u8 match_criteria_enable;
2380
2381         match_criteria_enable =
2382                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2383                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2384         match_criteria_enable |=
2385                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2386                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2387         match_criteria_enable |=
2388                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2389                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2390         match_criteria_enable |=
2391                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2392                 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2393
2394         return match_criteria_enable;
2395 }
2396
2397 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2398 {
2399         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2400         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2401 }
2402
2403 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2404                            bool inner)
2405 {
2406         if (inner) {
2407                 MLX5_SET(fte_match_set_misc,
2408                          misc_c, inner_ipv6_flow_label, mask);
2409                 MLX5_SET(fte_match_set_misc,
2410                          misc_v, inner_ipv6_flow_label, val);
2411         } else {
2412                 MLX5_SET(fte_match_set_misc,
2413                          misc_c, outer_ipv6_flow_label, mask);
2414                 MLX5_SET(fte_match_set_misc,
2415                          misc_v, outer_ipv6_flow_label, val);
2416         }
2417 }
2418
2419 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2420 {
2421         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2422         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2423         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2424         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2425 }
2426
2427 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2428 {
2429         if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2430             !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2431                 return -EOPNOTSUPP;
2432
2433         if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2434             !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2435                 return -EOPNOTSUPP;
2436
2437         if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2438             !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2439                 return -EOPNOTSUPP;
2440
2441         if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2442             !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2443                 return -EOPNOTSUPP;
2444
2445         return 0;
2446 }
2447
2448 #define LAST_ETH_FIELD vlan_tag
2449 #define LAST_IB_FIELD sl
2450 #define LAST_IPV4_FIELD tos
2451 #define LAST_IPV6_FIELD traffic_class
2452 #define LAST_TCP_UDP_FIELD src_port
2453 #define LAST_TUNNEL_FIELD tunnel_id
2454 #define LAST_FLOW_TAG_FIELD tag_id
2455 #define LAST_DROP_FIELD size
2456 #define LAST_COUNTERS_FIELD counters
2457
2458 /* Field is the last supported field */
2459 #define FIELDS_NOT_SUPPORTED(filter, field)\
2460         memchr_inv((void *)&filter.field  +\
2461                    sizeof(filter.field), 0,\
2462                    sizeof(filter) -\
2463                    offsetof(typeof(filter), field) -\
2464                    sizeof(filter.field))
2465
2466 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2467                            bool is_egress,
2468                            struct mlx5_flow_act *action)
2469 {
2470
2471         switch (maction->ib_action.type) {
2472         case IB_FLOW_ACTION_ESP:
2473                 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2474                                       MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2475                         return -EINVAL;
2476                 /* Currently only AES_GCM keymat is supported by the driver */
2477                 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2478                 action->action |= is_egress ?
2479                         MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2480                         MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2481                 return 0;
2482         case IB_FLOW_ACTION_UNSPECIFIED:
2483                 if (maction->flow_action_raw.sub_type ==
2484                     MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2485                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2486                                 return -EINVAL;
2487                         action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2488                         action->modify_id = maction->flow_action_raw.action_id;
2489                         return 0;
2490                 }
2491                 if (maction->flow_action_raw.sub_type ==
2492                     MLX5_IB_FLOW_ACTION_DECAP) {
2493                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2494                                 return -EINVAL;
2495                         action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2496                         return 0;
2497                 }
2498                 if (maction->flow_action_raw.sub_type ==
2499                     MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
2500                         if (action->action &
2501                             MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2502                                 return -EINVAL;
2503                         action->action |=
2504                                 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2505                         action->reformat_id =
2506                                 maction->flow_action_raw.action_id;
2507                         return 0;
2508                 }
2509                 /* fall through */
2510         default:
2511                 return -EOPNOTSUPP;
2512         }
2513 }
2514
2515 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2516                            u32 *match_v, const union ib_flow_spec *ib_spec,
2517                            const struct ib_flow_attr *flow_attr,
2518                            struct mlx5_flow_act *action, u32 prev_type)
2519 {
2520         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2521                                            misc_parameters);
2522         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2523                                            misc_parameters);
2524         void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2525                                             misc_parameters_2);
2526         void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2527                                             misc_parameters_2);
2528         void *headers_c;
2529         void *headers_v;
2530         int match_ipv;
2531         int ret;
2532
2533         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2534                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2535                                          inner_headers);
2536                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2537                                          inner_headers);
2538                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2539                                         ft_field_support.inner_ip_version);
2540         } else {
2541                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2542                                          outer_headers);
2543                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2544                                          outer_headers);
2545                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2546                                         ft_field_support.outer_ip_version);
2547         }
2548
2549         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2550         case IB_FLOW_SPEC_ETH:
2551                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2552                         return -EOPNOTSUPP;
2553
2554                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2555                                              dmac_47_16),
2556                                 ib_spec->eth.mask.dst_mac);
2557                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2558                                              dmac_47_16),
2559                                 ib_spec->eth.val.dst_mac);
2560
2561                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2562                                              smac_47_16),
2563                                 ib_spec->eth.mask.src_mac);
2564                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2565                                              smac_47_16),
2566                                 ib_spec->eth.val.src_mac);
2567
2568                 if (ib_spec->eth.mask.vlan_tag) {
2569                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2570                                  cvlan_tag, 1);
2571                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2572                                  cvlan_tag, 1);
2573
2574                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2575                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2576                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2577                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2578
2579                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2580                                  first_cfi,
2581                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2582                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2583                                  first_cfi,
2584                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2585
2586                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2587                                  first_prio,
2588                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2589                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2590                                  first_prio,
2591                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2592                 }
2593                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2594                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2595                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2596                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2597                 break;
2598         case IB_FLOW_SPEC_IPV4:
2599                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2600                         return -EOPNOTSUPP;
2601
2602                 if (match_ipv) {
2603                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2604                                  ip_version, 0xf);
2605                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2606                                  ip_version, MLX5_FS_IPV4_VERSION);
2607                 } else {
2608                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2609                                  ethertype, 0xffff);
2610                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2611                                  ethertype, ETH_P_IP);
2612                 }
2613
2614                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2615                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2616                        &ib_spec->ipv4.mask.src_ip,
2617                        sizeof(ib_spec->ipv4.mask.src_ip));
2618                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2619                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2620                        &ib_spec->ipv4.val.src_ip,
2621                        sizeof(ib_spec->ipv4.val.src_ip));
2622                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2623                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2624                        &ib_spec->ipv4.mask.dst_ip,
2625                        sizeof(ib_spec->ipv4.mask.dst_ip));
2626                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2627                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2628                        &ib_spec->ipv4.val.dst_ip,
2629                        sizeof(ib_spec->ipv4.val.dst_ip));
2630
2631                 set_tos(headers_c, headers_v,
2632                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2633
2634                 set_proto(headers_c, headers_v,
2635                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2636                 break;
2637         case IB_FLOW_SPEC_IPV6:
2638                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2639                         return -EOPNOTSUPP;
2640
2641                 if (match_ipv) {
2642                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2643                                  ip_version, 0xf);
2644                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2645                                  ip_version, MLX5_FS_IPV6_VERSION);
2646                 } else {
2647                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2648                                  ethertype, 0xffff);
2649                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2650                                  ethertype, ETH_P_IPV6);
2651                 }
2652
2653                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2654                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2655                        &ib_spec->ipv6.mask.src_ip,
2656                        sizeof(ib_spec->ipv6.mask.src_ip));
2657                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2658                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2659                        &ib_spec->ipv6.val.src_ip,
2660                        sizeof(ib_spec->ipv6.val.src_ip));
2661                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2662                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2663                        &ib_spec->ipv6.mask.dst_ip,
2664                        sizeof(ib_spec->ipv6.mask.dst_ip));
2665                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2666                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2667                        &ib_spec->ipv6.val.dst_ip,
2668                        sizeof(ib_spec->ipv6.val.dst_ip));
2669
2670                 set_tos(headers_c, headers_v,
2671                         ib_spec->ipv6.mask.traffic_class,
2672                         ib_spec->ipv6.val.traffic_class);
2673
2674                 set_proto(headers_c, headers_v,
2675                           ib_spec->ipv6.mask.next_hdr,
2676                           ib_spec->ipv6.val.next_hdr);
2677
2678                 set_flow_label(misc_params_c, misc_params_v,
2679                                ntohl(ib_spec->ipv6.mask.flow_label),
2680                                ntohl(ib_spec->ipv6.val.flow_label),
2681                                ib_spec->type & IB_FLOW_SPEC_INNER);
2682                 break;
2683         case IB_FLOW_SPEC_ESP:
2684                 if (ib_spec->esp.mask.seq)
2685                         return -EOPNOTSUPP;
2686
2687                 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2688                          ntohl(ib_spec->esp.mask.spi));
2689                 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2690                          ntohl(ib_spec->esp.val.spi));
2691                 break;
2692         case IB_FLOW_SPEC_TCP:
2693                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2694                                          LAST_TCP_UDP_FIELD))
2695                         return -EOPNOTSUPP;
2696
2697                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2698                          0xff);
2699                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2700                          IPPROTO_TCP);
2701
2702                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2703                          ntohs(ib_spec->tcp_udp.mask.src_port));
2704                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2705                          ntohs(ib_spec->tcp_udp.val.src_port));
2706
2707                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2708                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2709                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2710                          ntohs(ib_spec->tcp_udp.val.dst_port));
2711                 break;
2712         case IB_FLOW_SPEC_UDP:
2713                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2714                                          LAST_TCP_UDP_FIELD))
2715                         return -EOPNOTSUPP;
2716
2717                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2718                          0xff);
2719                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2720                          IPPROTO_UDP);
2721
2722                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2723                          ntohs(ib_spec->tcp_udp.mask.src_port));
2724                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2725                          ntohs(ib_spec->tcp_udp.val.src_port));
2726
2727                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2728                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2729                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2730                          ntohs(ib_spec->tcp_udp.val.dst_port));
2731                 break;
2732         case IB_FLOW_SPEC_GRE:
2733                 if (ib_spec->gre.mask.c_ks_res0_ver)
2734                         return -EOPNOTSUPP;
2735
2736                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2737                          0xff);
2738                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2739                          IPPROTO_GRE);
2740
2741                 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2742                          ntohs(ib_spec->gre.mask.protocol));
2743                 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2744                          ntohs(ib_spec->gre.val.protocol));
2745
2746                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2747                                     gre_key.nvgre.hi),
2748                        &ib_spec->gre.mask.key,
2749                        sizeof(ib_spec->gre.mask.key));
2750                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2751                                     gre_key.nvgre.hi),
2752                        &ib_spec->gre.val.key,
2753                        sizeof(ib_spec->gre.val.key));
2754                 break;
2755         case IB_FLOW_SPEC_MPLS:
2756                 switch (prev_type) {
2757                 case IB_FLOW_SPEC_UDP:
2758                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2759                                                    ft_field_support.outer_first_mpls_over_udp),
2760                                                    &ib_spec->mpls.mask.tag))
2761                                 return -EOPNOTSUPP;
2762
2763                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2764                                             outer_first_mpls_over_udp),
2765                                &ib_spec->mpls.val.tag,
2766                                sizeof(ib_spec->mpls.val.tag));
2767                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2768                                             outer_first_mpls_over_udp),
2769                                &ib_spec->mpls.mask.tag,
2770                                sizeof(ib_spec->mpls.mask.tag));
2771                         break;
2772                 case IB_FLOW_SPEC_GRE:
2773                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2774                                                    ft_field_support.outer_first_mpls_over_gre),
2775                                                    &ib_spec->mpls.mask.tag))
2776                                 return -EOPNOTSUPP;
2777
2778                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2779                                             outer_first_mpls_over_gre),
2780                                &ib_spec->mpls.val.tag,
2781                                sizeof(ib_spec->mpls.val.tag));
2782                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2783                                             outer_first_mpls_over_gre),
2784                                &ib_spec->mpls.mask.tag,
2785                                sizeof(ib_spec->mpls.mask.tag));
2786                         break;
2787                 default:
2788                         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2789                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2790                                                            ft_field_support.inner_first_mpls),
2791                                                            &ib_spec->mpls.mask.tag))
2792                                         return -EOPNOTSUPP;
2793
2794                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2795                                                     inner_first_mpls),
2796                                        &ib_spec->mpls.val.tag,
2797                                        sizeof(ib_spec->mpls.val.tag));
2798                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2799                                                     inner_first_mpls),
2800                                        &ib_spec->mpls.mask.tag,
2801                                        sizeof(ib_spec->mpls.mask.tag));
2802                         } else {
2803                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2804                                                            ft_field_support.outer_first_mpls),
2805                                                            &ib_spec->mpls.mask.tag))
2806                                         return -EOPNOTSUPP;
2807
2808                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2809                                                     outer_first_mpls),
2810                                        &ib_spec->mpls.val.tag,
2811                                        sizeof(ib_spec->mpls.val.tag));
2812                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2813                                                     outer_first_mpls),
2814                                        &ib_spec->mpls.mask.tag,
2815                                        sizeof(ib_spec->mpls.mask.tag));
2816                         }
2817                 }
2818                 break;
2819         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2820                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2821                                          LAST_TUNNEL_FIELD))
2822                         return -EOPNOTSUPP;
2823
2824                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2825                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2826                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2827                          ntohl(ib_spec->tunnel.val.tunnel_id));
2828                 break;
2829         case IB_FLOW_SPEC_ACTION_TAG:
2830                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2831                                          LAST_FLOW_TAG_FIELD))
2832                         return -EOPNOTSUPP;
2833                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2834                         return -EINVAL;
2835
2836                 action->flow_tag = ib_spec->flow_tag.tag_id;
2837                 action->flags |= FLOW_ACT_HAS_TAG;
2838                 break;
2839         case IB_FLOW_SPEC_ACTION_DROP:
2840                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2841                                          LAST_DROP_FIELD))
2842                         return -EOPNOTSUPP;
2843                 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2844                 break;
2845         case IB_FLOW_SPEC_ACTION_HANDLE:
2846                 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
2847                         flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
2848                 if (ret)
2849                         return ret;
2850                 break;
2851         case IB_FLOW_SPEC_ACTION_COUNT:
2852                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2853                                          LAST_COUNTERS_FIELD))
2854                         return -EOPNOTSUPP;
2855
2856                 /* for now support only one counters spec per flow */
2857                 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2858                         return -EINVAL;
2859
2860                 action->counters = ib_spec->flow_count.counters;
2861                 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2862                 break;
2863         default:
2864                 return -EINVAL;
2865         }
2866
2867         return 0;
2868 }
2869
2870 /* If a flow could catch both multicast and unicast packets,
2871  * it won't fall into the multicast flow steering table and this rule
2872  * could steal other multicast packets.
2873  */
2874 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2875 {
2876         union ib_flow_spec *flow_spec;
2877
2878         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2879             ib_attr->num_of_specs < 1)
2880                 return false;
2881
2882         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2883         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2884                 struct ib_flow_spec_ipv4 *ipv4_spec;
2885
2886                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2887                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2888                         return true;
2889
2890                 return false;
2891         }
2892
2893         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2894                 struct ib_flow_spec_eth *eth_spec;
2895
2896                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2897                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2898                        is_multicast_ether_addr(eth_spec->val.dst_mac);
2899         }
2900
2901         return false;
2902 }
2903
2904 enum valid_spec {
2905         VALID_SPEC_INVALID,
2906         VALID_SPEC_VALID,
2907         VALID_SPEC_NA,
2908 };
2909
2910 static enum valid_spec
2911 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2912                      const struct mlx5_flow_spec *spec,
2913                      const struct mlx5_flow_act *flow_act,
2914                      bool egress)
2915 {
2916         const u32 *match_c = spec->match_criteria;
2917         bool is_crypto =
2918                 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2919                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2920         bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2921         bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2922
2923         /*
2924          * Currently only crypto is supported in egress, when regular egress
2925          * rules would be supported, always return VALID_SPEC_NA.
2926          */
2927         if (!is_crypto)
2928                 return VALID_SPEC_NA;
2929
2930         return is_crypto && is_ipsec &&
2931                 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ?
2932                 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2933 }
2934
2935 static bool is_valid_spec(struct mlx5_core_dev *mdev,
2936                           const struct mlx5_flow_spec *spec,
2937                           const struct mlx5_flow_act *flow_act,
2938                           bool egress)
2939 {
2940         /* We curretly only support ipsec egress flow */
2941         return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2942 }
2943
2944 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2945                                const struct ib_flow_attr *flow_attr,
2946                                bool check_inner)
2947 {
2948         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2949         int match_ipv = check_inner ?
2950                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2951                                         ft_field_support.inner_ip_version) :
2952                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2953                                         ft_field_support.outer_ip_version);
2954         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2955         bool ipv4_spec_valid, ipv6_spec_valid;
2956         unsigned int ip_spec_type = 0;
2957         bool has_ethertype = false;
2958         unsigned int spec_index;
2959         bool mask_valid = true;
2960         u16 eth_type = 0;
2961         bool type_valid;
2962
2963         /* Validate that ethertype is correct */
2964         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2965                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2966                     ib_spec->eth.mask.ether_type) {
2967                         mask_valid = (ib_spec->eth.mask.ether_type ==
2968                                       htons(0xffff));
2969                         has_ethertype = true;
2970                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2971                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2972                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2973                         ip_spec_type = ib_spec->type;
2974                 }
2975                 ib_spec = (void *)ib_spec + ib_spec->size;
2976         }
2977
2978         type_valid = (!has_ethertype) || (!ip_spec_type);
2979         if (!type_valid && mask_valid) {
2980                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2981                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2982                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2983                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2984
2985                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2986                              (((eth_type == ETH_P_MPLS_UC) ||
2987                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2988         }
2989
2990         return type_valid;
2991 }
2992
2993 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2994                           const struct ib_flow_attr *flow_attr)
2995 {
2996         return is_valid_ethertype(mdev, flow_attr, false) &&
2997                is_valid_ethertype(mdev, flow_attr, true);
2998 }
2999
3000 static void put_flow_table(struct mlx5_ib_dev *dev,
3001                            struct mlx5_ib_flow_prio *prio, bool ft_added)
3002 {
3003         prio->refcount -= !!ft_added;
3004         if (!prio->refcount) {
3005                 mlx5_destroy_flow_table(prio->flow_table);
3006                 prio->flow_table = NULL;
3007         }
3008 }
3009
3010 static void counters_clear_description(struct ib_counters *counters)
3011 {
3012         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3013
3014         mutex_lock(&mcounters->mcntrs_mutex);
3015         kfree(mcounters->counters_data);
3016         mcounters->counters_data = NULL;
3017         mcounters->cntrs_max_index = 0;
3018         mutex_unlock(&mcounters->mcntrs_mutex);
3019 }
3020
3021 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3022 {
3023         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3024                                                           struct mlx5_ib_flow_handler,
3025                                                           ibflow);
3026         struct mlx5_ib_flow_handler *iter, *tmp;
3027         struct mlx5_ib_dev *dev = handler->dev;
3028
3029         mutex_lock(&dev->flow_db->lock);
3030
3031         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3032                 mlx5_del_flow_rules(iter->rule);
3033                 put_flow_table(dev, iter->prio, true);
3034                 list_del(&iter->list);
3035                 kfree(iter);
3036         }
3037
3038         mlx5_del_flow_rules(handler->rule);
3039         put_flow_table(dev, handler->prio, true);
3040         if (handler->ibcounters &&
3041             atomic_read(&handler->ibcounters->usecnt) == 1)
3042                 counters_clear_description(handler->ibcounters);
3043
3044         mutex_unlock(&dev->flow_db->lock);
3045         if (handler->flow_matcher)
3046                 atomic_dec(&handler->flow_matcher->usecnt);
3047         kfree(handler);
3048
3049         return 0;
3050 }
3051
3052 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3053 {
3054         priority *= 2;
3055         if (!dont_trap)
3056                 priority++;
3057         return priority;
3058 }
3059
3060 enum flow_table_type {
3061         MLX5_IB_FT_RX,
3062         MLX5_IB_FT_TX
3063 };
3064
3065 #define MLX5_FS_MAX_TYPES        6
3066 #define MLX5_FS_MAX_ENTRIES      BIT(16)
3067
3068 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3069                                            struct mlx5_ib_flow_prio *prio,
3070                                            int priority,
3071                                            int num_entries, int num_groups,
3072                                            u32 flags)
3073 {
3074         struct mlx5_flow_table *ft;
3075
3076         ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3077                                                  num_entries,
3078                                                  num_groups,
3079                                                  0, flags);
3080         if (IS_ERR(ft))
3081                 return ERR_CAST(ft);
3082
3083         prio->flow_table = ft;
3084         prio->refcount = 0;
3085         return prio;
3086 }
3087
3088 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3089                                                 struct ib_flow_attr *flow_attr,
3090                                                 enum flow_table_type ft_type)
3091 {
3092         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3093         struct mlx5_flow_namespace *ns = NULL;
3094         struct mlx5_ib_flow_prio *prio;
3095         struct mlx5_flow_table *ft;
3096         int max_table_size;
3097         int num_entries;
3098         int num_groups;
3099         u32 flags = 0;
3100         int priority;
3101
3102         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3103                                                        log_max_ft_size));
3104         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3105                 enum mlx5_flow_namespace_type fn_type;
3106
3107                 if (flow_is_multicast_only(flow_attr) &&
3108                     !dont_trap)
3109                         priority = MLX5_IB_FLOW_MCAST_PRIO;
3110                 else
3111                         priority = ib_prio_to_core_prio(flow_attr->priority,
3112                                                         dont_trap);
3113                 if (ft_type == MLX5_IB_FT_RX) {
3114                         fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3115                         prio = &dev->flow_db->prios[priority];
3116                         if (!dev->rep &&
3117                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3118                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3119                         if (!dev->rep &&
3120                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3121                                         reformat_l3_tunnel_to_l2))
3122                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3123                 } else {
3124                         max_table_size =
3125                                 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3126                                                               log_max_ft_size));
3127                         fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3128                         prio = &dev->flow_db->egress_prios[priority];
3129                         if (!dev->rep &&
3130                             MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3131                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3132                 }
3133                 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3134                 num_entries = MLX5_FS_MAX_ENTRIES;
3135                 num_groups = MLX5_FS_MAX_TYPES;
3136         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3137                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3138                 ns = mlx5_get_flow_namespace(dev->mdev,
3139                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
3140                 build_leftovers_ft_param(&priority,
3141                                          &num_entries,
3142                                          &num_groups);
3143                 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3144         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3145                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3146                                         allow_sniffer_and_nic_rx_shared_tir))
3147                         return ERR_PTR(-ENOTSUPP);
3148
3149                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3150                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3151                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3152
3153                 prio = &dev->flow_db->sniffer[ft_type];
3154                 priority = 0;
3155                 num_entries = 1;
3156                 num_groups = 1;
3157         }
3158
3159         if (!ns)
3160                 return ERR_PTR(-ENOTSUPP);
3161
3162         if (num_entries > max_table_size)
3163                 return ERR_PTR(-ENOMEM);
3164
3165         ft = prio->flow_table;
3166         if (!ft)
3167                 return _get_prio(ns, prio, priority, num_entries, num_groups,
3168                                  flags);
3169
3170         return prio;
3171 }
3172
3173 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3174                             struct mlx5_flow_spec *spec,
3175                             u32 underlay_qpn)
3176 {
3177         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3178                                            spec->match_criteria,
3179                                            misc_parameters);
3180         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3181                                            misc_parameters);
3182
3183         if (underlay_qpn &&
3184             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3185                                       ft_field_support.bth_dst_qp)) {
3186                 MLX5_SET(fte_match_set_misc,
3187                          misc_params_v, bth_dst_qp, underlay_qpn);
3188                 MLX5_SET(fte_match_set_misc,
3189                          misc_params_c, bth_dst_qp, 0xffffff);
3190         }
3191 }
3192
3193 static int read_flow_counters(struct ib_device *ibdev,
3194                               struct mlx5_read_counters_attr *read_attr)
3195 {
3196         struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3197         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3198
3199         return mlx5_fc_query(dev->mdev, fc,
3200                              &read_attr->out[IB_COUNTER_PACKETS],
3201                              &read_attr->out[IB_COUNTER_BYTES]);
3202 }
3203
3204 /* flow counters currently expose two counters packets and bytes */
3205 #define FLOW_COUNTERS_NUM 2
3206 static int counters_set_description(struct ib_counters *counters,
3207                                     enum mlx5_ib_counters_type counters_type,
3208                                     struct mlx5_ib_flow_counters_desc *desc_data,
3209                                     u32 ncounters)
3210 {
3211         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3212         u32 cntrs_max_index = 0;
3213         int i;
3214
3215         if (counters_type != MLX5_IB_COUNTERS_FLOW)
3216                 return -EINVAL;
3217
3218         /* init the fields for the object */
3219         mcounters->type = counters_type;
3220         mcounters->read_counters = read_flow_counters;
3221         mcounters->counters_num = FLOW_COUNTERS_NUM;
3222         mcounters->ncounters = ncounters;
3223         /* each counter entry have both description and index pair */
3224         for (i = 0; i < ncounters; i++) {
3225                 if (desc_data[i].description > IB_COUNTER_BYTES)
3226                         return -EINVAL;
3227
3228                 if (cntrs_max_index <= desc_data[i].index)
3229                         cntrs_max_index = desc_data[i].index + 1;
3230         }
3231
3232         mutex_lock(&mcounters->mcntrs_mutex);
3233         mcounters->counters_data = desc_data;
3234         mcounters->cntrs_max_index = cntrs_max_index;
3235         mutex_unlock(&mcounters->mcntrs_mutex);
3236
3237         return 0;
3238 }
3239
3240 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3241 static int flow_counters_set_data(struct ib_counters *ibcounters,
3242                                   struct mlx5_ib_create_flow *ucmd)
3243 {
3244         struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3245         struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3246         struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3247         bool hw_hndl = false;
3248         int ret = 0;
3249
3250         if (ucmd && ucmd->ncounters_data != 0) {
3251                 cntrs_data = ucmd->data;
3252                 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3253                         return -EINVAL;
3254
3255                 desc_data = kcalloc(cntrs_data->ncounters,
3256                                     sizeof(*desc_data),
3257                                     GFP_KERNEL);
3258                 if (!desc_data)
3259                         return  -ENOMEM;
3260
3261                 if (copy_from_user(desc_data,
3262                                    u64_to_user_ptr(cntrs_data->counters_data),
3263                                    sizeof(*desc_data) * cntrs_data->ncounters)) {
3264                         ret = -EFAULT;
3265                         goto free;
3266                 }
3267         }
3268
3269         if (!mcounters->hw_cntrs_hndl) {
3270                 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3271                         to_mdev(ibcounters->device)->mdev, false);
3272                 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3273                         ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3274                         goto free;
3275                 }
3276                 hw_hndl = true;
3277         }
3278
3279         if (desc_data) {
3280                 /* counters already bound to at least one flow */
3281                 if (mcounters->cntrs_max_index) {
3282                         ret = -EINVAL;
3283                         goto free_hndl;
3284                 }
3285
3286                 ret = counters_set_description(ibcounters,
3287                                                MLX5_IB_COUNTERS_FLOW,
3288                                                desc_data,
3289                                                cntrs_data->ncounters);
3290                 if (ret)
3291                         goto free_hndl;
3292
3293         } else if (!mcounters->cntrs_max_index) {
3294                 /* counters not bound yet, must have udata passed */
3295                 ret = -EINVAL;
3296                 goto free_hndl;
3297         }
3298
3299         return 0;
3300
3301 free_hndl:
3302         if (hw_hndl) {
3303                 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3304                                 mcounters->hw_cntrs_hndl);
3305                 mcounters->hw_cntrs_hndl = NULL;
3306         }
3307 free:
3308         kfree(desc_data);
3309         return ret;
3310 }
3311
3312 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3313                                                       struct mlx5_ib_flow_prio *ft_prio,
3314                                                       const struct ib_flow_attr *flow_attr,
3315                                                       struct mlx5_flow_destination *dst,
3316                                                       u32 underlay_qpn,
3317                                                       struct mlx5_ib_create_flow *ucmd)
3318 {
3319         struct mlx5_flow_table  *ft = ft_prio->flow_table;
3320         struct mlx5_ib_flow_handler *handler;
3321         struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3322         struct mlx5_flow_spec *spec;
3323         struct mlx5_flow_destination dest_arr[2] = {};
3324         struct mlx5_flow_destination *rule_dst = dest_arr;
3325         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3326         unsigned int spec_index;
3327         u32 prev_type = 0;
3328         int err = 0;
3329         int dest_num = 0;
3330         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3331
3332         if (!is_valid_attr(dev->mdev, flow_attr))
3333                 return ERR_PTR(-EINVAL);
3334
3335         if (dev->rep && is_egress)
3336                 return ERR_PTR(-EINVAL);
3337
3338         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3339         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3340         if (!handler || !spec) {
3341                 err = -ENOMEM;
3342                 goto free;
3343         }
3344
3345         INIT_LIST_HEAD(&handler->list);
3346         if (dst) {
3347                 memcpy(&dest_arr[0], dst, sizeof(*dst));
3348                 dest_num++;
3349         }
3350
3351         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3352                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3353                                       spec->match_value,
3354                                       ib_flow, flow_attr, &flow_act,
3355                                       prev_type);
3356                 if (err < 0)
3357                         goto free;
3358
3359                 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3360                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3361         }
3362
3363         if (!flow_is_multicast_only(flow_attr))
3364                 set_underlay_qp(dev, spec, underlay_qpn);
3365
3366         if (dev->rep) {
3367                 void *misc;
3368
3369                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3370                                     misc_parameters);
3371                 MLX5_SET(fte_match_set_misc, misc, source_port,
3372                          dev->rep->vport);
3373                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3374                                     misc_parameters);
3375                 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3376         }
3377
3378         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3379
3380         if (is_egress &&
3381             !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3382                 err = -EINVAL;
3383                 goto free;
3384         }
3385
3386         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3387                 struct mlx5_ib_mcounters *mcounters;
3388
3389                 err = flow_counters_set_data(flow_act.counters, ucmd);
3390                 if (err)
3391                         goto free;
3392
3393                 mcounters = to_mcounters(flow_act.counters);
3394                 handler->ibcounters = flow_act.counters;
3395                 dest_arr[dest_num].type =
3396                         MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3397                 dest_arr[dest_num].counter_id =
3398                         mlx5_fc_id(mcounters->hw_cntrs_hndl);
3399                 dest_num++;
3400         }
3401
3402         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3403                 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3404                         rule_dst = NULL;
3405                         dest_num = 0;
3406                 }
3407         } else {
3408                 if (is_egress)
3409                         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3410                 else
3411                         flow_act.action |=
3412                                 dest_num ?  MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3413                                         MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3414         }
3415
3416         if ((flow_act.flags & FLOW_ACT_HAS_TAG)  &&
3417             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3418              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3419                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3420                              flow_act.flow_tag, flow_attr->type);
3421                 err = -EINVAL;
3422                 goto free;
3423         }
3424         handler->rule = mlx5_add_flow_rules(ft, spec,
3425                                             &flow_act,
3426                                             rule_dst, dest_num);
3427
3428         if (IS_ERR(handler->rule)) {
3429                 err = PTR_ERR(handler->rule);
3430                 goto free;
3431         }
3432
3433         ft_prio->refcount++;
3434         handler->prio = ft_prio;
3435         handler->dev = dev;
3436
3437         ft_prio->flow_table = ft;
3438 free:
3439         if (err && handler) {
3440                 if (handler->ibcounters &&
3441                     atomic_read(&handler->ibcounters->usecnt) == 1)
3442                         counters_clear_description(handler->ibcounters);
3443                 kfree(handler);
3444         }
3445         kvfree(spec);
3446         return err ? ERR_PTR(err) : handler;
3447 }
3448
3449 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3450                                                      struct mlx5_ib_flow_prio *ft_prio,
3451                                                      const struct ib_flow_attr *flow_attr,
3452                                                      struct mlx5_flow_destination *dst)
3453 {
3454         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3455 }
3456
3457 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3458                                                           struct mlx5_ib_flow_prio *ft_prio,
3459                                                           struct ib_flow_attr *flow_attr,
3460                                                           struct mlx5_flow_destination *dst)
3461 {
3462         struct mlx5_ib_flow_handler *handler_dst = NULL;
3463         struct mlx5_ib_flow_handler *handler = NULL;
3464
3465         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3466         if (!IS_ERR(handler)) {
3467                 handler_dst = create_flow_rule(dev, ft_prio,
3468                                                flow_attr, dst);
3469                 if (IS_ERR(handler_dst)) {
3470                         mlx5_del_flow_rules(handler->rule);
3471                         ft_prio->refcount--;
3472                         kfree(handler);
3473                         handler = handler_dst;
3474                 } else {
3475                         list_add(&handler_dst->list, &handler->list);
3476                 }
3477         }
3478
3479         return handler;
3480 }
3481 enum {
3482         LEFTOVERS_MC,
3483         LEFTOVERS_UC,
3484 };
3485
3486 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3487                                                           struct mlx5_ib_flow_prio *ft_prio,
3488                                                           struct ib_flow_attr *flow_attr,
3489                                                           struct mlx5_flow_destination *dst)
3490 {
3491         struct mlx5_ib_flow_handler *handler_ucast = NULL;
3492         struct mlx5_ib_flow_handler *handler = NULL;
3493
3494         static struct {
3495                 struct ib_flow_attr     flow_attr;
3496                 struct ib_flow_spec_eth eth_flow;
3497         } leftovers_specs[] = {
3498                 [LEFTOVERS_MC] = {
3499                         .flow_attr = {
3500                                 .num_of_specs = 1,
3501                                 .size = sizeof(leftovers_specs[0])
3502                         },
3503                         .eth_flow = {
3504                                 .type = IB_FLOW_SPEC_ETH,
3505                                 .size = sizeof(struct ib_flow_spec_eth),
3506                                 .mask = {.dst_mac = {0x1} },
3507                                 .val =  {.dst_mac = {0x1} }
3508                         }
3509                 },
3510                 [LEFTOVERS_UC] = {
3511                         .flow_attr = {
3512                                 .num_of_specs = 1,
3513                                 .size = sizeof(leftovers_specs[0])
3514                         },
3515                         .eth_flow = {
3516                                 .type = IB_FLOW_SPEC_ETH,
3517                                 .size = sizeof(struct ib_flow_spec_eth),
3518                                 .mask = {.dst_mac = {0x1} },
3519                                 .val = {.dst_mac = {} }
3520                         }
3521                 }
3522         };
3523
3524         handler = create_flow_rule(dev, ft_prio,
3525                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
3526                                    dst);
3527         if (!IS_ERR(handler) &&
3528             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3529                 handler_ucast = create_flow_rule(dev, ft_prio,
3530                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
3531                                                  dst);
3532                 if (IS_ERR(handler_ucast)) {
3533                         mlx5_del_flow_rules(handler->rule);
3534                         ft_prio->refcount--;
3535                         kfree(handler);
3536                         handler = handler_ucast;
3537                 } else {
3538                         list_add(&handler_ucast->list, &handler->list);
3539                 }
3540         }
3541
3542         return handler;
3543 }
3544
3545 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3546                                                         struct mlx5_ib_flow_prio *ft_rx,
3547                                                         struct mlx5_ib_flow_prio *ft_tx,
3548                                                         struct mlx5_flow_destination *dst)
3549 {
3550         struct mlx5_ib_flow_handler *handler_rx;
3551         struct mlx5_ib_flow_handler *handler_tx;
3552         int err;
3553         static const struct ib_flow_attr flow_attr  = {
3554                 .num_of_specs = 0,
3555                 .size = sizeof(flow_attr)
3556         };
3557
3558         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3559         if (IS_ERR(handler_rx)) {
3560                 err = PTR_ERR(handler_rx);
3561                 goto err;
3562         }
3563
3564         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3565         if (IS_ERR(handler_tx)) {
3566                 err = PTR_ERR(handler_tx);
3567                 goto err_tx;
3568         }
3569
3570         list_add(&handler_tx->list, &handler_rx->list);
3571
3572         return handler_rx;
3573
3574 err_tx:
3575         mlx5_del_flow_rules(handler_rx->rule);
3576         ft_rx->refcount--;
3577         kfree(handler_rx);
3578 err:
3579         return ERR_PTR(err);
3580 }
3581
3582 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3583                                            struct ib_flow_attr *flow_attr,
3584                                            int domain,
3585                                            struct ib_udata *udata)
3586 {
3587         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3588         struct mlx5_ib_qp *mqp = to_mqp(qp);
3589         struct mlx5_ib_flow_handler *handler = NULL;
3590         struct mlx5_flow_destination *dst = NULL;
3591         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3592         struct mlx5_ib_flow_prio *ft_prio;
3593         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3594         struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3595         size_t min_ucmd_sz, required_ucmd_sz;
3596         int err;
3597         int underlay_qpn;
3598
3599         if (udata && udata->inlen) {
3600                 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3601                                 sizeof(ucmd_hdr.reserved);
3602                 if (udata->inlen < min_ucmd_sz)
3603                         return ERR_PTR(-EOPNOTSUPP);
3604
3605                 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3606                 if (err)
3607                         return ERR_PTR(err);
3608
3609                 /* currently supports only one counters data */
3610                 if (ucmd_hdr.ncounters_data > 1)
3611                         return ERR_PTR(-EINVAL);
3612
3613                 required_ucmd_sz = min_ucmd_sz +
3614                         sizeof(struct mlx5_ib_flow_counters_data) *
3615                         ucmd_hdr.ncounters_data;
3616                 if (udata->inlen > required_ucmd_sz &&
3617                     !ib_is_udata_cleared(udata, required_ucmd_sz,
3618                                          udata->inlen - required_ucmd_sz))
3619                         return ERR_PTR(-EOPNOTSUPP);
3620
3621                 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3622                 if (!ucmd)
3623                         return ERR_PTR(-ENOMEM);
3624
3625                 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3626                 if (err)
3627                         goto free_ucmd;
3628         }
3629
3630         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3631                 err = -ENOMEM;
3632                 goto free_ucmd;
3633         }
3634
3635         if (domain != IB_FLOW_DOMAIN_USER ||
3636             flow_attr->port > dev->num_ports ||
3637             (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3638                                   IB_FLOW_ATTR_FLAGS_EGRESS))) {
3639                 err = -EINVAL;
3640                 goto free_ucmd;
3641         }
3642
3643         if (is_egress &&
3644             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3645              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3646                 err = -EINVAL;
3647                 goto free_ucmd;
3648         }
3649
3650         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3651         if (!dst) {
3652                 err = -ENOMEM;
3653                 goto free_ucmd;
3654         }
3655
3656         mutex_lock(&dev->flow_db->lock);
3657
3658         ft_prio = get_flow_table(dev, flow_attr,
3659                                  is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3660         if (IS_ERR(ft_prio)) {
3661                 err = PTR_ERR(ft_prio);
3662                 goto unlock;
3663         }
3664         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3665                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3666                 if (IS_ERR(ft_prio_tx)) {
3667                         err = PTR_ERR(ft_prio_tx);
3668                         ft_prio_tx = NULL;
3669                         goto destroy_ft;
3670                 }
3671         }
3672
3673         if (is_egress) {
3674                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3675         } else {
3676                 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3677                 if (mqp->flags & MLX5_IB_QP_RSS)
3678                         dst->tir_num = mqp->rss_qp.tirn;
3679                 else
3680                         dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3681         }
3682
3683         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3684                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3685                         handler = create_dont_trap_rule(dev, ft_prio,
3686                                                         flow_attr, dst);
3687                 } else {
3688                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3689                                         mqp->underlay_qpn : 0;
3690                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3691                                                     dst, underlay_qpn, ucmd);
3692                 }
3693         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3694                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3695                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3696                                                 dst);
3697         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3698                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3699         } else {
3700                 err = -EINVAL;
3701                 goto destroy_ft;
3702         }
3703
3704         if (IS_ERR(handler)) {
3705                 err = PTR_ERR(handler);
3706                 handler = NULL;
3707                 goto destroy_ft;
3708         }
3709
3710         mutex_unlock(&dev->flow_db->lock);
3711         kfree(dst);
3712         kfree(ucmd);
3713
3714         return &handler->ibflow;
3715
3716 destroy_ft:
3717         put_flow_table(dev, ft_prio, false);
3718         if (ft_prio_tx)
3719                 put_flow_table(dev, ft_prio_tx, false);
3720 unlock:
3721         mutex_unlock(&dev->flow_db->lock);
3722         kfree(dst);
3723 free_ucmd:
3724         kfree(ucmd);
3725         return ERR_PTR(err);
3726 }
3727
3728 static struct mlx5_ib_flow_prio *
3729 _get_flow_table(struct mlx5_ib_dev *dev,
3730                 struct mlx5_ib_flow_matcher *fs_matcher,
3731                 bool mcast)
3732 {
3733         struct mlx5_flow_namespace *ns = NULL;
3734         struct mlx5_ib_flow_prio *prio;
3735         int max_table_size;
3736         u32 flags = 0;
3737         int priority;
3738
3739         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3740                 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3741                                         log_max_ft_size));
3742                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3743                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3744                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3745                                               reformat_l3_tunnel_to_l2))
3746                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3747         } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */
3748                 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3749                                         log_max_ft_size));
3750                 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3751                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3752         }
3753
3754         if (max_table_size < MLX5_FS_MAX_ENTRIES)
3755                 return ERR_PTR(-ENOMEM);
3756
3757         if (mcast)
3758                 priority = MLX5_IB_FLOW_MCAST_PRIO;
3759         else
3760                 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3761
3762         ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
3763         if (!ns)
3764                 return ERR_PTR(-ENOTSUPP);
3765
3766         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3767                 prio = &dev->flow_db->prios[priority];
3768         else
3769                 prio = &dev->flow_db->egress_prios[priority];
3770
3771         if (prio->flow_table)
3772                 return prio;
3773
3774         return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
3775                          MLX5_FS_MAX_TYPES, flags);
3776 }
3777
3778 static struct mlx5_ib_flow_handler *
3779 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
3780                       struct mlx5_ib_flow_prio *ft_prio,
3781                       struct mlx5_flow_destination *dst,
3782                       struct mlx5_ib_flow_matcher  *fs_matcher,
3783                       struct mlx5_flow_act *flow_act,
3784                       void *cmd_in, int inlen,
3785                       int dst_num)
3786 {
3787         struct mlx5_ib_flow_handler *handler;
3788         struct mlx5_flow_spec *spec;
3789         struct mlx5_flow_table *ft = ft_prio->flow_table;
3790         int err = 0;
3791
3792         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3793         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3794         if (!handler || !spec) {
3795                 err = -ENOMEM;
3796                 goto free;
3797         }
3798
3799         INIT_LIST_HEAD(&handler->list);
3800
3801         memcpy(spec->match_value, cmd_in, inlen);
3802         memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3803                fs_matcher->mask_len);
3804         spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3805
3806         handler->rule = mlx5_add_flow_rules(ft, spec,
3807                                             flow_act, dst, dst_num);
3808
3809         if (IS_ERR(handler->rule)) {
3810                 err = PTR_ERR(handler->rule);
3811                 goto free;
3812         }
3813
3814         ft_prio->refcount++;
3815         handler->prio = ft_prio;
3816         handler->dev = dev;
3817         ft_prio->flow_table = ft;
3818
3819 free:
3820         if (err)
3821                 kfree(handler);
3822         kvfree(spec);
3823         return err ? ERR_PTR(err) : handler;
3824 }
3825
3826 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3827                                 void *match_v)
3828 {
3829         void *match_c;
3830         void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3831         void *dmac, *dmac_mask;
3832         void *ipv4, *ipv4_mask;
3833
3834         if (!(fs_matcher->match_criteria_enable &
3835               (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3836                 return false;
3837
3838         match_c = fs_matcher->matcher_mask.match_params;
3839         match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3840                                            outer_headers);
3841         match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3842                                            outer_headers);
3843
3844         dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3845                             dmac_47_16);
3846         dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3847                                  dmac_47_16);
3848
3849         if (is_multicast_ether_addr(dmac) &&
3850             is_multicast_ether_addr(dmac_mask))
3851                 return true;
3852
3853         ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3854                             dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3855
3856         ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3857                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3858
3859         if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3860             ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3861                 return true;
3862
3863         return false;
3864 }
3865
3866 struct mlx5_ib_flow_handler *
3867 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3868                         struct mlx5_ib_flow_matcher *fs_matcher,
3869                         struct mlx5_flow_act *flow_act,
3870                         u32 counter_id,
3871                         void *cmd_in, int inlen, int dest_id,
3872                         int dest_type)
3873 {
3874         struct mlx5_flow_destination *dst;
3875         struct mlx5_ib_flow_prio *ft_prio;
3876         struct mlx5_ib_flow_handler *handler;
3877         int dst_num = 0;
3878         bool mcast;
3879         int err;
3880
3881         if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3882                 return ERR_PTR(-EOPNOTSUPP);
3883
3884         if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3885                 return ERR_PTR(-ENOMEM);
3886
3887         dst = kzalloc(sizeof(*dst) * 2, GFP_KERNEL);
3888         if (!dst)
3889                 return ERR_PTR(-ENOMEM);
3890
3891         mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3892         mutex_lock(&dev->flow_db->lock);
3893
3894         ft_prio = _get_flow_table(dev, fs_matcher, mcast);
3895         if (IS_ERR(ft_prio)) {
3896                 err = PTR_ERR(ft_prio);
3897                 goto unlock;
3898         }
3899
3900         if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
3901                 dst[dst_num].type = dest_type;
3902                 dst[dst_num].tir_num = dest_id;
3903                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3904         } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
3905                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3906                 dst[dst_num].ft_num = dest_id;
3907                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3908         } else {
3909                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3910                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3911         }
3912
3913         dst_num++;
3914
3915         if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3916                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3917                 dst[dst_num].counter_id = counter_id;
3918                 dst_num++;
3919         }
3920
3921         handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act,
3922                                         cmd_in, inlen, dst_num);
3923
3924         if (IS_ERR(handler)) {
3925                 err = PTR_ERR(handler);
3926                 goto destroy_ft;
3927         }
3928
3929         mutex_unlock(&dev->flow_db->lock);
3930         atomic_inc(&fs_matcher->usecnt);
3931         handler->flow_matcher = fs_matcher;
3932
3933         kfree(dst);
3934
3935         return handler;
3936
3937 destroy_ft:
3938         put_flow_table(dev, ft_prio, false);
3939 unlock:
3940         mutex_unlock(&dev->flow_db->lock);
3941         kfree(dst);
3942
3943         return ERR_PTR(err);
3944 }
3945
3946 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3947 {
3948         u32 flags = 0;
3949
3950         if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3951                 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3952
3953         return flags;
3954 }
3955
3956 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED      MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3957 static struct ib_flow_action *
3958 mlx5_ib_create_flow_action_esp(struct ib_device *device,
3959                                const struct ib_flow_action_attrs_esp *attr,
3960                                struct uverbs_attr_bundle *attrs)
3961 {
3962         struct mlx5_ib_dev *mdev = to_mdev(device);
3963         struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3964         struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3965         struct mlx5_ib_flow_action *action;
3966         u64 action_flags;
3967         u64 flags;
3968         int err = 0;
3969
3970         err = uverbs_get_flags64(
3971                 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3972                 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3973         if (err)
3974                 return ERR_PTR(err);
3975
3976         flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3977
3978         /* We current only support a subset of the standard features. Only a
3979          * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3980          * (with overlap). Full offload mode isn't supported.
3981          */
3982         if (!attr->keymat || attr->replay || attr->encap ||
3983             attr->spi || attr->seq || attr->tfc_pad ||
3984             attr->hard_limit_pkts ||
3985             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3986                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3987                 return ERR_PTR(-EOPNOTSUPP);
3988
3989         if (attr->keymat->protocol !=
3990             IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3991                 return ERR_PTR(-EOPNOTSUPP);
3992
3993         aes_gcm = &attr->keymat->keymat.aes_gcm;
3994
3995         if (aes_gcm->icv_len != 16 ||
3996             aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3997                 return ERR_PTR(-EOPNOTSUPP);
3998
3999         action = kmalloc(sizeof(*action), GFP_KERNEL);
4000         if (!action)
4001                 return ERR_PTR(-ENOMEM);
4002
4003         action->esp_aes_gcm.ib_flags = attr->flags;
4004         memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4005                sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4006         accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4007         memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4008                sizeof(accel_attrs.keymat.aes_gcm.salt));
4009         memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4010                sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4011         accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4012         accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4013         accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4014
4015         accel_attrs.esn = attr->esn;
4016         if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4017                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4018         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4019                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4020
4021         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4022                 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4023
4024         action->esp_aes_gcm.ctx =
4025                 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4026         if (IS_ERR(action->esp_aes_gcm.ctx)) {
4027                 err = PTR_ERR(action->esp_aes_gcm.ctx);
4028                 goto err_parse;
4029         }
4030
4031         action->esp_aes_gcm.ib_flags = attr->flags;
4032
4033         return &action->ib_action;
4034
4035 err_parse:
4036         kfree(action);
4037         return ERR_PTR(err);
4038 }
4039
4040 static int
4041 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4042                                const struct ib_flow_action_attrs_esp *attr,
4043                                struct uverbs_attr_bundle *attrs)
4044 {
4045         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4046         struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4047         int err = 0;
4048
4049         if (attr->keymat || attr->replay || attr->encap ||
4050             attr->spi || attr->seq || attr->tfc_pad ||
4051             attr->hard_limit_pkts ||
4052             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4053                              IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4054                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4055                 return -EOPNOTSUPP;
4056
4057         /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4058          * be modified.
4059          */
4060         if (!(maction->esp_aes_gcm.ib_flags &
4061               IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4062             attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4063                            IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4064                 return -EINVAL;
4065
4066         memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4067                sizeof(accel_attrs));
4068
4069         accel_attrs.esn = attr->esn;
4070         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4071                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4072         else
4073                 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4074
4075         err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4076                                          &accel_attrs);
4077         if (err)
4078                 return err;
4079
4080         maction->esp_aes_gcm.ib_flags &=
4081                 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4082         maction->esp_aes_gcm.ib_flags |=
4083                 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4084
4085         return 0;
4086 }
4087
4088 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4089 {
4090         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4091
4092         switch (action->type) {
4093         case IB_FLOW_ACTION_ESP:
4094                 /*
4095                  * We only support aes_gcm by now, so we implicitly know this is
4096                  * the underline crypto.
4097                  */
4098                 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4099                 break;
4100         case IB_FLOW_ACTION_UNSPECIFIED:
4101                 mlx5_ib_destroy_flow_action_raw(maction);
4102                 break;
4103         default:
4104                 WARN_ON(true);
4105                 break;
4106         }
4107
4108         kfree(maction);
4109         return 0;
4110 }
4111
4112 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4113 {
4114         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4115         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4116         int err;
4117         u16 uid;
4118
4119         uid = ibqp->pd ?
4120                 to_mpd(ibqp->pd)->uid : 0;
4121
4122         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4123                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4124                 return -EOPNOTSUPP;
4125         }
4126
4127         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4128         if (err)
4129                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4130                              ibqp->qp_num, gid->raw);
4131
4132         return err;
4133 }
4134
4135 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4136 {
4137         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4138         int err;
4139         u16 uid;
4140
4141         uid = ibqp->pd ?
4142                 to_mpd(ibqp->pd)->uid : 0;
4143         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4144         if (err)
4145                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4146                              ibqp->qp_num, gid->raw);
4147
4148         return err;
4149 }
4150
4151 static int init_node_data(struct mlx5_ib_dev *dev)
4152 {
4153         int err;
4154
4155         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4156         if (err)
4157                 return err;
4158
4159         dev->mdev->rev_id = dev->mdev->pdev->revision;
4160
4161         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4162 }
4163
4164 static ssize_t fw_pages_show(struct device *device,
4165                              struct device_attribute *attr, char *buf)
4166 {
4167         struct mlx5_ib_dev *dev =
4168                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4169
4170         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4171 }
4172 static DEVICE_ATTR_RO(fw_pages);
4173
4174 static ssize_t reg_pages_show(struct device *device,
4175                               struct device_attribute *attr, char *buf)
4176 {
4177         struct mlx5_ib_dev *dev =
4178                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4179
4180         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4181 }
4182 static DEVICE_ATTR_RO(reg_pages);
4183
4184 static ssize_t hca_type_show(struct device *device,
4185                              struct device_attribute *attr, char *buf)
4186 {
4187         struct mlx5_ib_dev *dev =
4188                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4189         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4190 }
4191 static DEVICE_ATTR_RO(hca_type);
4192
4193 static ssize_t hw_rev_show(struct device *device,
4194                            struct device_attribute *attr, char *buf)
4195 {
4196         struct mlx5_ib_dev *dev =
4197                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4198         return sprintf(buf, "%x\n", dev->mdev->rev_id);
4199 }
4200 static DEVICE_ATTR_RO(hw_rev);
4201
4202 static ssize_t board_id_show(struct device *device,
4203                              struct device_attribute *attr, char *buf)
4204 {
4205         struct mlx5_ib_dev *dev =
4206                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4207         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4208                        dev->mdev->board_id);
4209 }
4210 static DEVICE_ATTR_RO(board_id);
4211
4212 static struct attribute *mlx5_class_attributes[] = {
4213         &dev_attr_hw_rev.attr,
4214         &dev_attr_hca_type.attr,
4215         &dev_attr_board_id.attr,
4216         &dev_attr_fw_pages.attr,
4217         &dev_attr_reg_pages.attr,
4218         NULL,
4219 };
4220
4221 static const struct attribute_group mlx5_attr_group = {
4222         .attrs = mlx5_class_attributes,
4223 };
4224
4225 static void pkey_change_handler(struct work_struct *work)
4226 {
4227         struct mlx5_ib_port_resources *ports =
4228                 container_of(work, struct mlx5_ib_port_resources,
4229                              pkey_change_work);
4230
4231         mutex_lock(&ports->devr->mutex);
4232         mlx5_ib_gsi_pkey_change(ports->gsi);
4233         mutex_unlock(&ports->devr->mutex);
4234 }
4235
4236 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4237 {
4238         struct mlx5_ib_qp *mqp;
4239         struct mlx5_ib_cq *send_mcq, *recv_mcq;
4240         struct mlx5_core_cq *mcq;
4241         struct list_head cq_armed_list;
4242         unsigned long flags_qp;
4243         unsigned long flags_cq;
4244         unsigned long flags;
4245
4246         INIT_LIST_HEAD(&cq_armed_list);
4247
4248         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4249         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4250         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4251                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4252                 if (mqp->sq.tail != mqp->sq.head) {
4253                         send_mcq = to_mcq(mqp->ibqp.send_cq);
4254                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
4255                         if (send_mcq->mcq.comp &&
4256                             mqp->ibqp.send_cq->comp_handler) {
4257                                 if (!send_mcq->mcq.reset_notify_added) {
4258                                         send_mcq->mcq.reset_notify_added = 1;
4259                                         list_add_tail(&send_mcq->mcq.reset_notify,
4260                                                       &cq_armed_list);
4261                                 }
4262                         }
4263                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4264                 }
4265                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4266                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4267                 /* no handling is needed for SRQ */
4268                 if (!mqp->ibqp.srq) {
4269                         if (mqp->rq.tail != mqp->rq.head) {
4270                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4271                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4272                                 if (recv_mcq->mcq.comp &&
4273                                     mqp->ibqp.recv_cq->comp_handler) {
4274                                         if (!recv_mcq->mcq.reset_notify_added) {
4275                                                 recv_mcq->mcq.reset_notify_added = 1;
4276                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
4277                                                               &cq_armed_list);
4278                                         }
4279                                 }
4280                                 spin_unlock_irqrestore(&recv_mcq->lock,
4281                                                        flags_cq);
4282                         }
4283                 }
4284                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4285         }
4286         /*At that point all inflight post send were put to be executed as of we
4287          * lock/unlock above locks Now need to arm all involved CQs.
4288          */
4289         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4290                 mcq->comp(mcq);
4291         }
4292         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4293 }
4294
4295 static void delay_drop_handler(struct work_struct *work)
4296 {
4297         int err;
4298         struct mlx5_ib_delay_drop *delay_drop =
4299                 container_of(work, struct mlx5_ib_delay_drop,
4300                              delay_drop_work);
4301
4302         atomic_inc(&delay_drop->events_cnt);
4303
4304         mutex_lock(&delay_drop->lock);
4305         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4306                                        delay_drop->timeout);
4307         if (err) {
4308                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4309                              delay_drop->timeout);
4310                 delay_drop->activate = false;
4311         }
4312         mutex_unlock(&delay_drop->lock);
4313 }
4314
4315 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4316                                  struct ib_event *ibev)
4317 {
4318         switch (eqe->sub_type) {
4319         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
4320                 schedule_work(&ibdev->delay_drop.delay_drop_work);
4321                 break;
4322         default: /* do nothing */
4323                 return;
4324         }
4325 }
4326
4327 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4328                               struct ib_event *ibev)
4329 {
4330         u8 port = (eqe->data.port.port >> 4) & 0xf;
4331
4332         ibev->element.port_num = port;
4333
4334         switch (eqe->sub_type) {
4335         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4336         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4337         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4338                 /* In RoCE, port up/down events are handled in
4339                  * mlx5_netdev_event().
4340                  */
4341                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4342                                             IB_LINK_LAYER_ETHERNET)
4343                         return -EINVAL;
4344
4345                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4346                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4347                 break;
4348
4349         case MLX5_PORT_CHANGE_SUBTYPE_LID:
4350                 ibev->event = IB_EVENT_LID_CHANGE;
4351                 break;
4352
4353         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4354                 ibev->event = IB_EVENT_PKEY_CHANGE;
4355                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4356                 break;
4357
4358         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4359                 ibev->event = IB_EVENT_GID_CHANGE;
4360                 break;
4361
4362         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4363                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4364                 break;
4365         default:
4366                 return -EINVAL;
4367         }
4368
4369         return 0;
4370 }
4371
4372 static void mlx5_ib_handle_event(struct work_struct *_work)
4373 {
4374         struct mlx5_ib_event_work *work =
4375                 container_of(_work, struct mlx5_ib_event_work, work);
4376         struct mlx5_ib_dev *ibdev;
4377         struct ib_event ibev;
4378         bool fatal = false;
4379
4380         if (work->is_slave) {
4381                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
4382                 if (!ibdev)
4383                         goto out;
4384         } else {
4385                 ibdev = work->dev;
4386         }
4387
4388         switch (work->event) {
4389         case MLX5_DEV_EVENT_SYS_ERROR:
4390                 ibev.event = IB_EVENT_DEVICE_FATAL;
4391                 mlx5_ib_handle_internal_error(ibdev);
4392                 ibev.element.port_num  = (u8)(unsigned long)work->param;
4393                 fatal = true;
4394                 break;
4395         case MLX5_EVENT_TYPE_PORT_CHANGE:
4396                 if (handle_port_change(ibdev, work->param, &ibev))
4397                         goto out;
4398                 break;
4399         case MLX5_EVENT_TYPE_GENERAL_EVENT:
4400                 handle_general_event(ibdev, work->param, &ibev);
4401                 /* fall through */
4402         default:
4403                 goto out;
4404         }
4405
4406         ibev.device = &ibdev->ib_dev;
4407
4408         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4409                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
4410                 goto out;
4411         }
4412
4413         if (ibdev->ib_active)
4414                 ib_dispatch_event(&ibev);
4415
4416         if (fatal)
4417                 ibdev->ib_active = false;
4418 out:
4419         kfree(work);
4420 }
4421
4422 static int mlx5_ib_event(struct notifier_block *nb,
4423                          unsigned long event, void *param)
4424 {
4425         struct mlx5_ib_event_work *work;
4426
4427         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4428         if (!work)
4429                 return NOTIFY_DONE;
4430
4431         INIT_WORK(&work->work, mlx5_ib_handle_event);
4432         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4433         work->is_slave = false;
4434         work->param = param;
4435         work->event = event;
4436
4437         queue_work(mlx5_ib_event_wq, &work->work);
4438
4439         return NOTIFY_OK;
4440 }
4441
4442 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4443                                     unsigned long event, void *param)
4444 {
4445         struct mlx5_ib_event_work *work;
4446
4447         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4448         if (!work)
4449                 return NOTIFY_DONE;
4450
4451         INIT_WORK(&work->work, mlx5_ib_handle_event);
4452         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4453         work->is_slave = true;
4454         work->param = param;
4455         work->event = event;
4456         queue_work(mlx5_ib_event_wq, &work->work);
4457
4458         return NOTIFY_OK;
4459 }
4460
4461 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4462 {
4463         struct mlx5_hca_vport_context vport_ctx;
4464         int err;
4465         int port;
4466
4467         for (port = 1; port <= dev->num_ports; port++) {
4468                 dev->mdev->port_caps[port - 1].has_smi = false;
4469                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4470                     MLX5_CAP_PORT_TYPE_IB) {
4471                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4472                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4473                                                                    port, 0,
4474                                                                    &vport_ctx);
4475                                 if (err) {
4476                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4477                                                     port, err);
4478                                         return err;
4479                                 }
4480                                 dev->mdev->port_caps[port - 1].has_smi =
4481                                         vport_ctx.has_smi;
4482                         } else {
4483                                 dev->mdev->port_caps[port - 1].has_smi = true;
4484                         }
4485                 }
4486         }
4487         return 0;
4488 }
4489
4490 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4491 {
4492         int port;
4493
4494         for (port = 1; port <= dev->num_ports; port++)
4495                 mlx5_query_ext_port_caps(dev, port);
4496 }
4497
4498 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4499 {
4500         struct ib_device_attr *dprops = NULL;
4501         struct ib_port_attr *pprops = NULL;
4502         int err = -ENOMEM;
4503         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4504
4505         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4506         if (!pprops)
4507                 goto out;
4508
4509         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4510         if (!dprops)
4511                 goto out;
4512
4513         err = set_has_smi_cap(dev);
4514         if (err)
4515                 goto out;
4516
4517         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4518         if (err) {
4519                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4520                 goto out;
4521         }
4522
4523         memset(pprops, 0, sizeof(*pprops));
4524         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4525         if (err) {
4526                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4527                              port, err);
4528                 goto out;
4529         }
4530
4531         dev->mdev->port_caps[port - 1].pkey_table_len =
4532                                         dprops->max_pkeys;
4533         dev->mdev->port_caps[port - 1].gid_table_len =
4534                                         pprops->gid_tbl_len;
4535         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4536                     port, dprops->max_pkeys, pprops->gid_tbl_len);
4537
4538 out:
4539         kfree(pprops);
4540         kfree(dprops);
4541
4542         return err;
4543 }
4544
4545 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4546 {
4547         int err;
4548
4549         err = mlx5_mr_cache_cleanup(dev);
4550         if (err)
4551                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4552
4553         if (dev->umrc.qp)
4554                 mlx5_ib_destroy_qp(dev->umrc.qp);
4555         if (dev->umrc.cq)
4556                 ib_free_cq(dev->umrc.cq);
4557         if (dev->umrc.pd)
4558                 ib_dealloc_pd(dev->umrc.pd);
4559 }
4560
4561 enum {
4562         MAX_UMR_WR = 128,
4563 };
4564
4565 static int create_umr_res(struct mlx5_ib_dev *dev)
4566 {
4567         struct ib_qp_init_attr *init_attr = NULL;
4568         struct ib_qp_attr *attr = NULL;
4569         struct ib_pd *pd;
4570         struct ib_cq *cq;
4571         struct ib_qp *qp;
4572         int ret;
4573
4574         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4575         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4576         if (!attr || !init_attr) {
4577                 ret = -ENOMEM;
4578                 goto error_0;
4579         }
4580
4581         pd = ib_alloc_pd(&dev->ib_dev, 0);
4582         if (IS_ERR(pd)) {
4583                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4584                 ret = PTR_ERR(pd);
4585                 goto error_0;
4586         }
4587
4588         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4589         if (IS_ERR(cq)) {
4590                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4591                 ret = PTR_ERR(cq);
4592                 goto error_2;
4593         }
4594
4595         init_attr->send_cq = cq;
4596         init_attr->recv_cq = cq;
4597         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4598         init_attr->cap.max_send_wr = MAX_UMR_WR;
4599         init_attr->cap.max_send_sge = 1;
4600         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4601         init_attr->port_num = 1;
4602         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4603         if (IS_ERR(qp)) {
4604                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4605                 ret = PTR_ERR(qp);
4606                 goto error_3;
4607         }
4608         qp->device     = &dev->ib_dev;
4609         qp->real_qp    = qp;
4610         qp->uobject    = NULL;
4611         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4612         qp->send_cq    = init_attr->send_cq;
4613         qp->recv_cq    = init_attr->recv_cq;
4614
4615         attr->qp_state = IB_QPS_INIT;
4616         attr->port_num = 1;
4617         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4618                                 IB_QP_PORT, NULL);
4619         if (ret) {
4620                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4621                 goto error_4;
4622         }
4623
4624         memset(attr, 0, sizeof(*attr));
4625         attr->qp_state = IB_QPS_RTR;
4626         attr->path_mtu = IB_MTU_256;
4627
4628         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4629         if (ret) {
4630                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4631                 goto error_4;
4632         }
4633
4634         memset(attr, 0, sizeof(*attr));
4635         attr->qp_state = IB_QPS_RTS;
4636         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4637         if (ret) {
4638                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4639                 goto error_4;
4640         }
4641
4642         dev->umrc.qp = qp;
4643         dev->umrc.cq = cq;
4644         dev->umrc.pd = pd;
4645
4646         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4647         ret = mlx5_mr_cache_init(dev);
4648         if (ret) {
4649                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4650                 goto error_4;
4651         }
4652
4653         kfree(attr);
4654         kfree(init_attr);
4655
4656         return 0;
4657
4658 error_4:
4659         mlx5_ib_destroy_qp(qp);
4660         dev->umrc.qp = NULL;
4661
4662 error_3:
4663         ib_free_cq(cq);
4664         dev->umrc.cq = NULL;
4665
4666 error_2:
4667         ib_dealloc_pd(pd);
4668         dev->umrc.pd = NULL;
4669
4670 error_0:
4671         kfree(attr);
4672         kfree(init_attr);
4673         return ret;
4674 }
4675
4676 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4677 {
4678         switch (umr_fence_cap) {
4679         case MLX5_CAP_UMR_FENCE_NONE:
4680                 return MLX5_FENCE_MODE_NONE;
4681         case MLX5_CAP_UMR_FENCE_SMALL:
4682                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4683         default:
4684                 return MLX5_FENCE_MODE_STRONG_ORDERING;
4685         }
4686 }
4687
4688 static int create_dev_resources(struct mlx5_ib_resources *devr)
4689 {
4690         struct ib_srq_init_attr attr;
4691         struct mlx5_ib_dev *dev;
4692         struct ib_cq_init_attr cq_attr = {.cqe = 1};
4693         int port;
4694         int ret = 0;
4695
4696         dev = container_of(devr, struct mlx5_ib_dev, devr);
4697
4698         mutex_init(&devr->mutex);
4699
4700         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4701         if (IS_ERR(devr->p0)) {
4702                 ret = PTR_ERR(devr->p0);
4703                 goto error0;
4704         }
4705         devr->p0->device  = &dev->ib_dev;
4706         devr->p0->uobject = NULL;
4707         atomic_set(&devr->p0->usecnt, 0);
4708
4709         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4710         if (IS_ERR(devr->c0)) {
4711                 ret = PTR_ERR(devr->c0);
4712                 goto error1;
4713         }
4714         devr->c0->device        = &dev->ib_dev;
4715         devr->c0->uobject       = NULL;
4716         devr->c0->comp_handler  = NULL;
4717         devr->c0->event_handler = NULL;
4718         devr->c0->cq_context    = NULL;
4719         atomic_set(&devr->c0->usecnt, 0);
4720
4721         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4722         if (IS_ERR(devr->x0)) {
4723                 ret = PTR_ERR(devr->x0);
4724                 goto error2;
4725         }
4726         devr->x0->device = &dev->ib_dev;
4727         devr->x0->inode = NULL;
4728         atomic_set(&devr->x0->usecnt, 0);
4729         mutex_init(&devr->x0->tgt_qp_mutex);
4730         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4731
4732         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4733         if (IS_ERR(devr->x1)) {
4734                 ret = PTR_ERR(devr->x1);
4735                 goto error3;
4736         }
4737         devr->x1->device = &dev->ib_dev;
4738         devr->x1->inode = NULL;
4739         atomic_set(&devr->x1->usecnt, 0);
4740         mutex_init(&devr->x1->tgt_qp_mutex);
4741         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4742
4743         memset(&attr, 0, sizeof(attr));
4744         attr.attr.max_sge = 1;
4745         attr.attr.max_wr = 1;
4746         attr.srq_type = IB_SRQT_XRC;
4747         attr.ext.cq = devr->c0;
4748         attr.ext.xrc.xrcd = devr->x0;
4749
4750         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4751         if (IS_ERR(devr->s0)) {
4752                 ret = PTR_ERR(devr->s0);
4753                 goto error4;
4754         }
4755         devr->s0->device        = &dev->ib_dev;
4756         devr->s0->pd            = devr->p0;
4757         devr->s0->uobject       = NULL;
4758         devr->s0->event_handler = NULL;
4759         devr->s0->srq_context   = NULL;
4760         devr->s0->srq_type      = IB_SRQT_XRC;
4761         devr->s0->ext.xrc.xrcd  = devr->x0;
4762         devr->s0->ext.cq        = devr->c0;
4763         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4764         atomic_inc(&devr->s0->ext.cq->usecnt);
4765         atomic_inc(&devr->p0->usecnt);
4766         atomic_set(&devr->s0->usecnt, 0);
4767
4768         memset(&attr, 0, sizeof(attr));
4769         attr.attr.max_sge = 1;
4770         attr.attr.max_wr = 1;
4771         attr.srq_type = IB_SRQT_BASIC;
4772         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4773         if (IS_ERR(devr->s1)) {
4774                 ret = PTR_ERR(devr->s1);
4775                 goto error5;
4776         }
4777         devr->s1->device        = &dev->ib_dev;
4778         devr->s1->pd            = devr->p0;
4779         devr->s1->uobject       = NULL;
4780         devr->s1->event_handler = NULL;
4781         devr->s1->srq_context   = NULL;
4782         devr->s1->srq_type      = IB_SRQT_BASIC;
4783         devr->s1->ext.cq        = devr->c0;
4784         atomic_inc(&devr->p0->usecnt);
4785         atomic_set(&devr->s1->usecnt, 0);
4786
4787         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4788                 INIT_WORK(&devr->ports[port].pkey_change_work,
4789                           pkey_change_handler);
4790                 devr->ports[port].devr = devr;
4791         }
4792
4793         return 0;
4794
4795 error5:
4796         mlx5_ib_destroy_srq(devr->s0);
4797 error4:
4798         mlx5_ib_dealloc_xrcd(devr->x1);
4799 error3:
4800         mlx5_ib_dealloc_xrcd(devr->x0);
4801 error2:
4802         mlx5_ib_destroy_cq(devr->c0);
4803 error1:
4804         mlx5_ib_dealloc_pd(devr->p0);
4805 error0:
4806         return ret;
4807 }
4808
4809 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4810 {
4811         struct mlx5_ib_dev *dev =
4812                 container_of(devr, struct mlx5_ib_dev, devr);
4813         int port;
4814
4815         mlx5_ib_destroy_srq(devr->s1);
4816         mlx5_ib_destroy_srq(devr->s0);
4817         mlx5_ib_dealloc_xrcd(devr->x0);
4818         mlx5_ib_dealloc_xrcd(devr->x1);
4819         mlx5_ib_destroy_cq(devr->c0);
4820         mlx5_ib_dealloc_pd(devr->p0);
4821
4822         /* Make sure no change P_Key work items are still executing */
4823         for (port = 0; port < dev->num_ports; ++port)
4824                 cancel_work_sync(&devr->ports[port].pkey_change_work);
4825 }
4826
4827 static u32 get_core_cap_flags(struct ib_device *ibdev,
4828                               struct mlx5_hca_vport_context *rep)
4829 {
4830         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4831         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4832         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4833         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4834         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4835         u32 ret = 0;
4836
4837         if (rep->grh_required)
4838                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4839
4840         if (ll == IB_LINK_LAYER_INFINIBAND)
4841                 return ret | RDMA_CORE_PORT_IBA_IB;
4842
4843         if (raw_support)
4844                 ret |= RDMA_CORE_PORT_RAW_PACKET;
4845
4846         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4847                 return ret;
4848
4849         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4850                 return ret;
4851
4852         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4853                 ret |= RDMA_CORE_PORT_IBA_ROCE;
4854
4855         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4856                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4857
4858         return ret;
4859 }
4860
4861 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4862                                struct ib_port_immutable *immutable)
4863 {
4864         struct ib_port_attr attr;
4865         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4866         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4867         struct mlx5_hca_vport_context rep = {0};
4868         int err;
4869
4870         err = ib_query_port(ibdev, port_num, &attr);
4871         if (err)
4872                 return err;
4873
4874         if (ll == IB_LINK_LAYER_INFINIBAND) {
4875                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4876                                                    &rep);
4877                 if (err)
4878                         return err;
4879         }
4880
4881         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4882         immutable->gid_tbl_len = attr.gid_tbl_len;
4883         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
4884         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4885                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4886
4887         return 0;
4888 }
4889
4890 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4891                                    struct ib_port_immutable *immutable)
4892 {
4893         struct ib_port_attr attr;
4894         int err;
4895
4896         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4897
4898         err = ib_query_port(ibdev, port_num, &attr);
4899         if (err)
4900                 return err;
4901
4902         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4903         immutable->gid_tbl_len = attr.gid_tbl_len;
4904         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4905
4906         return 0;
4907 }
4908
4909 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4910 {
4911         struct mlx5_ib_dev *dev =
4912                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4913         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4914                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4915                  fw_rev_sub(dev->mdev));
4916 }
4917
4918 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4919 {
4920         struct mlx5_core_dev *mdev = dev->mdev;
4921         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4922                                                                  MLX5_FLOW_NAMESPACE_LAG);
4923         struct mlx5_flow_table *ft;
4924         int err;
4925
4926         if (!ns || !mlx5_lag_is_roce(mdev))
4927                 return 0;
4928
4929         err = mlx5_cmd_create_vport_lag(mdev);
4930         if (err)
4931                 return err;
4932
4933         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4934         if (IS_ERR(ft)) {
4935                 err = PTR_ERR(ft);
4936                 goto err_destroy_vport_lag;
4937         }
4938
4939         dev->flow_db->lag_demux_ft = ft;
4940         dev->lag_active = true;
4941         return 0;
4942
4943 err_destroy_vport_lag:
4944         mlx5_cmd_destroy_vport_lag(mdev);
4945         return err;
4946 }
4947
4948 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4949 {
4950         struct mlx5_core_dev *mdev = dev->mdev;
4951
4952         if (dev->lag_active) {
4953                 dev->lag_active = false;
4954
4955                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4956                 dev->flow_db->lag_demux_ft = NULL;
4957
4958                 mlx5_cmd_destroy_vport_lag(mdev);
4959         }
4960 }
4961
4962 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4963 {
4964         int err;
4965
4966         dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4967         err = register_netdevice_notifier(&dev->roce[port_num].nb);
4968         if (err) {
4969                 dev->roce[port_num].nb.notifier_call = NULL;
4970                 return err;
4971         }
4972
4973         return 0;
4974 }
4975
4976 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4977 {
4978         if (dev->roce[port_num].nb.notifier_call) {
4979                 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4980                 dev->roce[port_num].nb.notifier_call = NULL;
4981         }
4982 }
4983
4984 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
4985 {
4986         int err;
4987
4988         if (MLX5_CAP_GEN(dev->mdev, roce)) {
4989                 err = mlx5_nic_vport_enable_roce(dev->mdev);
4990                 if (err)
4991                         return err;
4992         }
4993
4994         err = mlx5_eth_lag_init(dev);
4995         if (err)
4996                 goto err_disable_roce;
4997
4998         return 0;
4999
5000 err_disable_roce:
5001         if (MLX5_CAP_GEN(dev->mdev, roce))
5002                 mlx5_nic_vport_disable_roce(dev->mdev);
5003
5004         return err;
5005 }
5006
5007 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
5008 {
5009         mlx5_eth_lag_cleanup(dev);
5010         if (MLX5_CAP_GEN(dev->mdev, roce))
5011                 mlx5_nic_vport_disable_roce(dev->mdev);
5012 }
5013
5014 struct mlx5_ib_counter {
5015         const char *name;
5016         size_t offset;
5017 };
5018
5019 #define INIT_Q_COUNTER(_name)           \
5020         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5021
5022 static const struct mlx5_ib_counter basic_q_cnts[] = {
5023         INIT_Q_COUNTER(rx_write_requests),
5024         INIT_Q_COUNTER(rx_read_requests),
5025         INIT_Q_COUNTER(rx_atomic_requests),
5026         INIT_Q_COUNTER(out_of_buffer),
5027 };
5028
5029 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
5030         INIT_Q_COUNTER(out_of_sequence),
5031 };
5032
5033 static const struct mlx5_ib_counter retrans_q_cnts[] = {
5034         INIT_Q_COUNTER(duplicate_request),
5035         INIT_Q_COUNTER(rnr_nak_retry_err),
5036         INIT_Q_COUNTER(packet_seq_err),
5037         INIT_Q_COUNTER(implied_nak_seq_err),
5038         INIT_Q_COUNTER(local_ack_timeout_err),
5039 };
5040
5041 #define INIT_CONG_COUNTER(_name)                \
5042         { .name = #_name, .offset =     \
5043                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5044
5045 static const struct mlx5_ib_counter cong_cnts[] = {
5046         INIT_CONG_COUNTER(rp_cnp_ignored),
5047         INIT_CONG_COUNTER(rp_cnp_handled),
5048         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5049         INIT_CONG_COUNTER(np_cnp_sent),
5050 };
5051
5052 static const struct mlx5_ib_counter extended_err_cnts[] = {
5053         INIT_Q_COUNTER(resp_local_length_error),
5054         INIT_Q_COUNTER(resp_cqe_error),
5055         INIT_Q_COUNTER(req_cqe_error),
5056         INIT_Q_COUNTER(req_remote_invalid_request),
5057         INIT_Q_COUNTER(req_remote_access_errors),
5058         INIT_Q_COUNTER(resp_remote_access_errors),
5059         INIT_Q_COUNTER(resp_cqe_flush_error),
5060         INIT_Q_COUNTER(req_cqe_flush_error),
5061 };
5062
5063 #define INIT_EXT_PPCNT_COUNTER(_name)           \
5064         { .name = #_name, .offset =     \
5065         MLX5_BYTE_OFF(ppcnt_reg, \
5066                       counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5067
5068 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5069         INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5070 };
5071
5072 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
5073 {
5074         int i;
5075
5076         for (i = 0; i < dev->num_ports; i++) {
5077                 if (dev->port[i].cnts.set_id_valid)
5078                         mlx5_core_dealloc_q_counter(dev->mdev,
5079                                                     dev->port[i].cnts.set_id);
5080                 kfree(dev->port[i].cnts.names);
5081                 kfree(dev->port[i].cnts.offsets);
5082         }
5083 }
5084
5085 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5086                                     struct mlx5_ib_counters *cnts)
5087 {
5088         u32 num_counters;
5089
5090         num_counters = ARRAY_SIZE(basic_q_cnts);
5091
5092         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5093                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5094
5095         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5096                 num_counters += ARRAY_SIZE(retrans_q_cnts);
5097
5098         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5099                 num_counters += ARRAY_SIZE(extended_err_cnts);
5100
5101         cnts->num_q_counters = num_counters;
5102
5103         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5104                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5105                 num_counters += ARRAY_SIZE(cong_cnts);
5106         }
5107         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5108                 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5109                 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5110         }
5111         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5112         if (!cnts->names)
5113                 return -ENOMEM;
5114
5115         cnts->offsets = kcalloc(num_counters,
5116                                 sizeof(cnts->offsets), GFP_KERNEL);
5117         if (!cnts->offsets)
5118                 goto err_names;
5119
5120         return 0;
5121
5122 err_names:
5123         kfree(cnts->names);
5124         cnts->names = NULL;
5125         return -ENOMEM;
5126 }
5127
5128 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5129                                   const char **names,
5130                                   size_t *offsets)
5131 {
5132         int i;
5133         int j = 0;
5134
5135         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5136                 names[j] = basic_q_cnts[i].name;
5137                 offsets[j] = basic_q_cnts[i].offset;
5138         }
5139
5140         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5141                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5142                         names[j] = out_of_seq_q_cnts[i].name;
5143                         offsets[j] = out_of_seq_q_cnts[i].offset;
5144                 }
5145         }
5146
5147         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5148                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5149                         names[j] = retrans_q_cnts[i].name;
5150                         offsets[j] = retrans_q_cnts[i].offset;
5151                 }
5152         }
5153
5154         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5155                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5156                         names[j] = extended_err_cnts[i].name;
5157                         offsets[j] = extended_err_cnts[i].offset;
5158                 }
5159         }
5160
5161         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5162                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5163                         names[j] = cong_cnts[i].name;
5164                         offsets[j] = cong_cnts[i].offset;
5165                 }
5166         }
5167
5168         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5169                 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5170                         names[j] = ext_ppcnt_cnts[i].name;
5171                         offsets[j] = ext_ppcnt_cnts[i].offset;
5172                 }
5173         }
5174 }
5175
5176 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5177 {
5178         int err = 0;
5179         int i;
5180         bool is_shared;
5181
5182         is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
5183
5184         for (i = 0; i < dev->num_ports; i++) {
5185                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5186                 if (err)
5187                         goto err_alloc;
5188
5189                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5190                                       dev->port[i].cnts.offsets);
5191
5192                 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5193                                                &dev->port[i].cnts.set_id,
5194                                                is_shared ?
5195                                                MLX5_SHARED_RESOURCE_UID : 0);
5196                 if (err) {
5197                         mlx5_ib_warn(dev,
5198                                      "couldn't allocate queue counter for port %d, err %d\n",
5199                                      i + 1, err);
5200                         goto err_alloc;
5201                 }
5202                 dev->port[i].cnts.set_id_valid = true;
5203         }
5204
5205         return 0;
5206
5207 err_alloc:
5208         mlx5_ib_dealloc_counters(dev);
5209         return err;
5210 }
5211
5212 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5213                                                     u8 port_num)
5214 {
5215         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5216         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5217
5218         /* We support only per port stats */
5219         if (port_num == 0)
5220                 return NULL;
5221
5222         return rdma_alloc_hw_stats_struct(port->cnts.names,
5223                                           port->cnts.num_q_counters +
5224                                           port->cnts.num_cong_counters +
5225                                           port->cnts.num_ext_ppcnt_counters,
5226                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
5227 }
5228
5229 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5230                                     struct mlx5_ib_port *port,
5231                                     struct rdma_hw_stats *stats)
5232 {
5233         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5234         void *out;
5235         __be32 val;
5236         int ret, i;
5237
5238         out = kvzalloc(outlen, GFP_KERNEL);
5239         if (!out)
5240                 return -ENOMEM;
5241
5242         ret = mlx5_core_query_q_counter(mdev,
5243                                         port->cnts.set_id, 0,
5244                                         out, outlen);
5245         if (ret)
5246                 goto free;
5247
5248         for (i = 0; i < port->cnts.num_q_counters; i++) {
5249                 val = *(__be32 *)(out + port->cnts.offsets[i]);
5250                 stats->value[i] = (u64)be32_to_cpu(val);
5251         }
5252
5253 free:
5254         kvfree(out);
5255         return ret;
5256 }
5257
5258 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5259                                           struct mlx5_ib_port *port,
5260                                           struct rdma_hw_stats *stats)
5261 {
5262         int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5263         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5264         int ret, i;
5265         void *out;
5266
5267         out = kvzalloc(sz, GFP_KERNEL);
5268         if (!out)
5269                 return -ENOMEM;
5270
5271         ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5272         if (ret)
5273                 goto free;
5274
5275         for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5276                 stats->value[i + offset] =
5277                         be64_to_cpup((__be64 *)(out +
5278                                     port->cnts.offsets[i + offset]));
5279         }
5280
5281 free:
5282         kvfree(out);
5283         return ret;
5284 }
5285
5286 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5287                                 struct rdma_hw_stats *stats,
5288                                 u8 port_num, int index)
5289 {
5290         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5291         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5292         struct mlx5_core_dev *mdev;
5293         int ret, num_counters;
5294         u8 mdev_port_num;
5295
5296         if (!stats)
5297                 return -EINVAL;
5298
5299         num_counters = port->cnts.num_q_counters +
5300                        port->cnts.num_cong_counters +
5301                        port->cnts.num_ext_ppcnt_counters;
5302
5303         /* q_counters are per IB device, query the master mdev */
5304         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
5305         if (ret)
5306                 return ret;
5307
5308         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5309                 ret =  mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5310                 if (ret)
5311                         return ret;
5312         }
5313
5314         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5315                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5316                                                     &mdev_port_num);
5317                 if (!mdev) {
5318                         /* If port is not affiliated yet, its in down state
5319                          * which doesn't have any counters yet, so it would be
5320                          * zero. So no need to read from the HCA.
5321                          */
5322                         goto done;
5323                 }
5324                 ret = mlx5_lag_query_cong_counters(dev->mdev,
5325                                                    stats->value +
5326                                                    port->cnts.num_q_counters,
5327                                                    port->cnts.num_cong_counters,
5328                                                    port->cnts.offsets +
5329                                                    port->cnts.num_q_counters);
5330
5331                 mlx5_ib_put_native_port_mdev(dev, port_num);
5332                 if (ret)
5333                         return ret;
5334         }
5335
5336 done:
5337         return num_counters;
5338 }
5339
5340 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5341                                  enum rdma_netdev_t type,
5342                                  struct rdma_netdev_alloc_params *params)
5343 {
5344         if (type != RDMA_NETDEV_IPOIB)
5345                 return -EOPNOTSUPP;
5346
5347         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
5348 }
5349
5350 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5351 {
5352         if (!dev->delay_drop.dbg)
5353                 return;
5354         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5355         kfree(dev->delay_drop.dbg);
5356         dev->delay_drop.dbg = NULL;
5357 }
5358
5359 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5360 {
5361         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5362                 return;
5363
5364         cancel_work_sync(&dev->delay_drop.delay_drop_work);
5365         delay_drop_debugfs_cleanup(dev);
5366 }
5367
5368 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5369                                        size_t count, loff_t *pos)
5370 {
5371         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5372         char lbuf[20];
5373         int len;
5374
5375         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5376         return simple_read_from_buffer(buf, count, pos, lbuf, len);
5377 }
5378
5379 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5380                                         size_t count, loff_t *pos)
5381 {
5382         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5383         u32 timeout;
5384         u32 var;
5385
5386         if (kstrtouint_from_user(buf, count, 0, &var))
5387                 return -EFAULT;
5388
5389         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5390                         1000);
5391         if (timeout != var)
5392                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5393                             timeout);
5394
5395         delay_drop->timeout = timeout;
5396
5397         return count;
5398 }
5399
5400 static const struct file_operations fops_delay_drop_timeout = {
5401         .owner  = THIS_MODULE,
5402         .open   = simple_open,
5403         .write  = delay_drop_timeout_write,
5404         .read   = delay_drop_timeout_read,
5405 };
5406
5407 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5408 {
5409         struct mlx5_ib_dbg_delay_drop *dbg;
5410
5411         if (!mlx5_debugfs_root)
5412                 return 0;
5413
5414         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5415         if (!dbg)
5416                 return -ENOMEM;
5417
5418         dev->delay_drop.dbg = dbg;
5419
5420         dbg->dir_debugfs =
5421                 debugfs_create_dir("delay_drop",
5422                                    dev->mdev->priv.dbg_root);
5423         if (!dbg->dir_debugfs)
5424                 goto out_debugfs;
5425
5426         dbg->events_cnt_debugfs =
5427                 debugfs_create_atomic_t("num_timeout_events", 0400,
5428                                         dbg->dir_debugfs,
5429                                         &dev->delay_drop.events_cnt);
5430         if (!dbg->events_cnt_debugfs)
5431                 goto out_debugfs;
5432
5433         dbg->rqs_cnt_debugfs =
5434                 debugfs_create_atomic_t("num_rqs", 0400,
5435                                         dbg->dir_debugfs,
5436                                         &dev->delay_drop.rqs_cnt);
5437         if (!dbg->rqs_cnt_debugfs)
5438                 goto out_debugfs;
5439
5440         dbg->timeout_debugfs =
5441                 debugfs_create_file("timeout", 0600,
5442                                     dbg->dir_debugfs,
5443                                     &dev->delay_drop,
5444                                     &fops_delay_drop_timeout);
5445         if (!dbg->timeout_debugfs)
5446                 goto out_debugfs;
5447
5448         return 0;
5449
5450 out_debugfs:
5451         delay_drop_debugfs_cleanup(dev);
5452         return -ENOMEM;
5453 }
5454
5455 static void init_delay_drop(struct mlx5_ib_dev *dev)
5456 {
5457         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5458                 return;
5459
5460         mutex_init(&dev->delay_drop.lock);
5461         dev->delay_drop.dev = dev;
5462         dev->delay_drop.activate = false;
5463         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5464         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5465         atomic_set(&dev->delay_drop.rqs_cnt, 0);
5466         atomic_set(&dev->delay_drop.events_cnt, 0);
5467
5468         if (delay_drop_debugfs_init(dev))
5469                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5470 }
5471
5472 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5473 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5474                                       struct mlx5_ib_multiport_info *mpi)
5475 {
5476         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5477         struct mlx5_ib_port *port = &ibdev->port[port_num];
5478         int comps;
5479         int err;
5480         int i;
5481
5482         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5483
5484         spin_lock(&port->mp.mpi_lock);
5485         if (!mpi->ibdev) {
5486                 spin_unlock(&port->mp.mpi_lock);
5487                 return;
5488         }
5489
5490         if (mpi->mdev_events.notifier_call)
5491                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5492         mpi->mdev_events.notifier_call = NULL;
5493
5494         mpi->ibdev = NULL;
5495
5496         spin_unlock(&port->mp.mpi_lock);
5497         mlx5_remove_netdev_notifier(ibdev, port_num);
5498         spin_lock(&port->mp.mpi_lock);
5499
5500         comps = mpi->mdev_refcnt;
5501         if (comps) {
5502                 mpi->unaffiliate = true;
5503                 init_completion(&mpi->unref_comp);
5504                 spin_unlock(&port->mp.mpi_lock);
5505
5506                 for (i = 0; i < comps; i++)
5507                         wait_for_completion(&mpi->unref_comp);
5508
5509                 spin_lock(&port->mp.mpi_lock);
5510                 mpi->unaffiliate = false;
5511         }
5512
5513         port->mp.mpi = NULL;
5514
5515         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5516
5517         spin_unlock(&port->mp.mpi_lock);
5518
5519         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5520
5521         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5522         /* Log an error, still needed to cleanup the pointers and add
5523          * it back to the list.
5524          */
5525         if (err)
5526                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5527                             port_num + 1);
5528
5529         ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5530 }
5531
5532 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5533 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5534                                     struct mlx5_ib_multiport_info *mpi)
5535 {
5536         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5537         int err;
5538
5539         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5540         if (ibdev->port[port_num].mp.mpi) {
5541                 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5542                             port_num + 1);
5543                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5544                 return false;
5545         }
5546
5547         ibdev->port[port_num].mp.mpi = mpi;
5548         mpi->ibdev = ibdev;
5549         mpi->mdev_events.notifier_call = NULL;
5550         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5551
5552         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5553         if (err)
5554                 goto unbind;
5555
5556         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5557         if (err)
5558                 goto unbind;
5559
5560         err = mlx5_add_netdev_notifier(ibdev, port_num);
5561         if (err) {
5562                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5563                             port_num + 1);
5564                 goto unbind;
5565         }
5566
5567         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5568         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5569
5570         err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5571         if (err)
5572                 goto unbind;
5573
5574         return true;
5575
5576 unbind:
5577         mlx5_ib_unbind_slave_port(ibdev, mpi);
5578         return false;
5579 }
5580
5581 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5582 {
5583         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5584         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5585                                                           port_num + 1);
5586         struct mlx5_ib_multiport_info *mpi;
5587         int err;
5588         int i;
5589
5590         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5591                 return 0;
5592
5593         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5594                                                      &dev->sys_image_guid);
5595         if (err)
5596                 return err;
5597
5598         err = mlx5_nic_vport_enable_roce(dev->mdev);
5599         if (err)
5600                 return err;
5601
5602         mutex_lock(&mlx5_ib_multiport_mutex);
5603         for (i = 0; i < dev->num_ports; i++) {
5604                 bool bound = false;
5605
5606                 /* build a stub multiport info struct for the native port. */
5607                 if (i == port_num) {
5608                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5609                         if (!mpi) {
5610                                 mutex_unlock(&mlx5_ib_multiport_mutex);
5611                                 mlx5_nic_vport_disable_roce(dev->mdev);
5612                                 return -ENOMEM;
5613                         }
5614
5615                         mpi->is_master = true;
5616                         mpi->mdev = dev->mdev;
5617                         mpi->sys_image_guid = dev->sys_image_guid;
5618                         dev->port[i].mp.mpi = mpi;
5619                         mpi->ibdev = dev;
5620                         mpi = NULL;
5621                         continue;
5622                 }
5623
5624                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5625                                     list) {
5626                         if (dev->sys_image_guid == mpi->sys_image_guid &&
5627                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5628                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
5629                         }
5630
5631                         if (bound) {
5632                                 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5633                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5634                                 list_del(&mpi->list);
5635                                 break;
5636                         }
5637                 }
5638                 if (!bound) {
5639                         get_port_caps(dev, i + 1);
5640                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
5641                                     i + 1);
5642                 }
5643         }
5644
5645         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5646         mutex_unlock(&mlx5_ib_multiport_mutex);
5647         return err;
5648 }
5649
5650 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5651 {
5652         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5653         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5654                                                           port_num + 1);
5655         int i;
5656
5657         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5658                 return;
5659
5660         mutex_lock(&mlx5_ib_multiport_mutex);
5661         for (i = 0; i < dev->num_ports; i++) {
5662                 if (dev->port[i].mp.mpi) {
5663                         /* Destroy the native port stub */
5664                         if (i == port_num) {
5665                                 kfree(dev->port[i].mp.mpi);
5666                                 dev->port[i].mp.mpi = NULL;
5667                         } else {
5668                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5669                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5670                         }
5671                 }
5672         }
5673
5674         mlx5_ib_dbg(dev, "removing from devlist\n");
5675         list_del(&dev->ib_dev_list);
5676         mutex_unlock(&mlx5_ib_multiport_mutex);
5677
5678         mlx5_nic_vport_disable_roce(dev->mdev);
5679 }
5680
5681 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5682         mlx5_ib_dm,
5683         UVERBS_OBJECT_DM,
5684         UVERBS_METHOD_DM_ALLOC,
5685         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5686                             UVERBS_ATTR_TYPE(u64),
5687                             UA_MANDATORY),
5688         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5689                             UVERBS_ATTR_TYPE(u16),
5690                             UA_MANDATORY));
5691
5692 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5693         mlx5_ib_flow_action,
5694         UVERBS_OBJECT_FLOW_ACTION,
5695         UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5696         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5697                              enum mlx5_ib_uapi_flow_action_flags));
5698
5699 static const struct uapi_definition mlx5_ib_defs[] = {
5700 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
5701         UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
5702         UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
5703 #endif
5704
5705         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
5706                                 &mlx5_ib_flow_action),
5707         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
5708         {}
5709 };
5710
5711 static int mlx5_ib_read_counters(struct ib_counters *counters,
5712                                  struct ib_counters_read_attr *read_attr,
5713                                  struct uverbs_attr_bundle *attrs)
5714 {
5715         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5716         struct mlx5_read_counters_attr mread_attr = {};
5717         struct mlx5_ib_flow_counters_desc *desc;
5718         int ret, i;
5719
5720         mutex_lock(&mcounters->mcntrs_mutex);
5721         if (mcounters->cntrs_max_index > read_attr->ncounters) {
5722                 ret = -EINVAL;
5723                 goto err_bound;
5724         }
5725
5726         mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5727                                  GFP_KERNEL);
5728         if (!mread_attr.out) {
5729                 ret = -ENOMEM;
5730                 goto err_bound;
5731         }
5732
5733         mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5734         mread_attr.flags = read_attr->flags;
5735         ret = mcounters->read_counters(counters->device, &mread_attr);
5736         if (ret)
5737                 goto err_read;
5738
5739         /* do the pass over the counters data array to assign according to the
5740          * descriptions and indexing pairs
5741          */
5742         desc = mcounters->counters_data;
5743         for (i = 0; i < mcounters->ncounters; i++)
5744                 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5745
5746 err_read:
5747         kfree(mread_attr.out);
5748 err_bound:
5749         mutex_unlock(&mcounters->mcntrs_mutex);
5750         return ret;
5751 }
5752
5753 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5754 {
5755         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5756
5757         counters_clear_description(counters);
5758         if (mcounters->hw_cntrs_hndl)
5759                 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5760                                 mcounters->hw_cntrs_hndl);
5761
5762         kfree(mcounters);
5763
5764         return 0;
5765 }
5766
5767 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5768                                                    struct uverbs_attr_bundle *attrs)
5769 {
5770         struct mlx5_ib_mcounters *mcounters;
5771
5772         mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5773         if (!mcounters)
5774                 return ERR_PTR(-ENOMEM);
5775
5776         mutex_init(&mcounters->mcntrs_mutex);
5777
5778         return &mcounters->ibcntrs;
5779 }
5780
5781 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5782 {
5783         mlx5_ib_cleanup_multiport_master(dev);
5784 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5785         cleanup_srcu_struct(&dev->mr_srcu);
5786         drain_workqueue(dev->advise_mr_wq);
5787         destroy_workqueue(dev->advise_mr_wq);
5788 #endif
5789         kfree(dev->port);
5790 }
5791
5792 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5793 {
5794         struct mlx5_core_dev *mdev = dev->mdev;
5795         int err;
5796         int i;
5797
5798         dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5799                             GFP_KERNEL);
5800         if (!dev->port)
5801                 return -ENOMEM;
5802
5803         for (i = 0; i < dev->num_ports; i++) {
5804                 spin_lock_init(&dev->port[i].mp.mpi_lock);
5805                 rwlock_init(&dev->roce[i].netdev_lock);
5806         }
5807
5808         err = mlx5_ib_init_multiport_master(dev);
5809         if (err)
5810                 goto err_free_port;
5811
5812         if (!mlx5_core_mp_enabled(mdev)) {
5813                 for (i = 1; i <= dev->num_ports; i++) {
5814                         err = get_port_caps(dev, i);
5815                         if (err)
5816                                 break;
5817                 }
5818         } else {
5819                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5820         }
5821         if (err)
5822                 goto err_mp;
5823
5824         if (mlx5_use_mad_ifc(dev))
5825                 get_ext_port_caps(dev);
5826
5827         dev->ib_dev.owner               = THIS_MODULE;
5828         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
5829         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
5830         dev->ib_dev.phys_port_cnt       = dev->num_ports;
5831         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_count(mdev);
5832         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
5833
5834         mutex_init(&dev->cap_mask_mutex);
5835         INIT_LIST_HEAD(&dev->qp_list);
5836         spin_lock_init(&dev->reset_flow_resource_lock);
5837
5838         spin_lock_init(&dev->memic.memic_lock);
5839         dev->memic.dev = mdev;
5840
5841 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5842         dev->advise_mr_wq = alloc_ordered_workqueue("mlx5_ib_advise_mr_wq", 0);
5843         if (!dev->advise_mr_wq) {
5844                 err = -ENOMEM;
5845                 goto err_mp;
5846         }
5847
5848         err = init_srcu_struct(&dev->mr_srcu);
5849         if (err) {
5850                 destroy_workqueue(dev->advise_mr_wq);
5851                 goto err_mp;
5852         }
5853 #endif
5854
5855         return 0;
5856 err_mp:
5857         mlx5_ib_cleanup_multiport_master(dev);
5858
5859 err_free_port:
5860         kfree(dev->port);
5861
5862         return -ENOMEM;
5863 }
5864
5865 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5866 {
5867         dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5868
5869         if (!dev->flow_db)
5870                 return -ENOMEM;
5871
5872         mutex_init(&dev->flow_db->lock);
5873
5874         return 0;
5875 }
5876
5877 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5878 {
5879         struct mlx5_ib_dev *nic_dev;
5880
5881         nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5882
5883         if (!nic_dev)
5884                 return -EINVAL;
5885
5886         dev->flow_db = nic_dev->flow_db;
5887
5888         return 0;
5889 }
5890
5891 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5892 {
5893         kfree(dev->flow_db);
5894 }
5895
5896 static const struct ib_device_ops mlx5_ib_dev_ops = {
5897         .add_gid = mlx5_ib_add_gid,
5898         .alloc_mr = mlx5_ib_alloc_mr,
5899         .alloc_pd = mlx5_ib_alloc_pd,
5900         .alloc_ucontext = mlx5_ib_alloc_ucontext,
5901         .attach_mcast = mlx5_ib_mcg_attach,
5902         .check_mr_status = mlx5_ib_check_mr_status,
5903         .create_ah = mlx5_ib_create_ah,
5904         .create_counters = mlx5_ib_create_counters,
5905         .create_cq = mlx5_ib_create_cq,
5906         .create_flow = mlx5_ib_create_flow,
5907         .create_qp = mlx5_ib_create_qp,
5908         .create_srq = mlx5_ib_create_srq,
5909         .dealloc_pd = mlx5_ib_dealloc_pd,
5910         .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
5911         .del_gid = mlx5_ib_del_gid,
5912         .dereg_mr = mlx5_ib_dereg_mr,
5913         .destroy_ah = mlx5_ib_destroy_ah,
5914         .destroy_counters = mlx5_ib_destroy_counters,
5915         .destroy_cq = mlx5_ib_destroy_cq,
5916         .destroy_flow = mlx5_ib_destroy_flow,
5917         .destroy_flow_action = mlx5_ib_destroy_flow_action,
5918         .destroy_qp = mlx5_ib_destroy_qp,
5919         .destroy_srq = mlx5_ib_destroy_srq,
5920         .detach_mcast = mlx5_ib_mcg_detach,
5921         .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
5922         .drain_rq = mlx5_ib_drain_rq,
5923         .drain_sq = mlx5_ib_drain_sq,
5924         .get_dev_fw_str = get_dev_fw_str,
5925         .get_dma_mr = mlx5_ib_get_dma_mr,
5926         .get_link_layer = mlx5_ib_port_link_layer,
5927         .map_mr_sg = mlx5_ib_map_mr_sg,
5928         .mmap = mlx5_ib_mmap,
5929         .modify_cq = mlx5_ib_modify_cq,
5930         .modify_device = mlx5_ib_modify_device,
5931         .modify_port = mlx5_ib_modify_port,
5932         .modify_qp = mlx5_ib_modify_qp,
5933         .modify_srq = mlx5_ib_modify_srq,
5934         .poll_cq = mlx5_ib_poll_cq,
5935         .post_recv = mlx5_ib_post_recv,
5936         .post_send = mlx5_ib_post_send,
5937         .post_srq_recv = mlx5_ib_post_srq_recv,
5938         .process_mad = mlx5_ib_process_mad,
5939         .query_ah = mlx5_ib_query_ah,
5940         .query_device = mlx5_ib_query_device,
5941         .query_gid = mlx5_ib_query_gid,
5942         .query_pkey = mlx5_ib_query_pkey,
5943         .query_qp = mlx5_ib_query_qp,
5944         .query_srq = mlx5_ib_query_srq,
5945         .read_counters = mlx5_ib_read_counters,
5946         .reg_user_mr = mlx5_ib_reg_user_mr,
5947         .req_notify_cq = mlx5_ib_arm_cq,
5948         .rereg_user_mr = mlx5_ib_rereg_user_mr,
5949         .resize_cq = mlx5_ib_resize_cq,
5950 };
5951
5952 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
5953         .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
5954         .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
5955 };
5956
5957 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
5958         .rdma_netdev_get_params = mlx5_ib_rn_get_params,
5959 };
5960
5961 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
5962         .get_vf_config = mlx5_ib_get_vf_config,
5963         .get_vf_stats = mlx5_ib_get_vf_stats,
5964         .set_vf_guid = mlx5_ib_set_vf_guid,
5965         .set_vf_link_state = mlx5_ib_set_vf_link_state,
5966 };
5967
5968 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
5969         .alloc_mw = mlx5_ib_alloc_mw,
5970         .dealloc_mw = mlx5_ib_dealloc_mw,
5971 };
5972
5973 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
5974         .alloc_xrcd = mlx5_ib_alloc_xrcd,
5975         .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
5976 };
5977
5978 static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
5979         .alloc_dm = mlx5_ib_alloc_dm,
5980         .dealloc_dm = mlx5_ib_dealloc_dm,
5981         .reg_dm_mr = mlx5_ib_reg_dm_mr,
5982 };
5983
5984 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5985 {
5986         struct mlx5_core_dev *mdev = dev->mdev;
5987         int err;
5988
5989         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
5990         dev->ib_dev.uverbs_cmd_mask     =
5991                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
5992                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
5993                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
5994                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
5995                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
5996                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
5997                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
5998                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
5999                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
6000                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
6001                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6002                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
6003                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
6004                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
6005                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
6006                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
6007                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
6008                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
6009                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
6010                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
6011                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
6012                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
6013                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
6014                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
6015                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
6016                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
6017         dev->ib_dev.uverbs_ex_cmd_mask =
6018                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
6019                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
6020                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
6021                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
6022                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ)        |
6023                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW)      |
6024                 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6025
6026         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6027             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
6028                 ib_set_device_ops(&dev->ib_dev,
6029                                   &mlx5_ib_dev_ipoib_enhanced_ops);
6030
6031         if (mlx5_core_is_pf(mdev))
6032                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
6033
6034         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6035
6036         if (MLX5_CAP_GEN(mdev, imaicl)) {
6037                 dev->ib_dev.uverbs_cmd_mask |=
6038                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
6039                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
6040                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
6041         }
6042
6043         if (MLX5_CAP_GEN(mdev, xrc)) {
6044                 dev->ib_dev.uverbs_cmd_mask |=
6045                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6046                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
6047                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
6048         }
6049
6050         if (MLX5_CAP_DEV_MEM(mdev, memic))
6051                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
6052
6053         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
6054             MLX5_ACCEL_IPSEC_CAP_DEVICE)
6055                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
6056         dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
6057         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
6058
6059         if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6060                 dev->ib_dev.driver_def = mlx5_ib_defs;
6061
6062         err = init_node_data(dev);
6063         if (err)
6064                 return err;
6065
6066         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
6067             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6068              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
6069                 mutex_init(&dev->lb.mutex);
6070
6071         return 0;
6072 }
6073
6074 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6075         .get_port_immutable = mlx5_port_immutable,
6076         .query_port = mlx5_ib_query_port,
6077 };
6078
6079 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6080 {
6081         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
6082         return 0;
6083 }
6084
6085 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6086         .get_port_immutable = mlx5_port_rep_immutable,
6087         .query_port = mlx5_ib_rep_query_port,
6088 };
6089
6090 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
6091 {
6092         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
6093         return 0;
6094 }
6095
6096 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6097         .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6098         .create_wq = mlx5_ib_create_wq,
6099         .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6100         .destroy_wq = mlx5_ib_destroy_wq,
6101         .get_netdev = mlx5_ib_get_netdev,
6102         .modify_wq = mlx5_ib_modify_wq,
6103 };
6104
6105 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
6106 {
6107         u8 port_num;
6108         int i;
6109
6110         for (i = 0; i < dev->num_ports; i++) {
6111                 dev->roce[i].dev = dev;
6112                 dev->roce[i].native_port_num = i + 1;
6113                 dev->roce[i].last_port_state = IB_PORT_DOWN;
6114         }
6115
6116         dev->ib_dev.uverbs_ex_cmd_mask |=
6117                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6118                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6119                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6120                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6121                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
6122         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
6123
6124         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6125
6126         return mlx5_add_netdev_notifier(dev, port_num);
6127 }
6128
6129 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6130 {
6131         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6132
6133         mlx5_remove_netdev_notifier(dev, port_num);
6134 }
6135
6136 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
6137 {
6138         struct mlx5_core_dev *mdev = dev->mdev;
6139         enum rdma_link_layer ll;
6140         int port_type_cap;
6141         int err = 0;
6142
6143         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6144         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6145
6146         if (ll == IB_LINK_LAYER_ETHERNET)
6147                 err = mlx5_ib_stage_common_roce_init(dev);
6148
6149         return err;
6150 }
6151
6152 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
6153 {
6154         mlx5_ib_stage_common_roce_cleanup(dev);
6155 }
6156
6157 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6158 {
6159         struct mlx5_core_dev *mdev = dev->mdev;
6160         enum rdma_link_layer ll;
6161         int port_type_cap;
6162         int err;
6163
6164         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6165         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6166
6167         if (ll == IB_LINK_LAYER_ETHERNET) {
6168                 err = mlx5_ib_stage_common_roce_init(dev);
6169                 if (err)
6170                         return err;
6171
6172                 err = mlx5_enable_eth(dev);
6173                 if (err)
6174                         goto cleanup;
6175         }
6176
6177         return 0;
6178 cleanup:
6179         mlx5_ib_stage_common_roce_cleanup(dev);
6180
6181         return err;
6182 }
6183
6184 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6185 {
6186         struct mlx5_core_dev *mdev = dev->mdev;
6187         enum rdma_link_layer ll;
6188         int port_type_cap;
6189
6190         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6191         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6192
6193         if (ll == IB_LINK_LAYER_ETHERNET) {
6194                 mlx5_disable_eth(dev);
6195                 mlx5_ib_stage_common_roce_cleanup(dev);
6196         }
6197 }
6198
6199 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6200 {
6201         return create_dev_resources(&dev->devr);
6202 }
6203
6204 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6205 {
6206         destroy_dev_resources(&dev->devr);
6207 }
6208
6209 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6210 {
6211         mlx5_ib_internal_fill_odp_caps(dev);
6212
6213         return mlx5_ib_odp_init_one(dev);
6214 }
6215
6216 void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6217 {
6218         mlx5_ib_odp_cleanup_one(dev);
6219 }
6220
6221 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6222         .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6223         .get_hw_stats = mlx5_ib_get_hw_stats,
6224 };
6225
6226 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6227 {
6228         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6229                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
6230
6231                 return mlx5_ib_alloc_counters(dev);
6232         }
6233
6234         return 0;
6235 }
6236
6237 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6238 {
6239         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6240                 mlx5_ib_dealloc_counters(dev);
6241 }
6242
6243 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6244 {
6245         return mlx5_ib_init_cong_debugfs(dev,
6246                                          mlx5_core_native_port_num(dev->mdev) - 1);
6247 }
6248
6249 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6250 {
6251         mlx5_ib_cleanup_cong_debugfs(dev,
6252                                      mlx5_core_native_port_num(dev->mdev) - 1);
6253 }
6254
6255 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6256 {
6257         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6258         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6259 }
6260
6261 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6262 {
6263         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6264 }
6265
6266 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6267 {
6268         int err;
6269
6270         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6271         if (err)
6272                 return err;
6273
6274         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6275         if (err)
6276                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6277
6278         return err;
6279 }
6280
6281 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6282 {
6283         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6284         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6285 }
6286
6287 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6288 {
6289         const char *name;
6290
6291         rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
6292         if (!mlx5_lag_is_roce(dev->mdev))
6293                 name = "mlx5_%d";
6294         else
6295                 name = "mlx5_bond_%d";
6296         return ib_register_device(&dev->ib_dev, name, NULL);
6297 }
6298
6299 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6300 {
6301         destroy_umrc_res(dev);
6302 }
6303
6304 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6305 {
6306         ib_unregister_device(&dev->ib_dev);
6307 }
6308
6309 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6310 {
6311         return create_umr_res(dev);
6312 }
6313
6314 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6315 {
6316         init_delay_drop(dev);
6317
6318         return 0;
6319 }
6320
6321 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6322 {
6323         cancel_delay_drop(dev);
6324 }
6325
6326 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6327 {
6328         dev->mdev_events.notifier_call = mlx5_ib_event;
6329         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6330         return 0;
6331 }
6332
6333 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6334 {
6335         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6336 }
6337
6338 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6339 {
6340         int uid;
6341
6342         uid = mlx5_ib_devx_create(dev, false);
6343         if (uid > 0)
6344                 dev->devx_whitelist_uid = uid;
6345
6346         return 0;
6347 }
6348 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6349 {
6350         if (dev->devx_whitelist_uid)
6351                 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6352 }
6353
6354 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6355                       const struct mlx5_ib_profile *profile,
6356                       int stage)
6357 {
6358         /* Number of stages to cleanup */
6359         while (stage) {
6360                 stage--;
6361                 if (profile->stage[stage].cleanup)
6362                         profile->stage[stage].cleanup(dev);
6363         }
6364 }
6365
6366 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6367                     const struct mlx5_ib_profile *profile)
6368 {
6369         int err;
6370         int i;
6371
6372         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6373                 if (profile->stage[i].init) {
6374                         err = profile->stage[i].init(dev);
6375                         if (err)
6376                                 goto err_out;
6377                 }
6378         }
6379
6380         dev->profile = profile;
6381         dev->ib_active = true;
6382
6383         return dev;
6384
6385 err_out:
6386         __mlx5_ib_remove(dev, profile, i);
6387
6388         return NULL;
6389 }
6390
6391 static const struct mlx5_ib_profile pf_profile = {
6392         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6393                      mlx5_ib_stage_init_init,
6394                      mlx5_ib_stage_init_cleanup),
6395         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6396                      mlx5_ib_stage_flow_db_init,
6397                      mlx5_ib_stage_flow_db_cleanup),
6398         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6399                      mlx5_ib_stage_caps_init,
6400                      NULL),
6401         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6402                      mlx5_ib_stage_non_default_cb,
6403                      NULL),
6404         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6405                      mlx5_ib_stage_roce_init,
6406                      mlx5_ib_stage_roce_cleanup),
6407         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6408                      mlx5_init_srq_table,
6409                      mlx5_cleanup_srq_table),
6410         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6411                      mlx5_ib_stage_dev_res_init,
6412                      mlx5_ib_stage_dev_res_cleanup),
6413         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6414                      mlx5_ib_stage_dev_notifier_init,
6415                      mlx5_ib_stage_dev_notifier_cleanup),
6416         STAGE_CREATE(MLX5_IB_STAGE_ODP,
6417                      mlx5_ib_stage_odp_init,
6418                      mlx5_ib_stage_odp_cleanup),
6419         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6420                      mlx5_ib_stage_counters_init,
6421                      mlx5_ib_stage_counters_cleanup),
6422         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6423                      mlx5_ib_stage_cong_debugfs_init,
6424                      mlx5_ib_stage_cong_debugfs_cleanup),
6425         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6426                      mlx5_ib_stage_uar_init,
6427                      mlx5_ib_stage_uar_cleanup),
6428         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6429                      mlx5_ib_stage_bfrag_init,
6430                      mlx5_ib_stage_bfrag_cleanup),
6431         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6432                      NULL,
6433                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6434         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6435                      mlx5_ib_stage_devx_init,
6436                      mlx5_ib_stage_devx_cleanup),
6437         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6438                      mlx5_ib_stage_ib_reg_init,
6439                      mlx5_ib_stage_ib_reg_cleanup),
6440         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6441                      mlx5_ib_stage_post_ib_reg_umr_init,
6442                      NULL),
6443         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6444                      mlx5_ib_stage_delay_drop_init,
6445                      mlx5_ib_stage_delay_drop_cleanup),
6446 };
6447
6448 const struct mlx5_ib_profile uplink_rep_profile = {
6449         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6450                      mlx5_ib_stage_init_init,
6451                      mlx5_ib_stage_init_cleanup),
6452         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6453                      mlx5_ib_stage_flow_db_init,
6454                      mlx5_ib_stage_flow_db_cleanup),
6455         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6456                      mlx5_ib_stage_caps_init,
6457                      NULL),
6458         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6459                      mlx5_ib_stage_rep_non_default_cb,
6460                      NULL),
6461         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6462                      mlx5_ib_stage_rep_roce_init,
6463                      mlx5_ib_stage_rep_roce_cleanup),
6464         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6465                      mlx5_init_srq_table,
6466                      mlx5_cleanup_srq_table),
6467         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6468                      mlx5_ib_stage_dev_res_init,
6469                      mlx5_ib_stage_dev_res_cleanup),
6470         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6471                      mlx5_ib_stage_dev_notifier_init,
6472                      mlx5_ib_stage_dev_notifier_cleanup),
6473         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6474                      mlx5_ib_stage_counters_init,
6475                      mlx5_ib_stage_counters_cleanup),
6476         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6477                      mlx5_ib_stage_uar_init,
6478                      mlx5_ib_stage_uar_cleanup),
6479         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6480                      mlx5_ib_stage_bfrag_init,
6481                      mlx5_ib_stage_bfrag_cleanup),
6482         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6483                      NULL,
6484                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6485         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6486                      mlx5_ib_stage_ib_reg_init,
6487                      mlx5_ib_stage_ib_reg_cleanup),
6488         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6489                      mlx5_ib_stage_post_ib_reg_umr_init,
6490                      NULL),
6491 };
6492
6493 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6494 {
6495         struct mlx5_ib_multiport_info *mpi;
6496         struct mlx5_ib_dev *dev;
6497         bool bound = false;
6498         int err;
6499
6500         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6501         if (!mpi)
6502                 return NULL;
6503
6504         mpi->mdev = mdev;
6505
6506         err = mlx5_query_nic_vport_system_image_guid(mdev,
6507                                                      &mpi->sys_image_guid);
6508         if (err) {
6509                 kfree(mpi);
6510                 return NULL;
6511         }
6512
6513         mutex_lock(&mlx5_ib_multiport_mutex);
6514         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6515                 if (dev->sys_image_guid == mpi->sys_image_guid)
6516                         bound = mlx5_ib_bind_slave_port(dev, mpi);
6517
6518                 if (bound) {
6519                         rdma_roce_rescan_device(&dev->ib_dev);
6520                         break;
6521                 }
6522         }
6523
6524         if (!bound) {
6525                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6526                 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
6527         }
6528         mutex_unlock(&mlx5_ib_multiport_mutex);
6529
6530         return mpi;
6531 }
6532
6533 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6534 {
6535         enum rdma_link_layer ll;
6536         struct mlx5_ib_dev *dev;
6537         int port_type_cap;
6538
6539         printk_once(KERN_INFO "%s", mlx5_version);
6540
6541         if (MLX5_ESWITCH_MANAGER(mdev) &&
6542             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6543                 mlx5_ib_register_vport_reps(mdev);
6544                 return mdev;
6545         }
6546
6547         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6548         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6549
6550         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6551                 return mlx5_ib_add_slave_port(mdev);
6552
6553         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6554         if (!dev)
6555                 return NULL;
6556
6557         dev->mdev = mdev;
6558         dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6559                              MLX5_CAP_GEN(mdev, num_vhca_ports));
6560
6561         return __mlx5_ib_add(dev, &pf_profile);
6562 }
6563
6564 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6565 {
6566         struct mlx5_ib_multiport_info *mpi;
6567         struct mlx5_ib_dev *dev;
6568
6569         if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6570                 mlx5_ib_unregister_vport_reps(mdev);
6571                 return;
6572         }
6573
6574         if (mlx5_core_is_mp_slave(mdev)) {
6575                 mpi = context;
6576                 mutex_lock(&mlx5_ib_multiport_mutex);
6577                 if (mpi->ibdev)
6578                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6579                 list_del(&mpi->list);
6580                 mutex_unlock(&mlx5_ib_multiport_mutex);
6581                 return;
6582         }
6583
6584         dev = context;
6585         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6586
6587         ib_dealloc_device((struct ib_device *)dev);
6588 }
6589
6590 static struct mlx5_interface mlx5_ib_interface = {
6591         .add            = mlx5_ib_add,
6592         .remove         = mlx5_ib_remove,
6593         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
6594 };
6595
6596 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6597 {
6598         mutex_lock(&xlt_emergency_page_mutex);
6599         return xlt_emergency_page;
6600 }
6601
6602 void mlx5_ib_put_xlt_emergency_page(void)
6603 {
6604         mutex_unlock(&xlt_emergency_page_mutex);
6605 }
6606
6607 static int __init mlx5_ib_init(void)
6608 {
6609         int err;
6610
6611         xlt_emergency_page = __get_free_page(GFP_KERNEL);
6612         if (!xlt_emergency_page)
6613                 return -ENOMEM;
6614
6615         mutex_init(&xlt_emergency_page_mutex);
6616
6617         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6618         if (!mlx5_ib_event_wq) {
6619                 free_page(xlt_emergency_page);
6620                 return -ENOMEM;
6621         }
6622
6623         mlx5_ib_odp_init();
6624
6625         err = mlx5_register_interface(&mlx5_ib_interface);
6626
6627         return err;
6628 }
6629
6630 static void __exit mlx5_ib_cleanup(void)
6631 {
6632         mlx5_unregister_interface(&mlx5_ib_interface);
6633         destroy_workqueue(mlx5_ib_event_wq);
6634         mutex_destroy(&xlt_emergency_page_mutex);
6635         free_page(xlt_emergency_page);
6636 }
6637
6638 module_init(mlx5_ib_init);
6639 module_exit(mlx5_ib_cleanup);