drivers/gpu/drm/amd/amdgpu/soc21.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_11_0_0_offset.h"
  40 #include "gc/gc_11_0_0_sh_mask.h"
  41 #include "mp/mp_13_0_0_offset.h"
  42
  43 #include "soc15.h"
  44 #include "soc15_common.h"
  45 #include "soc21.h"
  46 #include "mxgpu_nv.h"
  47
  48 static const struct amd_ip_funcs soc21_common_ip_funcs;
  49
  50 /* SOC21 */
  51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] =
  52 {
  53         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  54         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  55         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
  56 };
  57
  58 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] =
  59 {
  60         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  61         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  62 };
  63
  64 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 =
  65 {
  66         .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
  67         .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
  68 };
  69
  70 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 =
  71 {
  72         .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
  73         .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
  74 };
  75
  76 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] =
  77 {
  78         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
  79         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  80         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  81         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  82         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
  83 };
  84
  85 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] =
  86 {
  87         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
  88         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  89         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  90         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  91 };
  92
  93 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 =
  94 {
  95         .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
  96         .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
  97 };
  98
  99 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 =
 100 {
 101         .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
 102         .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
 103 };
 104
 105 /* SRIOV SOC21, not const since data is controlled by host */
 106 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 110 };
 111
 112 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
 113         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
 114         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
 115 };
 116
 117 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
 118         .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
 119         .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
 120 };
 121
 122 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
 123         .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
 124         .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
 125 };
 126
 127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
 128         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 129         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 130         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 131         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 132         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 133         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 134         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 135         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 136 };
 137
 138 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
 139         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 140         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 141         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 142         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 143         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 144         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 145         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 146 };
 147
 148 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
 149         .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
 150         .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
 151 };
 152
 153 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
 154         .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
 155         .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
 156 };
 157
 158 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
 159                                  const struct amdgpu_video_codecs **codecs)
 160 {
 161         if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
 162                 return -EINVAL;
 163
 164         switch (adev->ip_versions[UVD_HWIP][0]) {
 165         case IP_VERSION(4, 0, 0):
 166         case IP_VERSION(4, 0, 2):
 167         case IP_VERSION(4, 0, 4):
 168                 if (amdgpu_sriov_vf(adev)) {
 169                         if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
 170                         !amdgpu_sriov_is_av1_support(adev)) {
 171                                 if (encode)
 172                                         *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
 173                                 else
 174                                         *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
 175                         } else {
 176                                 if (encode)
 177                                         *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
 178                                 else
 179                                         *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
 180                         }
 181                 } else {
 182                         if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
 183                                 if (encode)
 184                                         *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
 185                                 else
 186                                         *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
 187                         } else {
 188                                 if (encode)
 189                                         *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
 190                                 else
 191                                         *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
 192                         }
 193                 }
 194                 return 0;
 195         default:
 196                 return -EINVAL;
 197         }
 198 }
 199 /*
 200  * Indirect registers accessor
 201  */
 202 static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 203 {
 204         unsigned long address, data;
 205         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 206         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 207
 208         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 209 }
 210
 211 static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 212 {
 213         unsigned long address, data;
 214
 215         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 216         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 217
 218         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 219 }
 220
 221 static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 222 {
 223         unsigned long address, data;
 224         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 225         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 226
 227         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 228 }
 229
 230 static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 231 {
 232         unsigned long address, data;
 233
 234         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 235         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 236
 237         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 238 }
 239
 240 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
 241 {
 242         unsigned long flags, address, data;
 243         u32 r;
 244
 245         address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
 246         data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
 247
 248         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 249         WREG32(address, (reg));
 250         r = RREG32(data);
 251         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 252         return r;
 253 }
 254
 255 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 256 {
 257         unsigned long flags, address, data;
 258
 259         address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
 260         data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
 261
 262         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 263         WREG32(address, (reg));
 264         WREG32(data, (v));
 265         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 266 }
 267
 268 static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
 269 {
 270         return adev->nbio.funcs->get_memsize(adev);
 271 }
 272
 273 static u32 soc21_get_xclk(struct amdgpu_device *adev)
 274 {
 275         return adev->clock.spll.reference_freq;
 276 }
 277
 278
 279 void soc21_grbm_select(struct amdgpu_device *adev,
 280                      u32 me, u32 pipe, u32 queue, u32 vmid)
 281 {
 282         u32 grbm_gfx_cntl = 0;
 283         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 284         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 285         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 286         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 287
 288         WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
 289 }
 290
 291 static void soc21_vga_set_state(struct amdgpu_device *adev, bool state)
 292 {
 293         /* todo */
 294 }
 295
 296 static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
 297 {
 298         /* todo */
 299         return false;
 300 }
 301
 302 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
 303         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
 304         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
 305         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
 306         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
 307         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
 308         { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
 309         { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
 310         { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
 311         { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
 312         { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
 313         { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
 314         { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
 315         { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
 316         { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
 317         { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
 318         { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
 319         { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
 320         { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
 321         { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
 322 };
 323
 324 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 325                                          u32 sh_num, u32 reg_offset)
 326 {
 327         uint32_t val;
 328
 329         mutex_lock(&adev->grbm_idx_mutex);
 330         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 331                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 332
 333         val = RREG32(reg_offset);
 334
 335         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 336                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 337         mutex_unlock(&adev->grbm_idx_mutex);
 338         return val;
 339 }
 340
 341 static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
 342                                       bool indexed, u32 se_num,
 343                                       u32 sh_num, u32 reg_offset)
 344 {
 345         if (indexed) {
 346                 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
 347         } else {
 348                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
 349                         return adev->gfx.config.gb_addr_config;
 350                 return RREG32(reg_offset);
 351         }
 352 }
 353
 354 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
 355                             u32 sh_num, u32 reg_offset, u32 *value)
 356 {
 357         uint32_t i;
 358         struct soc15_allowed_register_entry  *en;
 359
 360         *value = 0;
 361         for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
 362                 en = &soc21_allowed_read_registers[i];
 363                 if (!adev->reg_offset[en->hwip][en->inst])
 364                         continue;
 365                 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 366                                         + en->reg_offset))
 367                         continue;
 368
 369                 *value = soc21_get_register_value(adev,
 370                                                soc21_allowed_read_registers[i].grbm_indexed,
 371                                                se_num, sh_num, reg_offset);
 372                 return 0;
 373         }
 374         return -EINVAL;
 375 }
 376
 377 #if 0
 378 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
 379 {
 380         u32 i;
 381         int ret = 0;
 382
 383         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 384
 385         /* disable BM */
 386         pci_clear_master(adev->pdev);
 387
 388         amdgpu_device_cache_pci_state(adev->pdev);
 389
 390         if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
 391                 dev_info(adev->dev, "GPU smu mode1 reset\n");
 392                 ret = amdgpu_dpm_mode1_reset(adev);
 393         } else {
 394                 dev_info(adev->dev, "GPU psp mode1 reset\n");
 395                 ret = psp_gpu_reset(adev);
 396         }
 397
 398         if (ret)
 399                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 400         amdgpu_device_load_pci_state(adev->pdev);
 401
 402         /* wait for asic to come out of reset */
 403         for (i = 0; i < adev->usec_timeout; i++) {
 404                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 405
 406                 if (memsize != 0xffffffff)
 407                         break;
 408                 udelay(1);
 409         }
 410
 411         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 412
 413         return ret;
 414 }
 415 #endif
 416
 417 static enum amd_reset_method
 418 soc21_asic_reset_method(struct amdgpu_device *adev)
 419 {
 420         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 421             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 422             amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 423                 return amdgpu_reset_method;
 424
 425         if (amdgpu_reset_method != -1)
 426                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 427                                   amdgpu_reset_method);
 428
 429         switch (adev->ip_versions[MP1_HWIP][0]) {
 430         case IP_VERSION(13, 0, 0):
 431         case IP_VERSION(13, 0, 7):
 432         case IP_VERSION(13, 0, 10):
 433                 return AMD_RESET_METHOD_MODE1;
 434         case IP_VERSION(13, 0, 4):
 435         case IP_VERSION(13, 0, 11):
 436                 return AMD_RESET_METHOD_MODE2;
 437         default:
 438                 if (amdgpu_dpm_is_baco_supported(adev))
 439                         return AMD_RESET_METHOD_BACO;
 440                 else
 441                         return AMD_RESET_METHOD_MODE1;
 442         }
 443 }
 444
 445 static int soc21_asic_reset(struct amdgpu_device *adev)
 446 {
 447         int ret = 0;
 448
 449         switch (soc21_asic_reset_method(adev)) {
 450         case AMD_RESET_METHOD_PCI:
 451                 dev_info(adev->dev, "PCI reset\n");
 452                 ret = amdgpu_device_pci_reset(adev);
 453                 break;
 454         case AMD_RESET_METHOD_BACO:
 455                 dev_info(adev->dev, "BACO reset\n");
 456                 ret = amdgpu_dpm_baco_reset(adev);
 457                 break;
 458         case AMD_RESET_METHOD_MODE2:
 459                 dev_info(adev->dev, "MODE2 reset\n");
 460                 ret = amdgpu_dpm_mode2_reset(adev);
 461                 break;
 462         default:
 463                 dev_info(adev->dev, "MODE1 reset\n");
 464                 ret = amdgpu_device_mode1_reset(adev);
 465                 break;
 466         }
 467
 468         return ret;
 469 }
 470
 471 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 472 {
 473         /* todo */
 474         return 0;
 475 }
 476
 477 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 478 {
 479         /* todo */
 480         return 0;
 481 }
 482
 483 static void soc21_pcie_gen3_enable(struct amdgpu_device *adev)
 484 {
 485         if (pci_is_root_bus(adev->pdev->bus))
 486                 return;
 487
 488         if (amdgpu_pcie_gen2 == 0)
 489                 return;
 490
 491         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 492                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 493                 return;
 494
 495         /* todo */
 496 }
 497
 498 static void soc21_program_aspm(struct amdgpu_device *adev)
 499 {
 500         if (!amdgpu_device_should_use_aspm(adev))
 501                 return;
 502
 503         if (!(adev->flags & AMD_IS_APU) &&
 504             (adev->nbio.funcs->program_aspm))
 505                 adev->nbio.funcs->program_aspm(adev);
 506 }
 507
 508 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev,
 509                                         bool enable)
 510 {
 511         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 512         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 513 }
 514
 515 const struct amdgpu_ip_block_version soc21_common_ip_block =
 516 {
 517         .type = AMD_IP_BLOCK_TYPE_COMMON,
 518         .major = 1,
 519         .minor = 0,
 520         .rev = 0,
 521         .funcs = &soc21_common_ip_funcs,
 522 };
 523
 524 static uint32_t soc21_get_rev_id(struct amdgpu_device *adev)
 525 {
 526         return adev->nbio.funcs->get_rev_id(adev);
 527 }
 528
 529 static bool soc21_need_full_reset(struct amdgpu_device *adev)
 530 {
 531         switch (adev->ip_versions[GC_HWIP][0]) {
 532         case IP_VERSION(11, 0, 0):
 533                 return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);
 534         case IP_VERSION(11, 0, 2):
 535         case IP_VERSION(11, 0, 3):
 536                 return false;
 537         default:
 538                 return true;
 539         }
 540 }
 541
 542 static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
 543 {
 544         u32 sol_reg;
 545
 546         if (adev->flags & AMD_IS_APU)
 547                 return false;
 548
 549         /* Check sOS sign of life register to confirm sys driver and sOS
 550          * are already been loaded.
 551          */
 552         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 553         if (sol_reg)
 554                 return true;
 555
 556         return false;
 557 }
 558
 559 static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev)
 560 {
 561
 562         /* TODO
 563          * dummy implement for pcie_replay_count sysfs interface
 564          * */
 565
 566         return 0;
 567 }
 568
 569 static void soc21_init_doorbell_index(struct amdgpu_device *adev)
 570 {
 571         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 572         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 573         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 574         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 575         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 576         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 577         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 578         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 579         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 580         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 581         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 582         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 583         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 584         adev->doorbell_index.gfx_userqueue_start =
 585                 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
 586         adev->doorbell_index.gfx_userqueue_end =
 587                 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
 588         adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
 589         adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
 590         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 591         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 592         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 593         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 594         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 595         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 596         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 597         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 598         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 599
 600         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 601         adev->doorbell_index.sdma_doorbell_range = 20;
 602 }
 603
 604 static void soc21_pre_asic_init(struct amdgpu_device *adev)
 605 {
 606 }
 607
 608 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
 609                                           bool enter)
 610 {
 611         if (enter)
 612                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 613         else
 614                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 615
 616         if (adev->gfx.funcs->update_perfmon_mgcg)
 617                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 618
 619         return 0;
 620 }
 621
 622 static const struct amdgpu_asic_funcs soc21_asic_funcs =
 623 {
 624         .read_disabled_bios = &soc21_read_disabled_bios,
 625         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 626         .read_register = &soc21_read_register,
 627         .reset = &soc21_asic_reset,
 628         .reset_method = &soc21_asic_reset_method,
 629         .set_vga_state = &soc21_vga_set_state,
 630         .get_xclk = &soc21_get_xclk,
 631         .set_uvd_clocks = &soc21_set_uvd_clocks,
 632         .set_vce_clocks = &soc21_set_vce_clocks,
 633         .get_config_memsize = &soc21_get_config_memsize,
 634         .init_doorbell_index = &soc21_init_doorbell_index,
 635         .need_full_reset = &soc21_need_full_reset,
 636         .need_reset_on_init = &soc21_need_reset_on_init,
 637         .get_pcie_replay_count = &soc21_get_pcie_replay_count,
 638         .supports_baco = &amdgpu_dpm_is_baco_supported,
 639         .pre_asic_init = &soc21_pre_asic_init,
 640         .query_video_codecs = &soc21_query_video_codecs,
 641         .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
 642 };
 643
 644 static int soc21_common_early_init(void *handle)
 645 {
 646 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 647         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 648
 649         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 650         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 651         adev->smc_rreg = NULL;
 652         adev->smc_wreg = NULL;
 653         adev->pcie_rreg = &soc21_pcie_rreg;
 654         adev->pcie_wreg = &soc21_pcie_wreg;
 655         adev->pcie_rreg64 = &soc21_pcie_rreg64;
 656         adev->pcie_wreg64 = &soc21_pcie_wreg64;
 657         adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
 658         adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
 659
 660         /* TODO: will add them during VCN v2 implementation */
 661         adev->uvd_ctx_rreg = NULL;
 662         adev->uvd_ctx_wreg = NULL;
 663
 664         adev->didt_rreg = &soc21_didt_rreg;
 665         adev->didt_wreg = &soc21_didt_wreg;
 666
 667         adev->asic_funcs = &soc21_asic_funcs;
 668
 669         adev->rev_id = soc21_get_rev_id(adev);
 670         adev->external_rev_id = 0xff;
 671         switch (adev->ip_versions[GC_HWIP][0]) {
 672         case IP_VERSION(11, 0, 0):
 673                 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
 674                         AMD_CG_SUPPORT_GFX_CGLS |
 675 #if 0
 676                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 677                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 678 #endif
 679                         AMD_CG_SUPPORT_GFX_MGCG |
 680                         AMD_CG_SUPPORT_REPEATER_FGCG |
 681                         AMD_CG_SUPPORT_GFX_FGCG |
 682                         AMD_CG_SUPPORT_GFX_PERF_CLK |
 683                         AMD_CG_SUPPORT_VCN_MGCG |
 684                         AMD_CG_SUPPORT_JPEG_MGCG |
 685                         AMD_CG_SUPPORT_ATHUB_MGCG |
 686                         AMD_CG_SUPPORT_ATHUB_LS |
 687                         AMD_CG_SUPPORT_MC_MGCG |
 688                         AMD_CG_SUPPORT_MC_LS |
 689                         AMD_CG_SUPPORT_IH_CG |
 690                         AMD_CG_SUPPORT_HDP_SD;
 691                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 692                         AMD_PG_SUPPORT_VCN_DPG |
 693                         AMD_PG_SUPPORT_JPEG |
 694                         AMD_PG_SUPPORT_ATHUB |
 695                         AMD_PG_SUPPORT_MMHUB;
 696                 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
 697                 break;
 698         case IP_VERSION(11, 0, 2):
 699                 adev->cg_flags =
 700                         AMD_CG_SUPPORT_GFX_CGCG |
 701                         AMD_CG_SUPPORT_GFX_CGLS |
 702                         AMD_CG_SUPPORT_REPEATER_FGCG |
 703                         AMD_CG_SUPPORT_VCN_MGCG |
 704                         AMD_CG_SUPPORT_JPEG_MGCG |
 705                         AMD_CG_SUPPORT_ATHUB_MGCG |
 706                         AMD_CG_SUPPORT_ATHUB_LS |
 707                         AMD_CG_SUPPORT_IH_CG |
 708                         AMD_CG_SUPPORT_HDP_SD;
 709                 adev->pg_flags =
 710                         AMD_PG_SUPPORT_VCN |
 711                         AMD_PG_SUPPORT_VCN_DPG |
 712                         AMD_PG_SUPPORT_JPEG |
 713                         AMD_PG_SUPPORT_ATHUB |
 714                         AMD_PG_SUPPORT_MMHUB;
 715                 adev->external_rev_id = adev->rev_id + 0x10;
 716                 break;
 717         case IP_VERSION(11, 0, 1):
 718                 adev->cg_flags =
 719                         AMD_CG_SUPPORT_GFX_CGCG |
 720                         AMD_CG_SUPPORT_GFX_CGLS |
 721                         AMD_CG_SUPPORT_GFX_MGCG |
 722                         AMD_CG_SUPPORT_GFX_FGCG |
 723                         AMD_CG_SUPPORT_REPEATER_FGCG |
 724                         AMD_CG_SUPPORT_GFX_PERF_CLK |
 725                         AMD_CG_SUPPORT_MC_MGCG |
 726                         AMD_CG_SUPPORT_MC_LS |
 727                         AMD_CG_SUPPORT_HDP_MGCG |
 728                         AMD_CG_SUPPORT_HDP_LS |
 729                         AMD_CG_SUPPORT_ATHUB_MGCG |
 730                         AMD_CG_SUPPORT_ATHUB_LS |
 731                         AMD_CG_SUPPORT_IH_CG |
 732                         AMD_CG_SUPPORT_BIF_MGCG |
 733                         AMD_CG_SUPPORT_BIF_LS |
 734                         AMD_CG_SUPPORT_VCN_MGCG |
 735                         AMD_CG_SUPPORT_JPEG_MGCG;
 736                 adev->pg_flags =
 737                         AMD_PG_SUPPORT_GFX_PG |
 738                         AMD_PG_SUPPORT_VCN |
 739                         AMD_PG_SUPPORT_VCN_DPG |
 740                         AMD_PG_SUPPORT_JPEG;
 741                 adev->external_rev_id = adev->rev_id + 0x1;
 742                 break;
 743         case IP_VERSION(11, 0, 3):
 744                 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
 745                         AMD_CG_SUPPORT_JPEG_MGCG |
 746                         AMD_CG_SUPPORT_GFX_CGCG |
 747                         AMD_CG_SUPPORT_GFX_CGLS |
 748                         AMD_CG_SUPPORT_REPEATER_FGCG |
 749                         AMD_CG_SUPPORT_GFX_MGCG |
 750                         AMD_CG_SUPPORT_HDP_SD |
 751                         AMD_CG_SUPPORT_ATHUB_MGCG |
 752                         AMD_CG_SUPPORT_ATHUB_LS;
 753                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 754                         AMD_PG_SUPPORT_VCN_DPG |
 755                         AMD_PG_SUPPORT_JPEG;
 756                 adev->external_rev_id = adev->rev_id + 0x20;
 757                 break;
 758         case IP_VERSION(11, 0, 4):
 759                 adev->cg_flags =
 760                         AMD_CG_SUPPORT_GFX_CGCG |
 761                         AMD_CG_SUPPORT_GFX_CGLS |
 762                         AMD_CG_SUPPORT_GFX_MGCG |
 763                         AMD_CG_SUPPORT_GFX_FGCG |
 764                         AMD_CG_SUPPORT_REPEATER_FGCG |
 765                         AMD_CG_SUPPORT_GFX_PERF_CLK |
 766                         AMD_CG_SUPPORT_MC_MGCG |
 767                         AMD_CG_SUPPORT_MC_LS |
 768                         AMD_CG_SUPPORT_HDP_MGCG |
 769                         AMD_CG_SUPPORT_HDP_LS |
 770                         AMD_CG_SUPPORT_ATHUB_MGCG |
 771                         AMD_CG_SUPPORT_ATHUB_LS |
 772                         AMD_CG_SUPPORT_IH_CG |
 773                         AMD_CG_SUPPORT_BIF_MGCG |
 774                         AMD_CG_SUPPORT_BIF_LS |
 775                         AMD_CG_SUPPORT_VCN_MGCG |
 776                         AMD_CG_SUPPORT_JPEG_MGCG;
 777                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 778                         AMD_PG_SUPPORT_VCN_DPG |
 779                         AMD_PG_SUPPORT_GFX_PG |
 780                         AMD_PG_SUPPORT_JPEG;
 781                 adev->external_rev_id = adev->rev_id + 0x1;
 782                 break;
 783
 784         default:
 785                 /* FIXME: not supported yet */
 786                 return -EINVAL;
 787         }
 788
 789         if (amdgpu_sriov_vf(adev)) {
 790                 amdgpu_virt_init_setting(adev);
 791                 xgpu_nv_mailbox_set_irq_funcs(adev);
 792         }
 793
 794         return 0;
 795 }
 796
 797 static int soc21_common_late_init(void *handle)
 798 {
 799         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 800
 801         if (amdgpu_sriov_vf(adev)) {
 802                 xgpu_nv_mailbox_get_irq(adev);
 803                 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
 804                 !amdgpu_sriov_is_av1_support(adev)) {
 805                         amdgpu_virt_update_sriov_video_codec(adev,
 806                                                              sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
 807                                                              ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
 808                                                              sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
 809                                                              ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
 810                 } else {
 811                         amdgpu_virt_update_sriov_video_codec(adev,
 812                                                              sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
 813                                                              ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
 814                                                              sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
 815                                                              ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
 816                 }
 817         }
 818
 819         return 0;
 820 }
 821
 822 static int soc21_common_sw_init(void *handle)
 823 {
 824         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 825
 826         if (amdgpu_sriov_vf(adev))
 827                 xgpu_nv_mailbox_add_irq_id(adev);
 828
 829         return 0;
 830 }
 831
 832 static int soc21_common_sw_fini(void *handle)
 833 {
 834         return 0;
 835 }
 836
 837 static int soc21_common_hw_init(void *handle)
 838 {
 839         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 840
 841         /* enable pcie gen2/3 link */
 842         soc21_pcie_gen3_enable(adev);
 843         /* enable aspm */
 844         soc21_program_aspm(adev);
 845         /* setup nbio registers */
 846         adev->nbio.funcs->init_registers(adev);
 847         /* remap HDP registers to a hole in mmio space,
 848          * for the purpose of expose those registers
 849          * to process space
 850          */
 851         if (adev->nbio.funcs->remap_hdp_registers)
 852                 adev->nbio.funcs->remap_hdp_registers(adev);
 853         /* enable the doorbell aperture */
 854         soc21_enable_doorbell_aperture(adev, true);
 855
 856         return 0;
 857 }
 858
 859 static int soc21_common_hw_fini(void *handle)
 860 {
 861         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 862
 863         /* disable the doorbell aperture */
 864         soc21_enable_doorbell_aperture(adev, false);
 865
 866         if (amdgpu_sriov_vf(adev))
 867                 xgpu_nv_mailbox_put_irq(adev);
 868
 869         return 0;
 870 }
 871
 872 static int soc21_common_suspend(void *handle)
 873 {
 874         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 875
 876         return soc21_common_hw_fini(adev);
 877 }
 878
 879 static int soc21_common_resume(void *handle)
 880 {
 881         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 882
 883         return soc21_common_hw_init(adev);
 884 }
 885
 886 static bool soc21_common_is_idle(void *handle)
 887 {
 888         return true;
 889 }
 890
 891 static int soc21_common_wait_for_idle(void *handle)
 892 {
 893         return 0;
 894 }
 895
 896 static int soc21_common_soft_reset(void *handle)
 897 {
 898         return 0;
 899 }
 900
 901 static int soc21_common_set_clockgating_state(void *handle,
 902                                            enum amd_clockgating_state state)
 903 {
 904         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 905
 906         switch (adev->ip_versions[NBIO_HWIP][0]) {
 907         case IP_VERSION(4, 3, 0):
 908         case IP_VERSION(4, 3, 1):
 909         case IP_VERSION(7, 7, 0):
 910                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
 911                                 state == AMD_CG_STATE_GATE);
 912                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
 913                                 state == AMD_CG_STATE_GATE);
 914                 adev->hdp.funcs->update_clock_gating(adev,
 915                                 state == AMD_CG_STATE_GATE);
 916                 break;
 917         default:
 918                 break;
 919         }
 920         return 0;
 921 }
 922
 923 static int soc21_common_set_powergating_state(void *handle,
 924                                            enum amd_powergating_state state)
 925 {
 926         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 927
 928         switch (adev->ip_versions[LSDMA_HWIP][0]) {
 929         case IP_VERSION(6, 0, 0):
 930         case IP_VERSION(6, 0, 2):
 931                 adev->lsdma.funcs->update_memory_power_gating(adev,
 932                                 state == AMD_PG_STATE_GATE);
 933                 break;
 934         default:
 935                 break;
 936         }
 937
 938         return 0;
 939 }
 940
 941 static void soc21_common_get_clockgating_state(void *handle, u64 *flags)
 942 {
 943         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 944
 945         adev->nbio.funcs->get_clockgating_state(adev, flags);
 946
 947         adev->hdp.funcs->get_clock_gating_state(adev, flags);
 948
 949         return;
 950 }
 951
 952 static const struct amd_ip_funcs soc21_common_ip_funcs = {
 953         .name = "soc21_common",
 954         .early_init = soc21_common_early_init,
 955         .late_init = soc21_common_late_init,
 956         .sw_init = soc21_common_sw_init,
 957         .sw_fini = soc21_common_sw_fini,
 958         .hw_init = soc21_common_hw_init,
 959         .hw_fini = soc21_common_hw_fini,
 960         .suspend = soc21_common_suspend,
 961         .resume = soc21_common_resume,
 962         .is_idle = soc21_common_is_idle,
 963         .wait_for_idle = soc21_common_wait_for_idle,
 964         .soft_reset = soc21_common_soft_reset,
 965         .set_clockgating_state = soc21_common_set_clockgating_state,
 966         .set_powergating_state = soc21_common_set_powergating_state,
 967         .get_clockgating_state = soc21_common_get_clockgating_state,
 968 };