drivers/gpu/drm/omapdrm/omap_drv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   4  * Author: Rob Clark <[email protected]>
   5  */
   6
   7 #include <linux/of.h>
   8 #include <linux/sort.h>
   9 #include <linux/sys_soc.h>
  10
  11 #include <drm/drm_atomic.h>
  12 #include <drm/drm_atomic_helper.h>
  13 #include <drm/drm_fb_helper.h>
  14 #include <drm/drm_probe_helper.h>
  15 #include <drm/drm_panel.h>
  16
  17 #include "omap_dmm_tiler.h"
  18 #include "omap_drv.h"
  19
  20 #define DRIVER_NAME             MODULE_NAME
  21 #define DRIVER_DESC             "OMAP DRM"
  22 #define DRIVER_DATE             "20110917"
  23 #define DRIVER_MAJOR            1
  24 #define DRIVER_MINOR            0
  25 #define DRIVER_PATCHLEVEL       0
  26
  27 /*
  28  * mode config funcs
  29  */
  30
  31 /* Notes about mapping DSS and DRM entities:
  32  *    CRTC:        overlay
  33  *    encoder:     manager.. with some extension to allow one primary CRTC
  34  *                 and zero or more video CRTC's to be mapped to one encoder?
  35  *    connector:   dssdev.. manager can be attached/detached from different
  36  *                 devices
  37  */
  38
  39 static void omap_atomic_wait_for_completion(struct drm_device *dev,
  40                                             struct drm_atomic_state *old_state)
  41 {
  42         struct drm_crtc_state *new_crtc_state;
  43         struct drm_crtc *crtc;
  44         unsigned int i;
  45         int ret;
  46
  47         for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
  48                 if (!new_crtc_state->active)
  49                         continue;
  50
  51                 ret = omap_crtc_wait_pending(crtc);
  52
  53                 if (!ret)
  54                         dev_warn(dev->dev,
  55                                  "atomic complete timeout (pipe %u)!\n", i);
  56         }
  57 }
  58
  59 static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
  60 {
  61         struct drm_device *dev = old_state->dev;
  62         struct omap_drm_private *priv = dev->dev_private;
  63
  64         priv->dispc_ops->runtime_get(priv->dispc);
  65
  66         /* Apply the atomic update. */
  67         drm_atomic_helper_commit_modeset_disables(dev, old_state);
  68
  69         if (priv->omaprev != 0x3430) {
  70                 /* With the current dss dispc implementation we have to enable
  71                  * the new modeset before we can commit planes. The dispc ovl
  72                  * configuration relies on the video mode configuration been
  73                  * written into the HW when the ovl configuration is
  74                  * calculated.
  75                  *
  76                  * This approach is not ideal because after a mode change the
  77                  * plane update is executed only after the first vblank
  78                  * interrupt. The dispc implementation should be fixed so that
  79                  * it is able use uncommitted drm state information.
  80                  */
  81                 drm_atomic_helper_commit_modeset_enables(dev, old_state);
  82                 omap_atomic_wait_for_completion(dev, old_state);
  83
  84                 drm_atomic_helper_commit_planes(dev, old_state, 0);
  85
  86                 drm_atomic_helper_commit_hw_done(old_state);
  87         } else {
  88                 /*
  89                  * OMAP3 DSS seems to have issues with the work-around above,
  90                  * resulting in endless sync losts if a crtc is enabled without
  91                  * a plane. For now, skip the WA for OMAP3.
  92                  */
  93                 drm_atomic_helper_commit_planes(dev, old_state, 0);
  94
  95                 drm_atomic_helper_commit_modeset_enables(dev, old_state);
  96
  97                 drm_atomic_helper_commit_hw_done(old_state);
  98         }
  99
 100         /*
 101          * Wait for completion of the page flips to ensure that old buffers
 102          * can't be touched by the hardware anymore before cleaning up planes.
 103          */
 104         omap_atomic_wait_for_completion(dev, old_state);
 105
 106         drm_atomic_helper_cleanup_planes(dev, old_state);
 107
 108         priv->dispc_ops->runtime_put(priv->dispc);
 109 }
 110
 111 static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
 112         .atomic_commit_tail = omap_atomic_commit_tail,
 113 };
 114
 115 static const struct drm_mode_config_funcs omap_mode_config_funcs = {
 116         .fb_create = omap_framebuffer_create,
 117         .output_poll_changed = drm_fb_helper_output_poll_changed,
 118         .atomic_check = drm_atomic_helper_check,
 119         .atomic_commit = drm_atomic_helper_commit,
 120 };
 121
 122 static void omap_disconnect_pipelines(struct drm_device *ddev)
 123 {
 124         struct omap_drm_private *priv = ddev->dev_private;
 125         unsigned int i;
 126
 127         for (i = 0; i < priv->num_pipes; i++) {
 128                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 129
 130                 if (pipe->output->panel)
 131                         drm_panel_detach(pipe->output->panel);
 132
 133                 omapdss_device_disconnect(NULL, pipe->output);
 134
 135                 omapdss_device_put(pipe->output);
 136                 pipe->output = NULL;
 137         }
 138
 139         memset(&priv->channels, 0, sizeof(priv->channels));
 140
 141         priv->num_pipes = 0;
 142 }
 143
 144 static int omap_connect_pipelines(struct drm_device *ddev)
 145 {
 146         struct omap_drm_private *priv = ddev->dev_private;
 147         struct omap_dss_device *output = NULL;
 148         int r;
 149
 150         for_each_dss_output(output) {
 151                 r = omapdss_device_connect(priv->dss, NULL, output);
 152                 if (r == -EPROBE_DEFER) {
 153                         omapdss_device_put(output);
 154                         return r;
 155                 } else if (r) {
 156                         dev_warn(output->dev, "could not connect output %s\n",
 157                                  output->name);
 158                 } else {
 159                         struct omap_drm_pipeline *pipe;
 160
 161                         pipe = &priv->pipes[priv->num_pipes++];
 162                         pipe->output = omapdss_device_get(output);
 163
 164                         if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) {
 165                                 /* To balance the 'for_each_dss_output' loop */
 166                                 omapdss_device_put(output);
 167                                 break;
 168                         }
 169                 }
 170         }
 171
 172         return 0;
 173 }
 174
 175 static int omap_compare_pipelines(const void *a, const void *b)
 176 {
 177         const struct omap_drm_pipeline *pipe1 = a;
 178         const struct omap_drm_pipeline *pipe2 = b;
 179
 180         if (pipe1->alias_id > pipe2->alias_id)
 181                 return 1;
 182         else if (pipe1->alias_id < pipe2->alias_id)
 183                 return -1;
 184         return 0;
 185 }
 186
 187 static int omap_modeset_init_properties(struct drm_device *dev)
 188 {
 189         struct omap_drm_private *priv = dev->dev_private;
 190         unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc);
 191
 192         priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
 193                                                       num_planes - 1);
 194         if (!priv->zorder_prop)
 195                 return -ENOMEM;
 196
 197         return 0;
 198 }
 199
 200 static int omap_display_id(struct omap_dss_device *output)
 201 {
 202         struct device_node *node = NULL;
 203
 204         if (output->next) {
 205                 struct omap_dss_device *display;
 206
 207                 display = omapdss_display_get(output);
 208                 node = display->dev->of_node;
 209                 omapdss_device_put(display);
 210         } else if (output->bridge) {
 211                 struct drm_bridge *bridge = output->bridge;
 212
 213                 while (bridge->next)
 214                         bridge = bridge->next;
 215
 216                 node = bridge->of_node;
 217         } else if (output->panel) {
 218                 node = output->panel->dev->of_node;
 219         }
 220
 221         return node ? of_alias_get_id(node, "display") : -ENODEV;
 222 }
 223
 224 static int omap_modeset_init(struct drm_device *dev)
 225 {
 226         struct omap_drm_private *priv = dev->dev_private;
 227         int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc);
 228         int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
 229         unsigned int i;
 230         int ret;
 231         u32 plane_crtc_mask;
 232
 233         if (!omapdss_stack_is_ready())
 234                 return -EPROBE_DEFER;
 235
 236         drm_mode_config_init(dev);
 237
 238         ret = omap_modeset_init_properties(dev);
 239         if (ret < 0)
 240                 return ret;
 241
 242         /*
 243          * This function creates exactly one connector, encoder, crtc,
 244          * and primary plane per each connected dss-device. Each
 245          * connector->encoder->crtc chain is expected to be separate
 246          * and each crtc is connect to a single dss-channel. If the
 247          * configuration does not match the expectations or exceeds
 248          * the available resources, the configuration is rejected.
 249          */
 250         ret = omap_connect_pipelines(dev);
 251         if (ret < 0)
 252                 return ret;
 253
 254         if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) {
 255                 dev_err(dev->dev, "%s(): Too many connected displays\n",
 256                         __func__);
 257                 return -EINVAL;
 258         }
 259
 260         /* Create all planes first. They can all be put to any CRTC. */
 261         plane_crtc_mask = (1 << priv->num_pipes) - 1;
 262
 263         for (i = 0; i < num_ovls; i++) {
 264                 enum drm_plane_type type = i < priv->num_pipes
 265                                          ? DRM_PLANE_TYPE_PRIMARY
 266                                          : DRM_PLANE_TYPE_OVERLAY;
 267                 struct drm_plane *plane;
 268
 269                 if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
 270                         return -EINVAL;
 271
 272                 plane = omap_plane_init(dev, i, type, plane_crtc_mask);
 273                 if (IS_ERR(plane))
 274                         return PTR_ERR(plane);
 275
 276                 priv->planes[priv->num_planes++] = plane;
 277         }
 278
 279         /*
 280          * Create the encoders, attach the bridges and get the pipeline alias
 281          * IDs.
 282          */
 283         for (i = 0; i < priv->num_pipes; i++) {
 284                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 285                 int id;
 286
 287                 pipe->encoder = omap_encoder_init(dev, pipe->output);
 288                 if (!pipe->encoder)
 289                         return -ENOMEM;
 290
 291                 if (pipe->output->bridge) {
 292                         ret = drm_bridge_attach(pipe->encoder,
 293                                                 pipe->output->bridge, NULL);
 294                         if (ret < 0)
 295                                 return ret;
 296                 }
 297
 298                 id = omap_display_id(pipe->output);
 299                 pipe->alias_id = id >= 0 ? id : i;
 300         }
 301
 302         /* Sort the pipelines by DT aliases. */
 303         sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]),
 304              omap_compare_pipelines, NULL);
 305
 306         /*
 307          * Populate the pipeline lookup table by DISPC channel. Only one display
 308          * is allowed per channel.
 309          */
 310         for (i = 0; i < priv->num_pipes; ++i) {
 311                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 312                 enum omap_channel channel = pipe->output->dispc_channel;
 313
 314                 if (WARN_ON(priv->channels[channel] != NULL))
 315                         return -EINVAL;
 316
 317                 priv->channels[channel] = pipe;
 318         }
 319
 320         /* Create the connectors and CRTCs. */
 321         for (i = 0; i < priv->num_pipes; i++) {
 322                 struct omap_drm_pipeline *pipe = &priv->pipes[i];
 323                 struct drm_encoder *encoder = pipe->encoder;
 324                 struct drm_crtc *crtc;
 325
 326                 if (!pipe->output->bridge) {
 327                         pipe->connector = omap_connector_init(dev, pipe->output,
 328                                                               encoder);
 329                         if (!pipe->connector)
 330                                 return -ENOMEM;
 331
 332                         drm_connector_attach_encoder(pipe->connector, encoder);
 333
 334                         if (pipe->output->panel) {
 335                                 ret = drm_panel_attach(pipe->output->panel,
 336                                                        pipe->connector);
 337                                 if (ret < 0)
 338                                         return ret;
 339                         }
 340                 }
 341
 342                 crtc = omap_crtc_init(dev, pipe, priv->planes[i]);
 343                 if (IS_ERR(crtc))
 344                         return PTR_ERR(crtc);
 345
 346                 encoder->possible_crtcs = 1 << i;
 347                 pipe->crtc = crtc;
 348         }
 349
 350         DBG("registered %u planes, %u crtcs/encoders/connectors\n",
 351             priv->num_planes, priv->num_pipes);
 352
 353         dev->mode_config.min_width = 8;
 354         dev->mode_config.min_height = 2;
 355
 356         /*
 357          * Note: these values are used for multiple independent things:
 358          * connector mode filtering, buffer sizes, crtc sizes...
 359          * Use big enough values here to cover all use cases, and do more
 360          * specific checking in the respective code paths.
 361          */
 362         dev->mode_config.max_width = 8192;
 363         dev->mode_config.max_height = 8192;
 364
 365         /* We want the zpos to be normalized */
 366         dev->mode_config.normalize_zpos = true;
 367
 368         dev->mode_config.funcs = &omap_mode_config_funcs;
 369         dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
 370
 371         drm_mode_config_reset(dev);
 372
 373         omap_drm_irq_install(dev);
 374
 375         return 0;
 376 }
 377
 378 /*
 379  * Enable the HPD in external components if supported
 380  */
 381 static void omap_modeset_enable_external_hpd(struct drm_device *ddev)
 382 {
 383         struct omap_drm_private *priv = ddev->dev_private;
 384         unsigned int i;
 385
 386         for (i = 0; i < priv->num_pipes; i++) {
 387                 if (priv->pipes[i].connector)
 388                         omap_connector_enable_hpd(priv->pipes[i].connector);
 389         }
 390 }
 391
 392 /*
 393  * Disable the HPD in external components if supported
 394  */
 395 static void omap_modeset_disable_external_hpd(struct drm_device *ddev)
 396 {
 397         struct omap_drm_private *priv = ddev->dev_private;
 398         unsigned int i;
 399
 400         for (i = 0; i < priv->num_pipes; i++) {
 401                 if (priv->pipes[i].connector)
 402                         omap_connector_disable_hpd(priv->pipes[i].connector);
 403         }
 404 }
 405
 406 /*
 407  * drm ioctl funcs
 408  */
 409
 410
 411 static int ioctl_get_param(struct drm_device *dev, void *data,
 412                 struct drm_file *file_priv)
 413 {
 414         struct omap_drm_private *priv = dev->dev_private;
 415         struct drm_omap_param *args = data;
 416
 417         DBG("%p: param=%llu", dev, args->param);
 418
 419         switch (args->param) {
 420         case OMAP_PARAM_CHIPSET_ID:
 421                 args->value = priv->omaprev;
 422                 break;
 423         default:
 424                 DBG("unknown parameter %lld", args->param);
 425                 return -EINVAL;
 426         }
 427
 428         return 0;
 429 }
 430
 431 static int ioctl_set_param(struct drm_device *dev, void *data,
 432                 struct drm_file *file_priv)
 433 {
 434         struct drm_omap_param *args = data;
 435
 436         switch (args->param) {
 437         default:
 438                 DBG("unknown parameter %lld", args->param);
 439                 return -EINVAL;
 440         }
 441
 442         return 0;
 443 }
 444
 445 #define OMAP_BO_USER_MASK       0x00ffffff      /* flags settable by userspace */
 446
 447 static int ioctl_gem_new(struct drm_device *dev, void *data,
 448                 struct drm_file *file_priv)
 449 {
 450         struct drm_omap_gem_new *args = data;
 451         u32 flags = args->flags & OMAP_BO_USER_MASK;
 452
 453         VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
 454              args->size.bytes, flags);
 455
 456         return omap_gem_new_handle(dev, file_priv, args->size, flags,
 457                                    &args->handle);
 458 }
 459
 460 static int ioctl_gem_info(struct drm_device *dev, void *data,
 461                 struct drm_file *file_priv)
 462 {
 463         struct drm_omap_gem_info *args = data;
 464         struct drm_gem_object *obj;
 465         int ret = 0;
 466
 467         VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
 468
 469         obj = drm_gem_object_lookup(file_priv, args->handle);
 470         if (!obj)
 471                 return -ENOENT;
 472
 473         args->size = omap_gem_mmap_size(obj);
 474         args->offset = omap_gem_mmap_offset(obj);
 475
 476         drm_gem_object_put_unlocked(obj);
 477
 478         return ret;
 479 }
 480
 481 static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
 482         DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
 483                           DRM_AUTH | DRM_RENDER_ALLOW),
 484         DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param,
 485                           DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
 486         DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
 487                           DRM_AUTH | DRM_RENDER_ALLOW),
 488         /* Deprecated, to be removed. */
 489         DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
 490                           DRM_AUTH | DRM_RENDER_ALLOW),
 491         /* Deprecated, to be removed. */
 492         DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
 493                           DRM_AUTH | DRM_RENDER_ALLOW),
 494         DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
 495                           DRM_AUTH | DRM_RENDER_ALLOW),
 496 };
 497
 498 /*
 499  * drm driver funcs
 500  */
 501
 502 static int dev_open(struct drm_device *dev, struct drm_file *file)
 503 {
 504         file->driver_priv = NULL;
 505
 506         DBG("open: dev=%p, file=%p", dev, file);
 507
 508         return 0;
 509 }
 510
 511 static const struct vm_operations_struct omap_gem_vm_ops = {
 512         .fault = omap_gem_fault,
 513         .open = drm_gem_vm_open,
 514         .close = drm_gem_vm_close,
 515 };
 516
 517 static const struct file_operations omapdriver_fops = {
 518         .owner = THIS_MODULE,
 519         .open = drm_open,
 520         .unlocked_ioctl = drm_ioctl,
 521         .compat_ioctl = drm_compat_ioctl,
 522         .release = drm_release,
 523         .mmap = omap_gem_mmap,
 524         .poll = drm_poll,
 525         .read = drm_read,
 526         .llseek = noop_llseek,
 527 };
 528
 529 static struct drm_driver omap_drm_driver = {
 530         .driver_features = DRIVER_MODESET | DRIVER_GEM  | DRIVER_PRIME |
 531                 DRIVER_ATOMIC | DRIVER_RENDER,
 532         .open = dev_open,
 533         .lastclose = drm_fb_helper_lastclose,
 534 #ifdef CONFIG_DEBUG_FS
 535         .debugfs_init = omap_debugfs_init,
 536 #endif
 537         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 538         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 539         .gem_prime_export = omap_gem_prime_export,
 540         .gem_prime_import = omap_gem_prime_import,
 541         .gem_free_object_unlocked = omap_gem_free_object,
 542         .gem_vm_ops = &omap_gem_vm_ops,
 543         .dumb_create = omap_gem_dumb_create,
 544         .dumb_map_offset = omap_gem_dumb_map_offset,
 545         .ioctls = ioctls,
 546         .num_ioctls = DRM_OMAP_NUM_IOCTLS,
 547         .fops = &omapdriver_fops,
 548         .name = DRIVER_NAME,
 549         .desc = DRIVER_DESC,
 550         .date = DRIVER_DATE,
 551         .major = DRIVER_MAJOR,
 552         .minor = DRIVER_MINOR,
 553         .patchlevel = DRIVER_PATCHLEVEL,
 554 };
 555
 556 static const struct soc_device_attribute omapdrm_soc_devices[] = {
 557         { .family = "OMAP3", .data = (void *)0x3430 },
 558         { .family = "OMAP4", .data = (void *)0x4430 },
 559         { .family = "OMAP5", .data = (void *)0x5430 },
 560         { .family = "DRA7",  .data = (void *)0x0752 },
 561         { /* sentinel */ }
 562 };
 563
 564 static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
 565 {
 566         const struct soc_device_attribute *soc;
 567         struct drm_device *ddev;
 568         unsigned int i;
 569         int ret;
 570
 571         DBG("%s", dev_name(dev));
 572
 573         /* Allocate and initialize the DRM device. */
 574         ddev = drm_dev_alloc(&omap_drm_driver, dev);
 575         if (IS_ERR(ddev))
 576                 return PTR_ERR(ddev);
 577
 578         priv->ddev = ddev;
 579         ddev->dev_private = priv;
 580
 581         priv->dev = dev;
 582         priv->dss = omapdss_get_dss();
 583         priv->dispc = dispc_get_dispc(priv->dss);
 584         priv->dispc_ops = dispc_get_ops(priv->dss);
 585
 586         omap_crtc_pre_init(priv);
 587
 588         soc = soc_device_match(omapdrm_soc_devices);
 589         priv->omaprev = soc ? (unsigned int)soc->data : 0;
 590         priv->wq = alloc_ordered_workqueue("omapdrm", 0);
 591
 592         mutex_init(&priv->list_lock);
 593         INIT_LIST_HEAD(&priv->obj_list);
 594
 595         /* Get memory bandwidth limits */
 596         if (priv->dispc_ops->get_memory_bandwidth_limit)
 597                 priv->max_bandwidth =
 598                         priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc);
 599
 600         omap_gem_init(ddev);
 601
 602         ret = omap_modeset_init(ddev);
 603         if (ret) {
 604                 dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
 605                 goto err_gem_deinit;
 606         }
 607
 608         /* Initialize vblank handling, start with all CRTCs disabled. */
 609         ret = drm_vblank_init(ddev, priv->num_pipes);
 610         if (ret) {
 611                 dev_err(priv->dev, "could not init vblank\n");
 612                 goto err_cleanup_modeset;
 613         }
 614
 615         for (i = 0; i < priv->num_pipes; i++)
 616                 drm_crtc_vblank_off(priv->pipes[i].crtc);
 617
 618         omap_fbdev_init(ddev);
 619
 620         drm_kms_helper_poll_init(ddev);
 621         omap_modeset_enable_external_hpd(ddev);
 622
 623         /*
 624          * Register the DRM device with the core and the connectors with
 625          * sysfs.
 626          */
 627         ret = drm_dev_register(ddev, 0);
 628         if (ret)
 629                 goto err_cleanup_helpers;
 630
 631         return 0;
 632
 633 err_cleanup_helpers:
 634         omap_modeset_disable_external_hpd(ddev);
 635         drm_kms_helper_poll_fini(ddev);
 636
 637         omap_fbdev_fini(ddev);
 638 err_cleanup_modeset:
 639         drm_mode_config_cleanup(ddev);
 640         omap_drm_irq_uninstall(ddev);
 641 err_gem_deinit:
 642         omap_gem_deinit(ddev);
 643         destroy_workqueue(priv->wq);
 644         omap_disconnect_pipelines(ddev);
 645         omap_crtc_pre_uninit(priv);
 646         drm_dev_put(ddev);
 647         return ret;
 648 }
 649
 650 static void omapdrm_cleanup(struct omap_drm_private *priv)
 651 {
 652         struct drm_device *ddev = priv->ddev;
 653
 654         DBG("");
 655
 656         drm_dev_unregister(ddev);
 657
 658         omap_modeset_disable_external_hpd(ddev);
 659         drm_kms_helper_poll_fini(ddev);
 660
 661         omap_fbdev_fini(ddev);
 662
 663         drm_atomic_helper_shutdown(ddev);
 664
 665         drm_mode_config_cleanup(ddev);
 666
 667         omap_drm_irq_uninstall(ddev);
 668         omap_gem_deinit(ddev);
 669
 670         destroy_workqueue(priv->wq);
 671
 672         omap_disconnect_pipelines(ddev);
 673         omap_crtc_pre_uninit(priv);
 674
 675         drm_dev_put(ddev);
 676 }
 677
 678 static int pdev_probe(struct platform_device *pdev)
 679 {
 680         struct omap_drm_private *priv;
 681         int ret;
 682
 683         if (omapdss_is_initialized() == false)
 684                 return -EPROBE_DEFER;
 685
 686         ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 687         if (ret) {
 688                 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
 689                 return ret;
 690         }
 691
 692         /* Allocate and initialize the driver private structure. */
 693         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 694         if (!priv)
 695                 return -ENOMEM;
 696
 697         platform_set_drvdata(pdev, priv);
 698
 699         ret = omapdrm_init(priv, &pdev->dev);
 700         if (ret < 0)
 701                 kfree(priv);
 702
 703         return ret;
 704 }
 705
 706 static int pdev_remove(struct platform_device *pdev)
 707 {
 708         struct omap_drm_private *priv = platform_get_drvdata(pdev);
 709
 710         omapdrm_cleanup(priv);
 711         kfree(priv);
 712
 713         return 0;
 714 }
 715
 716 #ifdef CONFIG_PM_SLEEP
 717 static int omap_drm_suspend(struct device *dev)
 718 {
 719         struct omap_drm_private *priv = dev_get_drvdata(dev);
 720         struct drm_device *drm_dev = priv->ddev;
 721
 722         return drm_mode_config_helper_suspend(drm_dev);
 723 }
 724
 725 static int omap_drm_resume(struct device *dev)
 726 {
 727         struct omap_drm_private *priv = dev_get_drvdata(dev);
 728         struct drm_device *drm_dev = priv->ddev;
 729
 730         drm_mode_config_helper_resume(drm_dev);
 731
 732         return omap_gem_resume(drm_dev);
 733 }
 734 #endif
 735
 736 static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
 737
 738 static struct platform_driver pdev = {
 739         .driver = {
 740                 .name = "omapdrm",
 741                 .pm = &omapdrm_pm_ops,
 742         },
 743         .probe = pdev_probe,
 744         .remove = pdev_remove,
 745 };
 746
 747 static struct platform_driver * const drivers[] = {
 748         &omap_dmm_driver,
 749         &pdev,
 750 };
 751
 752 static int __init omap_drm_init(void)
 753 {
 754         DBG("init");
 755
 756         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
 757 }
 758
 759 static void __exit omap_drm_fini(void)
 760 {
 761         DBG("fini");
 762
 763         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
 764 }
 765
 766 /* need late_initcall() so we load after dss_driver's are loaded */
 767 late_initcall(omap_drm_init);
 768 module_exit(omap_drm_fini);
 769
 770 MODULE_AUTHOR("Rob Clark <[email protected]>");
 771 MODULE_DESCRIPTION("OMAP DRM Display Driver");
 772 MODULE_ALIAS("platform:" DRIVER_NAME);
 773 MODULE_LICENSE("GPL v2");