drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/kthread.h>
  25 #include <linux/wait.h>
  26 #include <linux/sched.h>
  27
  28 #include <drm/drm_drv.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32 #include "amdgpu_reset.h"
  33
  34 static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
  35 {
  36         struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
  37         struct amdgpu_job *job = to_amdgpu_job(s_job);
  38         struct amdgpu_task_info *ti;
  39         struct amdgpu_device *adev = ring->adev;
  40         int idx;
  41         int r;
  42
  43         if (!drm_dev_enter(adev_to_drm(adev), &idx)) {
  44                 DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s",
  45                          __func__, s_job->sched->name);
  46
  47                 /* Effectively the job is aborted as the device is gone */
  48                 return DRM_GPU_SCHED_STAT_ENODEV;
  49         }
  50
  51
  52         adev->job_hang = true;
  53
  54         if (amdgpu_gpu_recovery &&
  55             amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
  56                 DRM_ERROR("ring %s timeout, but soft recovered\n",
  57                           s_job->sched->name);
  58                 goto exit;
  59         }
  60
  61         DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
  62                    job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
  63                    ring->fence_drv.sync_seq);
  64
  65         ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid);
  66         if (ti) {
  67                 DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
  68                           ti->process_name, ti->tgid, ti->task_name, ti->pid);
  69                 amdgpu_vm_put_task_info(ti);
  70         }
  71
  72         dma_fence_set_error(&s_job->s_fence->finished, -ETIME);
  73
  74         if (amdgpu_device_should_recover_gpu(ring->adev)) {
  75                 struct amdgpu_reset_context reset_context;
  76                 memset(&reset_context, 0, sizeof(reset_context));
  77
  78                 reset_context.method = AMD_RESET_METHOD_NONE;
  79                 reset_context.reset_req_dev = adev;
  80                 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
  81
  82                 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context);
  83                 if (r)
  84                         DRM_ERROR("GPU Recovery Failed: %d\n", r);
  85         } else {
  86                 drm_sched_suspend_timeout(&ring->sched);
  87                 if (amdgpu_sriov_vf(adev))
  88                         adev->virt.tdr_debug = true;
  89         }
  90
  91 exit:
  92         adev->job_hang = false;
  93         drm_dev_exit(idx);
  94         return DRM_GPU_SCHED_STAT_NOMINAL;
  95 }
  96
  97 int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  98                      struct drm_sched_entity *entity, void *owner,
  99                      unsigned int num_ibs, struct amdgpu_job **job)
 100 {
 101         if (num_ibs == 0)
 102                 return -EINVAL;
 103
 104         *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL);
 105         if (!*job)
 106                 return -ENOMEM;
 107
 108         /*
 109          * Initialize the scheduler to at least some ring so that we always
 110          * have a pointer to adev.
 111          */
 112         (*job)->base.sched = &adev->rings[0]->sched;
 113         (*job)->vm = vm;
 114
 115         amdgpu_sync_create(&(*job)->explicit_sync);
 116         (*job)->generation = amdgpu_vm_generation(adev, vm);
 117         (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
 118
 119         if (!entity)
 120                 return 0;
 121
 122         return drm_sched_job_init(&(*job)->base, entity, 1, owner);
 123 }
 124
 125 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
 126                              struct drm_sched_entity *entity, void *owner,
 127                              size_t size, enum amdgpu_ib_pool_type pool_type,
 128                              struct amdgpu_job **job)
 129 {
 130         int r;
 131
 132         r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job);
 133         if (r)
 134                 return r;
 135
 136         (*job)->num_ibs = 1;
 137         r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
 138         if (r) {
 139                 if (entity)
 140                         drm_sched_job_cleanup(&(*job)->base);
 141                 kfree(*job);
 142         }
 143
 144         return r;
 145 }
 146
 147 void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
 148                               struct amdgpu_bo *gws, struct amdgpu_bo *oa)
 149 {
 150         if (gds) {
 151                 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
 152                 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
 153         }
 154         if (gws) {
 155                 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
 156                 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
 157         }
 158         if (oa) {
 159                 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
 160                 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
 161         }
 162 }
 163
 164 void amdgpu_job_free_resources(struct amdgpu_job *job)
 165 {
 166         struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
 167         struct dma_fence *f;
 168         unsigned i;
 169
 170         /* Check if any fences where initialized */
 171         if (job->base.s_fence && job->base.s_fence->finished.ops)
 172                 f = &job->base.s_fence->finished;
 173         else if (job->hw_fence.ops)
 174                 f = &job->hw_fence;
 175         else
 176                 f = NULL;
 177
 178         for (i = 0; i < job->num_ibs; ++i)
 179                 amdgpu_ib_free(ring->adev, &job->ibs[i], f);
 180 }
 181
 182 static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
 183 {
 184         struct amdgpu_job *job = to_amdgpu_job(s_job);
 185
 186         drm_sched_job_cleanup(s_job);
 187
 188         amdgpu_sync_free(&job->explicit_sync);
 189
 190         /* only put the hw fence if has embedded fence */
 191         if (!job->hw_fence.ops)
 192                 kfree(job);
 193         else
 194                 dma_fence_put(&job->hw_fence);
 195 }
 196
 197 void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
 198                                 struct amdgpu_job *leader)
 199 {
 200         struct dma_fence *fence = &leader->base.s_fence->scheduled;
 201
 202         WARN_ON(job->gang_submit);
 203
 204         /*
 205          * Don't add a reference when we are the gang leader to avoid circle
 206          * dependency.
 207          */
 208         if (job != leader)
 209                 dma_fence_get(fence);
 210         job->gang_submit = fence;
 211 }
 212
 213 void amdgpu_job_free(struct amdgpu_job *job)
 214 {
 215         if (job->base.entity)
 216                 drm_sched_job_cleanup(&job->base);
 217
 218         amdgpu_job_free_resources(job);
 219         amdgpu_sync_free(&job->explicit_sync);
 220         if (job->gang_submit != &job->base.s_fence->scheduled)
 221                 dma_fence_put(job->gang_submit);
 222
 223         if (!job->hw_fence.ops)
 224                 kfree(job);
 225         else
 226                 dma_fence_put(&job->hw_fence);
 227 }
 228
 229 struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job)
 230 {
 231         struct dma_fence *f;
 232
 233         drm_sched_job_arm(&job->base);
 234         f = dma_fence_get(&job->base.s_fence->finished);
 235         amdgpu_job_free_resources(job);
 236         drm_sched_entity_push_job(&job->base);
 237
 238         return f;
 239 }
 240
 241 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
 242                              struct dma_fence **fence)
 243 {
 244         int r;
 245
 246         job->base.sched = &ring->sched;
 247         r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence);
 248
 249         if (r)
 250                 return r;
 251
 252         amdgpu_job_free(job);
 253         return 0;
 254 }
 255
 256 static struct dma_fence *
 257 amdgpu_job_prepare_job(struct drm_sched_job *sched_job,
 258                       struct drm_sched_entity *s_entity)
 259 {
 260         struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
 261         struct amdgpu_job *job = to_amdgpu_job(sched_job);
 262         struct dma_fence *fence = NULL;
 263         int r;
 264
 265         /* Ignore soft recovered fences here */
 266         r = drm_sched_entity_error(s_entity);
 267         if (r && r != -ENODATA)
 268                 goto error;
 269
 270         if (!fence && job->gang_submit)
 271                 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
 272
 273         while (!fence && job->vm && !job->vmid) {
 274                 r = amdgpu_vmid_grab(job->vm, ring, job, &fence);
 275                 if (r) {
 276                         DRM_ERROR("Error getting VM ID (%d)\n", r);
 277                         goto error;
 278                 }
 279         }
 280
 281         return fence;
 282
 283 error:
 284         dma_fence_set_error(&job->base.s_fence->finished, r);
 285         return NULL;
 286 }
 287
 288 static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
 289 {
 290         struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
 291         struct amdgpu_device *adev = ring->adev;
 292         struct dma_fence *fence = NULL, *finished;
 293         struct amdgpu_job *job;
 294         int r = 0;
 295
 296         job = to_amdgpu_job(sched_job);
 297         finished = &job->base.s_fence->finished;
 298
 299         trace_amdgpu_sched_run_job(job);
 300
 301         /* Skip job if VRAM is lost and never resubmit gangs */
 302         if (job->generation != amdgpu_vm_generation(adev, job->vm) ||
 303             (job->job_run_counter && job->gang_submit))
 304                 dma_fence_set_error(finished, -ECANCELED);
 305
 306         if (finished->error < 0) {
 307                 dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)",
 308                         ring->name);
 309         } else {
 310                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
 311                                        &fence);
 312                 if (r)
 313                         dev_err(adev->dev,
 314                                 "Error scheduling IBs (%d) in ring(%s)", r,
 315                                 ring->name);
 316         }
 317
 318         job->job_run_counter++;
 319         amdgpu_job_free_resources(job);
 320
 321         fence = r ? ERR_PTR(r) : fence;
 322         return fence;
 323 }
 324
 325 #define to_drm_sched_job(sched_job)             \
 326                 container_of((sched_job), struct drm_sched_job, queue_node)
 327
 328 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
 329 {
 330         struct drm_sched_job *s_job;
 331         struct drm_sched_entity *s_entity = NULL;
 332         int i;
 333
 334         /* Signal all jobs not yet scheduled */
 335         for (i = DRM_SCHED_PRIORITY_KERNEL; i < sched->num_rqs; i++) {
 336                 struct drm_sched_rq *rq = sched->sched_rq[i];
 337                 spin_lock(&rq->lock);
 338                 list_for_each_entry(s_entity, &rq->entities, list) {
 339                         while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
 340                                 struct drm_sched_fence *s_fence = s_job->s_fence;
 341
 342                                 dma_fence_signal(&s_fence->scheduled);
 343                                 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
 344                                 dma_fence_signal(&s_fence->finished);
 345                         }
 346                 }
 347                 spin_unlock(&rq->lock);
 348         }
 349
 350         /* Signal all jobs already scheduled to HW */
 351         list_for_each_entry(s_job, &sched->pending_list, list) {
 352                 struct drm_sched_fence *s_fence = s_job->s_fence;
 353
 354                 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
 355                 dma_fence_signal(&s_fence->finished);
 356         }
 357 }
 358
 359 const struct drm_sched_backend_ops amdgpu_sched_ops = {
 360         .prepare_job = amdgpu_job_prepare_job,
 361         .run_job = amdgpu_job_run,
 362         .timedout_job = amdgpu_job_timedout,
 363         .free_job = amdgpu_job_free_cb
 364 };