drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #define MAX_KIQ_REG_WAIT        5000 /* in usecs, 5ms */
  26 #define MAX_KIQ_REG_BAILOUT_INTERVAL    5 /* in msecs, 5ms */
  27 #define MAX_KIQ_REG_TRY 20
  28
  29 uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
  30 {
  31         uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
  32
  33         addr -= AMDGPU_VA_RESERVED_SIZE;
  34
  35         if (addr >= AMDGPU_VA_HOLE_START)
  36                 addr |= AMDGPU_VA_HOLE_END;
  37
  38         return addr;
  39 }
  40
  41 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
  42 {
  43         /* By now all MMIO pages except mailbox are blocked */
  44         /* if blocking is enabled in hypervisor. Choose the */
  45         /* SCRATCH_REG0 to test. */
  46         return RREG32_NO_KIQ(0xc040) == 0xffffffff;
  47 }
  48
  49 int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
  50 {
  51         int r;
  52         void *ptr;
  53
  54         r = amdgpu_bo_create_kernel(adev, AMDGPU_CSA_SIZE, PAGE_SIZE,
  55                                 AMDGPU_GEM_DOMAIN_VRAM, &adev->virt.csa_obj,
  56                                 &adev->virt.csa_vmid0_addr, &ptr);
  57         if (r)
  58                 return r;
  59
  60         memset(ptr, 0, AMDGPU_CSA_SIZE);
  61         return 0;
  62 }
  63
  64 void amdgpu_free_static_csa(struct amdgpu_device *adev) {
  65         amdgpu_bo_free_kernel(&adev->virt.csa_obj,
  66                                                 &adev->virt.csa_vmid0_addr,
  67                                                 NULL);
  68 }
  69
  70 /*
  71  * amdgpu_map_static_csa should be called during amdgpu_vm_init
  72  * it maps virtual address amdgpu_csa_vaddr() to this VM, and each command
  73  * submission of GFX should use this virtual address within META_DATA init
  74  * package to support SRIOV gfx preemption.
  75  */
  76 int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  77                           struct amdgpu_bo_va **bo_va)
  78 {
  79         uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_VA_HOLE_MASK;
  80         struct ww_acquire_ctx ticket;
  81         struct list_head list;
  82         struct amdgpu_bo_list_entry pd;
  83         struct ttm_validate_buffer csa_tv;
  84         int r;
  85
  86         INIT_LIST_HEAD(&list);
  87         INIT_LIST_HEAD(&csa_tv.head);
  88         csa_tv.bo = &adev->virt.csa_obj->tbo;
  89         csa_tv.shared = true;
  90
  91         list_add(&csa_tv.head, &list);
  92         amdgpu_vm_get_pd_bo(vm, &list, &pd);
  93
  94         r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
  95         if (r) {
  96                 DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r);
  97                 return r;
  98         }
  99
 100         *bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj);
 101         if (!*bo_va) {
 102                 ttm_eu_backoff_reservation(&ticket, &list);
 103                 DRM_ERROR("failed to create bo_va for static CSA\n");
 104                 return -ENOMEM;
 105         }
 106
 107         r = amdgpu_vm_alloc_pts(adev, (*bo_va)->base.vm, csa_addr,
 108                                 AMDGPU_CSA_SIZE);
 109         if (r) {
 110                 DRM_ERROR("failed to allocate pts for static CSA, err=%d\n", r);
 111                 amdgpu_vm_bo_rmv(adev, *bo_va);
 112                 ttm_eu_backoff_reservation(&ticket, &list);
 113                 return r;
 114         }
 115
 116         r = amdgpu_vm_bo_map(adev, *bo_va, csa_addr, 0, AMDGPU_CSA_SIZE,
 117                              AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |
 118                              AMDGPU_PTE_EXECUTABLE);
 119
 120         if (r) {
 121                 DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
 122                 amdgpu_vm_bo_rmv(adev, *bo_va);
 123                 ttm_eu_backoff_reservation(&ticket, &list);
 124                 return r;
 125         }
 126
 127         ttm_eu_backoff_reservation(&ticket, &list);
 128         return 0;
 129 }
 130
 131 void amdgpu_virt_init_setting(struct amdgpu_device *adev)
 132 {
 133         /* enable virtual display */
 134         adev->mode_info.num_crtc = 1;
 135         adev->enable_virtual_display = true;
 136         adev->cg_flags = 0;
 137         adev->pg_flags = 0;
 138 }
 139
 140 uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 141 {
 142         signed long r, cnt = 0;
 143         unsigned long flags;
 144         uint32_t seq;
 145         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 146         struct amdgpu_ring *ring = &kiq->ring;
 147
 148         BUG_ON(!ring->funcs->emit_rreg);
 149
 150         spin_lock_irqsave(&kiq->ring_lock, flags);
 151         amdgpu_ring_alloc(ring, 32);
 152         amdgpu_ring_emit_rreg(ring, reg);
 153         amdgpu_fence_emit_polling(ring, &seq);
 154         amdgpu_ring_commit(ring);
 155         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 156
 157         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 158
 159         /* don't wait anymore for gpu reset case because this way may
 160          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 161          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 162          * never return if we keep waiting in virt_kiq_rreg, which cause
 163          * gpu_recover() hang there.
 164          *
 165          * also don't wait anymore for IRQ context
 166          * */
 167         if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
 168                 goto failed_kiq_read;
 169
 170         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 171                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 172                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 173         }
 174
 175         if (cnt > MAX_KIQ_REG_TRY)
 176                 goto failed_kiq_read;
 177
 178         return adev->wb.wb[adev->virt.reg_val_offs];
 179
 180 failed_kiq_read:
 181         pr_err("failed to read reg:%x\n", reg);
 182         return ~0;
 183 }
 184
 185 void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 186 {
 187         signed long r, cnt = 0;
 188         unsigned long flags;
 189         uint32_t seq;
 190         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 191         struct amdgpu_ring *ring = &kiq->ring;
 192
 193         BUG_ON(!ring->funcs->emit_wreg);
 194
 195         spin_lock_irqsave(&kiq->ring_lock, flags);
 196         amdgpu_ring_alloc(ring, 32);
 197         amdgpu_ring_emit_wreg(ring, reg, v);
 198         amdgpu_fence_emit_polling(ring, &seq);
 199         amdgpu_ring_commit(ring);
 200         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 201
 202         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 203
 204         /* don't wait anymore for gpu reset case because this way may
 205          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 206          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 207          * never return if we keep waiting in virt_kiq_rreg, which cause
 208          * gpu_recover() hang there.
 209          *
 210          * also don't wait anymore for IRQ context
 211          * */
 212         if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
 213                 goto failed_kiq_write;
 214
 215         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 216                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 217                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 218         }
 219
 220         if (cnt > MAX_KIQ_REG_TRY)
 221                 goto failed_kiq_write;
 222
 223         return;
 224
 225 failed_kiq_write:
 226         pr_err("failed to write reg:%x\n", reg);
 227 }
 228
 229 /**
 230  * amdgpu_virt_request_full_gpu() - request full gpu access
 231  * @amdgpu:     amdgpu device.
 232  * @init:       is driver init time.
 233  * When start to init/fini driver, first need to request full gpu access.
 234  * Return: Zero if request success, otherwise will return error.
 235  */
 236 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
 237 {
 238         struct amdgpu_virt *virt = &adev->virt;
 239         int r;
 240
 241         if (virt->ops && virt->ops->req_full_gpu) {
 242                 r = virt->ops->req_full_gpu(adev, init);
 243                 if (r)
 244                         return r;
 245
 246                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 247         }
 248
 249         return 0;
 250 }
 251
 252 /**
 253  * amdgpu_virt_release_full_gpu() - release full gpu access
 254  * @amdgpu:     amdgpu device.
 255  * @init:       is driver init time.
 256  * When finishing driver init/fini, need to release full gpu access.
 257  * Return: Zero if release success, otherwise will returen error.
 258  */
 259 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
 260 {
 261         struct amdgpu_virt *virt = &adev->virt;
 262         int r;
 263
 264         if (virt->ops && virt->ops->rel_full_gpu) {
 265                 r = virt->ops->rel_full_gpu(adev, init);
 266                 if (r)
 267                         return r;
 268
 269                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
 270         }
 271         return 0;
 272 }
 273
 274 /**
 275  * amdgpu_virt_reset_gpu() - reset gpu
 276  * @amdgpu:     amdgpu device.
 277  * Send reset command to GPU hypervisor to reset GPU that VM is using
 278  * Return: Zero if reset success, otherwise will return error.
 279  */
 280 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
 281 {
 282         struct amdgpu_virt *virt = &adev->virt;
 283         int r;
 284
 285         if (virt->ops && virt->ops->reset_gpu) {
 286                 r = virt->ops->reset_gpu(adev);
 287                 if (r)
 288                         return r;
 289
 290                 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
 291         }
 292
 293         return 0;
 294 }
 295
 296 /**
 297  * amdgpu_virt_wait_reset() - wait for reset gpu completed
 298  * @amdgpu:     amdgpu device.
 299  * Wait for GPU reset completed.
 300  * Return: Zero if reset success, otherwise will return error.
 301  */
 302 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
 303 {
 304         struct amdgpu_virt *virt = &adev->virt;
 305
 306         if (!virt->ops || !virt->ops->wait_reset)
 307                 return -EINVAL;
 308
 309         return virt->ops->wait_reset(adev);
 310 }
 311
 312 /**
 313  * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
 314  * @amdgpu:     amdgpu device.
 315  * MM table is used by UVD and VCE for its initialization
 316  * Return: Zero if allocate success.
 317  */
 318 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
 319 {
 320         int r;
 321
 322         if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
 323                 return 0;
 324
 325         r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
 326                                     AMDGPU_GEM_DOMAIN_VRAM,
 327                                     &adev->virt.mm_table.bo,
 328                                     &adev->virt.mm_table.gpu_addr,
 329                                     (void *)&adev->virt.mm_table.cpu_addr);
 330         if (r) {
 331                 DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
 332                 return r;
 333         }
 334
 335         memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
 336         DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
 337                  adev->virt.mm_table.gpu_addr,
 338                  adev->virt.mm_table.cpu_addr);
 339         return 0;
 340 }
 341
 342 /**
 343  * amdgpu_virt_free_mm_table() - free mm table memory
 344  * @amdgpu:     amdgpu device.
 345  * Free MM table memory
 346  */
 347 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
 348 {
 349         if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
 350                 return;
 351
 352         amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
 353                               &adev->virt.mm_table.gpu_addr,
 354                               (void *)&adev->virt.mm_table.cpu_addr);
 355         adev->virt.mm_table.gpu_addr = 0;
 356 }
 357
 358
 359 int amdgpu_virt_fw_reserve_get_checksum(void *obj,
 360                                         unsigned long obj_size,
 361                                         unsigned int key,
 362                                         unsigned int chksum)
 363 {
 364         unsigned int ret = key;
 365         unsigned long i = 0;
 366         unsigned char *pos;
 367
 368         pos = (char *)obj;
 369         /* calculate checksum */
 370         for (i = 0; i < obj_size; ++i)
 371                 ret += *(pos + i);
 372         /* minus the chksum itself */
 373         pos = (char *)&chksum;
 374         for (i = 0; i < sizeof(chksum); ++i)
 375                 ret -= *(pos + i);
 376         return ret;
 377 }
 378
 379 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
 380 {
 381         uint32_t pf2vf_size = 0;
 382         uint32_t checksum = 0;
 383         uint32_t checkval;
 384         char *str;
 385
 386         adev->virt.fw_reserve.p_pf2vf = NULL;
 387         adev->virt.fw_reserve.p_vf2pf = NULL;
 388
 389         if (adev->fw_vram_usage.va != NULL) {
 390                 adev->virt.fw_reserve.p_pf2vf =
 391                         (struct amdgim_pf2vf_info_header *)(
 392                         adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
 393                 AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
 394                 AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
 395                 AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature);
 396
 397                 /* pf2vf message must be in 4K */
 398                 if (pf2vf_size > 0 && pf2vf_size < 4096) {
 399                         checkval = amdgpu_virt_fw_reserve_get_checksum(
 400                                 adev->virt.fw_reserve.p_pf2vf, pf2vf_size,
 401                                 adev->virt.fw_reserve.checksum_key, checksum);
 402                         if (checkval == checksum) {
 403                                 adev->virt.fw_reserve.p_vf2pf =
 404                                         ((void *)adev->virt.fw_reserve.p_pf2vf +
 405                                         pf2vf_size);
 406                                 memset((void *)adev->virt.fw_reserve.p_vf2pf, 0,
 407                                         sizeof(amdgim_vf2pf_info));
 408                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.version,
 409                                         AMDGPU_FW_VRAM_VF2PF_VER);
 410                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.size,
 411                                         sizeof(amdgim_vf2pf_info));
 412                                 AMDGPU_FW_VRAM_VF2PF_READ(adev, driver_version,
 413                                         &str);
 414 #ifdef MODULE
 415                                 if (THIS_MODULE->version != NULL)
 416                                         strcpy(str, THIS_MODULE->version);
 417                                 else
 418 #endif
 419                                         strcpy(str, "N/A");
 420                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, driver_cert,
 421                                         0);
 422                                 AMDGPU_FW_VRAM_VF2PF_WRITE(adev, checksum,
 423                                         amdgpu_virt_fw_reserve_get_checksum(
 424                                         adev->virt.fw_reserve.p_vf2pf,
 425                                         pf2vf_size,
 426                                         adev->virt.fw_reserve.checksum_key, 0));
 427                         }
 428                 }
 429         }
 430 }
 431
 432