drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_ras.h"
  25 #include "mmhub_v1_7.h"
  26
  27 #include "mmhub/mmhub_1_7_offset.h"
  28 #include "mmhub/mmhub_1_7_sh_mask.h"
  29 #include "vega10_enum.h"
  30
  31 #include "soc15_common.h"
  32 #include "soc15.h"
  33
  34 #define regVM_L2_CNTL3_DEFAULT  0x80100007
  35 #define regVM_L2_CNTL4_DEFAULT  0x000000c1
  36
  37 static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev)
  38 {
  39         u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);
  40         u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);
  41
  42         base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  43         base <<= 24;
  44
  45         top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  46         top <<= 24;
  47
  48         adev->gmc.fb_start = base;
  49         adev->gmc.fb_end = top;
  50
  51         return base;
  52 }
  53
  54 static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  55                                 uint64_t page_table_base)
  56 {
  57         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
  58
  59         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  60                         hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
  61
  62         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  63                         hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));
  64 }
  65
  66 static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev)
  67 {
  68         uint64_t pt_base;
  69
  70         if (adev->gmc.pdb0_bo)
  71                 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
  72         else
  73                 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  74
  75         mmhub_v1_7_setup_vm_pt_regs(adev, 0, pt_base);
  76
  77         /* If use GART for FB translation, vmid0 page table covers both
  78          * vram and system memory (gart)
  79          */
  80         if (adev->gmc.pdb0_bo) {
  81                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  82                                 (u32)(adev->gmc.fb_start >> 12));
  83                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  84                                 (u32)(adev->gmc.fb_start >> 44));
  85
  86                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  87                                 (u32)(adev->gmc.gart_end >> 12));
  88                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  89                                 (u32)(adev->gmc.gart_end >> 44));
  90
  91         } else {
  92                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  93                                 (u32)(adev->gmc.gart_start >> 12));
  94                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  95                                 (u32)(adev->gmc.gart_start >> 44));
  96
  97                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  98                                 (u32)(adev->gmc.gart_end >> 12));
  99                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 100                                 (u32)(adev->gmc.gart_end >> 44));
 101         }
 102 }
 103
 104 static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
 105 {
 106         uint64_t value;
 107         uint32_t tmp;
 108
 109         /* Program the AGP BAR */
 110         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BASE, 0);
 111         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 112         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 113
 114         /* Program the system aperture low logical page number. */
 115         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 116                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 117
 118         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 119                      max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 120
 121         /* In the case squeezing vram into GART aperture, we don't use
 122          * FB aperture and AGP aperture. Disable them.
 123          */
 124         if (adev->gmc.pdb0_bo) {
 125                 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF);
 126                 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0);
 127                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0);
 128                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
 129                 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
 130                 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
 131         }
 132         if (amdgpu_sriov_vf(adev))
 133                 return;
 134
 135         /* Set default page address. */
 136         value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
 137         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 138                      (u32)(value >> 12));
 139         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 140                      (u32)(value >> 44));
 141
 142         /* Program "protection fault". */
 143         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 144                      (u32)(adev->dummy_page_addr >> 12));
 145         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 146                      (u32)((u64)adev->dummy_page_addr >> 44));
 147
 148         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2);
 149         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 150                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 151         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 152 }
 153
 154 static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev)
 155 {
 156         uint32_t tmp;
 157
 158         /* Setup TLB control */
 159         tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
 160
 161         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 162         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 163         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 164                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 165         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 166                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 167         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 168         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 169                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 170         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 171
 172         WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
 173 }
 174
 175 static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev)
 176 {
 177         uint32_t tmp;
 178
 179         if (amdgpu_sriov_vf(adev))
 180                 return;
 181
 182         /* Setup L2 cache */
 183         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
 184         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 185         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 186         /* XXX for emulation, Refer to closed source code.*/
 187         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 188                             0);
 189         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 190         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 191         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 192         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
 193
 194         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2);
 195         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 196         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 197         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp);
 198
 199         tmp = regVM_L2_CNTL3_DEFAULT;
 200         if (adev->gmc.translate_further) {
 201                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 202                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 203                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 204         } else {
 205                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 206                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 207                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 208         }
 209         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp);
 210
 211         tmp = regVM_L2_CNTL4_DEFAULT;
 212         if (adev->gmc.xgmi.connected_to_cpu) {
 213                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 214                                     VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
 215                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 216                                     VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
 217         } else {
 218                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 219                                     VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 220                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 221                                     VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 222         }
 223         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp);
 224 }
 225
 226 static void mmhub_v1_7_enable_system_domain(struct amdgpu_device *adev)
 227 {
 228         uint32_t tmp;
 229
 230         tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);
 231         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 232         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
 233                         adev->gmc.vmid0_page_table_depth);
 234         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
 235                         adev->gmc.vmid0_page_table_block_size);
 236         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 237                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 238         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp);
 239 }
 240
 241 static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev)
 242 {
 243         if (amdgpu_sriov_vf(adev))
 244                 return;
 245
 246         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 247                      0XFFFFFFFF);
 248         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 249                      0x0000000F);
 250
 251         WREG32_SOC15(MMHUB, 0,
 252                      regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 253         WREG32_SOC15(MMHUB, 0,
 254                      regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 255
 256         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 257                      0);
 258         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 259                      0);
 260 }
 261
 262 static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
 263 {
 264         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 265         unsigned num_level, block_size;
 266         uint32_t tmp;
 267         int i;
 268
 269         num_level = adev->vm_manager.num_level;
 270         block_size = adev->vm_manager.block_size;
 271         if (adev->gmc.translate_further)
 272                 num_level -= 1;
 273         else
 274                 block_size -= 9;
 275
 276         for (i = 0; i <= 14; i++) {
 277                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i);
 278                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 279                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 280                                     num_level);
 281                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 282                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 283                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 284                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 285                                     1);
 286                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 287                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 288                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 289                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 290                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 291                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 292                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 293                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 294                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 295                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 296                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 297                                     PAGE_TABLE_BLOCK_SIZE,
 298                                     block_size);
 299                 /* On Aldebaran, XNACK can be enabled in the SQ per-process.
 300                  * Retry faults need to be enabled for that to work.
 301                  */
 302                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 303                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 304                                     1);
 305                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL,
 306                                     i * hub->ctx_distance, tmp);
 307                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 308                                     i * hub->ctx_addr_distance, 0);
 309                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 310                                     i * hub->ctx_addr_distance, 0);
 311                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 312                                     i * hub->ctx_addr_distance,
 313                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 314                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 315                                     i * hub->ctx_addr_distance,
 316                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 317         }
 318 }
 319
 320 static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev)
 321 {
 322         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 323         unsigned i;
 324
 325         for (i = 0; i < 18; ++i) {
 326                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 327                                     i * hub->eng_addr_distance, 0xffffffff);
 328                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 329                                     i * hub->eng_addr_distance, 0x1f);
 330         }
 331 }
 332
 333 static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)
 334 {
 335         if (amdgpu_sriov_vf(adev)) {
 336                 /*
 337                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 338                  * VF copy registers so vbios post doesn't program them, for
 339                  * SRIOV driver need to program them
 340                  */
 341                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE,
 342                              adev->gmc.vram_start >> 24);
 343                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP,
 344                              adev->gmc.vram_end >> 24);
 345         }
 346
 347         /* GART Enable. */
 348         mmhub_v1_7_init_gart_aperture_regs(adev);
 349         mmhub_v1_7_init_system_aperture_regs(adev);
 350         mmhub_v1_7_init_tlb_regs(adev);
 351         mmhub_v1_7_init_cache_regs(adev);
 352
 353         mmhub_v1_7_enable_system_domain(adev);
 354         mmhub_v1_7_disable_identity_aperture(adev);
 355         mmhub_v1_7_setup_vmid_config(adev);
 356         mmhub_v1_7_program_invalidation(adev);
 357
 358         return 0;
 359 }
 360
 361 static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev)
 362 {
 363         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 364         u32 tmp;
 365         u32 i;
 366
 367         /* Disable all tables */
 368         for (i = 0; i < 16; i++)
 369                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL,
 370                                     i * hub->ctx_distance, 0);
 371
 372         /* Setup TLB control */
 373         tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
 374         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 375         tmp = REG_SET_FIELD(tmp,
 376                                 MC_VM_MX_L1_TLB_CNTL,
 377                                 ENABLE_ADVANCED_DRIVER_MODEL,
 378                                 0);
 379         WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
 380
 381         if (!amdgpu_sriov_vf(adev)) {
 382                 /* Setup L2 cache */
 383                 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
 384                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 385                 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
 386                 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, 0);
 387         }
 388 }
 389
 390 /**
 391  * mmhub_v1_7_set_fault_enable_default - update GART/VM fault handling
 392  *
 393  * @adev: amdgpu_device pointer
 394  * @value: true redirects VM faults to the default page
 395  */
 396 static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 397 {
 398         u32 tmp;
 399
 400         if (amdgpu_sriov_vf(adev))
 401                 return;
 402
 403         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
 404         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 405                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 406         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 407                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 408         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 409                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 410         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 411                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 412         tmp = REG_SET_FIELD(tmp,
 413                         VM_L2_PROTECTION_FAULT_CNTL,
 414                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 415                         value);
 416         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 417                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 418         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 419                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 420         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 421                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 422         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 423                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 424         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 425                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 426         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 427                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 428         if (!value) {
 429                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 430                                 CRASH_ON_NO_RETRY_FAULT, 1);
 431                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 432                                 CRASH_ON_RETRY_FAULT, 1);
 433     }
 434
 435         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
 436 }
 437
 438 static void mmhub_v1_7_init(struct amdgpu_device *adev)
 439 {
 440         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 441
 442         hub->ctx0_ptb_addr_lo32 =
 443                 SOC15_REG_OFFSET(MMHUB, 0,
 444                                  regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 445         hub->ctx0_ptb_addr_hi32 =
 446                 SOC15_REG_OFFSET(MMHUB, 0,
 447                                  regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 448         hub->vm_inv_eng0_req =
 449                 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ);
 450         hub->vm_inv_eng0_ack =
 451                 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK);
 452         hub->vm_context0_cntl =
 453                 SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL);
 454         hub->vm_l2_pro_fault_status =
 455                 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS);
 456         hub->vm_l2_pro_fault_cntl =
 457                 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
 458
 459         hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL;
 460         hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 461                 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 462         hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ;
 463         hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 464                 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 465
 466 }
 467
 468 static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 469                                                         bool enable)
 470 {
 471         uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
 472
 473         def  = data  = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
 474
 475         def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
 476         def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);
 477
 478         if (enable) {
 479                 data |= ATC_L2_MISC_CG__ENABLE_MASK;
 480
 481                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 482                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 483                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 484                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 485                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 486                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 487
 488                 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 489                            DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 490                            DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 491                            DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 492                            DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 493                            DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 494         } else {
 495                 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
 496
 497                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 498                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 499                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 500                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 501                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 502                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 503
 504                 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 505                           DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 506                           DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 507                           DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 508                           DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 509                           DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 510         }
 511
 512         if (def != data)
 513                 WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data);
 514
 515         if (def1 != data1)
 516                 WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);
 517
 518         if (def2 != data2)
 519                 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
 520 }
 521
 522 static void mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 523                                                        bool enable)
 524 {
 525         uint32_t def, data;
 526
 527         def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
 528
 529         if (enable)
 530                 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 531         else
 532                 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 533
 534         if (def != data)
 535                 WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data);
 536 }
 537
 538 static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev,
 539                                enum amd_clockgating_state state)
 540 {
 541         if (amdgpu_sriov_vf(adev))
 542                 return 0;
 543
 544         /* Change state only if MCCG support is enabled through driver */
 545         if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)
 546                 mmhub_v1_7_update_medium_grain_clock_gating(adev,
 547                                 state == AMD_CG_STATE_GATE);
 548
 549         /* Change state only if LS support is enabled through driver */
 550         if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)
 551                 mmhub_v1_7_update_medium_grain_light_sleep(adev,
 552                                 state == AMD_CG_STATE_GATE);
 553
 554         return 0;
 555 }
 556
 557 static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 558 {
 559         int data, data1;
 560
 561         if (amdgpu_sriov_vf(adev))
 562                 *flags = 0;
 563
 564         data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
 565
 566         data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
 567
 568         /* AMD_CG_SUPPORT_MC_MGCG */
 569         if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
 570             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 571                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 572                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 573                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 574                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 575                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 576                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 577
 578         /* AMD_CG_SUPPORT_MC_LS */
 579         if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 580                 *flags |= AMD_CG_SUPPORT_MC_LS;
 581 }
 582
 583 static const struct soc15_ras_field_entry mmhub_v1_7_ras_fields[] = {
 584         /* MMHUB Range 0 */
 585         { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 586         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 587         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 588         },
 589         { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 590         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 591         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 592         },
 593         { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 594         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 595         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 596         },
 597         { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 598         SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 599         SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 600         },
 601         { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 602         SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 603         SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 604         },
 605         { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 606         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 607         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 608         },
 609         { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 610         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 611         0, 0,
 612         },
 613         { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 614         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 615         0, 0,
 616         },
 617         { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 618         SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 619         0, 0,
 620         },
 621         { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 622         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 623         0, 0,
 624         },
 625         { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 626         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 627         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 628         },
 629         { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 630         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 631         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 632         },
 633         { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 634         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 635         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 636         },
 637         { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 638         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 639         0, 0,
 640         },
 641         { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 642         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 643         0, 0,
 644         },
 645         { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 646         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 647         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 648         },
 649         { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 650         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 651         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 652         },
 653         { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 654         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 655         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 656         },
 657         { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 658         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 659         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 660         },
 661         { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 662         0, 0,
 663         SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 664         },
 665         { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 666         0, 0,
 667         SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 668         },
 669         { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 670         0, 0,
 671         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 672         },
 673         { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 674         0, 0,
 675         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 676         },
 677         { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 678         0, 0,
 679         SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 680         },
 681         { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 682         0, 0,
 683         SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 684         },
 685
 686         /* MMHUB Range 1 */
 687         { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 688         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 689         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 690         },
 691         { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 692         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 693         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 694         },
 695         { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 696         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 697         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 698         },
 699         { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 700         SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 701         SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 702         },
 703         { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 704         SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 705         SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 706         },
 707         { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 708         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 709         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 710         },
 711         { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 712         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 713         0, 0,
 714         },
 715         { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 716         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 717         0, 0,
 718         },
 719         { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 720         SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 721         0, 0,
 722         },
 723         { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 724         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 725         0, 0,
 726         },
 727         { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 728         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 729         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 730         },
 731         { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 732         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 733         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 734         },
 735         { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 736         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 737         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 738         },
 739         { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 740         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 741         0, 0,
 742         },
 743         { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 744         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 745         0, 0,
 746         },
 747         { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 748         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 749         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 750         },
 751         { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 752         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 753         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 754         },
 755         { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 756         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 757         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 758         },
 759         { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 760         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 761         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 762         },
 763         { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 764         0, 0,
 765         SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 766         },
 767         { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 768         0, 0,
 769         SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 770         },
 771         { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 772         0, 0,
 773         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 774         },
 775         { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 776         0, 0,
 777         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 778         },
 779         { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 780         0, 0,
 781         SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 782         },
 783         { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 784         0, 0,
 785         SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 786         },
 787
 788         /* MMHAB Range 2*/
 789         { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 790         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 791         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 792         },
 793         { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 794         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 795         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 796         },
 797         { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 798         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 799         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 800         },
 801         { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 802         SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 803         SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 804         },
 805         { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 806         SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 807         SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 808         },
 809         { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 810         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 811         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 812         },
 813         { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 814         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 815         0, 0,
 816         },
 817         { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 818         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 819         0, 0,
 820         },
 821         { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 822         SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 823         0, 0,
 824         },
 825         { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 826         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 827         0, 0,
 828         },
 829         { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 830         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 831         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 832         },
 833         { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 834         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 835         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 836         },
 837         { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 838         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 839         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 840         },
 841         { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 842         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 843         0, 0,
 844         },
 845         { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 846         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 847         0, 0,
 848         },
 849         { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 850         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 851         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 852         },
 853         { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 854         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 855         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 856         },
 857         { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 858         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 859         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 860         },
 861         { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 862         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 863         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 864         },
 865         { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 866         0, 0,
 867         SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 868         },
 869         { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 870         0, 0,
 871         SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 872         },
 873         { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 874         0, 0,
 875         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 876         },
 877         { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 878         0, 0,
 879         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 880         },
 881         { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 882         0, 0,
 883         SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 884         },
 885         { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 886         0, 0,
 887         SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 888         },
 889
 890         /* MMHUB Rang 3 */
 891         { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 892         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 893         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 894         },
 895         { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 896         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 897         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 898         },
 899         { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 900         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 901         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 902         },
 903         { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 904         SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 905         SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 906         },
 907         { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 908         SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 909         SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 910         },
 911         { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 912         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 913         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 914         },
 915         { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 916         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 917         0, 0,
 918         },
 919         { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 920         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 921         0, 0,
 922         },
 923         { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 924         SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 925         0, 0,
 926         },
 927         { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 928         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 929         0, 0,
 930         },
 931         { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 932         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 933         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 934         },
 935         { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 936         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 937         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 938         },
 939         { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 940         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 941         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 942         },
 943         { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 944         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 945         0, 0,
 946         },
 947         { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 948         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 949         0, 0,
 950         },
 951         { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 952         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 953         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 954         },
 955         { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 956         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 957         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 958         },
 959         { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 960         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 961         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 962         },
 963         { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 964         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 965         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 966         },
 967         { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 968         0, 0,
 969         SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 970         },
 971         { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 972         0, 0,
 973         SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 974         },
 975         { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 976         0, 0,
 977         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 978         },
 979         { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 980         0, 0,
 981         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 982         },
 983         { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 984         0, 0,
 985         SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 986         },
 987         { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 988         0, 0,
 989         SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 990         },
 991
 992         /* MMHUB Range 4 */
 993         { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
 994         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 995         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 996         },
 997         { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
 998         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 999         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1000         },
1001         { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1002         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1003         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1004         },
1005         { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1006         SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1007         SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1008         },
1009         { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1010         SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1011         SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1012         },
1013         { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1014         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1015         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
1016         },
1017         { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1018         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1019         0, 0,
1020         },
1021         { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1022         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1023         0, 0,
1024         },
1025         { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1026         SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1027         0, 0,
1028         },
1029         { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1030         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1031         0, 0,
1032         },
1033         { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1034         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1035         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1036         },
1037         { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1038         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1039         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1040         },
1041         { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1042         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1043         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1044         },
1045         { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1046         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1047         0, 0,
1048         },
1049         { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1050         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1051         0, 0,
1052         },
1053         { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1054         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1055         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1056         },
1057         { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1058         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1059         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1060         },
1061         { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1062         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1063         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1064         },
1065         { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1066         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1067         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1068         },
1069         { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1070         0, 0,
1071         SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1072         },
1073         { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1074         0, 0,
1075         SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1076         },
1077         { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1078         0, 0,
1079         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1080         },
1081         { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1082         0, 0,
1083         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1084         },
1085         { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1086         0, 0,
1087         SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1088         },
1089         { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1090         0, 0,
1091         SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1092         },
1093
1094         /* MMHUAB Range 5 */
1095         { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1096         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1097         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1098         },
1099         { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1100         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1101         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1102         },
1103         { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1104         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1105         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1106         },
1107         { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1108         SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1109         SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1110         },
1111         { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1112         SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1113         SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1114         },
1115         { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1116         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1117         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
1118         },
1119         { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1120         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1121         0, 0,
1122         },
1123         { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1124         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1125         0, 0,
1126         },
1127         { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1128         SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1129         0, 0,
1130         },
1131         { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1132         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1133         0, 0,
1134         },
1135         { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1136         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1137         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1138         },
1139         { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1140         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1141         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1142         },
1143         { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1144         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1145         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1146         },
1147         { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1148         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1149         0, 0,
1150         },
1151         { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1152         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1153         0, 0,
1154         },
1155         { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1156         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1157         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1158         },
1159         { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1160         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1161         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1162         },
1163         { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1164         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1165         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1166         },
1167         { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1168         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1169         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1170         },
1171         { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1172         0, 0,
1173         SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1174         },
1175         { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1176         0, 0,
1177         SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1178         },
1179         { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1180         0, 0,
1181         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1182         },
1183         { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1184         0, 0,
1185         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1186         },
1187         { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1188         0, 0,
1189         SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1190         },
1191         { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1192         0, 0,
1193         SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1194         },
1195 };
1196
1197 static const struct soc15_reg_entry mmhub_v1_7_edc_cnt_regs[] = {
1198         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 },
1199         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 },
1200         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 },
1201         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 },
1202         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 },
1203         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 },
1204         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 },
1205         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 },
1206         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 0, 0, 0 },
1207         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 },
1208         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 0, 0, 0 },
1209         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 0, 0, 0 },
1210         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 },
1211         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 0, 0, 0 },
1212         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 0, 0, 0 },
1213         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 0, 0, 0 },
1214         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 0, 0, 0 },
1215         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 0, 0, 0 },
1216 };
1217
1218 static int mmhub_v1_7_get_ras_error_count(struct amdgpu_device *adev,
1219                                           const struct soc15_reg_entry *reg,
1220                                           uint32_t value,
1221                                           uint32_t *sec_count,
1222                                           uint32_t *ded_count)
1223 {
1224         uint32_t i;
1225         uint32_t sec_cnt, ded_cnt;
1226
1227         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ras_fields); i++) {
1228                 if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset)
1229                         continue;
1230
1231                 sec_cnt = (value &
1232                                 mmhub_v1_7_ras_fields[i].sec_count_mask) >>
1233                                 mmhub_v1_7_ras_fields[i].sec_count_shift;
1234                 if (sec_cnt) {
1235                         dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1236                                  mmhub_v1_7_ras_fields[i].name,
1237                                  sec_cnt);
1238                         *sec_count += sec_cnt;
1239                 }
1240
1241                 ded_cnt = (value &
1242                                 mmhub_v1_7_ras_fields[i].ded_count_mask) >>
1243                                 mmhub_v1_7_ras_fields[i].ded_count_shift;
1244                 if (ded_cnt) {
1245                         dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1246                                  mmhub_v1_7_ras_fields[i].name,
1247                                  ded_cnt);
1248                         *ded_count += ded_cnt;
1249                 }
1250         }
1251
1252         return 0;
1253 }
1254
1255 static void mmhub_v1_7_query_ras_error_count(struct amdgpu_device *adev,
1256                                              void *ras_error_status)
1257 {
1258         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1259         uint32_t sec_count = 0, ded_count = 0;
1260         uint32_t i;
1261         uint32_t reg_value;
1262
1263         err_data->ue_count = 0;
1264         err_data->ce_count = 0;
1265
1266         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) {
1267                 reg_value =
1268                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]));
1269                 if (reg_value)
1270                         mmhub_v1_7_get_ras_error_count(adev, &mmhub_v1_7_edc_cnt_regs[i],
1271                                 reg_value, &sec_count, &ded_count);
1272         }
1273
1274         err_data->ce_count += sec_count;
1275         err_data->ue_count += ded_count;
1276 }
1277
1278 static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev)
1279 {
1280         uint32_t i;
1281
1282         /* write 0 to reset the edc counters */
1283         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1284                 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++)
1285                         WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0);
1286         }
1287 }
1288
1289 static const struct soc15_reg_entry mmhub_v1_7_ea_err_status_regs[] = {
1290         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_ERR_STATUS), 0, 0, 0 },
1291         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_ERR_STATUS), 0, 0, 0 },
1292         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_ERR_STATUS), 0, 0, 0 },
1293         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_ERR_STATUS), 0, 0, 0 },
1294         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_ERR_STATUS), 0, 0, 0 },
1295         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_ERR_STATUS), 0, 0, 0 },
1296 };
1297
1298 static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev)
1299 {
1300         int i;
1301         uint32_t reg_value;
1302
1303         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1304                 return;
1305
1306         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
1307                 reg_value =
1308                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]));
1309                 if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
1310                     REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
1311                     REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1312                         dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",
1313                                         i, reg_value);
1314                 }
1315         }
1316 }
1317
1318 static void mmhub_v1_7_reset_ras_error_status(struct amdgpu_device *adev)
1319 {
1320         int i;
1321         uint32_t reg_value;
1322
1323         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1324                 return;
1325
1326         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
1327                 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
1328                         mmhub_v1_7_ea_err_status_regs[i]));
1329                 reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS,
1330                                           CLEAR_ERROR_STATUS, 0x01);
1331                 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]),
1332                        reg_value);
1333         }
1334 }
1335
1336 const struct amdgpu_mmhub_ras_funcs mmhub_v1_7_ras_funcs = {
1337         .ras_late_init = amdgpu_mmhub_ras_late_init,
1338         .ras_fini = amdgpu_mmhub_ras_fini,
1339         .query_ras_error_count = mmhub_v1_7_query_ras_error_count,
1340         .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count,
1341         .query_ras_error_status = mmhub_v1_7_query_ras_error_status,
1342         .reset_ras_error_status = mmhub_v1_7_reset_ras_error_status,
1343 };
1344
1345 const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = {
1346         .get_fb_location = mmhub_v1_7_get_fb_location,
1347         .init = mmhub_v1_7_init,
1348         .gart_enable = mmhub_v1_7_gart_enable,
1349         .set_fault_enable_default = mmhub_v1_7_set_fault_enable_default,
1350         .gart_disable = mmhub_v1_7_gart_disable,
1351         .set_clockgating = mmhub_v1_7_set_clockgating,
1352         .get_clockgating = mmhub_v1_7_get_clockgating,
1353         .setup_vm_pt_regs = mmhub_v1_7_setup_vm_pt_regs,
1354 };