drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /*
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 110 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 111 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 113 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 115 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 116 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 117 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 118 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 119 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 120 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 121 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 122 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 123 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 124 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 125 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 126 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 127 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 128
 129 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 130 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 131 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 132 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 133 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 134 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 135 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 136 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 137 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 138 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 139 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 140 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 141
 142 #define mmCPG_PSP_DEBUG                         0x5c10
 143 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 144 #define mmCPC_PSP_DEBUG                         0x5c11
 145 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 146 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 147 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 148
 149 //CC_GC_SA_UNIT_DISABLE
 150 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 151 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 152 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 154 //GC_USER_SA_UNIT_DISABLE
 155 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 156 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 157 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 159 //PA_SC_ENHANCE_3
 160 #define mmPA_SC_ENHANCE_3                       0x1085
 161 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 162 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 164
 165 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 166 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 167
 168 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 170 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 172
 173 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 175
 176 #define GFX_RLCG_GC_WRITE_OLD   (0x8 << 28)
 177 #define GFX_RLCG_GC_WRITE       (0x0 << 28)
 178 #define GFX_RLCG_GC_READ        (0x1 << 28)
 179 #define GFX_RLCG_MMHUB_WRITE    (0x2 << 28)
 180
 181 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 182 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 183 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 184 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 185 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 186 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 187
 188 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 189 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 190 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 191 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 192 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 195 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 196 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 197 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 199
 200 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 201 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 202 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 203 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 204 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 205 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 206
 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 208 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 209 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 210 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 213
 214 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 215 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 216 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 217 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 218 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 219 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 220
 221 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 222 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 223 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 224 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 225 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 226 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 227
 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 229 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 230 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 231 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 234
 235 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 236 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 237 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 238 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 239 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 240 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 241
 242 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 243 {
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 284 };
 285
 286 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 287 {
 288         /* Pending on emulation bring up */
 289 };
 290
 291 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 292 {
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1345 };
1346
1347 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1348 {
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1387 };
1388
1389 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1390 {
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1433 };
1434
1435 static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
1436                                  int write, u32 *rlcg_flag)
1437 {
1438         switch (hwip) {
1439         case GC_HWIP:
1440                 if (amdgpu_sriov_reg_indirect_gc(adev)) {
1441                         *rlcg_flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1442
1443                         return true;
1444                 /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
1445                 } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ)) {
1446                         *rlcg_flag = GFX_RLCG_GC_WRITE_OLD;
1447
1448                         return true;
1449                 }
1450
1451                 break;
1452         case MMHUB_HWIP:
1453                 if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
1454                     (acc_flags & AMDGPU_REGS_RLC) && write) {
1455                         *rlcg_flag = GFX_RLCG_MMHUB_WRITE;
1456                         return true;
1457                 }
1458
1459                 break;
1460         default:
1461                 DRM_DEBUG("Not program register by RLCG\n");
1462         }
1463
1464         return false;
1465 }
1466
1467 static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
1468 {
1469         static void *scratch_reg0;
1470         static void *scratch_reg1;
1471         static void *scratch_reg2;
1472         static void *scratch_reg3;
1473         static void *spare_int;
1474         static uint32_t grbm_cntl;
1475         static uint32_t grbm_idx;
1476         uint32_t i = 0;
1477         uint32_t retries = 50000;
1478         u32 ret = 0;
1479
1480         scratch_reg0 = adev->rmmio +
1481                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4;
1482         scratch_reg1 = adev->rmmio +
1483                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4;
1484         scratch_reg2 = adev->rmmio +
1485                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
1486         scratch_reg3 = adev->rmmio +
1487                        (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1488         spare_int = adev->rmmio +
1489                     (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1490
1491         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1492         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1493
1494         if (offset == grbm_cntl || offset == grbm_idx) {
1495                 if (offset  == grbm_cntl)
1496                         writel(v, scratch_reg2);
1497                 else if (offset == grbm_idx)
1498                         writel(v, scratch_reg3);
1499
1500                 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1501         } else {
1502                 writel(v, scratch_reg0);
1503                 writel(offset | flag, scratch_reg1);
1504                 writel(1, spare_int);
1505                 for (i = 0; i < retries; i++) {
1506                         u32 tmp;
1507
1508                         tmp = readl(scratch_reg1);
1509                         if (!(tmp & flag))
1510                                 break;
1511
1512                         udelay(10);
1513                 }
1514
1515                 if (i >= retries)
1516                         pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1517         }
1518
1519         ret = readl(scratch_reg0);
1520
1521         return ret;
1522 }
1523
1524 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip)
1525 {
1526         u32 rlcg_flag;
1527
1528         if (!amdgpu_sriov_runtime(adev) &&
1529             gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
1530                 gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
1531                 return;
1532         }
1533
1534         if (acc_flags & AMDGPU_REGS_NO_KIQ)
1535                 WREG32_NO_KIQ(offset, value);
1536         else
1537                 WREG32(offset, value);
1538 }
1539
1540 static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
1541 {
1542         u32 rlcg_flag;
1543
1544         if (!amdgpu_sriov_runtime(adev) &&
1545             gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
1546                 return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
1547
1548         if (acc_flags & AMDGPU_REGS_NO_KIQ)
1549                 return RREG32_NO_KIQ(offset);
1550         else
1551                 return RREG32(offset);
1552 }
1553
1554 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1555 {
1556         /* Pending on emulation bring up */
1557 };
1558
1559 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1560 {
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2181 };
2182
2183 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2184 {
2185         /* Pending on emulation bring up */
2186 };
2187
2188 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2189 {
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3242 };
3243
3244 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3245 {
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3288 };
3289
3290 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3291 {
3292         /* Pending on emulation bring up */
3293 };
3294
3295 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3296 {
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3338
3339         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3341 };
3342
3343 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3344 {
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3368
3369         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3371 };
3372
3373 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3374 {
3375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3410 };
3411
3412 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3445 };
3446
3447 #define DEFAULT_SH_MEM_CONFIG \
3448         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3449          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3450          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3451          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3452
3453
3454 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3455 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3456 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3457 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3458 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3459                                  struct amdgpu_cu_info *cu_info);
3460 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3461 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3462                                    u32 sh_num, u32 instance);
3463 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3464
3465 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3466 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3467 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3468 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3469 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3470 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3471 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3472 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3473 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3474 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3475
3476 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3477 {
3478         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3479         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3480                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3481         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3482         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3483         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3484         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3485         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3486         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3487 }
3488
3489 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3490                                  struct amdgpu_ring *ring)
3491 {
3492         struct amdgpu_device *adev = kiq_ring->adev;
3493         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3494         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3495         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3496
3497         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3498         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3499         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3500                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3501                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3502                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3503                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3504                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3505                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3506                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3507                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3508                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3509         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3510         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3511         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3512         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3513         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3514 }
3515
3516 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3517                                    struct amdgpu_ring *ring,
3518                                    enum amdgpu_unmap_queues_action action,
3519                                    u64 gpu_addr, u64 seq)
3520 {
3521         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3522
3523         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3524         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3525                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3526                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3527                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3528                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3529         amdgpu_ring_write(kiq_ring,
3530                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3531
3532         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3533                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3534                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3535                 amdgpu_ring_write(kiq_ring, seq);
3536         } else {
3537                 amdgpu_ring_write(kiq_ring, 0);
3538                 amdgpu_ring_write(kiq_ring, 0);
3539                 amdgpu_ring_write(kiq_ring, 0);
3540         }
3541 }
3542
3543 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3544                                    struct amdgpu_ring *ring,
3545                                    u64 addr,
3546                                    u64 seq)
3547 {
3548         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3549
3550         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3551         amdgpu_ring_write(kiq_ring,
3552                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3553                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3554                           PACKET3_QUERY_STATUS_COMMAND(2));
3555         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3556                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3557                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3558         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3559         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3560         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3561         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3562 }
3563
3564 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3565                                 uint16_t pasid, uint32_t flush_type,
3566                                 bool all_hub)
3567 {
3568         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3569         amdgpu_ring_write(kiq_ring,
3570                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3571                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3572                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3573                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3574 }
3575
3576 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3577         .kiq_set_resources = gfx10_kiq_set_resources,
3578         .kiq_map_queues = gfx10_kiq_map_queues,
3579         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3580         .kiq_query_status = gfx10_kiq_query_status,
3581         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3582         .set_resources_size = 8,
3583         .map_queues_size = 7,
3584         .unmap_queues_size = 6,
3585         .query_status_size = 7,
3586         .invalidate_tlbs_size = 2,
3587 };
3588
3589 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3590 {
3591         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3592 }
3593
3594 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3595 {
3596         switch (adev->asic_type) {
3597         case CHIP_NAVI10:
3598                 soc15_program_register_sequence(adev,
3599                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3600                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3601                 break;
3602         case CHIP_NAVI14:
3603                 soc15_program_register_sequence(adev,
3604                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3605                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3606                 break;
3607         case CHIP_NAVI12:
3608                 soc15_program_register_sequence(adev,
3609                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3610                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3611                 break;
3612         default:
3613                 break;
3614         }
3615 }
3616
3617 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3618 {
3619         switch (adev->asic_type) {
3620         case CHIP_NAVI10:
3621                 soc15_program_register_sequence(adev,
3622                                                 golden_settings_gc_10_1,
3623                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3624                 soc15_program_register_sequence(adev,
3625                                                 golden_settings_gc_10_0_nv10,
3626                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3627                 break;
3628         case CHIP_NAVI14:
3629                 soc15_program_register_sequence(adev,
3630                                                 golden_settings_gc_10_1_1,
3631                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3632                 soc15_program_register_sequence(adev,
3633                                                 golden_settings_gc_10_1_nv14,
3634                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3635                 break;
3636         case CHIP_NAVI12:
3637                 soc15_program_register_sequence(adev,
3638                                                 golden_settings_gc_10_1_2,
3639                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3640                 soc15_program_register_sequence(adev,
3641                                                 golden_settings_gc_10_1_2_nv12,
3642                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3643                 break;
3644         case CHIP_SIENNA_CICHLID:
3645                 soc15_program_register_sequence(adev,
3646                                                 golden_settings_gc_10_3,
3647                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3648                 soc15_program_register_sequence(adev,
3649                                                 golden_settings_gc_10_3_sienna_cichlid,
3650                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3651                 break;
3652         case CHIP_NAVY_FLOUNDER:
3653                 soc15_program_register_sequence(adev,
3654                                                 golden_settings_gc_10_3_2,
3655                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3656                 break;
3657         case CHIP_VANGOGH:
3658                 soc15_program_register_sequence(adev,
3659                                                 golden_settings_gc_10_3_vangogh,
3660                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3661                 break;
3662         case CHIP_DIMGREY_CAVEFISH:
3663                 soc15_program_register_sequence(adev,
3664                                                 golden_settings_gc_10_3_4,
3665                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3666                 break;
3667         case CHIP_BEIGE_GOBY:
3668                 soc15_program_register_sequence(adev,
3669                                                 golden_settings_gc_10_3_5,
3670                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3671                 break;
3672         default:
3673                 break;
3674         }
3675         gfx_v10_0_init_spm_golden_registers(adev);
3676 }
3677
3678 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3679 {
3680         adev->gfx.scratch.num_reg = 8;
3681         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3682         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3683 }
3684
3685 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3686                                        bool wc, uint32_t reg, uint32_t val)
3687 {
3688         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3689         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3690                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3691         amdgpu_ring_write(ring, reg);
3692         amdgpu_ring_write(ring, 0);
3693         amdgpu_ring_write(ring, val);
3694 }
3695
3696 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3697                                   int mem_space, int opt, uint32_t addr0,
3698                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3699                                   uint32_t inv)
3700 {
3701         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3702         amdgpu_ring_write(ring,
3703                           /* memory (1) or register (0) */
3704                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3705                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3706                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3707                            WAIT_REG_MEM_ENGINE(eng_sel)));
3708
3709         if (mem_space)
3710                 BUG_ON(addr0 & 0x3); /* Dword align */
3711         amdgpu_ring_write(ring, addr0);
3712         amdgpu_ring_write(ring, addr1);
3713         amdgpu_ring_write(ring, ref);
3714         amdgpu_ring_write(ring, mask);
3715         amdgpu_ring_write(ring, inv); /* poll interval */
3716 }
3717
3718 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3719 {
3720         struct amdgpu_device *adev = ring->adev;
3721         uint32_t scratch;
3722         uint32_t tmp = 0;
3723         unsigned i;
3724         int r;
3725
3726         r = amdgpu_gfx_scratch_get(adev, &scratch);
3727         if (r) {
3728                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3729                 return r;
3730         }
3731
3732         WREG32(scratch, 0xCAFEDEAD);
3733
3734         r = amdgpu_ring_alloc(ring, 3);
3735         if (r) {
3736                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3737                           ring->idx, r);
3738                 amdgpu_gfx_scratch_free(adev, scratch);
3739                 return r;
3740         }
3741
3742         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3743         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3744         amdgpu_ring_write(ring, 0xDEADBEEF);
3745         amdgpu_ring_commit(ring);
3746
3747         for (i = 0; i < adev->usec_timeout; i++) {
3748                 tmp = RREG32(scratch);
3749                 if (tmp == 0xDEADBEEF)
3750                         break;
3751                 if (amdgpu_emu_mode == 1)
3752                         msleep(1);
3753                 else
3754                         udelay(1);
3755         }
3756
3757         if (i >= adev->usec_timeout)
3758                 r = -ETIMEDOUT;
3759
3760         amdgpu_gfx_scratch_free(adev, scratch);
3761
3762         return r;
3763 }
3764
3765 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3766 {
3767         struct amdgpu_device *adev = ring->adev;
3768         struct amdgpu_ib ib;
3769         struct dma_fence *f = NULL;
3770         unsigned index;
3771         uint64_t gpu_addr;
3772         uint32_t tmp;
3773         long r;
3774
3775         r = amdgpu_device_wb_get(adev, &index);
3776         if (r)
3777                 return r;
3778
3779         gpu_addr = adev->wb.gpu_addr + (index * 4);
3780         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3781         memset(&ib, 0, sizeof(ib));
3782         r = amdgpu_ib_get(adev, NULL, 16,
3783                                         AMDGPU_IB_POOL_DIRECT, &ib);
3784         if (r)
3785                 goto err1;
3786
3787         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3788         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3789         ib.ptr[2] = lower_32_bits(gpu_addr);
3790         ib.ptr[3] = upper_32_bits(gpu_addr);
3791         ib.ptr[4] = 0xDEADBEEF;
3792         ib.length_dw = 5;
3793
3794         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3795         if (r)
3796                 goto err2;
3797
3798         r = dma_fence_wait_timeout(f, false, timeout);
3799         if (r == 0) {
3800                 r = -ETIMEDOUT;
3801                 goto err2;
3802         } else if (r < 0) {
3803                 goto err2;
3804         }
3805
3806         tmp = adev->wb.wb[index];
3807         if (tmp == 0xDEADBEEF)
3808                 r = 0;
3809         else
3810                 r = -EINVAL;
3811 err2:
3812         amdgpu_ib_free(adev, &ib, NULL);
3813         dma_fence_put(f);
3814 err1:
3815         amdgpu_device_wb_free(adev, index);
3816         return r;
3817 }
3818
3819 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3820 {
3821         release_firmware(adev->gfx.pfp_fw);
3822         adev->gfx.pfp_fw = NULL;
3823         release_firmware(adev->gfx.me_fw);
3824         adev->gfx.me_fw = NULL;
3825         release_firmware(adev->gfx.ce_fw);
3826         adev->gfx.ce_fw = NULL;
3827         release_firmware(adev->gfx.rlc_fw);
3828         adev->gfx.rlc_fw = NULL;
3829         release_firmware(adev->gfx.mec_fw);
3830         adev->gfx.mec_fw = NULL;
3831         release_firmware(adev->gfx.mec2_fw);
3832         adev->gfx.mec2_fw = NULL;
3833
3834         kfree(adev->gfx.rlc.register_list_format);
3835 }
3836
3837 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3838 {
3839         adev->gfx.cp_fw_write_wait = false;
3840
3841         switch (adev->asic_type) {
3842         case CHIP_NAVI10:
3843         case CHIP_NAVI12:
3844         case CHIP_NAVI14:
3845                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3846                     (adev->gfx.me_feature_version >= 27) &&
3847                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3848                     (adev->gfx.pfp_feature_version >= 27) &&
3849                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3850                     (adev->gfx.mec_feature_version >= 27))
3851                         adev->gfx.cp_fw_write_wait = true;
3852                 break;
3853         case CHIP_SIENNA_CICHLID:
3854         case CHIP_NAVY_FLOUNDER:
3855         case CHIP_VANGOGH:
3856         case CHIP_DIMGREY_CAVEFISH:
3857         case CHIP_BEIGE_GOBY:
3858                 adev->gfx.cp_fw_write_wait = true;
3859                 break;
3860         default:
3861                 break;
3862         }
3863
3864         if (!adev->gfx.cp_fw_write_wait)
3865                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3866 }
3867
3868
3869 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3870 {
3871         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3872
3873         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3874         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3875         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3876         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3877         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3878         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3879         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3880         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3881         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3882         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3883         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3884         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3885         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3886         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3887                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3888 }
3889
3890 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3891 {
3892         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3893
3894         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3895         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3896         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3897         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3898         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3899 }
3900
3901 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3902 {
3903         bool ret = false;
3904
3905         switch (adev->pdev->revision) {
3906         case 0xc2:
3907         case 0xc3:
3908                 ret = true;
3909                 break;
3910         default:
3911                 ret = false;
3912                 break;
3913         }
3914
3915         return ret ;
3916 }
3917
3918 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3919 {
3920         switch (adev->asic_type) {
3921         case CHIP_NAVI10:
3922                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3923                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3924                 break;
3925         default:
3926                 break;
3927         }
3928 }
3929
3930 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3931 {
3932         const char *chip_name;
3933         char fw_name[40];
3934         char *wks = "";
3935         int err;
3936         struct amdgpu_firmware_info *info = NULL;
3937         const struct common_firmware_header *header = NULL;
3938         const struct gfx_firmware_header_v1_0 *cp_hdr;
3939         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3940         unsigned int *tmp = NULL;
3941         unsigned int i = 0;
3942         uint16_t version_major;
3943         uint16_t version_minor;
3944
3945         DRM_DEBUG("\n");
3946
3947         switch (adev->asic_type) {
3948         case CHIP_NAVI10:
3949                 chip_name = "navi10";
3950                 break;
3951         case CHIP_NAVI14:
3952                 chip_name = "navi14";
3953                 if (!(adev->pdev->device == 0x7340 &&
3954                       adev->pdev->revision != 0x00))
3955                         wks = "_wks";
3956                 break;
3957         case CHIP_NAVI12:
3958                 chip_name = "navi12";
3959                 break;
3960         case CHIP_SIENNA_CICHLID:
3961                 chip_name = "sienna_cichlid";
3962                 break;
3963         case CHIP_NAVY_FLOUNDER:
3964                 chip_name = "navy_flounder";
3965                 break;
3966         case CHIP_VANGOGH:
3967                 chip_name = "vangogh";
3968                 break;
3969         case CHIP_DIMGREY_CAVEFISH:
3970                 chip_name = "dimgrey_cavefish";
3971                 break;
3972         case CHIP_BEIGE_GOBY:
3973                 chip_name = "beige_goby";
3974                 break;
3975         default:
3976                 BUG();
3977         }
3978
3979         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3980         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3981         if (err)
3982                 goto out;
3983         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3984         if (err)
3985                 goto out;
3986         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3987         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3988         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3989
3990         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3991         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3992         if (err)
3993                 goto out;
3994         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3995         if (err)
3996                 goto out;
3997         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3998         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3999         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4000
4001         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4002         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4003         if (err)
4004                 goto out;
4005         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4006         if (err)
4007                 goto out;
4008         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4009         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4010         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4011
4012         if (!amdgpu_sriov_vf(adev)) {
4013                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4014                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4015                 if (err)
4016                         goto out;
4017                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4018                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4019                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4020                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4021
4022                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4023                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4024                 adev->gfx.rlc.save_and_restore_offset =
4025                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
4026                 adev->gfx.rlc.clear_state_descriptor_offset =
4027                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4028                 adev->gfx.rlc.avail_scratch_ram_locations =
4029                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4030                 adev->gfx.rlc.reg_restore_list_size =
4031                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
4032                 adev->gfx.rlc.reg_list_format_start =
4033                         le32_to_cpu(rlc_hdr->reg_list_format_start);
4034                 adev->gfx.rlc.reg_list_format_separate_start =
4035                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4036                 adev->gfx.rlc.starting_offsets_start =
4037                         le32_to_cpu(rlc_hdr->starting_offsets_start);
4038                 adev->gfx.rlc.reg_list_format_size_bytes =
4039                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4040                 adev->gfx.rlc.reg_list_size_bytes =
4041                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4042                 adev->gfx.rlc.register_list_format =
4043                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4044                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4045                 if (!adev->gfx.rlc.register_list_format) {
4046                         err = -ENOMEM;
4047                         goto out;
4048                 }
4049
4050                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4051                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4052                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4053                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4054
4055                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4056
4057                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4058                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4059                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4060                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4061
4062                 if (version_major == 2) {
4063                         if (version_minor >= 1)
4064                                 gfx_v10_0_init_rlc_ext_microcode(adev);
4065                         if (version_minor == 2)
4066                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4067                 }
4068         }
4069
4070         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4071         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4072         if (err)
4073                 goto out;
4074         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4075         if (err)
4076                 goto out;
4077         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4078         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4079         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4080
4081         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4082         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4083         if (!err) {
4084                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4085                 if (err)
4086                         goto out;
4087                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4088                 adev->gfx.mec2_fw->data;
4089                 adev->gfx.mec2_fw_version =
4090                 le32_to_cpu(cp_hdr->header.ucode_version);
4091                 adev->gfx.mec2_feature_version =
4092                 le32_to_cpu(cp_hdr->ucode_feature_version);
4093         } else {
4094                 err = 0;
4095                 adev->gfx.mec2_fw = NULL;
4096         }
4097
4098         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4099                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4100                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4101                 info->fw = adev->gfx.pfp_fw;
4102                 header = (const struct common_firmware_header *)info->fw->data;
4103                 adev->firmware.fw_size +=
4104                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4105
4106                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4107                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4108                 info->fw = adev->gfx.me_fw;
4109                 header = (const struct common_firmware_header *)info->fw->data;
4110                 adev->firmware.fw_size +=
4111                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4112
4113                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4114                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4115                 info->fw = adev->gfx.ce_fw;
4116                 header = (const struct common_firmware_header *)info->fw->data;
4117                 adev->firmware.fw_size +=
4118                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4119
4120                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4121                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4122                 info->fw = adev->gfx.rlc_fw;
4123                 if (info->fw) {
4124                         header = (const struct common_firmware_header *)info->fw->data;
4125                         adev->firmware.fw_size +=
4126                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4127                 }
4128                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4129                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4130                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4131                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4132                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4133                         info->fw = adev->gfx.rlc_fw;
4134                         adev->firmware.fw_size +=
4135                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4136
4137                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4138                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4139                         info->fw = adev->gfx.rlc_fw;
4140                         adev->firmware.fw_size +=
4141                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4142
4143                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4144                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4145                         info->fw = adev->gfx.rlc_fw;
4146                         adev->firmware.fw_size +=
4147                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4148
4149                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4150                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4151                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4152                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4153                                 info->fw = adev->gfx.rlc_fw;
4154                                 adev->firmware.fw_size +=
4155                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4156
4157                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4158                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4159                                 info->fw = adev->gfx.rlc_fw;
4160                                 adev->firmware.fw_size +=
4161                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4162                         }
4163                 }
4164
4165                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4166                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4167                 info->fw = adev->gfx.mec_fw;
4168                 header = (const struct common_firmware_header *)info->fw->data;
4169                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4170                 adev->firmware.fw_size +=
4171                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4172                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4173
4174                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4175                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4176                 info->fw = adev->gfx.mec_fw;
4177                 adev->firmware.fw_size +=
4178                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4179
4180                 if (adev->gfx.mec2_fw) {
4181                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4182                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4183                         info->fw = adev->gfx.mec2_fw;
4184                         header = (const struct common_firmware_header *)info->fw->data;
4185                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4186                         adev->firmware.fw_size +=
4187                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4188                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4189                                       PAGE_SIZE);
4190                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4191                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4192                         info->fw = adev->gfx.mec2_fw;
4193                         adev->firmware.fw_size +=
4194                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4195                                       PAGE_SIZE);
4196                 }
4197         }
4198
4199         gfx_v10_0_check_fw_write_wait(adev);
4200 out:
4201         if (err) {
4202                 dev_err(adev->dev,
4203                         "gfx10: Failed to load firmware \"%s\"\n",
4204                         fw_name);
4205                 release_firmware(adev->gfx.pfp_fw);
4206                 adev->gfx.pfp_fw = NULL;
4207                 release_firmware(adev->gfx.me_fw);
4208                 adev->gfx.me_fw = NULL;
4209                 release_firmware(adev->gfx.ce_fw);
4210                 adev->gfx.ce_fw = NULL;
4211                 release_firmware(adev->gfx.rlc_fw);
4212                 adev->gfx.rlc_fw = NULL;
4213                 release_firmware(adev->gfx.mec_fw);
4214                 adev->gfx.mec_fw = NULL;
4215                 release_firmware(adev->gfx.mec2_fw);
4216                 adev->gfx.mec2_fw = NULL;
4217         }
4218
4219         gfx_v10_0_check_gfxoff_flag(adev);
4220
4221         return err;
4222 }
4223
4224 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4225 {
4226         u32 count = 0;
4227         const struct cs_section_def *sect = NULL;
4228         const struct cs_extent_def *ext = NULL;
4229
4230         /* begin clear state */
4231         count += 2;
4232         /* context control state */
4233         count += 3;
4234
4235         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4236                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4237                         if (sect->id == SECT_CONTEXT)
4238                                 count += 2 + ext->reg_count;
4239                         else
4240                                 return 0;
4241                 }
4242         }
4243
4244         /* set PA_SC_TILE_STEERING_OVERRIDE */
4245         count += 3;
4246         /* end clear state */
4247         count += 2;
4248         /* clear state */
4249         count += 2;
4250
4251         return count;
4252 }
4253
4254 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4255                                     volatile u32 *buffer)
4256 {
4257         u32 count = 0, i;
4258         const struct cs_section_def *sect = NULL;
4259         const struct cs_extent_def *ext = NULL;
4260         int ctx_reg_offset;
4261
4262         if (adev->gfx.rlc.cs_data == NULL)
4263                 return;
4264         if (buffer == NULL)
4265                 return;
4266
4267         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4268         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4269
4270         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4271         buffer[count++] = cpu_to_le32(0x80000000);
4272         buffer[count++] = cpu_to_le32(0x80000000);
4273
4274         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4275                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4276                         if (sect->id == SECT_CONTEXT) {
4277                                 buffer[count++] =
4278                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4279                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4280                                                 PACKET3_SET_CONTEXT_REG_START);
4281                                 for (i = 0; i < ext->reg_count; i++)
4282                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4283                         } else {
4284                                 return;
4285                         }
4286                 }
4287         }
4288
4289         ctx_reg_offset =
4290                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4291         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4292         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4293         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4294
4295         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4296         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4297
4298         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4299         buffer[count++] = cpu_to_le32(0);
4300 }
4301
4302 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4303 {
4304         /* clear state block */
4305         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4306                         &adev->gfx.rlc.clear_state_gpu_addr,
4307                         (void **)&adev->gfx.rlc.cs_ptr);
4308
4309         /* jump table block */
4310         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4311                         &adev->gfx.rlc.cp_table_gpu_addr,
4312                         (void **)&adev->gfx.rlc.cp_table_ptr);
4313 }
4314
4315 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4316 {
4317         const struct cs_section_def *cs_data;
4318         int r;
4319
4320         adev->gfx.rlc.cs_data = gfx10_cs_data;
4321
4322         cs_data = adev->gfx.rlc.cs_data;
4323
4324         if (cs_data) {
4325                 /* init clear state block */
4326                 r = amdgpu_gfx_rlc_init_csb(adev);
4327                 if (r)
4328                         return r;
4329         }
4330
4331         /* init spm vmid with 0xf */
4332         if (adev->gfx.rlc.funcs->update_spm_vmid)
4333                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4334
4335         return 0;
4336 }
4337
4338 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4339 {
4340         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4341         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4342 }
4343
4344 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4345 {
4346         int r;
4347
4348         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4349
4350         amdgpu_gfx_graphics_queue_acquire(adev);
4351
4352         r = gfx_v10_0_init_microcode(adev);
4353         if (r)
4354                 DRM_ERROR("Failed to load gfx firmware!\n");
4355
4356         return r;
4357 }
4358
4359 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4360 {
4361         int r;
4362         u32 *hpd;
4363         const __le32 *fw_data = NULL;
4364         unsigned fw_size;
4365         u32 *fw = NULL;
4366         size_t mec_hpd_size;
4367
4368         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4369
4370         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4371
4372         /* take ownership of the relevant compute queues */
4373         amdgpu_gfx_compute_queue_acquire(adev);
4374         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4375
4376         if (mec_hpd_size) {
4377                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4378                                               AMDGPU_GEM_DOMAIN_GTT,
4379                                               &adev->gfx.mec.hpd_eop_obj,
4380                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4381                                               (void **)&hpd);
4382                 if (r) {
4383                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4384                         gfx_v10_0_mec_fini(adev);
4385                         return r;
4386                 }
4387
4388                 memset(hpd, 0, mec_hpd_size);
4389
4390                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4391                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4392         }
4393
4394         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4395                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4396
4397                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4398                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4399                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4400
4401                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4402                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4403                                               &adev->gfx.mec.mec_fw_obj,
4404                                               &adev->gfx.mec.mec_fw_gpu_addr,
4405                                               (void **)&fw);
4406                 if (r) {
4407                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4408                         gfx_v10_0_mec_fini(adev);
4409                         return r;
4410                 }
4411
4412                 memcpy(fw, fw_data, fw_size);
4413
4414                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4415                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4416         }
4417
4418         return 0;
4419 }
4420
4421 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4422 {
4423         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4424                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4425                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4426         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4427 }
4428
4429 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4430                            uint32_t thread, uint32_t regno,
4431                            uint32_t num, uint32_t *out)
4432 {
4433         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4434                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4435                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4436                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4437                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4438         while (num--)
4439                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4440 }
4441
4442 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4443 {
4444         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4445          * field when performing a select_se_sh so it should be
4446          * zero here */
4447         WARN_ON(simd != 0);
4448
4449         /* type 2 wave data */
4450         dst[(*no_fields)++] = 2;
4451         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4452         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4453         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4454         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4455         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4456         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4457         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4458         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4459         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4460         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4461         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4462         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4463         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4464         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4465         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4466 }
4467
4468 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4469                                      uint32_t wave, uint32_t start,
4470                                      uint32_t size, uint32_t *dst)
4471 {
4472         WARN_ON(simd != 0);
4473
4474         wave_read_regs(
4475                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4476                 dst);
4477 }
4478
4479 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4480                                       uint32_t wave, uint32_t thread,
4481                                       uint32_t start, uint32_t size,
4482                                       uint32_t *dst)
4483 {
4484         wave_read_regs(
4485                 adev, wave, thread,
4486                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4487 }
4488
4489 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4490                                        u32 me, u32 pipe, u32 q, u32 vm)
4491 {
4492         nv_grbm_select(adev, me, pipe, q, vm);
4493 }
4494
4495 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4496                                           bool enable)
4497 {
4498         uint32_t data, def;
4499
4500         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4501
4502         if (enable)
4503                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4504         else
4505                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4506
4507         if (data != def)
4508                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4509 }
4510
4511 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4512         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4513         .select_se_sh = &gfx_v10_0_select_se_sh,
4514         .read_wave_data = &gfx_v10_0_read_wave_data,
4515         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4516         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4517         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4518         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4519         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4520 };
4521
4522 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4523 {
4524         u32 gb_addr_config;
4525
4526         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4527
4528         switch (adev->asic_type) {
4529         case CHIP_NAVI10:
4530         case CHIP_NAVI14:
4531         case CHIP_NAVI12:
4532                 adev->gfx.config.max_hw_contexts = 8;
4533                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4534                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4535                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4536                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4537                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4538                 break;
4539         case CHIP_SIENNA_CICHLID:
4540         case CHIP_NAVY_FLOUNDER:
4541         case CHIP_VANGOGH:
4542         case CHIP_DIMGREY_CAVEFISH:
4543         case CHIP_BEIGE_GOBY:
4544                 adev->gfx.config.max_hw_contexts = 8;
4545                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4546                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4547                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4548                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4549                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4550                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4551                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4552                 break;
4553         default:
4554                 BUG();
4555                 break;
4556         }
4557
4558         adev->gfx.config.gb_addr_config = gb_addr_config;
4559
4560         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4561                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4562                                       GB_ADDR_CONFIG, NUM_PIPES);
4563
4564         adev->gfx.config.max_tile_pipes =
4565                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4566
4567         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4568                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4569                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4570         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4571                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4572                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4573         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4574                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4575                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4576         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4577                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4578                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4579 }
4580
4581 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4582                                    int me, int pipe, int queue)
4583 {
4584         int r;
4585         struct amdgpu_ring *ring;
4586         unsigned int irq_type;
4587
4588         ring = &adev->gfx.gfx_ring[ring_id];
4589
4590         ring->me = me;
4591         ring->pipe = pipe;
4592         ring->queue = queue;
4593
4594         ring->ring_obj = NULL;
4595         ring->use_doorbell = true;
4596
4597         if (!ring_id)
4598                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4599         else
4600                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4601         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4602
4603         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4604         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4605                              AMDGPU_RING_PRIO_DEFAULT, NULL);
4606         if (r)
4607                 return r;
4608         return 0;
4609 }
4610
4611 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4612                                        int mec, int pipe, int queue)
4613 {
4614         int r;
4615         unsigned irq_type;
4616         struct amdgpu_ring *ring;
4617         unsigned int hw_prio;
4618
4619         ring = &adev->gfx.compute_ring[ring_id];
4620
4621         /* mec0 is me1 */
4622         ring->me = mec + 1;
4623         ring->pipe = pipe;
4624         ring->queue = queue;
4625
4626         ring->ring_obj = NULL;
4627         ring->use_doorbell = true;
4628         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4629         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4630                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4631         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4632
4633         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4634                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4635                 + ring->pipe;
4636         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4637                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4638         /* type-2 packets are deprecated on MEC, use type-3 instead */
4639         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4640                              hw_prio, NULL);
4641         if (r)
4642                 return r;
4643
4644         return 0;
4645 }
4646
4647 static int gfx_v10_0_sw_init(void *handle)
4648 {
4649         int i, j, k, r, ring_id = 0;
4650         struct amdgpu_kiq *kiq;
4651         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4652
4653         switch (adev->asic_type) {
4654         case CHIP_NAVI10:
4655         case CHIP_NAVI14:
4656         case CHIP_NAVI12:
4657                 adev->gfx.me.num_me = 1;
4658                 adev->gfx.me.num_pipe_per_me = 1;
4659                 adev->gfx.me.num_queue_per_pipe = 1;
4660                 adev->gfx.mec.num_mec = 2;
4661                 adev->gfx.mec.num_pipe_per_mec = 4;
4662                 adev->gfx.mec.num_queue_per_pipe = 8;
4663                 break;
4664         case CHIP_SIENNA_CICHLID:
4665         case CHIP_NAVY_FLOUNDER:
4666         case CHIP_VANGOGH:
4667         case CHIP_DIMGREY_CAVEFISH:
4668         case CHIP_BEIGE_GOBY:
4669                 adev->gfx.me.num_me = 1;
4670                 adev->gfx.me.num_pipe_per_me = 1;
4671                 adev->gfx.me.num_queue_per_pipe = 1;
4672                 adev->gfx.mec.num_mec = 2;
4673                 adev->gfx.mec.num_pipe_per_mec = 4;
4674                 adev->gfx.mec.num_queue_per_pipe = 4;
4675                 break;
4676         default:
4677                 adev->gfx.me.num_me = 1;
4678                 adev->gfx.me.num_pipe_per_me = 1;
4679                 adev->gfx.me.num_queue_per_pipe = 1;
4680                 adev->gfx.mec.num_mec = 1;
4681                 adev->gfx.mec.num_pipe_per_mec = 4;
4682                 adev->gfx.mec.num_queue_per_pipe = 8;
4683                 break;
4684         }
4685
4686         /* KIQ event */
4687         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4688                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4689                               &adev->gfx.kiq.irq);
4690         if (r)
4691                 return r;
4692
4693         /* EOP Event */
4694         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4695                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4696                               &adev->gfx.eop_irq);
4697         if (r)
4698                 return r;
4699
4700         /* Privileged reg */
4701         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4702                               &adev->gfx.priv_reg_irq);
4703         if (r)
4704                 return r;
4705
4706         /* Privileged inst */
4707         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4708                               &adev->gfx.priv_inst_irq);
4709         if (r)
4710                 return r;
4711
4712         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4713
4714         gfx_v10_0_scratch_init(adev);
4715
4716         r = gfx_v10_0_me_init(adev);
4717         if (r)
4718                 return r;
4719
4720         r = gfx_v10_0_rlc_init(adev);
4721         if (r) {
4722                 DRM_ERROR("Failed to init rlc BOs!\n");
4723                 return r;
4724         }
4725
4726         r = gfx_v10_0_mec_init(adev);
4727         if (r) {
4728                 DRM_ERROR("Failed to init MEC BOs!\n");
4729                 return r;
4730         }
4731
4732         /* set up the gfx ring */
4733         for (i = 0; i < adev->gfx.me.num_me; i++) {
4734                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4735                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4736                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4737                                         continue;
4738
4739                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4740                                                             i, k, j);
4741                                 if (r)
4742                                         return r;
4743                                 ring_id++;
4744                         }
4745                 }
4746         }
4747
4748         ring_id = 0;
4749         /* set up the compute queues - allocate horizontally across pipes */
4750         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4751                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4752                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4753                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4754                                                                      j))
4755                                         continue;
4756
4757                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4758                                                                 i, k, j);
4759                                 if (r)
4760                                         return r;
4761
4762                                 ring_id++;
4763                         }
4764                 }
4765         }
4766
4767         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4768         if (r) {
4769                 DRM_ERROR("Failed to init KIQ BOs!\n");
4770                 return r;
4771         }
4772
4773         kiq = &adev->gfx.kiq;
4774         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4775         if (r)
4776                 return r;
4777
4778         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4779         if (r)
4780                 return r;
4781
4782         /* allocate visible FB for rlc auto-loading fw */
4783         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4784                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4785                 if (r)
4786                         return r;
4787         }
4788
4789         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4790
4791         gfx_v10_0_gpu_early_init(adev);
4792
4793         return 0;
4794 }
4795
4796 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4797 {
4798         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4799                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4800                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4801 }
4802
4803 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4804 {
4805         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4806                               &adev->gfx.ce.ce_fw_gpu_addr,
4807                               (void **)&adev->gfx.ce.ce_fw_ptr);
4808 }
4809
4810 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4811 {
4812         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4813                               &adev->gfx.me.me_fw_gpu_addr,
4814                               (void **)&adev->gfx.me.me_fw_ptr);
4815 }
4816
4817 static int gfx_v10_0_sw_fini(void *handle)
4818 {
4819         int i;
4820         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4821
4822         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4823                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4824         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4825                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4826
4827         amdgpu_gfx_mqd_sw_fini(adev);
4828         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4829         amdgpu_gfx_kiq_fini(adev);
4830
4831         gfx_v10_0_pfp_fini(adev);
4832         gfx_v10_0_ce_fini(adev);
4833         gfx_v10_0_me_fini(adev);
4834         gfx_v10_0_rlc_fini(adev);
4835         gfx_v10_0_mec_fini(adev);
4836
4837         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4838                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4839
4840         gfx_v10_0_free_microcode(adev);
4841
4842         return 0;
4843 }
4844
4845 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4846                                    u32 sh_num, u32 instance)
4847 {
4848         u32 data;
4849
4850         if (instance == 0xffffffff)
4851                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4852                                      INSTANCE_BROADCAST_WRITES, 1);
4853         else
4854                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4855                                      instance);
4856
4857         if (se_num == 0xffffffff)
4858                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4859                                      1);
4860         else
4861                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4862
4863         if (sh_num == 0xffffffff)
4864                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4865                                      1);
4866         else
4867                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4868
4869         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4870 }
4871
4872 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4873 {
4874         u32 data, mask;
4875
4876         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4877         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4878
4879         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4880         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4881
4882         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4883                                          adev->gfx.config.max_sh_per_se);
4884
4885         return (~data) & mask;
4886 }
4887
4888 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4889 {
4890         int i, j;
4891         u32 data;
4892         u32 active_rbs = 0;
4893         u32 bitmap;
4894         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4895                                         adev->gfx.config.max_sh_per_se;
4896
4897         mutex_lock(&adev->grbm_idx_mutex);
4898         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4899                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4900                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4901                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4902                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4903                                 continue;
4904                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4905                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4906                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4907                                                rb_bitmap_width_per_sh);
4908                 }
4909         }
4910         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4911         mutex_unlock(&adev->grbm_idx_mutex);
4912
4913         adev->gfx.config.backend_enable_mask = active_rbs;
4914         adev->gfx.config.num_rbs = hweight32(active_rbs);
4915 }
4916
4917 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4918 {
4919         uint32_t num_sc;
4920         uint32_t enabled_rb_per_sh;
4921         uint32_t active_rb_bitmap;
4922         uint32_t num_rb_per_sc;
4923         uint32_t num_packer_per_sc;
4924         uint32_t pa_sc_tile_steering_override;
4925
4926         /* for ASICs that integrates GFX v10.3
4927          * pa_sc_tile_steering_override should be set to 0 */
4928         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4929                 return 0;
4930
4931         /* init num_sc */
4932         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4933                         adev->gfx.config.num_sc_per_sh;
4934         /* init num_rb_per_sc */
4935         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4936         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4937         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4938         /* init num_packer_per_sc */
4939         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4940
4941         pa_sc_tile_steering_override = 0;
4942         pa_sc_tile_steering_override |=
4943                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4944                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4945         pa_sc_tile_steering_override |=
4946                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4947                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4948         pa_sc_tile_steering_override |=
4949                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4950                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4951
4952         return pa_sc_tile_steering_override;
4953 }
4954
4955 #define DEFAULT_SH_MEM_BASES    (0x6000)
4956
4957 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4958 {
4959         int i;
4960         uint32_t sh_mem_bases;
4961
4962         /*
4963          * Configure apertures:
4964          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4965          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4966          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4967          */
4968         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4969
4970         mutex_lock(&adev->srbm_mutex);
4971         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4972                 nv_grbm_select(adev, 0, 0, 0, i);
4973                 /* CP and shaders */
4974                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4975                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4976         }
4977         nv_grbm_select(adev, 0, 0, 0, 0);
4978         mutex_unlock(&adev->srbm_mutex);
4979
4980         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4981            acccess. These should be enabled by FW for target VMIDs. */
4982         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4983                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4984                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4985                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4986                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4987         }
4988 }
4989
4990 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4991 {
4992         int vmid;
4993
4994         /*
4995          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4996          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4997          * the driver can enable them for graphics. VMID0 should maintain
4998          * access so that HWS firmware can save/restore entries.
4999          */
5000         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5001                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5002                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5003                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5004                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5005         }
5006 }
5007
5008
5009 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5010 {
5011         int i, j, k;
5012         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5013         u32 tmp, wgp_active_bitmap = 0;
5014         u32 gcrd_targets_disable_tcp = 0;
5015         u32 utcl_invreq_disable = 0;
5016         /*
5017          * GCRD_TARGETS_DISABLE field contains
5018          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5019          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5020          */
5021         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5022                 2 * max_wgp_per_sh + /* TCP */
5023                 max_wgp_per_sh + /* SQC */
5024                 4); /* GL1C */
5025         /*
5026          * UTCL1_UTCL0_INVREQ_DISABLE field contains
5027          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5028          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5029          */
5030         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5031                 2 * max_wgp_per_sh + /* TCP */
5032                 2 * max_wgp_per_sh + /* SQC */
5033                 4 + /* RMI */
5034                 1); /* SQG */
5035
5036         if (adev->asic_type == CHIP_NAVI10 ||
5037             adev->asic_type == CHIP_NAVI14 ||
5038             adev->asic_type == CHIP_NAVI12) {
5039                 mutex_lock(&adev->grbm_idx_mutex);
5040                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5041                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5042                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5043                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5044                                 /*
5045                                  * Set corresponding TCP bits for the inactive WGPs in
5046                                  * GCRD_SA_TARGETS_DISABLE
5047                                  */
5048                                 gcrd_targets_disable_tcp = 0;
5049                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5050                                 utcl_invreq_disable = 0;
5051
5052                                 for (k = 0; k < max_wgp_per_sh; k++) {
5053                                         if (!(wgp_active_bitmap & (1 << k))) {
5054                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
5055                                                 utcl_invreq_disable |= (3 << (2 * k)) |
5056                                                         (3 << (2 * (max_wgp_per_sh + k)));
5057                                         }
5058                                 }
5059
5060                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5061                                 /* only override TCP & SQC bits */
5062                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
5063                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5064                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5065
5066                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5067                                 /* only override TCP bits */
5068                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
5069                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5070                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5071                         }
5072                 }
5073
5074                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5075                 mutex_unlock(&adev->grbm_idx_mutex);
5076         }
5077 }
5078
5079 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5080 {
5081         /* TCCs are global (not instanced). */
5082         uint32_t tcc_disable;
5083
5084         if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
5085                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5086                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5087         } else {
5088                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5089                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5090         }
5091
5092         adev->gfx.config.tcc_disabled_mask =
5093                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5094                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5095 }
5096
5097 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5098 {
5099         u32 tmp;
5100         int i;
5101
5102         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5103
5104         gfx_v10_0_setup_rb(adev);
5105         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5106         gfx_v10_0_get_tcc_info(adev);
5107         adev->gfx.config.pa_sc_tile_steering_override =
5108                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5109
5110         /* XXX SH_MEM regs */
5111         /* where to put LDS, scratch, GPUVM in FSA64 space */
5112         mutex_lock(&adev->srbm_mutex);
5113         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5114                 nv_grbm_select(adev, 0, 0, 0, i);
5115                 /* CP and shaders */
5116                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5117                 if (i != 0) {
5118                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5119                                 (adev->gmc.private_aperture_start >> 48));
5120                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5121                                 (adev->gmc.shared_aperture_start >> 48));
5122                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5123                 }
5124         }
5125         nv_grbm_select(adev, 0, 0, 0, 0);
5126
5127         mutex_unlock(&adev->srbm_mutex);
5128
5129         gfx_v10_0_init_compute_vmid(adev);
5130         gfx_v10_0_init_gds_vmid(adev);
5131
5132 }
5133
5134 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5135                                                bool enable)
5136 {
5137         u32 tmp;
5138
5139         if (amdgpu_sriov_vf(adev))
5140                 return;
5141
5142         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5143
5144         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5145                             enable ? 1 : 0);
5146         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5147                             enable ? 1 : 0);
5148         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5149                             enable ? 1 : 0);
5150         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5151                             enable ? 1 : 0);
5152
5153         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5154 }
5155
5156 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5157 {
5158         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5159
5160         /* csib */
5161         if (adev->asic_type == CHIP_NAVI12) {
5162                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5163                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5164                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5165                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5166                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5167         } else {
5168                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5169                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5170                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5171                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5172                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5173         }
5174         return 0;
5175 }
5176
5177 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5178 {
5179         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5180
5181         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5182         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5183 }
5184
5185 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5186 {
5187         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5188         udelay(50);
5189         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5190         udelay(50);
5191 }
5192
5193 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5194                                              bool enable)
5195 {
5196         uint32_t rlc_pg_cntl;
5197
5198         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5199
5200         if (!enable) {
5201                 /* RLC_PG_CNTL[23] = 0 (default)
5202                  * RLC will wait for handshake acks with SMU
5203                  * GFXOFF will be enabled
5204                  * RLC_PG_CNTL[23] = 1
5205                  * RLC will not issue any message to SMU
5206                  * hence no handshake between SMU & RLC
5207                  * GFXOFF will be disabled
5208                  */
5209                 rlc_pg_cntl |= 0x800000;
5210         } else
5211                 rlc_pg_cntl &= ~0x800000;
5212         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5213 }
5214
5215 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5216 {
5217         /* TODO: enable rlc & smu handshake until smu
5218          * and gfxoff feature works as expected */
5219         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5220                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5221
5222         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5223         udelay(50);
5224 }
5225
5226 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5227 {
5228         uint32_t tmp;
5229
5230         /* enable Save Restore Machine */
5231         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5232         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5233         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5234         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5235 }
5236
5237 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5238 {
5239         const struct rlc_firmware_header_v2_0 *hdr;
5240         const __le32 *fw_data;
5241         unsigned i, fw_size;
5242
5243         if (!adev->gfx.rlc_fw)
5244                 return -EINVAL;
5245
5246         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5247         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5248
5249         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5250                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5251         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5252
5253         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5254                      RLCG_UCODE_LOADING_START_ADDRESS);
5255
5256         for (i = 0; i < fw_size; i++)
5257                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5258                              le32_to_cpup(fw_data++));
5259
5260         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5261
5262         return 0;
5263 }
5264
5265 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5266 {
5267         int r;
5268
5269         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5270
5271                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5272                 if (r)
5273                         return r;
5274
5275                 gfx_v10_0_init_csb(adev);
5276
5277                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5278                         gfx_v10_0_rlc_enable_srm(adev);
5279         } else {
5280                 if (amdgpu_sriov_vf(adev)) {
5281                         gfx_v10_0_init_csb(adev);
5282                         return 0;
5283                 }
5284
5285                 adev->gfx.rlc.funcs->stop(adev);
5286
5287                 /* disable CG */
5288                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5289
5290                 /* disable PG */
5291                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5292
5293                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5294                         /* legacy rlc firmware loading */
5295                         r = gfx_v10_0_rlc_load_microcode(adev);
5296                         if (r)
5297                                 return r;
5298                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5299                         /* rlc backdoor autoload firmware */
5300                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5301                         if (r)
5302                                 return r;
5303                 }
5304
5305                 gfx_v10_0_init_csb(adev);
5306
5307                 adev->gfx.rlc.funcs->start(adev);
5308
5309                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5310                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5311                         if (r)
5312                                 return r;
5313                 }
5314         }
5315         return 0;
5316 }
5317
5318 static struct {
5319         FIRMWARE_ID     id;
5320         unsigned int    offset;
5321         unsigned int    size;
5322 } rlc_autoload_info[FIRMWARE_ID_MAX];
5323
5324 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5325 {
5326         int ret;
5327         RLC_TABLE_OF_CONTENT *rlc_toc;
5328
5329         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5330                                         AMDGPU_GEM_DOMAIN_GTT,
5331                                         &adev->gfx.rlc.rlc_toc_bo,
5332                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5333                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5334         if (ret) {
5335                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5336                 return ret;
5337         }
5338
5339         /* Copy toc from psp sos fw to rlc toc buffer */
5340         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5341
5342         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5343         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5344                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5345                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5346                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5347                         /* Offset needs 4KB alignment */
5348                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5349                 }
5350
5351                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5352                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5353                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5354
5355                 rlc_toc++;
5356         }
5357
5358         return 0;
5359 }
5360
5361 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5362 {
5363         uint32_t total_size = 0;
5364         FIRMWARE_ID id;
5365         int ret;
5366
5367         ret = gfx_v10_0_parse_rlc_toc(adev);
5368         if (ret) {
5369                 dev_err(adev->dev, "failed to parse rlc toc\n");
5370                 return 0;
5371         }
5372
5373         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5374                 total_size += rlc_autoload_info[id].size;
5375
5376         /* In case the offset in rlc toc ucode is aligned */
5377         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5378                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5379                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5380
5381         return total_size;
5382 }
5383
5384 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5385 {
5386         int r;
5387         uint32_t total_size;
5388
5389         total_size = gfx_v10_0_calc_toc_total_size(adev);
5390
5391         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5392                                       AMDGPU_GEM_DOMAIN_GTT,
5393                                       &adev->gfx.rlc.rlc_autoload_bo,
5394                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5395                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5396         if (r) {
5397                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5398                 return r;
5399         }
5400
5401         return 0;
5402 }
5403
5404 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5405 {
5406         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5407                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5408                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5409         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5410                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5411                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5412 }
5413
5414 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5415                                                        FIRMWARE_ID id,
5416                                                        const void *fw_data,
5417                                                        uint32_t fw_size)
5418 {
5419         uint32_t toc_offset;
5420         uint32_t toc_fw_size;
5421         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5422
5423         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5424                 return;
5425
5426         toc_offset = rlc_autoload_info[id].offset;
5427         toc_fw_size = rlc_autoload_info[id].size;
5428
5429         if (fw_size == 0)
5430                 fw_size = toc_fw_size;
5431
5432         if (fw_size > toc_fw_size)
5433                 fw_size = toc_fw_size;
5434
5435         memcpy(ptr + toc_offset, fw_data, fw_size);
5436
5437         if (fw_size < toc_fw_size)
5438                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5439 }
5440
5441 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5442 {
5443         void *data;
5444         uint32_t size;
5445
5446         data = adev->gfx.rlc.rlc_toc_buf;
5447         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5448
5449         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5450                                                    FIRMWARE_ID_RLC_TOC,
5451                                                    data, size);
5452 }
5453
5454 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5455 {
5456         const __le32 *fw_data;
5457         uint32_t fw_size;
5458         const struct gfx_firmware_header_v1_0 *cp_hdr;
5459         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5460
5461         /* pfp ucode */
5462         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5463                 adev->gfx.pfp_fw->data;
5464         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5465                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5466         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5467         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5468                                                    FIRMWARE_ID_CP_PFP,
5469                                                    fw_data, fw_size);
5470
5471         /* ce ucode */
5472         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5473                 adev->gfx.ce_fw->data;
5474         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5475                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5476         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5477         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5478                                                    FIRMWARE_ID_CP_CE,
5479                                                    fw_data, fw_size);
5480
5481         /* me ucode */
5482         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5483                 adev->gfx.me_fw->data;
5484         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5485                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5486         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5487         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5488                                                    FIRMWARE_ID_CP_ME,
5489                                                    fw_data, fw_size);
5490
5491         /* rlc ucode */
5492         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5493                 adev->gfx.rlc_fw->data;
5494         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5495                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5496         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5497         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5498                                                    FIRMWARE_ID_RLC_G_UCODE,
5499                                                    fw_data, fw_size);
5500
5501         /* mec1 ucode */
5502         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5503                 adev->gfx.mec_fw->data;
5504         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5505                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5506         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5507                 cp_hdr->jt_size * 4;
5508         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5509                                                    FIRMWARE_ID_CP_MEC,
5510                                                    fw_data, fw_size);
5511         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5512 }
5513
5514 /* Temporarily put sdma part here */
5515 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5516 {
5517         const __le32 *fw_data;
5518         uint32_t fw_size;
5519         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5520         int i;
5521
5522         for (i = 0; i < adev->sdma.num_instances; i++) {
5523                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5524                         adev->sdma.instance[i].fw->data;
5525                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5526                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5527                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5528
5529                 if (i == 0) {
5530                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5531                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5532                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5533                                 FIRMWARE_ID_SDMA0_JT,
5534                                 (uint32_t *)fw_data +
5535                                 sdma_hdr->jt_offset,
5536                                 sdma_hdr->jt_size * 4);
5537                 } else if (i == 1) {
5538                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5539                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5540                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5541                                 FIRMWARE_ID_SDMA1_JT,
5542                                 (uint32_t *)fw_data +
5543                                 sdma_hdr->jt_offset,
5544                                 sdma_hdr->jt_size * 4);
5545                 }
5546         }
5547 }
5548
5549 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5550 {
5551         uint32_t rlc_g_offset, rlc_g_size, tmp;
5552         uint64_t gpu_addr;
5553
5554         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5555         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5556         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5557
5558         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5559         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5560         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5561
5562         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5563         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5564         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5565
5566         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5567         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5568                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5569                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5570                 return -EINVAL;
5571         }
5572
5573         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5574         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5575                 DRM_ERROR("RLC ROM should halt itself\n");
5576                 return -EINVAL;
5577         }
5578
5579         return 0;
5580 }
5581
5582 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5583 {
5584         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5585         uint32_t tmp;
5586         int i;
5587         uint64_t addr;
5588
5589         /* Trigger an invalidation of the L1 instruction caches */
5590         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5591         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5592         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5593
5594         /* Wait for invalidation complete */
5595         for (i = 0; i < usec_timeout; i++) {
5596                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5597                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5598                         INVALIDATE_CACHE_COMPLETE))
5599                         break;
5600                 udelay(1);
5601         }
5602
5603         if (i >= usec_timeout) {
5604                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5605                 return -EINVAL;
5606         }
5607
5608         /* Program me ucode address into intruction cache address register */
5609         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5610                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5611         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5612                         lower_32_bits(addr) & 0xFFFFF000);
5613         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5614                         upper_32_bits(addr));
5615
5616         return 0;
5617 }
5618
5619 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5620 {
5621         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5622         uint32_t tmp;
5623         int i;
5624         uint64_t addr;
5625
5626         /* Trigger an invalidation of the L1 instruction caches */
5627         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5628         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5629         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5630
5631         /* Wait for invalidation complete */
5632         for (i = 0; i < usec_timeout; i++) {
5633                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5634                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5635                         INVALIDATE_CACHE_COMPLETE))
5636                         break;
5637                 udelay(1);
5638         }
5639
5640         if (i >= usec_timeout) {
5641                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5642                 return -EINVAL;
5643         }
5644
5645         /* Program ce ucode address into intruction cache address register */
5646         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5647                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5648         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5649                         lower_32_bits(addr) & 0xFFFFF000);
5650         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5651                         upper_32_bits(addr));
5652
5653         return 0;
5654 }
5655
5656 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5657 {
5658         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5659         uint32_t tmp;
5660         int i;
5661         uint64_t addr;
5662
5663         /* Trigger an invalidation of the L1 instruction caches */
5664         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5665         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5666         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5667
5668         /* Wait for invalidation complete */
5669         for (i = 0; i < usec_timeout; i++) {
5670                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5671                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5672                         INVALIDATE_CACHE_COMPLETE))
5673                         break;
5674                 udelay(1);
5675         }
5676
5677         if (i >= usec_timeout) {
5678                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5679                 return -EINVAL;
5680         }
5681
5682         /* Program pfp ucode address into intruction cache address register */
5683         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5684                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5685         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5686                         lower_32_bits(addr) & 0xFFFFF000);
5687         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5688                         upper_32_bits(addr));
5689
5690         return 0;
5691 }
5692
5693 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5694 {
5695         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5696         uint32_t tmp;
5697         int i;
5698         uint64_t addr;
5699
5700         /* Trigger an invalidation of the L1 instruction caches */
5701         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5702         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5703         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5704
5705         /* Wait for invalidation complete */
5706         for (i = 0; i < usec_timeout; i++) {
5707                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5708                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5709                         INVALIDATE_CACHE_COMPLETE))
5710                         break;
5711                 udelay(1);
5712         }
5713
5714         if (i >= usec_timeout) {
5715                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5716                 return -EINVAL;
5717         }
5718
5719         /* Program mec1 ucode address into intruction cache address register */
5720         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5721                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5722         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5723                         lower_32_bits(addr) & 0xFFFFF000);
5724         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5725                         upper_32_bits(addr));
5726
5727         return 0;
5728 }
5729
5730 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5731 {
5732         uint32_t cp_status;
5733         uint32_t bootload_status;
5734         int i, r;
5735
5736         for (i = 0; i < adev->usec_timeout; i++) {
5737                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5738                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5739                 if ((cp_status == 0) &&
5740                     (REG_GET_FIELD(bootload_status,
5741                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5742                         break;
5743                 }
5744                 udelay(1);
5745         }
5746
5747         if (i >= adev->usec_timeout) {
5748                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5749                 return -ETIMEDOUT;
5750         }
5751
5752         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5753                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5754                 if (r)
5755                         return r;
5756
5757                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5758                 if (r)
5759                         return r;
5760
5761                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5762                 if (r)
5763                         return r;
5764
5765                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5766                 if (r)
5767                         return r;
5768         }
5769
5770         return 0;
5771 }
5772
5773 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5774 {
5775         int i;
5776         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5777
5778         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5779         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5780         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5781
5782         if (adev->asic_type == CHIP_NAVI12) {
5783                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5784         } else {
5785                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5786         }
5787
5788         for (i = 0; i < adev->usec_timeout; i++) {
5789                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5790                         break;
5791                 udelay(1);
5792         }
5793
5794         if (i >= adev->usec_timeout)
5795                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5796
5797         return 0;
5798 }
5799
5800 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5801 {
5802         int r;
5803         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5804         const __le32 *fw_data;
5805         unsigned i, fw_size;
5806         uint32_t tmp;
5807         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5808
5809         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5810                 adev->gfx.pfp_fw->data;
5811
5812         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5813
5814         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5815                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5816         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5817
5818         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5819                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5820                                       &adev->gfx.pfp.pfp_fw_obj,
5821                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5822                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5823         if (r) {
5824                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5825                 gfx_v10_0_pfp_fini(adev);
5826                 return r;
5827         }
5828
5829         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5830
5831         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5832         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5833
5834         /* Trigger an invalidation of the L1 instruction caches */
5835         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5836         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5837         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5838
5839         /* Wait for invalidation complete */
5840         for (i = 0; i < usec_timeout; i++) {
5841                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5842                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5843                         INVALIDATE_CACHE_COMPLETE))
5844                         break;
5845                 udelay(1);
5846         }
5847
5848         if (i >= usec_timeout) {
5849                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5850                 return -EINVAL;
5851         }
5852
5853         if (amdgpu_emu_mode == 1)
5854                 adev->hdp.funcs->flush_hdp(adev, NULL);
5855
5856         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5857         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5858         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5859         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5860         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5861         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5862         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5863                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5864         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5865                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5866
5867         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5868
5869         for (i = 0; i < pfp_hdr->jt_size; i++)
5870                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5871                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5872
5873         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5874
5875         return 0;
5876 }
5877
5878 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5879 {
5880         int r;
5881         const struct gfx_firmware_header_v1_0 *ce_hdr;
5882         const __le32 *fw_data;
5883         unsigned i, fw_size;
5884         uint32_t tmp;
5885         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5886
5887         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5888                 adev->gfx.ce_fw->data;
5889
5890         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5891
5892         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5893                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5894         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5895
5896         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5897                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5898                                       &adev->gfx.ce.ce_fw_obj,
5899                                       &adev->gfx.ce.ce_fw_gpu_addr,
5900                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5901         if (r) {
5902                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5903                 gfx_v10_0_ce_fini(adev);
5904                 return r;
5905         }
5906
5907         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5908
5909         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5910         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5911
5912         /* Trigger an invalidation of the L1 instruction caches */
5913         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5914         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5915         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5916
5917         /* Wait for invalidation complete */
5918         for (i = 0; i < usec_timeout; i++) {
5919                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5920                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5921                         INVALIDATE_CACHE_COMPLETE))
5922                         break;
5923                 udelay(1);
5924         }
5925
5926         if (i >= usec_timeout) {
5927                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5928                 return -EINVAL;
5929         }
5930
5931         if (amdgpu_emu_mode == 1)
5932                 adev->hdp.funcs->flush_hdp(adev, NULL);
5933
5934         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5935         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5936         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5937         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5938         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5939         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5940                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5941         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5942                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5943
5944         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5945
5946         for (i = 0; i < ce_hdr->jt_size; i++)
5947                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5948                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5949
5950         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5951
5952         return 0;
5953 }
5954
5955 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5956 {
5957         int r;
5958         const struct gfx_firmware_header_v1_0 *me_hdr;
5959         const __le32 *fw_data;
5960         unsigned i, fw_size;
5961         uint32_t tmp;
5962         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5963
5964         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5965                 adev->gfx.me_fw->data;
5966
5967         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5968
5969         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5970                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5971         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5972
5973         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5974                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5975                                       &adev->gfx.me.me_fw_obj,
5976                                       &adev->gfx.me.me_fw_gpu_addr,
5977                                       (void **)&adev->gfx.me.me_fw_ptr);
5978         if (r) {
5979                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5980                 gfx_v10_0_me_fini(adev);
5981                 return r;
5982         }
5983
5984         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5985
5986         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5987         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5988
5989         /* Trigger an invalidation of the L1 instruction caches */
5990         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5991         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5992         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5993
5994         /* Wait for invalidation complete */
5995         for (i = 0; i < usec_timeout; i++) {
5996                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5997                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5998                         INVALIDATE_CACHE_COMPLETE))
5999                         break;
6000                 udelay(1);
6001         }
6002
6003         if (i >= usec_timeout) {
6004                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6005                 return -EINVAL;
6006         }
6007
6008         if (amdgpu_emu_mode == 1)
6009                 adev->hdp.funcs->flush_hdp(adev, NULL);
6010
6011         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6012         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6013         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6014         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6015         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6016         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6017                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6018         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6019                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6020
6021         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6022
6023         for (i = 0; i < me_hdr->jt_size; i++)
6024                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6025                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6026
6027         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6028
6029         return 0;
6030 }
6031
6032 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6033 {
6034         int r;
6035
6036         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6037                 return -EINVAL;
6038
6039         gfx_v10_0_cp_gfx_enable(adev, false);
6040
6041         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6042         if (r) {
6043                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6044                 return r;
6045         }
6046
6047         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6048         if (r) {
6049                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6050                 return r;
6051         }
6052
6053         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6054         if (r) {
6055                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6056                 return r;
6057         }
6058
6059         return 0;
6060 }
6061
6062 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6063 {
6064         struct amdgpu_ring *ring;
6065         const struct cs_section_def *sect = NULL;
6066         const struct cs_extent_def *ext = NULL;
6067         int r, i;
6068         int ctx_reg_offset;
6069
6070         /* init the CP */
6071         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6072                      adev->gfx.config.max_hw_contexts - 1);
6073         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6074
6075         gfx_v10_0_cp_gfx_enable(adev, true);
6076
6077         ring = &adev->gfx.gfx_ring[0];
6078         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6079         if (r) {
6080                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6081                 return r;
6082         }
6083
6084         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6085         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6086
6087         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6088         amdgpu_ring_write(ring, 0x80000000);
6089         amdgpu_ring_write(ring, 0x80000000);
6090
6091         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6092                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6093                         if (sect->id == SECT_CONTEXT) {
6094                                 amdgpu_ring_write(ring,
6095                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6096                                                           ext->reg_count));
6097                                 amdgpu_ring_write(ring, ext->reg_index -
6098                                                   PACKET3_SET_CONTEXT_REG_START);
6099                                 for (i = 0; i < ext->reg_count; i++)
6100                                         amdgpu_ring_write(ring, ext->extent[i]);
6101                         }
6102                 }
6103         }
6104
6105         ctx_reg_offset =
6106                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6107         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6108         amdgpu_ring_write(ring, ctx_reg_offset);
6109         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6110
6111         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6112         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6113
6114         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6115         amdgpu_ring_write(ring, 0);
6116
6117         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6118         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6119         amdgpu_ring_write(ring, 0x8000);
6120         amdgpu_ring_write(ring, 0x8000);
6121
6122         amdgpu_ring_commit(ring);
6123
6124         /* submit cs packet to copy state 0 to next available state */
6125         if (adev->gfx.num_gfx_rings > 1) {
6126                 /* maximum supported gfx ring is 2 */
6127                 ring = &adev->gfx.gfx_ring[1];
6128                 r = amdgpu_ring_alloc(ring, 2);
6129                 if (r) {
6130                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6131                         return r;
6132                 }
6133
6134                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6135                 amdgpu_ring_write(ring, 0);
6136
6137                 amdgpu_ring_commit(ring);
6138         }
6139         return 0;
6140 }
6141
6142 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6143                                          CP_PIPE_ID pipe)
6144 {
6145         u32 tmp;
6146
6147         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6148         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6149
6150         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6151 }
6152
6153 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6154                                           struct amdgpu_ring *ring)
6155 {
6156         u32 tmp;
6157
6158         if (!amdgpu_async_gfx_ring) {
6159                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6160                 if (ring->use_doorbell) {
6161                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6162                                                 DOORBELL_OFFSET, ring->doorbell_index);
6163                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6164                                                 DOORBELL_EN, 1);
6165                 } else {
6166                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6167                                                 DOORBELL_EN, 0);
6168                 }
6169                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6170         }
6171         switch (adev->asic_type) {
6172         case CHIP_SIENNA_CICHLID:
6173         case CHIP_NAVY_FLOUNDER:
6174         case CHIP_VANGOGH:
6175         case CHIP_DIMGREY_CAVEFISH:
6176         case CHIP_BEIGE_GOBY:
6177                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6178                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6179                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6180
6181                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6182                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6183                 break;
6184         default:
6185                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6186                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6187                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6188
6189                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6190                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6191                 break;
6192         }
6193 }
6194
6195 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6196 {
6197         struct amdgpu_ring *ring;
6198         u32 tmp;
6199         u32 rb_bufsz;
6200         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6201         u32 i;
6202
6203         /* Set the write pointer delay */
6204         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6205
6206         /* set the RB to use vmid 0 */
6207         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6208
6209         /* Init gfx ring 0 for pipe 0 */
6210         mutex_lock(&adev->srbm_mutex);
6211         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6212
6213         /* Set ring buffer size */
6214         ring = &adev->gfx.gfx_ring[0];
6215         rb_bufsz = order_base_2(ring->ring_size / 8);
6216         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6217         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6218 #ifdef __BIG_ENDIAN
6219         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6220 #endif
6221         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6222
6223         /* Initialize the ring buffer's write pointers */
6224         ring->wptr = 0;
6225         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6226         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6227
6228         /* set the wb address wether it's enabled or not */
6229         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6230         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6231         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6232                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6233
6234         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6235         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6236                      lower_32_bits(wptr_gpu_addr));
6237         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6238                      upper_32_bits(wptr_gpu_addr));
6239
6240         mdelay(1);
6241         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6242
6243         rb_addr = ring->gpu_addr >> 8;
6244         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6245         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6246
6247         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6248
6249         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6250         mutex_unlock(&adev->srbm_mutex);
6251
6252         /* Init gfx ring 1 for pipe 1 */
6253         if (adev->gfx.num_gfx_rings > 1) {
6254                 mutex_lock(&adev->srbm_mutex);
6255                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6256                 /* maximum supported gfx ring is 2 */
6257                 ring = &adev->gfx.gfx_ring[1];
6258                 rb_bufsz = order_base_2(ring->ring_size / 8);
6259                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6260                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6261                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6262                 /* Initialize the ring buffer's write pointers */
6263                 ring->wptr = 0;
6264                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6265                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6266                 /* Set the wb address wether it's enabled or not */
6267                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6268                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6269                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6270                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6271                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6272                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6273                              lower_32_bits(wptr_gpu_addr));
6274                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6275                              upper_32_bits(wptr_gpu_addr));
6276
6277                 mdelay(1);
6278                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6279
6280                 rb_addr = ring->gpu_addr >> 8;
6281                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6282                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6283                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6284
6285                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6286                 mutex_unlock(&adev->srbm_mutex);
6287         }
6288         /* Switch to pipe 0 */
6289         mutex_lock(&adev->srbm_mutex);
6290         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6291         mutex_unlock(&adev->srbm_mutex);
6292
6293         /* start the ring */
6294         gfx_v10_0_cp_gfx_start(adev);
6295
6296         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6297                 ring = &adev->gfx.gfx_ring[i];
6298                 ring->sched.ready = true;
6299         }
6300
6301         return 0;
6302 }
6303
6304 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6305 {
6306         if (enable) {
6307                 switch (adev->asic_type) {
6308                 case CHIP_SIENNA_CICHLID:
6309                 case CHIP_NAVY_FLOUNDER:
6310                 case CHIP_VANGOGH:
6311                 case CHIP_DIMGREY_CAVEFISH:
6312                 case CHIP_BEIGE_GOBY:
6313                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6314                         break;
6315                 default:
6316                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6317                         break;
6318                 }
6319         } else {
6320                 switch (adev->asic_type) {
6321                 case CHIP_SIENNA_CICHLID:
6322                 case CHIP_NAVY_FLOUNDER:
6323                 case CHIP_VANGOGH:
6324                 case CHIP_DIMGREY_CAVEFISH:
6325                 case CHIP_BEIGE_GOBY:
6326                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6327                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6328                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6329                         break;
6330                 default:
6331                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6332                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6333                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6334                         break;
6335                 }
6336                 adev->gfx.kiq.ring.sched.ready = false;
6337         }
6338         udelay(50);
6339 }
6340
6341 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6342 {
6343         const struct gfx_firmware_header_v1_0 *mec_hdr;
6344         const __le32 *fw_data;
6345         unsigned i;
6346         u32 tmp;
6347         u32 usec_timeout = 50000; /* Wait for 50 ms */
6348
6349         if (!adev->gfx.mec_fw)
6350                 return -EINVAL;
6351
6352         gfx_v10_0_cp_compute_enable(adev, false);
6353
6354         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6355         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6356
6357         fw_data = (const __le32 *)
6358                 (adev->gfx.mec_fw->data +
6359                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6360
6361         /* Trigger an invalidation of the L1 instruction caches */
6362         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6363         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6364         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6365
6366         /* Wait for invalidation complete */
6367         for (i = 0; i < usec_timeout; i++) {
6368                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6369                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6370                                        INVALIDATE_CACHE_COMPLETE))
6371                         break;
6372                 udelay(1);
6373         }
6374
6375         if (i >= usec_timeout) {
6376                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6377                 return -EINVAL;
6378         }
6379
6380         if (amdgpu_emu_mode == 1)
6381                 adev->hdp.funcs->flush_hdp(adev, NULL);
6382
6383         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6384         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6385         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6386         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6387         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6388
6389         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6390                      0xFFFFF000);
6391         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6392                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6393
6394         /* MEC1 */
6395         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6396
6397         for (i = 0; i < mec_hdr->jt_size; i++)
6398                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6399                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6400
6401         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6402
6403         /*
6404          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6405          * different microcode than MEC1.
6406          */
6407
6408         return 0;
6409 }
6410
6411 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6412 {
6413         uint32_t tmp;
6414         struct amdgpu_device *adev = ring->adev;
6415
6416         /* tell RLC which is KIQ queue */
6417         switch (adev->asic_type) {
6418         case CHIP_SIENNA_CICHLID:
6419         case CHIP_NAVY_FLOUNDER:
6420         case CHIP_VANGOGH:
6421         case CHIP_DIMGREY_CAVEFISH:
6422         case CHIP_BEIGE_GOBY:
6423                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6424                 tmp &= 0xffffff00;
6425                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6426                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6427                 tmp |= 0x80;
6428                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6429                 break;
6430         default:
6431                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6432                 tmp &= 0xffffff00;
6433                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6434                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6435                 tmp |= 0x80;
6436                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6437                 break;
6438         }
6439 }
6440
6441 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6442 {
6443         struct amdgpu_device *adev = ring->adev;
6444         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6445         uint64_t hqd_gpu_addr, wb_gpu_addr;
6446         uint32_t tmp;
6447         uint32_t rb_bufsz;
6448
6449         /* set up gfx hqd wptr */
6450         mqd->cp_gfx_hqd_wptr = 0;
6451         mqd->cp_gfx_hqd_wptr_hi = 0;
6452
6453         /* set the pointer to the MQD */
6454         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6455         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6456
6457         /* set up mqd control */
6458         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6459         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6460         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6461         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6462         mqd->cp_gfx_mqd_control = tmp;
6463
6464         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6465         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6466         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6467         mqd->cp_gfx_hqd_vmid = 0;
6468
6469         /* set up default queue priority level
6470          * 0x0 = low priority, 0x1 = high priority */
6471         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6472         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6473         mqd->cp_gfx_hqd_queue_priority = tmp;
6474
6475         /* set up time quantum */
6476         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6477         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6478         mqd->cp_gfx_hqd_quantum = tmp;
6479
6480         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6481         hqd_gpu_addr = ring->gpu_addr >> 8;
6482         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6483         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6484
6485         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6486         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6487         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6488         mqd->cp_gfx_hqd_rptr_addr_hi =
6489                 upper_32_bits(wb_gpu_addr) & 0xffff;
6490
6491         /* set up rb_wptr_poll addr */
6492         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6493         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6494         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6495
6496         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6497         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6498         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6499         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6500         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6501 #ifdef __BIG_ENDIAN
6502         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6503 #endif
6504         mqd->cp_gfx_hqd_cntl = tmp;
6505
6506         /* set up cp_doorbell_control */
6507         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6508         if (ring->use_doorbell) {
6509                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6510                                     DOORBELL_OFFSET, ring->doorbell_index);
6511                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6512                                     DOORBELL_EN, 1);
6513         } else
6514                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6515                                     DOORBELL_EN, 0);
6516         mqd->cp_rb_doorbell_control = tmp;
6517
6518         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6519          *otherwise the range of the second ring will override the first ring */
6520         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6521                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6522
6523         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6524         ring->wptr = 0;
6525         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6526
6527         /* active the queue */
6528         mqd->cp_gfx_hqd_active = 1;
6529
6530         return 0;
6531 }
6532
6533 #ifdef BRING_UP_DEBUG
6534 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6535 {
6536         struct amdgpu_device *adev = ring->adev;
6537         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6538
6539         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6540         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6541         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6542
6543         /* set GFX_MQD_BASE */
6544         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6545         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6546
6547         /* set GFX_MQD_CONTROL */
6548         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6549
6550         /* set GFX_HQD_VMID to 0 */
6551         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6552
6553         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6554                         mqd->cp_gfx_hqd_queue_priority);
6555         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6556
6557         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6558         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6559         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6560
6561         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6562         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6563         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6564
6565         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6566         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6567
6568         /* set RB_WPTR_POLL_ADDR */
6569         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6570         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6571
6572         /* set RB_DOORBELL_CONTROL */
6573         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6574
6575         /* active the queue */
6576         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6577
6578         return 0;
6579 }
6580 #endif
6581
6582 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6583 {
6584         struct amdgpu_device *adev = ring->adev;
6585         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6586         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6587
6588         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6589                 memset((void *)mqd, 0, sizeof(*mqd));
6590                 mutex_lock(&adev->srbm_mutex);
6591                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6592                 gfx_v10_0_gfx_mqd_init(ring);
6593 #ifdef BRING_UP_DEBUG
6594                 gfx_v10_0_gfx_queue_init_register(ring);
6595 #endif
6596                 nv_grbm_select(adev, 0, 0, 0, 0);
6597                 mutex_unlock(&adev->srbm_mutex);
6598                 if (adev->gfx.me.mqd_backup[mqd_idx])
6599                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6600         } else if (amdgpu_in_reset(adev)) {
6601                 /* reset mqd with the backup copy */
6602                 if (adev->gfx.me.mqd_backup[mqd_idx])
6603                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6604                 /* reset the ring */
6605                 ring->wptr = 0;
6606                 adev->wb.wb[ring->wptr_offs] = 0;
6607                 amdgpu_ring_clear_ring(ring);
6608 #ifdef BRING_UP_DEBUG
6609                 mutex_lock(&adev->srbm_mutex);
6610                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6611                 gfx_v10_0_gfx_queue_init_register(ring);
6612                 nv_grbm_select(adev, 0, 0, 0, 0);
6613                 mutex_unlock(&adev->srbm_mutex);
6614 #endif
6615         } else {
6616                 amdgpu_ring_clear_ring(ring);
6617         }
6618
6619         return 0;
6620 }
6621
6622 #ifndef BRING_UP_DEBUG
6623 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6624 {
6625         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6626         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6627         int r, i;
6628
6629         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6630                 return -EINVAL;
6631
6632         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6633                                         adev->gfx.num_gfx_rings);
6634         if (r) {
6635                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6636                 return r;
6637         }
6638
6639         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6640                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6641
6642         return amdgpu_ring_test_helper(kiq_ring);
6643 }
6644 #endif
6645
6646 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6647 {
6648         int r, i;
6649         struct amdgpu_ring *ring;
6650
6651         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6652                 ring = &adev->gfx.gfx_ring[i];
6653
6654                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6655                 if (unlikely(r != 0))
6656                         goto done;
6657
6658                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6659                 if (!r) {
6660                         r = gfx_v10_0_gfx_init_queue(ring);
6661                         amdgpu_bo_kunmap(ring->mqd_obj);
6662                         ring->mqd_ptr = NULL;
6663                 }
6664                 amdgpu_bo_unreserve(ring->mqd_obj);
6665                 if (r)
6666                         goto done;
6667         }
6668 #ifndef BRING_UP_DEBUG
6669         r = gfx_v10_0_kiq_enable_kgq(adev);
6670         if (r)
6671                 goto done;
6672 #endif
6673         r = gfx_v10_0_cp_gfx_start(adev);
6674         if (r)
6675                 goto done;
6676
6677         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6678                 ring = &adev->gfx.gfx_ring[i];
6679                 ring->sched.ready = true;
6680         }
6681 done:
6682         return r;
6683 }
6684
6685 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6686 {
6687         struct amdgpu_device *adev = ring->adev;
6688
6689         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6690                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6691                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6692                         mqd->cp_hqd_queue_priority =
6693                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6694                 }
6695         }
6696 }
6697
6698 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6699 {
6700         struct amdgpu_device *adev = ring->adev;
6701         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6702         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6703         uint32_t tmp;
6704
6705         mqd->header = 0xC0310800;
6706         mqd->compute_pipelinestat_enable = 0x00000001;
6707         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6708         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6709         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6710         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6711         mqd->compute_misc_reserved = 0x00000003;
6712
6713         eop_base_addr = ring->eop_gpu_addr >> 8;
6714         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6715         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6716
6717         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6718         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6719         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6720                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6721
6722         mqd->cp_hqd_eop_control = tmp;
6723
6724         /* enable doorbell? */
6725         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6726
6727         if (ring->use_doorbell) {
6728                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6729                                     DOORBELL_OFFSET, ring->doorbell_index);
6730                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6731                                     DOORBELL_EN, 1);
6732                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6733                                     DOORBELL_SOURCE, 0);
6734                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6735                                     DOORBELL_HIT, 0);
6736         } else {
6737                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6738                                     DOORBELL_EN, 0);
6739         }
6740
6741         mqd->cp_hqd_pq_doorbell_control = tmp;
6742
6743         /* disable the queue if it's active */
6744         ring->wptr = 0;
6745         mqd->cp_hqd_dequeue_request = 0;
6746         mqd->cp_hqd_pq_rptr = 0;
6747         mqd->cp_hqd_pq_wptr_lo = 0;
6748         mqd->cp_hqd_pq_wptr_hi = 0;
6749
6750         /* set the pointer to the MQD */
6751         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6752         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6753
6754         /* set MQD vmid to 0 */
6755         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6756         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6757         mqd->cp_mqd_control = tmp;
6758
6759         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6760         hqd_gpu_addr = ring->gpu_addr >> 8;
6761         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6762         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6763
6764         /* set up the HQD, this is similar to CP_RB0_CNTL */
6765         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6766         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6767                             (order_base_2(ring->ring_size / 4) - 1));
6768         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6769                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6770 #ifdef __BIG_ENDIAN
6771         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6772 #endif
6773         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6774         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6775         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6776         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6777         mqd->cp_hqd_pq_control = tmp;
6778
6779         /* set the wb address whether it's enabled or not */
6780         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6781         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6782         mqd->cp_hqd_pq_rptr_report_addr_hi =
6783                 upper_32_bits(wb_gpu_addr) & 0xffff;
6784
6785         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6786         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6787         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6788         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6789
6790         tmp = 0;
6791         /* enable the doorbell if requested */
6792         if (ring->use_doorbell) {
6793                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6794                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6795                                 DOORBELL_OFFSET, ring->doorbell_index);
6796
6797                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6798                                     DOORBELL_EN, 1);
6799                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6800                                     DOORBELL_SOURCE, 0);
6801                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6802                                     DOORBELL_HIT, 0);
6803         }
6804
6805         mqd->cp_hqd_pq_doorbell_control = tmp;
6806
6807         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6808         ring->wptr = 0;
6809         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6810
6811         /* set the vmid for the queue */
6812         mqd->cp_hqd_vmid = 0;
6813
6814         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6815         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6816         mqd->cp_hqd_persistent_state = tmp;
6817
6818         /* set MIN_IB_AVAIL_SIZE */
6819         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6820         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6821         mqd->cp_hqd_ib_control = tmp;
6822
6823         /* set static priority for a compute queue/ring */
6824         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6825
6826         /* map_queues packet doesn't need activate the queue,
6827          * so only kiq need set this field.
6828          */
6829         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6830                 mqd->cp_hqd_active = 1;
6831
6832         return 0;
6833 }
6834
6835 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6836 {
6837         struct amdgpu_device *adev = ring->adev;
6838         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6839         int j;
6840
6841         /* inactivate the queue */
6842         if (amdgpu_sriov_vf(adev))
6843                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6844
6845         /* disable wptr polling */
6846         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6847
6848         /* write the EOP addr */
6849         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6850                mqd->cp_hqd_eop_base_addr_lo);
6851         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6852                mqd->cp_hqd_eop_base_addr_hi);
6853
6854         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6855         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6856                mqd->cp_hqd_eop_control);
6857
6858         /* enable doorbell? */
6859         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6860                mqd->cp_hqd_pq_doorbell_control);
6861
6862         /* disable the queue if it's active */
6863         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6864                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6865                 for (j = 0; j < adev->usec_timeout; j++) {
6866                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6867                                 break;
6868                         udelay(1);
6869                 }
6870                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6871                        mqd->cp_hqd_dequeue_request);
6872                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6873                        mqd->cp_hqd_pq_rptr);
6874                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6875                        mqd->cp_hqd_pq_wptr_lo);
6876                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6877                        mqd->cp_hqd_pq_wptr_hi);
6878         }
6879
6880         /* set the pointer to the MQD */
6881         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6882                mqd->cp_mqd_base_addr_lo);
6883         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6884                mqd->cp_mqd_base_addr_hi);
6885
6886         /* set MQD vmid to 0 */
6887         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6888                mqd->cp_mqd_control);
6889
6890         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6891         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6892                mqd->cp_hqd_pq_base_lo);
6893         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6894                mqd->cp_hqd_pq_base_hi);
6895
6896         /* set up the HQD, this is similar to CP_RB0_CNTL */
6897         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6898                mqd->cp_hqd_pq_control);
6899
6900         /* set the wb address whether it's enabled or not */
6901         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6902                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6903         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6904                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6905
6906         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6907         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6908                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6909         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6910                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6911
6912         /* enable the doorbell if requested */
6913         if (ring->use_doorbell) {
6914                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6915                         (adev->doorbell_index.kiq * 2) << 2);
6916                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6917                         (adev->doorbell_index.userqueue_end * 2) << 2);
6918         }
6919
6920         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6921                mqd->cp_hqd_pq_doorbell_control);
6922
6923         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6924         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6925                mqd->cp_hqd_pq_wptr_lo);
6926         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6927                mqd->cp_hqd_pq_wptr_hi);
6928
6929         /* set the vmid for the queue */
6930         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6931
6932         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6933                mqd->cp_hqd_persistent_state);
6934
6935         /* activate the queue */
6936         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6937                mqd->cp_hqd_active);
6938
6939         if (ring->use_doorbell)
6940                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6941
6942         return 0;
6943 }
6944
6945 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6946 {
6947         struct amdgpu_device *adev = ring->adev;
6948         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6949         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6950
6951         gfx_v10_0_kiq_setting(ring);
6952
6953         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6954                 /* reset MQD to a clean status */
6955                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6956                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6957
6958                 /* reset ring buffer */
6959                 ring->wptr = 0;
6960                 amdgpu_ring_clear_ring(ring);
6961
6962                 mutex_lock(&adev->srbm_mutex);
6963                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6964                 gfx_v10_0_kiq_init_register(ring);
6965                 nv_grbm_select(adev, 0, 0, 0, 0);
6966                 mutex_unlock(&adev->srbm_mutex);
6967         } else {
6968                 memset((void *)mqd, 0, sizeof(*mqd));
6969                 mutex_lock(&adev->srbm_mutex);
6970                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6971                 gfx_v10_0_compute_mqd_init(ring);
6972                 gfx_v10_0_kiq_init_register(ring);
6973                 nv_grbm_select(adev, 0, 0, 0, 0);
6974                 mutex_unlock(&adev->srbm_mutex);
6975
6976                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6977                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6978         }
6979
6980         return 0;
6981 }
6982
6983 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6984 {
6985         struct amdgpu_device *adev = ring->adev;
6986         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6987         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6988
6989         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6990                 memset((void *)mqd, 0, sizeof(*mqd));
6991                 mutex_lock(&adev->srbm_mutex);
6992                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6993                 gfx_v10_0_compute_mqd_init(ring);
6994                 nv_grbm_select(adev, 0, 0, 0, 0);
6995                 mutex_unlock(&adev->srbm_mutex);
6996
6997                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6998                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6999         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7000                 /* reset MQD to a clean status */
7001                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7002                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7003
7004                 /* reset ring buffer */
7005                 ring->wptr = 0;
7006                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
7007                 amdgpu_ring_clear_ring(ring);
7008         } else {
7009                 amdgpu_ring_clear_ring(ring);
7010         }
7011
7012         return 0;
7013 }
7014
7015 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7016 {
7017         struct amdgpu_ring *ring;
7018         int r;
7019
7020         ring = &adev->gfx.kiq.ring;
7021
7022         r = amdgpu_bo_reserve(ring->mqd_obj, false);
7023         if (unlikely(r != 0))
7024                 return r;
7025
7026         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7027         if (unlikely(r != 0))
7028                 return r;
7029
7030         gfx_v10_0_kiq_init_queue(ring);
7031         amdgpu_bo_kunmap(ring->mqd_obj);
7032         ring->mqd_ptr = NULL;
7033         amdgpu_bo_unreserve(ring->mqd_obj);
7034         ring->sched.ready = true;
7035         return 0;
7036 }
7037
7038 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7039 {
7040         struct amdgpu_ring *ring = NULL;
7041         int r = 0, i;
7042
7043         gfx_v10_0_cp_compute_enable(adev, true);
7044
7045         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7046                 ring = &adev->gfx.compute_ring[i];
7047
7048                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7049                 if (unlikely(r != 0))
7050                         goto done;
7051                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7052                 if (!r) {
7053                         r = gfx_v10_0_kcq_init_queue(ring);
7054                         amdgpu_bo_kunmap(ring->mqd_obj);
7055                         ring->mqd_ptr = NULL;
7056                 }
7057                 amdgpu_bo_unreserve(ring->mqd_obj);
7058                 if (r)
7059                         goto done;
7060         }
7061
7062         r = amdgpu_gfx_enable_kcq(adev);
7063 done:
7064         return r;
7065 }
7066
7067 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7068 {
7069         int r, i;
7070         struct amdgpu_ring *ring;
7071
7072         if (!(adev->flags & AMD_IS_APU))
7073                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7074
7075         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7076                 /* legacy firmware loading */
7077                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7078                 if (r)
7079                         return r;
7080
7081                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7082                 if (r)
7083                         return r;
7084         }
7085
7086         r = gfx_v10_0_kiq_resume(adev);
7087         if (r)
7088                 return r;
7089
7090         r = gfx_v10_0_kcq_resume(adev);
7091         if (r)
7092                 return r;
7093
7094         if (!amdgpu_async_gfx_ring) {
7095                 r = gfx_v10_0_cp_gfx_resume(adev);
7096                 if (r)
7097                         return r;
7098         } else {
7099                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7100                 if (r)
7101                         return r;
7102         }
7103
7104         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7105                 ring = &adev->gfx.gfx_ring[i];
7106                 r = amdgpu_ring_test_helper(ring);
7107                 if (r)
7108                         return r;
7109         }
7110
7111         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7112                 ring = &adev->gfx.compute_ring[i];
7113                 r = amdgpu_ring_test_helper(ring);
7114                 if (r)
7115                         return r;
7116         }
7117
7118         return 0;
7119 }
7120
7121 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7122 {
7123         gfx_v10_0_cp_gfx_enable(adev, enable);
7124         gfx_v10_0_cp_compute_enable(adev, enable);
7125 }
7126
7127 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7128 {
7129         uint32_t data, pattern = 0xDEADBEEF;
7130
7131         /* check if mmVGT_ESGS_RING_SIZE_UMD
7132          * has been remapped to mmVGT_ESGS_RING_SIZE */
7133         switch (adev->asic_type) {
7134         case CHIP_SIENNA_CICHLID:
7135         case CHIP_NAVY_FLOUNDER:
7136         case CHIP_DIMGREY_CAVEFISH:
7137         case CHIP_BEIGE_GOBY:
7138                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7139                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7140                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7141
7142                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7143                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7144                         return true;
7145                 } else {
7146                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7147                         return false;
7148                 }
7149                 break;
7150         case CHIP_VANGOGH:
7151                 return true;
7152         default:
7153                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7154                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7155                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7156
7157                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7158                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7159                         return true;
7160                 } else {
7161                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7162                         return false;
7163                 }
7164                 break;
7165         }
7166 }
7167
7168 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7169 {
7170         uint32_t data;
7171
7172         if (amdgpu_sriov_vf(adev))
7173                 return;
7174
7175         /* initialize cam_index to 0
7176          * index will auto-inc after each data writting */
7177         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7178
7179         switch (adev->asic_type) {
7180         case CHIP_SIENNA_CICHLID:
7181         case CHIP_NAVY_FLOUNDER:
7182         case CHIP_VANGOGH:
7183         case CHIP_DIMGREY_CAVEFISH:
7184         case CHIP_BEIGE_GOBY:
7185                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7186                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7187                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7188                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7189                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7190                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7191                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7192
7193                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7194                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7195                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7196                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7197                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7198                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7199                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7200
7201                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7202                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7203                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7204                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7205                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7206                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7207                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7208
7209                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7210                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7211                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7212                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7213                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7214                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7215                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7216
7217                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7218                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7219                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7220                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7221                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7222                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7223                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7224
7225                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7226                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7227                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7228                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7229                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7230                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7231                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7232
7233                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7234                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7235                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7236                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7237                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7238                 break;
7239         default:
7240                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7241                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7242                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7243                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7244                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7245                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7246                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7247
7248                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7249                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7250                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7251                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7252                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7253                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7254                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7255
7256                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7257                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7258                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7259                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7260                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7261                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7262                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7263
7264                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7265                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7266                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7267                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7268                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7269                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7270                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7271
7272                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7273                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7274                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7275                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7276                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7277                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7278                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7279
7280                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7281                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7282                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7283                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7284                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7285                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7286                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7287
7288                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7289                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7290                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7291                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7292                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7293                 break;
7294         }
7295
7296         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7297         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7298 }
7299
7300 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7301 {
7302         uint32_t data;
7303         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7304         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7305         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7306
7307         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7308         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7309         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7310 }
7311
7312 static int gfx_v10_0_hw_init(void *handle)
7313 {
7314         int r;
7315         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7316
7317         if (!amdgpu_emu_mode)
7318                 gfx_v10_0_init_golden_registers(adev);
7319
7320         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7321                 /**
7322                  * For gfx 10, rlc firmware loading relies on smu firmware is
7323                  * loaded firstly, so in direct type, it has to load smc ucode
7324                  * here before rlc.
7325                  */
7326                 if (!(adev->flags & AMD_IS_APU)) {
7327                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7328                         if (r)
7329                                 return r;
7330                 }
7331                 gfx_v10_0_disable_gpa_mode(adev);
7332         }
7333
7334         /* if GRBM CAM not remapped, set up the remapping */
7335         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7336                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7337
7338         gfx_v10_0_constants_init(adev);
7339
7340         r = gfx_v10_0_rlc_resume(adev);
7341         if (r)
7342                 return r;
7343
7344         /*
7345          * init golden registers and rlc resume may override some registers,
7346          * reconfig them here
7347          */
7348         gfx_v10_0_tcp_harvest(adev);
7349
7350         r = gfx_v10_0_cp_resume(adev);
7351         if (r)
7352                 return r;
7353
7354         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7355                 gfx_v10_3_program_pbb_mode(adev);
7356
7357         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7358                 gfx_v10_3_set_power_brake_sequence(adev);
7359
7360         return r;
7361 }
7362
7363 #ifndef BRING_UP_DEBUG
7364 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7365 {
7366         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7367         struct amdgpu_ring *kiq_ring = &kiq->ring;
7368         int i;
7369
7370         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7371                 return -EINVAL;
7372
7373         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7374                                         adev->gfx.num_gfx_rings))
7375                 return -ENOMEM;
7376
7377         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7378                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7379                                            PREEMPT_QUEUES, 0, 0);
7380
7381         return amdgpu_ring_test_helper(kiq_ring);
7382 }
7383 #endif
7384
7385 static int gfx_v10_0_hw_fini(void *handle)
7386 {
7387         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7388         int r;
7389         uint32_t tmp;
7390
7391         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7392         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7393
7394         if (!adev->no_hw_access) {
7395 #ifndef BRING_UP_DEBUG
7396                 if (amdgpu_async_gfx_ring) {
7397                         r = gfx_v10_0_kiq_disable_kgq(adev);
7398                         if (r)
7399                                 DRM_ERROR("KGQ disable failed\n");
7400                 }
7401 #endif
7402                 if (amdgpu_gfx_disable_kcq(adev))
7403                         DRM_ERROR("KCQ disable failed\n");
7404         }
7405
7406         if (amdgpu_sriov_vf(adev)) {
7407                 gfx_v10_0_cp_gfx_enable(adev, false);
7408                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7409                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7410                 tmp &= 0xffffff00;
7411                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7412
7413                 return 0;
7414         }
7415         gfx_v10_0_cp_enable(adev, false);
7416         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7417
7418         return 0;
7419 }
7420
7421 static int gfx_v10_0_suspend(void *handle)
7422 {
7423         return gfx_v10_0_hw_fini(handle);
7424 }
7425
7426 static int gfx_v10_0_resume(void *handle)
7427 {
7428         return gfx_v10_0_hw_init(handle);
7429 }
7430
7431 static bool gfx_v10_0_is_idle(void *handle)
7432 {
7433         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7434
7435         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7436                                 GRBM_STATUS, GUI_ACTIVE))
7437                 return false;
7438         else
7439                 return true;
7440 }
7441
7442 static int gfx_v10_0_wait_for_idle(void *handle)
7443 {
7444         unsigned i;
7445         u32 tmp;
7446         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7447
7448         for (i = 0; i < adev->usec_timeout; i++) {
7449                 /* read MC_STATUS */
7450                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7451                         GRBM_STATUS__GUI_ACTIVE_MASK;
7452
7453                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7454                         return 0;
7455                 udelay(1);
7456         }
7457         return -ETIMEDOUT;
7458 }
7459
7460 static int gfx_v10_0_soft_reset(void *handle)
7461 {
7462         u32 grbm_soft_reset = 0;
7463         u32 tmp;
7464         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7465
7466         /* GRBM_STATUS */
7467         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7468         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7469                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7470                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7471                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7472                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7473                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7474                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7475                                                 1);
7476                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7477                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7478                                                 1);
7479         }
7480
7481         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7482                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7483                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7484                                                 1);
7485         }
7486
7487         /* GRBM_STATUS2 */
7488         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7489         switch (adev->asic_type) {
7490         case CHIP_SIENNA_CICHLID:
7491         case CHIP_NAVY_FLOUNDER:
7492         case CHIP_VANGOGH:
7493         case CHIP_DIMGREY_CAVEFISH:
7494         case CHIP_BEIGE_GOBY:
7495                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7496                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7497                                                         GRBM_SOFT_RESET,
7498                                                         SOFT_RESET_RLC,
7499                                                         1);
7500                 break;
7501         default:
7502                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7503                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7504                                                         GRBM_SOFT_RESET,
7505                                                         SOFT_RESET_RLC,
7506                                                         1);
7507                 break;
7508         }
7509
7510         if (grbm_soft_reset) {
7511                 /* stop the rlc */
7512                 gfx_v10_0_rlc_stop(adev);
7513
7514                 /* Disable GFX parsing/prefetching */
7515                 gfx_v10_0_cp_gfx_enable(adev, false);
7516
7517                 /* Disable MEC parsing/prefetching */
7518                 gfx_v10_0_cp_compute_enable(adev, false);
7519
7520                 if (grbm_soft_reset) {
7521                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7522                         tmp |= grbm_soft_reset;
7523                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7524                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7525                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7526
7527                         udelay(50);
7528
7529                         tmp &= ~grbm_soft_reset;
7530                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7531                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7532                 }
7533
7534                 /* Wait a little for things to settle down */
7535                 udelay(50);
7536         }
7537         return 0;
7538 }
7539
7540 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7541 {
7542         uint64_t clock;
7543
7544         amdgpu_gfx_off_ctrl(adev, false);
7545         mutex_lock(&adev->gfx.gpu_clock_mutex);
7546         switch (adev->asic_type) {
7547         case CHIP_VANGOGH:
7548                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7549                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7550                 break;
7551         default:
7552                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7553                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7554                 break;
7555         }
7556         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7557         amdgpu_gfx_off_ctrl(adev, true);
7558         return clock;
7559 }
7560
7561 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7562                                            uint32_t vmid,
7563                                            uint32_t gds_base, uint32_t gds_size,
7564                                            uint32_t gws_base, uint32_t gws_size,
7565                                            uint32_t oa_base, uint32_t oa_size)
7566 {
7567         struct amdgpu_device *adev = ring->adev;
7568
7569         /* GDS Base */
7570         gfx_v10_0_write_data_to_reg(ring, 0, false,
7571                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7572                                     gds_base);
7573
7574         /* GDS Size */
7575         gfx_v10_0_write_data_to_reg(ring, 0, false,
7576                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7577                                     gds_size);
7578
7579         /* GWS */
7580         gfx_v10_0_write_data_to_reg(ring, 0, false,
7581                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7582                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7583
7584         /* OA */
7585         gfx_v10_0_write_data_to_reg(ring, 0, false,
7586                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7587                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7588 }
7589
7590 static int gfx_v10_0_early_init(void *handle)
7591 {
7592         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7593
7594         switch (adev->asic_type) {
7595         case CHIP_NAVI10:
7596         case CHIP_NAVI14:
7597         case CHIP_NAVI12:
7598                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7599                 break;
7600         case CHIP_SIENNA_CICHLID:
7601         case CHIP_NAVY_FLOUNDER:
7602         case CHIP_VANGOGH:
7603         case CHIP_DIMGREY_CAVEFISH:
7604         case CHIP_BEIGE_GOBY:
7605                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7606                 break;
7607         default:
7608                 break;
7609         }
7610
7611         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7612                                           AMDGPU_MAX_COMPUTE_RINGS);
7613
7614         gfx_v10_0_set_kiq_pm4_funcs(adev);
7615         gfx_v10_0_set_ring_funcs(adev);
7616         gfx_v10_0_set_irq_funcs(adev);
7617         gfx_v10_0_set_gds_init(adev);
7618         gfx_v10_0_set_rlc_funcs(adev);
7619
7620         return 0;
7621 }
7622
7623 static int gfx_v10_0_late_init(void *handle)
7624 {
7625         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7626         int r;
7627
7628         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7629         if (r)
7630                 return r;
7631
7632         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7633         if (r)
7634                 return r;
7635
7636         return 0;
7637 }
7638
7639 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7640 {
7641         uint32_t rlc_cntl;
7642
7643         /* if RLC is not enabled, do nothing */
7644         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7645         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7646 }
7647
7648 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7649 {
7650         uint32_t data;
7651         unsigned i;
7652
7653         data = RLC_SAFE_MODE__CMD_MASK;
7654         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7655
7656         switch (adev->asic_type) {
7657         case CHIP_SIENNA_CICHLID:
7658         case CHIP_NAVY_FLOUNDER:
7659         case CHIP_VANGOGH:
7660         case CHIP_DIMGREY_CAVEFISH:
7661         case CHIP_BEIGE_GOBY:
7662                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7663
7664                 /* wait for RLC_SAFE_MODE */
7665                 for (i = 0; i < adev->usec_timeout; i++) {
7666                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7667                                            RLC_SAFE_MODE, CMD))
7668                                 break;
7669                         udelay(1);
7670                 }
7671                 break;
7672         default:
7673                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7674
7675                 /* wait for RLC_SAFE_MODE */
7676                 for (i = 0; i < adev->usec_timeout; i++) {
7677                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7678                                            RLC_SAFE_MODE, CMD))
7679                                 break;
7680                         udelay(1);
7681                 }
7682                 break;
7683         }
7684 }
7685
7686 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7687 {
7688         uint32_t data;
7689
7690         data = RLC_SAFE_MODE__CMD_MASK;
7691         switch (adev->asic_type) {
7692         case CHIP_SIENNA_CICHLID:
7693         case CHIP_NAVY_FLOUNDER:
7694         case CHIP_VANGOGH:
7695         case CHIP_DIMGREY_CAVEFISH:
7696         case CHIP_BEIGE_GOBY:
7697                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7698                 break;
7699         default:
7700                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7701                 break;
7702         }
7703 }
7704
7705 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7706                                                       bool enable)
7707 {
7708         uint32_t data, def;
7709
7710         /* It is disabled by HW by default */
7711         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7712                 /* 0 - Disable some blocks' MGCG */
7713                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7714                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7715                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7716                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7717
7718                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7719                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7720                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7721                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7722                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7723                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7724                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7725
7726                 if (def != data)
7727                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7728
7729                 /* MGLS is a global flag to control all MGLS in GFX */
7730                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7731                         /* 2 - RLC memory Light sleep */
7732                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7733                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7734                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7735                                 if (def != data)
7736                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7737                         }
7738                         /* 3 - CP memory Light sleep */
7739                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7740                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7741                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7742                                 if (def != data)
7743                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7744                         }
7745                 }
7746         } else {
7747                 /* 1 - MGCG_OVERRIDE */
7748                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7749                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7750                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7751                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7752                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7753                 if (def != data)
7754                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7755
7756                 /* 2 - disable MGLS in CP */
7757                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7758                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7759                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7760                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7761                 }
7762
7763                 /* 3 - disable MGLS in RLC */
7764                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7765                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7766                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7767                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7768                 }
7769
7770         }
7771 }
7772
7773 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7774                                            bool enable)
7775 {
7776         uint32_t data, def;
7777
7778         /* Enable 3D CGCG/CGLS */
7779         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7780                 /* write cmd to clear cgcg/cgls ov */
7781                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7782                 /* unset CGCG override */
7783                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7784                 /* update CGCG and CGLS override bits */
7785                 if (def != data)
7786                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7787                 /* enable 3Dcgcg FSM(0x0000363f) */
7788                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7789                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7790                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7791                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7792                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7793                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7794                 if (def != data)
7795                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7796
7797                 /* set IDLE_POLL_COUNT(0x00900100) */
7798                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7799                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7800                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7801                 if (def != data)
7802                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7803         } else {
7804                 /* Disable CGCG/CGLS */
7805                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7806                 /* disable cgcg, cgls should be disabled */
7807                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7808                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7809                 /* disable cgcg and cgls in FSM */
7810                 if (def != data)
7811                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7812         }
7813 }
7814
7815 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7816                                                       bool enable)
7817 {
7818         uint32_t def, data;
7819
7820         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7821                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7822                 /* unset CGCG override */
7823                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7824                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7825                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7826                 else
7827                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7828                 /* update CGCG and CGLS override bits */
7829                 if (def != data)
7830                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7831
7832                 /* enable cgcg FSM(0x0000363F) */
7833                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7834                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7835                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7836                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7837                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7838                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7839                 if (def != data)
7840                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7841
7842                 /* set IDLE_POLL_COUNT(0x00900100) */
7843                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7844                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7845                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7846                 if (def != data)
7847                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7848         } else {
7849                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7850                 /* reset CGCG/CGLS bits */
7851                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7852                 /* disable cgcg and cgls in FSM */
7853                 if (def != data)
7854                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7855         }
7856 }
7857
7858 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7859                                                       bool enable)
7860 {
7861         uint32_t def, data;
7862
7863         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7864                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7865                 /* unset FGCG override */
7866                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7867                 /* update FGCG override bits */
7868                 if (def != data)
7869                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7870
7871                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7872                 /* unset RLC SRAM CLK GATER override */
7873                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7874                 /* update RLC SRAM CLK GATER override bits */
7875                 if (def != data)
7876                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7877         } else {
7878                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7879                 /* reset FGCG bits */
7880                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7881                 /* disable FGCG*/
7882                 if (def != data)
7883                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7884
7885                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7886                 /* reset RLC SRAM CLK GATER bits */
7887                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7888                 /* disable RLC SRAM CLK*/
7889                 if (def != data)
7890                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7891         }
7892 }
7893
7894 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7895                                             bool enable)
7896 {
7897         amdgpu_gfx_rlc_enter_safe_mode(adev);
7898
7899         if (enable) {
7900                 /* enable FGCG firstly*/
7901                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7902                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7903                  * ===  MGCG + MGLS ===
7904                  */
7905                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7906                 /* ===  CGCG /CGLS for GFX 3D Only === */
7907                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7908                 /* ===  CGCG + CGLS === */
7909                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7910         } else {
7911                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7912                  * ===  CGCG + CGLS ===
7913                  */
7914                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7915                 /* ===  CGCG /CGLS for GFX 3D Only === */
7916                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7917                 /* ===  MGCG + MGLS === */
7918                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7919                 /* disable fgcg at last*/
7920                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7921         }
7922
7923         if (adev->cg_flags &
7924             (AMD_CG_SUPPORT_GFX_MGCG |
7925              AMD_CG_SUPPORT_GFX_CGLS |
7926              AMD_CG_SUPPORT_GFX_CGCG |
7927              AMD_CG_SUPPORT_GFX_3D_CGCG |
7928              AMD_CG_SUPPORT_GFX_3D_CGLS))
7929                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7930
7931         amdgpu_gfx_rlc_exit_safe_mode(adev);
7932
7933         return 0;
7934 }
7935
7936 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7937 {
7938         u32 reg, data;
7939         /* not for *_SOC15 */
7940         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7941         if (amdgpu_sriov_is_pp_one_vf(adev))
7942                 data = RREG32_NO_KIQ(reg);
7943         else
7944                 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
7945
7946         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7947         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7948
7949         if (amdgpu_sriov_is_pp_one_vf(adev))
7950                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7951         else
7952                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7953 }
7954
7955 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7956                                         uint32_t offset,
7957                                         struct soc15_reg_rlcg *entries, int arr_size)
7958 {
7959         int i;
7960         uint32_t reg;
7961
7962         if (!entries)
7963                 return false;
7964
7965         for (i = 0; i < arr_size; i++) {
7966                 const struct soc15_reg_rlcg *entry;
7967
7968                 entry = &entries[i];
7969                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7970                 if (offset == reg)
7971                         return true;
7972         }
7973
7974         return false;
7975 }
7976
7977 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7978 {
7979         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7980 }
7981
7982 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7983 {
7984         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7985
7986         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7987                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7988         else
7989                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7990
7991         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7992
7993         /*
7994          * CGPG enablement required and the register to program the hysteresis value
7995          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
7996          * in refclk count. Note that RLC FW is modified to take 16 bits from
7997          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
7998          *
7999          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
8000          * as part of CGPG enablement starting point.
8001          */
8002         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
8003                 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8004                 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8005         }
8006 }
8007
8008 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8009 {
8010         amdgpu_gfx_rlc_enter_safe_mode(adev);
8011
8012         gfx_v10_cntl_power_gating(adev, enable);
8013
8014         amdgpu_gfx_rlc_exit_safe_mode(adev);
8015 }
8016
8017 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8018         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8019         .set_safe_mode = gfx_v10_0_set_safe_mode,
8020         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8021         .init = gfx_v10_0_rlc_init,
8022         .get_csb_size = gfx_v10_0_get_csb_size,
8023         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8024         .resume = gfx_v10_0_rlc_resume,
8025         .stop = gfx_v10_0_rlc_stop,
8026         .reset = gfx_v10_0_rlc_reset,
8027         .start = gfx_v10_0_rlc_start,
8028         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8029 };
8030
8031 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8032         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8033         .set_safe_mode = gfx_v10_0_set_safe_mode,
8034         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8035         .init = gfx_v10_0_rlc_init,
8036         .get_csb_size = gfx_v10_0_get_csb_size,
8037         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8038         .resume = gfx_v10_0_rlc_resume,
8039         .stop = gfx_v10_0_rlc_stop,
8040         .reset = gfx_v10_0_rlc_reset,
8041         .start = gfx_v10_0_rlc_start,
8042         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8043         .rlcg_wreg = gfx_v10_rlcg_wreg,
8044         .rlcg_rreg = gfx_v10_rlcg_rreg,
8045         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8046 };
8047
8048 static int gfx_v10_0_set_powergating_state(void *handle,
8049                                           enum amd_powergating_state state)
8050 {
8051         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8052         bool enable = (state == AMD_PG_STATE_GATE);
8053
8054         if (amdgpu_sriov_vf(adev))
8055                 return 0;
8056
8057         switch (adev->asic_type) {
8058         case CHIP_NAVI10:
8059         case CHIP_NAVI14:
8060         case CHIP_NAVI12:
8061         case CHIP_SIENNA_CICHLID:
8062         case CHIP_NAVY_FLOUNDER:
8063         case CHIP_DIMGREY_CAVEFISH:
8064         case CHIP_BEIGE_GOBY:
8065                 amdgpu_gfx_off_ctrl(adev, enable);
8066                 break;
8067         case CHIP_VANGOGH:
8068                 gfx_v10_cntl_pg(adev, enable);
8069                 amdgpu_gfx_off_ctrl(adev, enable);
8070                 break;
8071         default:
8072                 break;
8073         }
8074         return 0;
8075 }
8076
8077 static int gfx_v10_0_set_clockgating_state(void *handle,
8078                                           enum amd_clockgating_state state)
8079 {
8080         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8081
8082         if (amdgpu_sriov_vf(adev))
8083                 return 0;
8084
8085         switch (adev->asic_type) {
8086         case CHIP_NAVI10:
8087         case CHIP_NAVI14:
8088         case CHIP_NAVI12:
8089         case CHIP_SIENNA_CICHLID:
8090         case CHIP_NAVY_FLOUNDER:
8091         case CHIP_VANGOGH:
8092         case CHIP_DIMGREY_CAVEFISH:
8093         case CHIP_BEIGE_GOBY:
8094                 gfx_v10_0_update_gfx_clock_gating(adev,
8095                                                  state == AMD_CG_STATE_GATE);
8096                 break;
8097         default:
8098                 break;
8099         }
8100         return 0;
8101 }
8102
8103 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
8104 {
8105         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8106         int data;
8107
8108         /* AMD_CG_SUPPORT_GFX_FGCG */
8109         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8110         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8111                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8112
8113         /* AMD_CG_SUPPORT_GFX_MGCG */
8114         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8115         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8116                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8117
8118         /* AMD_CG_SUPPORT_GFX_CGCG */
8119         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8120         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8121                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8122
8123         /* AMD_CG_SUPPORT_GFX_CGLS */
8124         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8125                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8126
8127         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8128         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8129         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8130                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8131
8132         /* AMD_CG_SUPPORT_GFX_CP_LS */
8133         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8134         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8135                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8136
8137         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8138         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8139         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8140                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8141
8142         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8143         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8144                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8145 }
8146
8147 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8148 {
8149         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8150 }
8151
8152 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8153 {
8154         struct amdgpu_device *adev = ring->adev;
8155         u64 wptr;
8156
8157         /* XXX check if swapping is necessary on BE */
8158         if (ring->use_doorbell) {
8159                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8160         } else {
8161                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8162                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8163         }
8164
8165         return wptr;
8166 }
8167
8168 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8169 {
8170         struct amdgpu_device *adev = ring->adev;
8171
8172         if (ring->use_doorbell) {
8173                 /* XXX check if swapping is necessary on BE */
8174                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8175                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8176         } else {
8177                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8178                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8179         }
8180 }
8181
8182 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8183 {
8184         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8185 }
8186
8187 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8188 {
8189         u64 wptr;
8190
8191         /* XXX check if swapping is necessary on BE */
8192         if (ring->use_doorbell)
8193                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8194         else
8195                 BUG();
8196         return wptr;
8197 }
8198
8199 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8200 {
8201         struct amdgpu_device *adev = ring->adev;
8202
8203         /* XXX check if swapping is necessary on BE */
8204         if (ring->use_doorbell) {
8205                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8206                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8207         } else {
8208                 BUG(); /* only DOORBELL method supported on gfx10 now */
8209         }
8210 }
8211
8212 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8213 {
8214         struct amdgpu_device *adev = ring->adev;
8215         u32 ref_and_mask, reg_mem_engine;
8216         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8217
8218         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8219                 switch (ring->me) {
8220                 case 1:
8221                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8222                         break;
8223                 case 2:
8224                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8225                         break;
8226                 default:
8227                         return;
8228                 }
8229                 reg_mem_engine = 0;
8230         } else {
8231                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8232                 reg_mem_engine = 1; /* pfp */
8233         }
8234
8235         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8236                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8237                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8238                                ref_and_mask, ref_and_mask, 0x20);
8239 }
8240
8241 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8242                                        struct amdgpu_job *job,
8243                                        struct amdgpu_ib *ib,
8244                                        uint32_t flags)
8245 {
8246         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8247         u32 header, control = 0;
8248
8249         if (ib->flags & AMDGPU_IB_FLAG_CE)
8250                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8251         else
8252                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8253
8254         control |= ib->length_dw | (vmid << 24);
8255
8256         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8257                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8258
8259                 if (flags & AMDGPU_IB_PREEMPTED)
8260                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8261
8262                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8263                         gfx_v10_0_ring_emit_de_meta(ring,
8264                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8265         }
8266
8267         amdgpu_ring_write(ring, header);
8268         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8269         amdgpu_ring_write(ring,
8270 #ifdef __BIG_ENDIAN
8271                 (2 << 0) |
8272 #endif
8273                 lower_32_bits(ib->gpu_addr));
8274         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8275         amdgpu_ring_write(ring, control);
8276 }
8277
8278 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8279                                            struct amdgpu_job *job,
8280                                            struct amdgpu_ib *ib,
8281                                            uint32_t flags)
8282 {
8283         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8284         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8285
8286         /* Currently, there is a high possibility to get wave ID mismatch
8287          * between ME and GDS, leading to a hw deadlock, because ME generates
8288          * different wave IDs than the GDS expects. This situation happens
8289          * randomly when at least 5 compute pipes use GDS ordered append.
8290          * The wave IDs generated by ME are also wrong after suspend/resume.
8291          * Those are probably bugs somewhere else in the kernel driver.
8292          *
8293          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8294          * GDS to 0 for this ring (me/pipe).
8295          */
8296         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8297                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8298                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8299                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8300         }
8301
8302         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8303         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8304         amdgpu_ring_write(ring,
8305 #ifdef __BIG_ENDIAN
8306                                 (2 << 0) |
8307 #endif
8308                                 lower_32_bits(ib->gpu_addr));
8309         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8310         amdgpu_ring_write(ring, control);
8311 }
8312
8313 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8314                                      u64 seq, unsigned flags)
8315 {
8316         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8317         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8318
8319         /* RELEASE_MEM - flush caches, send int */
8320         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8321         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8322                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8323                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8324                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8325                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8326                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8327                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8328         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8329                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8330
8331         /*
8332          * the address should be Qword aligned if 64bit write, Dword
8333          * aligned if only send 32bit data low (discard data high)
8334          */
8335         if (write64bit)
8336                 BUG_ON(addr & 0x7);
8337         else
8338                 BUG_ON(addr & 0x3);
8339         amdgpu_ring_write(ring, lower_32_bits(addr));
8340         amdgpu_ring_write(ring, upper_32_bits(addr));
8341         amdgpu_ring_write(ring, lower_32_bits(seq));
8342         amdgpu_ring_write(ring, upper_32_bits(seq));
8343         amdgpu_ring_write(ring, 0);
8344 }
8345
8346 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8347 {
8348         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8349         uint32_t seq = ring->fence_drv.sync_seq;
8350         uint64_t addr = ring->fence_drv.gpu_addr;
8351
8352         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8353                                upper_32_bits(addr), seq, 0xffffffff, 4);
8354 }
8355
8356 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8357                                          unsigned vmid, uint64_t pd_addr)
8358 {
8359         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8360
8361         /* compute doesn't have PFP */
8362         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8363                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8364                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8365                 amdgpu_ring_write(ring, 0x0);
8366         }
8367 }
8368
8369 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8370                                           u64 seq, unsigned int flags)
8371 {
8372         struct amdgpu_device *adev = ring->adev;
8373
8374         /* we only allocate 32bit for each seq wb address */
8375         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8376
8377         /* write fence seq to the "addr" */
8378         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8379         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8380                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8381         amdgpu_ring_write(ring, lower_32_bits(addr));
8382         amdgpu_ring_write(ring, upper_32_bits(addr));
8383         amdgpu_ring_write(ring, lower_32_bits(seq));
8384
8385         if (flags & AMDGPU_FENCE_FLAG_INT) {
8386                 /* set register to trigger INT */
8387                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8388                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8389                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8390                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8391                 amdgpu_ring_write(ring, 0);
8392                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8393         }
8394 }
8395
8396 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8397 {
8398         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8399         amdgpu_ring_write(ring, 0);
8400 }
8401
8402 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8403                                          uint32_t flags)
8404 {
8405         uint32_t dw2 = 0;
8406
8407         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8408                 gfx_v10_0_ring_emit_ce_meta(ring,
8409                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8410
8411         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8412         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8413                 /* set load_global_config & load_global_uconfig */
8414                 dw2 |= 0x8001;
8415                 /* set load_cs_sh_regs */
8416                 dw2 |= 0x01000000;
8417                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8418                 dw2 |= 0x10002;
8419
8420                 /* set load_ce_ram if preamble presented */
8421                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8422                         dw2 |= 0x10000000;
8423         } else {
8424                 /* still load_ce_ram if this is the first time preamble presented
8425                  * although there is no context switch happens.
8426                  */
8427                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8428                         dw2 |= 0x10000000;
8429         }
8430
8431         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8432         amdgpu_ring_write(ring, dw2);
8433         amdgpu_ring_write(ring, 0);
8434 }
8435
8436 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8437 {
8438         unsigned ret;
8439
8440         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8441         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8442         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8443         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8444         ret = ring->wptr & ring->buf_mask;
8445         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8446
8447         return ret;
8448 }
8449
8450 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8451 {
8452         unsigned cur;
8453         BUG_ON(offset > ring->buf_mask);
8454         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8455
8456         cur = (ring->wptr - 1) & ring->buf_mask;
8457         if (likely(cur > offset))
8458                 ring->ring[offset] = cur - offset;
8459         else
8460                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8461 }
8462
8463 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8464 {
8465         int i, r = 0;
8466         struct amdgpu_device *adev = ring->adev;
8467         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8468         struct amdgpu_ring *kiq_ring = &kiq->ring;
8469         unsigned long flags;
8470
8471         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8472                 return -EINVAL;
8473
8474         spin_lock_irqsave(&kiq->ring_lock, flags);
8475
8476         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8477                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8478                 return -ENOMEM;
8479         }
8480
8481         /* assert preemption condition */
8482         amdgpu_ring_set_preempt_cond_exec(ring, false);
8483
8484         /* assert IB preemption, emit the trailing fence */
8485         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8486                                    ring->trail_fence_gpu_addr,
8487                                    ++ring->trail_seq);
8488         amdgpu_ring_commit(kiq_ring);
8489
8490         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8491
8492         /* poll the trailing fence */
8493         for (i = 0; i < adev->usec_timeout; i++) {
8494                 if (ring->trail_seq ==
8495                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8496                         break;
8497                 udelay(1);
8498         }
8499
8500         if (i >= adev->usec_timeout) {
8501                 r = -EINVAL;
8502                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8503         }
8504
8505         /* deassert preemption condition */
8506         amdgpu_ring_set_preempt_cond_exec(ring, true);
8507         return r;
8508 }
8509
8510 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8511 {
8512         struct amdgpu_device *adev = ring->adev;
8513         struct v10_ce_ib_state ce_payload = {0};
8514         uint64_t csa_addr;
8515         int cnt;
8516
8517         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8518         csa_addr = amdgpu_csa_vaddr(ring->adev);
8519
8520         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8521         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8522                                  WRITE_DATA_DST_SEL(8) |
8523                                  WR_CONFIRM) |
8524                                  WRITE_DATA_CACHE_POLICY(0));
8525         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8526                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8527         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8528                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8529
8530         if (resume)
8531                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8532                                            offsetof(struct v10_gfx_meta_data,
8533                                                     ce_payload),
8534                                            sizeof(ce_payload) >> 2);
8535         else
8536                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8537                                            sizeof(ce_payload) >> 2);
8538 }
8539
8540 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8541 {
8542         struct amdgpu_device *adev = ring->adev;
8543         struct v10_de_ib_state de_payload = {0};
8544         uint64_t csa_addr, gds_addr;
8545         int cnt;
8546
8547         csa_addr = amdgpu_csa_vaddr(ring->adev);
8548         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8549                          PAGE_SIZE);
8550         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8551         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8552
8553         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8554         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8555         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8556                                  WRITE_DATA_DST_SEL(8) |
8557                                  WR_CONFIRM) |
8558                                  WRITE_DATA_CACHE_POLICY(0));
8559         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8560                               offsetof(struct v10_gfx_meta_data, de_payload)));
8561         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8562                               offsetof(struct v10_gfx_meta_data, de_payload)));
8563
8564         if (resume)
8565                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8566                                            offsetof(struct v10_gfx_meta_data,
8567                                                     de_payload),
8568                                            sizeof(de_payload) >> 2);
8569         else
8570                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8571                                            sizeof(de_payload) >> 2);
8572 }
8573
8574 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8575                                     bool secure)
8576 {
8577         uint32_t v = secure ? FRAME_TMZ : 0;
8578
8579         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8580         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8581 }
8582
8583 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8584                                      uint32_t reg_val_offs)
8585 {
8586         struct amdgpu_device *adev = ring->adev;
8587
8588         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8589         amdgpu_ring_write(ring, 0 |     /* src: register*/
8590                                 (5 << 8) |      /* dst: memory */
8591                                 (1 << 20));     /* write confirm */
8592         amdgpu_ring_write(ring, reg);
8593         amdgpu_ring_write(ring, 0);
8594         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8595                                 reg_val_offs * 4));
8596         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8597                                 reg_val_offs * 4));
8598 }
8599
8600 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8601                                    uint32_t val)
8602 {
8603         uint32_t cmd = 0;
8604
8605         switch (ring->funcs->type) {
8606         case AMDGPU_RING_TYPE_GFX:
8607                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8608                 break;
8609         case AMDGPU_RING_TYPE_KIQ:
8610                 cmd = (1 << 16); /* no inc addr */
8611                 break;
8612         default:
8613                 cmd = WR_CONFIRM;
8614                 break;
8615         }
8616         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8617         amdgpu_ring_write(ring, cmd);
8618         amdgpu_ring_write(ring, reg);
8619         amdgpu_ring_write(ring, 0);
8620         amdgpu_ring_write(ring, val);
8621 }
8622
8623 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8624                                         uint32_t val, uint32_t mask)
8625 {
8626         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8627 }
8628
8629 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8630                                                    uint32_t reg0, uint32_t reg1,
8631                                                    uint32_t ref, uint32_t mask)
8632 {
8633         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8634         struct amdgpu_device *adev = ring->adev;
8635         bool fw_version_ok = false;
8636
8637         fw_version_ok = adev->gfx.cp_fw_write_wait;
8638
8639         if (fw_version_ok)
8640                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8641                                        ref, mask, 0x20);
8642         else
8643                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8644                                                            ref, mask);
8645 }
8646
8647 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8648                                          unsigned vmid)
8649 {
8650         struct amdgpu_device *adev = ring->adev;
8651         uint32_t value = 0;
8652
8653         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8654         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8655         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8656         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8657         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8658 }
8659
8660 static void
8661 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8662                                       uint32_t me, uint32_t pipe,
8663                                       enum amdgpu_interrupt_state state)
8664 {
8665         uint32_t cp_int_cntl, cp_int_cntl_reg;
8666
8667         if (!me) {
8668                 switch (pipe) {
8669                 case 0:
8670                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8671                         break;
8672                 case 1:
8673                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8674                         break;
8675                 default:
8676                         DRM_DEBUG("invalid pipe %d\n", pipe);
8677                         return;
8678                 }
8679         } else {
8680                 DRM_DEBUG("invalid me %d\n", me);
8681                 return;
8682         }
8683
8684         switch (state) {
8685         case AMDGPU_IRQ_STATE_DISABLE:
8686                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8687                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8688                                             TIME_STAMP_INT_ENABLE, 0);
8689                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8690                 break;
8691         case AMDGPU_IRQ_STATE_ENABLE:
8692                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8693                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8694                                             TIME_STAMP_INT_ENABLE, 1);
8695                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8696                 break;
8697         default:
8698                 break;
8699         }
8700 }
8701
8702 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8703                                                      int me, int pipe,
8704                                                      enum amdgpu_interrupt_state state)
8705 {
8706         u32 mec_int_cntl, mec_int_cntl_reg;
8707
8708         /*
8709          * amdgpu controls only the first MEC. That's why this function only
8710          * handles the setting of interrupts for this specific MEC. All other
8711          * pipes' interrupts are set by amdkfd.
8712          */
8713
8714         if (me == 1) {
8715                 switch (pipe) {
8716                 case 0:
8717                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8718                         break;
8719                 case 1:
8720                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8721                         break;
8722                 case 2:
8723                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8724                         break;
8725                 case 3:
8726                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8727                         break;
8728                 default:
8729                         DRM_DEBUG("invalid pipe %d\n", pipe);
8730                         return;
8731                 }
8732         } else {
8733                 DRM_DEBUG("invalid me %d\n", me);
8734                 return;
8735         }
8736
8737         switch (state) {
8738         case AMDGPU_IRQ_STATE_DISABLE:
8739                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8740                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8741                                              TIME_STAMP_INT_ENABLE, 0);
8742                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8743                 break;
8744         case AMDGPU_IRQ_STATE_ENABLE:
8745                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8746                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8747                                              TIME_STAMP_INT_ENABLE, 1);
8748                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8749                 break;
8750         default:
8751                 break;
8752         }
8753 }
8754
8755 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8756                                             struct amdgpu_irq_src *src,
8757                                             unsigned type,
8758                                             enum amdgpu_interrupt_state state)
8759 {
8760         switch (type) {
8761         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8762                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8763                 break;
8764         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8765                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8766                 break;
8767         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8768                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8769                 break;
8770         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8771                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8772                 break;
8773         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8774                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8775                 break;
8776         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8777                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8778                 break;
8779         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8780                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8781                 break;
8782         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8783                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8784                 break;
8785         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8786                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8787                 break;
8788         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8789                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8790                 break;
8791         default:
8792                 break;
8793         }
8794         return 0;
8795 }
8796
8797 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8798                              struct amdgpu_irq_src *source,
8799                              struct amdgpu_iv_entry *entry)
8800 {
8801         int i;
8802         u8 me_id, pipe_id, queue_id;
8803         struct amdgpu_ring *ring;
8804
8805         DRM_DEBUG("IH: CP EOP\n");
8806         me_id = (entry->ring_id & 0x0c) >> 2;
8807         pipe_id = (entry->ring_id & 0x03) >> 0;
8808         queue_id = (entry->ring_id & 0x70) >> 4;
8809
8810         switch (me_id) {
8811         case 0:
8812                 if (pipe_id == 0)
8813                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8814                 else
8815                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8816                 break;
8817         case 1:
8818         case 2:
8819                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8820                         ring = &adev->gfx.compute_ring[i];
8821                         /* Per-queue interrupt is supported for MEC starting from VI.
8822                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8823                           */
8824                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8825                                 amdgpu_fence_process(ring);
8826                 }
8827                 break;
8828         }
8829         return 0;
8830 }
8831
8832 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8833                                               struct amdgpu_irq_src *source,
8834                                               unsigned type,
8835                                               enum amdgpu_interrupt_state state)
8836 {
8837         switch (state) {
8838         case AMDGPU_IRQ_STATE_DISABLE:
8839         case AMDGPU_IRQ_STATE_ENABLE:
8840                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8841                                PRIV_REG_INT_ENABLE,
8842                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8843                 break;
8844         default:
8845                 break;
8846         }
8847
8848         return 0;
8849 }
8850
8851 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8852                                                struct amdgpu_irq_src *source,
8853                                                unsigned type,
8854                                                enum amdgpu_interrupt_state state)
8855 {
8856         switch (state) {
8857         case AMDGPU_IRQ_STATE_DISABLE:
8858         case AMDGPU_IRQ_STATE_ENABLE:
8859                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8860                                PRIV_INSTR_INT_ENABLE,
8861                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8862                 break;
8863         default:
8864                 break;
8865         }
8866
8867         return 0;
8868 }
8869
8870 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8871                                         struct amdgpu_iv_entry *entry)
8872 {
8873         u8 me_id, pipe_id, queue_id;
8874         struct amdgpu_ring *ring;
8875         int i;
8876
8877         me_id = (entry->ring_id & 0x0c) >> 2;
8878         pipe_id = (entry->ring_id & 0x03) >> 0;
8879         queue_id = (entry->ring_id & 0x70) >> 4;
8880
8881         switch (me_id) {
8882         case 0:
8883                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8884                         ring = &adev->gfx.gfx_ring[i];
8885                         /* we only enabled 1 gfx queue per pipe for now */
8886                         if (ring->me == me_id && ring->pipe == pipe_id)
8887                                 drm_sched_fault(&ring->sched);
8888                 }
8889                 break;
8890         case 1:
8891         case 2:
8892                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8893                         ring = &adev->gfx.compute_ring[i];
8894                         if (ring->me == me_id && ring->pipe == pipe_id &&
8895                             ring->queue == queue_id)
8896                                 drm_sched_fault(&ring->sched);
8897                 }
8898                 break;
8899         default:
8900                 BUG();
8901         }
8902 }
8903
8904 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8905                                   struct amdgpu_irq_src *source,
8906                                   struct amdgpu_iv_entry *entry)
8907 {
8908         DRM_ERROR("Illegal register access in command stream\n");
8909         gfx_v10_0_handle_priv_fault(adev, entry);
8910         return 0;
8911 }
8912
8913 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8914                                    struct amdgpu_irq_src *source,
8915                                    struct amdgpu_iv_entry *entry)
8916 {
8917         DRM_ERROR("Illegal instruction in command stream\n");
8918         gfx_v10_0_handle_priv_fault(adev, entry);
8919         return 0;
8920 }
8921
8922 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8923                                              struct amdgpu_irq_src *src,
8924                                              unsigned int type,
8925                                              enum amdgpu_interrupt_state state)
8926 {
8927         uint32_t tmp, target;
8928         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8929
8930         if (ring->me == 1)
8931                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8932         else
8933                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8934         target += ring->pipe;
8935
8936         switch (type) {
8937         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8938                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8939                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8940                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8941                                             GENERIC2_INT_ENABLE, 0);
8942                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8943
8944                         tmp = RREG32_SOC15_IP(GC, target);
8945                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8946                                             GENERIC2_INT_ENABLE, 0);
8947                         WREG32_SOC15_IP(GC, target, tmp);
8948                 } else {
8949                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8950                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8951                                             GENERIC2_INT_ENABLE, 1);
8952                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8953
8954                         tmp = RREG32_SOC15_IP(GC, target);
8955                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8956                                             GENERIC2_INT_ENABLE, 1);
8957                         WREG32_SOC15_IP(GC, target, tmp);
8958                 }
8959                 break;
8960         default:
8961                 BUG(); /* kiq only support GENERIC2_INT now */
8962                 break;
8963         }
8964         return 0;
8965 }
8966
8967 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8968                              struct amdgpu_irq_src *source,
8969                              struct amdgpu_iv_entry *entry)
8970 {
8971         u8 me_id, pipe_id, queue_id;
8972         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8973
8974         me_id = (entry->ring_id & 0x0c) >> 2;
8975         pipe_id = (entry->ring_id & 0x03) >> 0;
8976         queue_id = (entry->ring_id & 0x70) >> 4;
8977         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8978                    me_id, pipe_id, queue_id);
8979
8980         amdgpu_fence_process(ring);
8981         return 0;
8982 }
8983
8984 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8985 {
8986         const unsigned int gcr_cntl =
8987                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8988                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8989                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8990                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8991                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8992                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8993                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8994                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8995
8996         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8997         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8998         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8999         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9000         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9001         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9002         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9003         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9004         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9005 }
9006
9007 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9008         .name = "gfx_v10_0",
9009         .early_init = gfx_v10_0_early_init,
9010         .late_init = gfx_v10_0_late_init,
9011         .sw_init = gfx_v10_0_sw_init,
9012         .sw_fini = gfx_v10_0_sw_fini,
9013         .hw_init = gfx_v10_0_hw_init,
9014         .hw_fini = gfx_v10_0_hw_fini,
9015         .suspend = gfx_v10_0_suspend,
9016         .resume = gfx_v10_0_resume,
9017         .is_idle = gfx_v10_0_is_idle,
9018         .wait_for_idle = gfx_v10_0_wait_for_idle,
9019         .soft_reset = gfx_v10_0_soft_reset,
9020         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9021         .set_powergating_state = gfx_v10_0_set_powergating_state,
9022         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9023 };
9024
9025 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9026         .type = AMDGPU_RING_TYPE_GFX,
9027         .align_mask = 0xff,
9028         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9029         .support_64bit_ptrs = true,
9030         .vmhub = AMDGPU_GFXHUB_0,
9031         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9032         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9033         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9034         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9035                 5 + /* COND_EXEC */
9036                 7 + /* PIPELINE_SYNC */
9037                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9038                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9039                 2 + /* VM_FLUSH */
9040                 8 + /* FENCE for VM_FLUSH */
9041                 20 + /* GDS switch */
9042                 4 + /* double SWITCH_BUFFER,
9043                      * the first COND_EXEC jump to the place
9044                      * just prior to this double SWITCH_BUFFER
9045                      */
9046                 5 + /* COND_EXEC */
9047                 7 + /* HDP_flush */
9048                 4 + /* VGT_flush */
9049                 14 + /* CE_META */
9050                 31 + /* DE_META */
9051                 3 + /* CNTX_CTRL */
9052                 5 + /* HDP_INVL */
9053                 8 + 8 + /* FENCE x2 */
9054                 2 + /* SWITCH_BUFFER */
9055                 8, /* gfx_v10_0_emit_mem_sync */
9056         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9057         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9058         .emit_fence = gfx_v10_0_ring_emit_fence,
9059         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9060         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9061         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9062         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9063         .test_ring = gfx_v10_0_ring_test_ring,
9064         .test_ib = gfx_v10_0_ring_test_ib,
9065         .insert_nop = amdgpu_ring_insert_nop,
9066         .pad_ib = amdgpu_ring_generic_pad_ib,
9067         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9068         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9069         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9070         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9071         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9072         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9073         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9074         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9075         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9076         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9077         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9078 };
9079
9080 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9081         .type = AMDGPU_RING_TYPE_COMPUTE,
9082         .align_mask = 0xff,
9083         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9084         .support_64bit_ptrs = true,
9085         .vmhub = AMDGPU_GFXHUB_0,
9086         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9087         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9088         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9089         .emit_frame_size =
9090                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9091                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9092                 5 + /* hdp invalidate */
9093                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9094                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9095                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9096                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9097                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9098                 8, /* gfx_v10_0_emit_mem_sync */
9099         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9100         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9101         .emit_fence = gfx_v10_0_ring_emit_fence,
9102         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9103         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9104         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9105         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9106         .test_ring = gfx_v10_0_ring_test_ring,
9107         .test_ib = gfx_v10_0_ring_test_ib,
9108         .insert_nop = amdgpu_ring_insert_nop,
9109         .pad_ib = amdgpu_ring_generic_pad_ib,
9110         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9111         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9112         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9113         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9114 };
9115
9116 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9117         .type = AMDGPU_RING_TYPE_KIQ,
9118         .align_mask = 0xff,
9119         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9120         .support_64bit_ptrs = true,
9121         .vmhub = AMDGPU_GFXHUB_0,
9122         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9123         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9124         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9125         .emit_frame_size =
9126                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9127                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9128                 5 + /*hdp invalidate */
9129                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9130                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9131                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9132                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9133                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9134         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9135         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9136         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9137         .test_ring = gfx_v10_0_ring_test_ring,
9138         .test_ib = gfx_v10_0_ring_test_ib,
9139         .insert_nop = amdgpu_ring_insert_nop,
9140         .pad_ib = amdgpu_ring_generic_pad_ib,
9141         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9142         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9143         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9144         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9145 };
9146
9147 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9148 {
9149         int i;
9150
9151         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9152
9153         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9154                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9155
9156         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9157                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9158 }
9159
9160 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9161         .set = gfx_v10_0_set_eop_interrupt_state,
9162         .process = gfx_v10_0_eop_irq,
9163 };
9164
9165 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9166         .set = gfx_v10_0_set_priv_reg_fault_state,
9167         .process = gfx_v10_0_priv_reg_irq,
9168 };
9169
9170 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9171         .set = gfx_v10_0_set_priv_inst_fault_state,
9172         .process = gfx_v10_0_priv_inst_irq,
9173 };
9174
9175 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9176         .set = gfx_v10_0_kiq_set_interrupt_state,
9177         .process = gfx_v10_0_kiq_irq,
9178 };
9179
9180 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9181 {
9182         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9183         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9184
9185         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9186         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9187
9188         adev->gfx.priv_reg_irq.num_types = 1;
9189         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9190
9191         adev->gfx.priv_inst_irq.num_types = 1;
9192         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9193 }
9194
9195 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9196 {
9197         switch (adev->asic_type) {
9198         case CHIP_NAVI10:
9199         case CHIP_NAVI14:
9200         case CHIP_SIENNA_CICHLID:
9201         case CHIP_NAVY_FLOUNDER:
9202         case CHIP_VANGOGH:
9203         case CHIP_DIMGREY_CAVEFISH:
9204         case CHIP_BEIGE_GOBY:
9205                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9206                 break;
9207         case CHIP_NAVI12:
9208                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9209                 break;
9210         default:
9211                 break;
9212         }
9213 }
9214
9215 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9216 {
9217         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9218                             adev->gfx.config.max_sh_per_se *
9219                             adev->gfx.config.max_shader_engines;
9220
9221         adev->gds.gds_size = 0x10000;
9222         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9223         adev->gds.gws_size = 64;
9224         adev->gds.oa_size = 16;
9225 }
9226
9227 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9228                                                           u32 bitmap)
9229 {
9230         u32 data;
9231
9232         if (!bitmap)
9233                 return;
9234
9235         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9236         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9237
9238         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9239 }
9240
9241 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9242 {
9243         u32 data, wgp_bitmask;
9244         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9245         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9246
9247         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9248         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9249
9250         wgp_bitmask =
9251                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9252
9253         return (~data) & wgp_bitmask;
9254 }
9255
9256 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9257 {
9258         u32 wgp_idx, wgp_active_bitmap;
9259         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9260
9261         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9262         cu_active_bitmap = 0;
9263
9264         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9265                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9266                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9267                 if (wgp_active_bitmap & (1 << wgp_idx))
9268                         cu_active_bitmap |= cu_bitmap_per_wgp;
9269         }
9270
9271         return cu_active_bitmap;
9272 }
9273
9274 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9275                                  struct amdgpu_cu_info *cu_info)
9276 {
9277         int i, j, k, counter, active_cu_number = 0;
9278         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9279         unsigned disable_masks[4 * 2];
9280
9281         if (!adev || !cu_info)
9282                 return -EINVAL;
9283
9284         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9285
9286         mutex_lock(&adev->grbm_idx_mutex);
9287         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9288                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9289                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9290                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9291                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9292                                 continue;
9293                         mask = 1;
9294                         ao_bitmap = 0;
9295                         counter = 0;
9296                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9297                         if (i < 4 && j < 2)
9298                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9299                                         adev, disable_masks[i * 2 + j]);
9300                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9301                         cu_info->bitmap[i][j] = bitmap;
9302
9303                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9304                                 if (bitmap & mask) {
9305                                         if (counter < adev->gfx.config.max_cu_per_sh)
9306                                                 ao_bitmap |= mask;
9307                                         counter++;
9308                                 }
9309                                 mask <<= 1;
9310                         }
9311                         active_cu_number += counter;
9312                         if (i < 2 && j < 2)
9313                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9314                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9315                 }
9316         }
9317         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9318         mutex_unlock(&adev->grbm_idx_mutex);
9319
9320         cu_info->number = active_cu_number;
9321         cu_info->ao_cu_mask = ao_cu_mask;
9322         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9323
9324         return 0;
9325 }
9326
9327 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9328 {
9329         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9330
9331         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9332         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9333         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9334
9335         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9336         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9337         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9338
9339         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9340                                                 adev->gfx.config.max_shader_engines);
9341         disabled_sa = efuse_setting | vbios_setting;
9342         disabled_sa &= max_sa_mask;
9343
9344         return disabled_sa;
9345 }
9346
9347 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9348 {
9349         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9350         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9351
9352         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9353
9354         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9355         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9356         max_shader_engines = adev->gfx.config.max_shader_engines;
9357
9358         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9359                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9360                 disabled_sa_per_se &= max_sa_per_se_mask;
9361                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9362                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9363                         break;
9364                 }
9365         }
9366 }
9367
9368 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9369 {
9370         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9371                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9372                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9373                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9374
9375         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9376         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9377                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9378                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9379                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9380                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9381
9382         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9383                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9384                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9385                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9386
9387         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9388
9389         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9390                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9391 }
9392
9393 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9394 {
9395         .type = AMD_IP_BLOCK_TYPE_GFX,
9396         .major = 10,
9397         .minor = 0,
9398         .rev = 0,
9399         .funcs = &gfx_v10_0_ip_funcs,
9400 };