drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include "amdgpu_display.h"
  33 #include <asm/div64.h>
  34
  35 #include <linux/pci.h>
  36 #include <linux/pm_runtime.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <drm/drm_edid.h>
  39 #include <drm/drm_gem_framebuffer_helper.h>
  40 #include <drm/drm_fb_helper.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_vblank.h>
  43
  44 static void amdgpu_display_flip_callback(struct dma_fence *f,
  45                                          struct dma_fence_cb *cb)
  46 {
  47         struct amdgpu_flip_work *work =
  48                 container_of(cb, struct amdgpu_flip_work, cb);
  49
  50         dma_fence_put(f);
  51         schedule_work(&work->flip_work.work);
  52 }
  53
  54 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
  55                                              struct dma_fence **f)
  56 {
  57         struct dma_fence *fence= *f;
  58
  59         if (fence == NULL)
  60                 return false;
  61
  62         *f = NULL;
  63
  64         if (!dma_fence_add_callback(fence, &work->cb,
  65                                     amdgpu_display_flip_callback))
  66                 return true;
  67
  68         dma_fence_put(fence);
  69         return false;
  70 }
  71
  72 static void amdgpu_display_flip_work_func(struct work_struct *__work)
  73 {
  74         struct delayed_work *delayed_work =
  75                 container_of(__work, struct delayed_work, work);
  76         struct amdgpu_flip_work *work =
  77                 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
  78         struct amdgpu_device *adev = work->adev;
  79         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
  80
  81         struct drm_crtc *crtc = &amdgpu_crtc->base;
  82         unsigned long flags;
  83         unsigned i;
  84         int vpos, hpos;
  85
  86         if (amdgpu_display_flip_handle_fence(work, &work->excl))
  87                 return;
  88
  89         for (i = 0; i < work->shared_count; ++i)
  90                 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
  91                         return;
  92
  93         /* Wait until we're out of the vertical blank period before the one
  94          * targeted by the flip
  95          */
  96         if (amdgpu_crtc->enabled &&
  97             (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
  98                                                 &vpos, &hpos, NULL, NULL,
  99                                                 &crtc->hwmode)
 100              & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 101             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 102             (int)(work->target_vblank -
 103                   amdgpu_get_vblank_counter_kms(crtc)) > 0) {
 104                 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
 105                 return;
 106         }
 107
 108         /* We borrow the event spin lock for protecting flip_status */
 109         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 110
 111         /* Do the flip (mmio) */
 112         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 113
 114         /* Set the flip status */
 115         amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 116         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 117
 118
 119         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 120                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 121
 122 }
 123
 124 /*
 125  * Handle unpin events outside the interrupt handler proper.
 126  */
 127 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
 128 {
 129         struct amdgpu_flip_work *work =
 130                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 131         int r;
 132
 133         /* unpin of the old buffer */
 134         r = amdgpu_bo_reserve(work->old_abo, true);
 135         if (likely(r == 0)) {
 136                 amdgpu_bo_unpin(work->old_abo);
 137                 amdgpu_bo_unreserve(work->old_abo);
 138         } else
 139                 DRM_ERROR("failed to reserve buffer after flip\n");
 140
 141         amdgpu_bo_unref(&work->old_abo);
 142         kfree(work->shared);
 143         kfree(work);
 144 }
 145
 146 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 147                                 struct drm_framebuffer *fb,
 148                                 struct drm_pending_vblank_event *event,
 149                                 uint32_t page_flip_flags, uint32_t target,
 150                                 struct drm_modeset_acquire_ctx *ctx)
 151 {
 152         struct drm_device *dev = crtc->dev;
 153         struct amdgpu_device *adev = drm_to_adev(dev);
 154         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 155         struct drm_gem_object *obj;
 156         struct amdgpu_flip_work *work;
 157         struct amdgpu_bo *new_abo;
 158         unsigned long flags;
 159         u64 tiling_flags;
 160         int i, r;
 161
 162         work = kzalloc(sizeof *work, GFP_KERNEL);
 163         if (work == NULL)
 164                 return -ENOMEM;
 165
 166         INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
 167         INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
 168
 169         work->event = event;
 170         work->adev = adev;
 171         work->crtc_id = amdgpu_crtc->crtc_id;
 172         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 173
 174         /* schedule unpin of the old buffer */
 175         obj = crtc->primary->fb->obj[0];
 176
 177         /* take a reference to the old object */
 178         work->old_abo = gem_to_amdgpu_bo(obj);
 179         amdgpu_bo_ref(work->old_abo);
 180
 181         obj = fb->obj[0];
 182         new_abo = gem_to_amdgpu_bo(obj);
 183
 184         /* pin the new buffer */
 185         r = amdgpu_bo_reserve(new_abo, false);
 186         if (unlikely(r != 0)) {
 187                 DRM_ERROR("failed to reserve new abo buffer before flip\n");
 188                 goto cleanup;
 189         }
 190
 191         if (!adev->enable_virtual_display) {
 192                 r = amdgpu_bo_pin(new_abo,
 193                                   amdgpu_display_supported_domains(adev, new_abo->flags));
 194                 if (unlikely(r != 0)) {
 195                         DRM_ERROR("failed to pin new abo buffer before flip\n");
 196                         goto unreserve;
 197                 }
 198         }
 199
 200         r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
 201         if (unlikely(r != 0)) {
 202                 DRM_ERROR("%p bind failed\n", new_abo);
 203                 goto unpin;
 204         }
 205
 206         r = dma_resv_get_fences(new_abo->tbo.base.resv, &work->excl,
 207                                 &work->shared_count, &work->shared);
 208         if (unlikely(r != 0)) {
 209                 DRM_ERROR("failed to get fences for buffer\n");
 210                 goto unpin;
 211         }
 212
 213         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
 214         amdgpu_bo_unreserve(new_abo);
 215
 216         if (!adev->enable_virtual_display)
 217                 work->base = amdgpu_bo_gpu_offset(new_abo);
 218         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 219                 amdgpu_get_vblank_counter_kms(crtc);
 220
 221         /* we borrow the event spin lock for protecting flip_wrok */
 222         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 223         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 224                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 225                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 226                 r = -EBUSY;
 227                 goto pflip_cleanup;
 228         }
 229
 230         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 231         amdgpu_crtc->pflip_works = work;
 232
 233
 234         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 235                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 236         /* update crtc fb */
 237         crtc->primary->fb = fb;
 238         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 239         amdgpu_display_flip_work_func(&work->flip_work.work);
 240         return 0;
 241
 242 pflip_cleanup:
 243         if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
 244                 DRM_ERROR("failed to reserve new abo in error path\n");
 245                 goto cleanup;
 246         }
 247 unpin:
 248         if (!adev->enable_virtual_display)
 249                 amdgpu_bo_unpin(new_abo);
 250
 251 unreserve:
 252         amdgpu_bo_unreserve(new_abo);
 253
 254 cleanup:
 255         amdgpu_bo_unref(&work->old_abo);
 256         dma_fence_put(work->excl);
 257         for (i = 0; i < work->shared_count; ++i)
 258                 dma_fence_put(work->shared[i]);
 259         kfree(work->shared);
 260         kfree(work);
 261
 262         return r;
 263 }
 264
 265 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
 266                                    struct drm_modeset_acquire_ctx *ctx)
 267 {
 268         struct drm_device *dev;
 269         struct amdgpu_device *adev;
 270         struct drm_crtc *crtc;
 271         bool active = false;
 272         int ret;
 273
 274         if (!set || !set->crtc)
 275                 return -EINVAL;
 276
 277         dev = set->crtc->dev;
 278
 279         ret = pm_runtime_get_sync(dev->dev);
 280         if (ret < 0)
 281                 goto out;
 282
 283         ret = drm_crtc_helper_set_config(set, ctx);
 284
 285         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 286                 if (crtc->enabled)
 287                         active = true;
 288
 289         pm_runtime_mark_last_busy(dev->dev);
 290
 291         adev = drm_to_adev(dev);
 292         /* if we have active crtcs and we don't have a power ref,
 293            take the current one */
 294         if (active && !adev->have_disp_power_ref) {
 295                 adev->have_disp_power_ref = true;
 296                 return ret;
 297         }
 298         /* if we have no active crtcs, then drop the power ref
 299            we got before */
 300         if (!active && adev->have_disp_power_ref) {
 301                 pm_runtime_put_autosuspend(dev->dev);
 302                 adev->have_disp_power_ref = false;
 303         }
 304
 305 out:
 306         /* drop the power reference we got coming in here */
 307         pm_runtime_put_autosuspend(dev->dev);
 308         return ret;
 309 }
 310
 311 static const char *encoder_names[41] = {
 312         "NONE",
 313         "INTERNAL_LVDS",
 314         "INTERNAL_TMDS1",
 315         "INTERNAL_TMDS2",
 316         "INTERNAL_DAC1",
 317         "INTERNAL_DAC2",
 318         "INTERNAL_SDVOA",
 319         "INTERNAL_SDVOB",
 320         "SI170B",
 321         "CH7303",
 322         "CH7301",
 323         "INTERNAL_DVO1",
 324         "EXTERNAL_SDVOA",
 325         "EXTERNAL_SDVOB",
 326         "TITFP513",
 327         "INTERNAL_LVTM1",
 328         "VT1623",
 329         "HDMI_SI1930",
 330         "HDMI_INTERNAL",
 331         "INTERNAL_KLDSCP_TMDS1",
 332         "INTERNAL_KLDSCP_DVO1",
 333         "INTERNAL_KLDSCP_DAC1",
 334         "INTERNAL_KLDSCP_DAC2",
 335         "SI178",
 336         "MVPU_FPGA",
 337         "INTERNAL_DDI",
 338         "VT1625",
 339         "HDMI_SI1932",
 340         "DP_AN9801",
 341         "DP_DP501",
 342         "INTERNAL_UNIPHY",
 343         "INTERNAL_KLDSCP_LVTMA",
 344         "INTERNAL_UNIPHY1",
 345         "INTERNAL_UNIPHY2",
 346         "NUTMEG",
 347         "TRAVIS",
 348         "INTERNAL_VCE",
 349         "INTERNAL_UNIPHY3",
 350         "HDMI_ANX9805",
 351         "INTERNAL_AMCLK",
 352         "VIRTUAL",
 353 };
 354
 355 static const char *hpd_names[6] = {
 356         "HPD1",
 357         "HPD2",
 358         "HPD3",
 359         "HPD4",
 360         "HPD5",
 361         "HPD6",
 362 };
 363
 364 void amdgpu_display_print_display_setup(struct drm_device *dev)
 365 {
 366         struct drm_connector *connector;
 367         struct amdgpu_connector *amdgpu_connector;
 368         struct drm_encoder *encoder;
 369         struct amdgpu_encoder *amdgpu_encoder;
 370         struct drm_connector_list_iter iter;
 371         uint32_t devices;
 372         int i = 0;
 373
 374         drm_connector_list_iter_begin(dev, &iter);
 375         DRM_INFO("AMDGPU Display Connectors\n");
 376         drm_for_each_connector_iter(connector, &iter) {
 377                 amdgpu_connector = to_amdgpu_connector(connector);
 378                 DRM_INFO("Connector %d:\n", i);
 379                 DRM_INFO("  %s\n", connector->name);
 380                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 381                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 382                 if (amdgpu_connector->ddc_bus) {
 383                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 384                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 385                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 386                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 387                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 388                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 389                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 390                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 391                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 392                         if (amdgpu_connector->router.ddc_valid)
 393                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 394                                          amdgpu_connector->router.ddc_mux_control_pin,
 395                                          amdgpu_connector->router.ddc_mux_state);
 396                         if (amdgpu_connector->router.cd_valid)
 397                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 398                                          amdgpu_connector->router.cd_mux_control_pin,
 399                                          amdgpu_connector->router.cd_mux_state);
 400                 } else {
 401                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 402                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 403                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 404                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 405                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 406                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 407                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to [email protected]\n");
 408                 }
 409                 DRM_INFO("  Encoders:\n");
 410                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 411                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 412                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 413                         if (devices) {
 414                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 415                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 416                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 417                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 418                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 419                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 420                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 421                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 422                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 423                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 424                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 425                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 426                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 427                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 428                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 429                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 430                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 431                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 432                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 433                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 434                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 435                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 436                         }
 437                 }
 438                 i++;
 439         }
 440         drm_connector_list_iter_end(&iter);
 441 }
 442
 443 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 444                               bool use_aux)
 445 {
 446         u8 out = 0x0;
 447         u8 buf[8];
 448         int ret;
 449         struct i2c_msg msgs[] = {
 450                 {
 451                         .addr = DDC_ADDR,
 452                         .flags = 0,
 453                         .len = 1,
 454                         .buf = &out,
 455                 },
 456                 {
 457                         .addr = DDC_ADDR,
 458                         .flags = I2C_M_RD,
 459                         .len = 8,
 460                         .buf = buf,
 461                 }
 462         };
 463
 464         /* on hw with routers, select right port */
 465         if (amdgpu_connector->router.ddc_valid)
 466                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 467
 468         if (use_aux) {
 469                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 470         } else {
 471                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 472         }
 473
 474         if (ret != 2)
 475                 /* Couldn't find an accessible DDC on this connector */
 476                 return false;
 477         /* Probe also for valid EDID header
 478          * EDID header starts with:
 479          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 480          * Only the first 6 bytes must be valid as
 481          * drm_edid_block_valid() can fix the last 2 bytes */
 482         if (drm_edid_header_is_valid(buf) < 6) {
 483                 /* Couldn't find an accessible EDID on this
 484                  * connector */
 485                 return false;
 486         }
 487         return true;
 488 }
 489
 490 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 491         .destroy = drm_gem_fb_destroy,
 492         .create_handle = drm_gem_fb_create_handle,
 493 };
 494
 495 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 496                                           uint64_t bo_flags)
 497 {
 498         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 499
 500 #if defined(CONFIG_DRM_AMD_DC)
 501         /*
 502          * if amdgpu_bo_support_uswc returns false it means that USWC mappings
 503          * is not supported for this board. But this mapping is required
 504          * to avoid hang caused by placement of scanout BO in GTT on certain
 505          * APUs. So force the BO placement to VRAM in case this architecture
 506          * will not allow USWC mappings.
 507          * Also, don't allow GTT domain if the BO doesn't have USWC flag set.
 508          */
 509         if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 510             amdgpu_bo_support_uswc(bo_flags) &&
 511             amdgpu_device_asic_has_dc_support(adev->asic_type)) {
 512                 switch (adev->asic_type) {
 513                 case CHIP_CARRIZO:
 514                 case CHIP_STONEY:
 515                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 516                         break;
 517                 case CHIP_RAVEN:
 518                         /* enable S/G on PCO and RV2 */
 519                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
 520                             (adev->apu_flags & AMD_APU_IS_PICASSO))
 521                                 domain |= AMDGPU_GEM_DOMAIN_GTT;
 522                         break;
 523                 case CHIP_RENOIR:
 524                 case CHIP_VANGOGH:
 525                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 526                         break;
 527
 528                 default:
 529                         break;
 530                 }
 531         }
 532 #endif
 533
 534         return domain;
 535 }
 536
 537 static const struct drm_format_info dcc_formats[] = {
 538         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 539           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 540          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
 541           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 542         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
 543           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 544            .has_alpha = true, },
 545         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 546           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 547           .has_alpha = true, },
 548         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
 549           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 550           .has_alpha = true, },
 551         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
 552           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 553         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
 554           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 555         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
 556           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 557           .has_alpha = true, },
 558         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
 559           .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 560           .has_alpha = true, },
 561         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
 562           .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 563 };
 564
 565 static const struct drm_format_info dcc_retile_formats[] = {
 566         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
 567           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 568          { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
 569           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 570         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
 571           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 572            .has_alpha = true, },
 573         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
 574           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 575           .has_alpha = true, },
 576         { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
 577           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 578           .has_alpha = true, },
 579         { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
 580           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 581         { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
 582           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 583         { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
 584           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 585           .has_alpha = true, },
 586         { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
 587           .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
 588           .has_alpha = true, },
 589         { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
 590           .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
 591 };
 592
 593 static const struct drm_format_info *
 594 lookup_format_info(const struct drm_format_info formats[],
 595                   int num_formats, u32 format)
 596 {
 597         int i;
 598
 599         for (i = 0; i < num_formats; i++) {
 600                 if (formats[i].format == format)
 601                         return &formats[i];
 602         }
 603
 604         return NULL;
 605 }
 606
 607 const struct drm_format_info *
 608 amdgpu_lookup_format_info(u32 format, uint64_t modifier)
 609 {
 610         if (!IS_AMD_FMT_MOD(modifier))
 611                 return NULL;
 612
 613         if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
 614                 return lookup_format_info(dcc_retile_formats,
 615                                           ARRAY_SIZE(dcc_retile_formats),
 616                                           format);
 617
 618         if (AMD_FMT_MOD_GET(DCC, modifier))
 619                 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
 620                                           format);
 621
 622         /* returning NULL will cause the default format structs to be used. */
 623         return NULL;
 624 }
 625
 626
 627 /*
 628  * Tries to extract the renderable DCC offset from the opaque metadata attached
 629  * to the buffer.
 630  */
 631 static int
 632 extract_render_dcc_offset(struct amdgpu_device *adev,
 633                           struct drm_gem_object *obj,
 634                           uint64_t *offset)
 635 {
 636         struct amdgpu_bo *rbo;
 637         int r = 0;
 638         uint32_t metadata[10]; /* Something that fits a descriptor + header. */
 639         uint32_t size;
 640
 641         rbo = gem_to_amdgpu_bo(obj);
 642         r = amdgpu_bo_reserve(rbo, false);
 643
 644         if (unlikely(r)) {
 645                 /* Don't show error message when returning -ERESTARTSYS */
 646                 if (r != -ERESTARTSYS)
 647                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
 648                 return r;
 649         }
 650
 651         r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL);
 652         amdgpu_bo_unreserve(rbo);
 653
 654         if (r)
 655                 return r;
 656
 657         /*
 658          * The first word is the metadata version, and we need space for at least
 659          * the version + pci vendor+device id + 8 words for a descriptor.
 660          */
 661         if (size < 40  || metadata[0] != 1)
 662                 return -EINVAL;
 663
 664         if (adev->family >= AMDGPU_FAMILY_NV) {
 665                 /* resource word 6/7 META_DATA_ADDRESS{_LO} */
 666                 *offset = ((u64)metadata[9] << 16u) |
 667                           ((metadata[8] & 0xFF000000u) >> 16);
 668         } else {
 669                 /* resource word 5/7 META_DATA_ADDRESS */
 670                 *offset = ((u64)metadata[9] << 8u) |
 671                           ((u64)(metadata[7] & 0x1FE0000u) << 23);
 672         }
 673
 674         return 0;
 675 }
 676
 677 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 678 {
 679         struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 680         uint64_t modifier = 0;
 681
 682         if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 683                 modifier = DRM_FORMAT_MOD_LINEAR;
 684         } else {
 685                 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
 686                 bool has_xor = swizzle >= 16;
 687                 int block_size_bits;
 688                 int version;
 689                 int pipe_xor_bits = 0;
 690                 int bank_xor_bits = 0;
 691                 int packers = 0;
 692                 int rb = 0;
 693                 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
 694                 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 695
 696                 switch (swizzle >> 2) {
 697                 case 0: /* 256B */
 698                         block_size_bits = 8;
 699                         break;
 700                 case 1: /* 4KiB */
 701                 case 5: /* 4KiB _X */
 702                         block_size_bits = 12;
 703                         break;
 704                 case 2: /* 64KiB */
 705                 case 4: /* 64 KiB _T */
 706                 case 6: /* 64 KiB _X */
 707                         block_size_bits = 16;
 708                         break;
 709                 default:
 710                         /* RESERVED or VAR */
 711                         return -EINVAL;
 712                 }
 713
 714                 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 715                         version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 716                 else if (adev->family == AMDGPU_FAMILY_NV)
 717                         version = AMD_FMT_MOD_TILE_VER_GFX10;
 718                 else
 719                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 720
 721                 switch (swizzle & 3) {
 722                 case 0: /* Z microtiling */
 723                         return -EINVAL;
 724                 case 1: /* S microtiling */
 725                         if (!has_xor)
 726                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 727                         break;
 728                 case 2:
 729                         if (!has_xor && afb->base.format->cpp[0] != 4)
 730                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 731                         break;
 732                 case 3:
 733                         break;
 734                 }
 735
 736                 if (has_xor) {
 737                         switch (version) {
 738                         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 739                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 740                                 packers = min(block_size_bits - 8 - pipe_xor_bits,
 741                                               ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
 742                                 break;
 743                         case AMD_FMT_MOD_TILE_VER_GFX10:
 744                                 pipe_xor_bits = min(block_size_bits - 8, pipes);
 745                                 break;
 746                         case AMD_FMT_MOD_TILE_VER_GFX9:
 747                                 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
 748                                      ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
 749                                 pipe_xor_bits = min(block_size_bits - 8, pipes +
 750                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
 751                                 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
 752                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
 753                                 break;
 754                         }
 755                 }
 756
 757                 modifier = AMD_FMT_MOD |
 758                            AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
 759                            AMD_FMT_MOD_SET(TILE_VERSION, version) |
 760                            AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
 761                            AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
 762                            AMD_FMT_MOD_SET(PACKERS, packers);
 763
 764                 if (dcc_offset != 0) {
 765                         bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
 766                         bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 767                         const struct drm_format_info *format_info;
 768                         u64 render_dcc_offset;
 769
 770                         /* Enable constant encode on RAVEN2 and later. */
 771                         bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
 772                                                    (adev->asic_type == CHIP_RAVEN &&
 773                                                     adev->external_rev_id >= 0x81);
 774
 775                         int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 776                                               dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
 777                                               AMD_FMT_MOD_DCC_BLOCK_256B;
 778
 779                         modifier |= AMD_FMT_MOD_SET(DCC, 1) |
 780                                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
 781                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
 782                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
 783                                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
 784
 785                         afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
 786                         afb->base.pitches[1] =
 787                                 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
 788
 789                         /*
 790                          * If the userspace driver uses retiling the tiling flags do not contain
 791                          * info on the renderable DCC buffer. Luckily the opaque metadata contains
 792                          * the info so we can try to extract it. The kernel does not use this info
 793                          * but we should convert it to a modifier plane for getfb2, so the
 794                          * userspace driver that gets it doesn't have to juggle around another DCC
 795                          * plane internally.
 796                          */
 797                         if (extract_render_dcc_offset(adev, afb->base.obj[0],
 798                                                       &render_dcc_offset) == 0 &&
 799                             render_dcc_offset != 0 &&
 800                             render_dcc_offset != afb->base.offsets[1] &&
 801                             render_dcc_offset < UINT_MAX) {
 802                                 uint32_t dcc_block_bits;  /* of base surface data */
 803
 804                                 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
 805                                 afb->base.offsets[2] = render_dcc_offset;
 806
 807                                 if (adev->family >= AMDGPU_FAMILY_NV) {
 808                                         int extra_pipe = 0;
 809
 810                                         if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
 811                                             pipes == packers && pipes > 1)
 812                                                 extra_pipe = 1;
 813
 814                                         dcc_block_bits = max(20, 16 + pipes + extra_pipe);
 815                                 } else {
 816                                         modifier |= AMD_FMT_MOD_SET(RB, rb) |
 817                                                     AMD_FMT_MOD_SET(PIPE, pipes);
 818                                         dcc_block_bits = max(20, 18 + rb);
 819                                 }
 820
 821                                 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
 822                                 afb->base.pitches[2] = ALIGN(afb->base.width,
 823                                                              1u << ((dcc_block_bits + 1) / 2));
 824                         }
 825                         format_info = amdgpu_lookup_format_info(afb->base.format->format,
 826                                                                 modifier);
 827                         if (!format_info)
 828                                 return -EINVAL;
 829
 830                         afb->base.format = format_info;
 831                 }
 832         }
 833
 834         afb->base.modifier = modifier;
 835         afb->base.flags |= DRM_MODE_FB_MODIFIERS;
 836         return 0;
 837 }
 838
 839 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp,
 840                                  unsigned int *width, unsigned int *height)
 841 {
 842         unsigned int cpp_log2 = ilog2(cpp);
 843         unsigned int pixel_log2 = block_log2 - cpp_log2;
 844         unsigned int width_log2 = (pixel_log2 + 1) / 2;
 845         unsigned int height_log2 = pixel_log2 - width_log2;
 846
 847         *width = 1 << width_log2;
 848         *height = 1 << height_log2;
 849 }
 850
 851 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,
 852                                        bool pipe_aligned)
 853 {
 854         unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);
 855
 856         switch (ver) {
 857         case AMD_FMT_MOD_TILE_VER_GFX9: {
 858                 /*
 859                  * TODO: for pipe aligned we may need to check the alignment of the
 860                  * total size of the surface, which may need to be bigger than the
 861                  * natural alignment due to some HW workarounds
 862                  */
 863                 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);
 864         }
 865         case AMD_FMT_MOD_TILE_VER_GFX10:
 866         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: {
 867                 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
 868
 869                 if (ver == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 &&
 870                     AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)
 871                         ++pipes_log2;
 872
 873                 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12);
 874         }
 875         default:
 876                 return 0;
 877         }
 878 }
 879
 880 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane,
 881                                        const struct drm_format_info *format,
 882                                        unsigned int block_width, unsigned int block_height,
 883                                        unsigned int block_size_log2)
 884 {
 885         unsigned int width = rfb->base.width /
 886                 ((plane && plane < format->num_planes) ? format->hsub : 1);
 887         unsigned int height = rfb->base.height /
 888                 ((plane && plane < format->num_planes) ? format->vsub : 1);
 889         unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1;
 890         unsigned int block_pitch = block_width * cpp;
 891         unsigned int min_pitch = ALIGN(width * cpp, block_pitch);
 892         unsigned int block_size = 1 << block_size_log2;
 893         uint64_t size;
 894
 895         if (rfb->base.pitches[plane] % block_pitch) {
 896                 drm_dbg_kms(rfb->base.dev,
 897                             "pitch %d for plane %d is not a multiple of block pitch %d\n",
 898                             rfb->base.pitches[plane], plane, block_pitch);
 899                 return -EINVAL;
 900         }
 901         if (rfb->base.pitches[plane] < min_pitch) {
 902                 drm_dbg_kms(rfb->base.dev,
 903                             "pitch %d for plane %d is less than minimum pitch %d\n",
 904                             rfb->base.pitches[plane], plane, min_pitch);
 905                 return -EINVAL;
 906         }
 907
 908         /* Force at least natural alignment. */
 909         if (rfb->base.offsets[plane] % block_size) {
 910                 drm_dbg_kms(rfb->base.dev,
 911                             "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n",
 912                             rfb->base.offsets[plane], plane, block_size);
 913                 return -EINVAL;
 914         }
 915
 916         size = rfb->base.offsets[plane] +
 917                 (uint64_t)rfb->base.pitches[plane] / block_pitch *
 918                 block_size * DIV_ROUND_UP(height, block_height);
 919
 920         if (rfb->base.obj[0]->size < size) {
 921                 drm_dbg_kms(rfb->base.dev,
 922                             "BO size 0x%zx is less than 0x%llx required for plane %d\n",
 923                             rfb->base.obj[0]->size, size, plane);
 924                 return -EINVAL;
 925         }
 926
 927         return 0;
 928 }
 929
 930
 931 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
 932 {
 933         const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format);
 934         uint64_t modifier = rfb->base.modifier;
 935         int ret;
 936         unsigned int i, block_width, block_height, block_size_log2;
 937
 938         if (!rfb->base.dev->mode_config.allow_fb_modifiers)
 939                 return 0;
 940
 941         for (i = 0; i < format_info->num_planes; ++i) {
 942                 if (modifier == DRM_FORMAT_MOD_LINEAR) {
 943                         block_width = 256 / format_info->cpp[i];
 944                         block_height = 1;
 945                         block_size_log2 = 8;
 946                 } else {
 947                         int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
 948
 949                         switch ((swizzle & ~3) + 1) {
 950                         case DC_SW_256B_S:
 951                                 block_size_log2 = 8;
 952                                 break;
 953                         case DC_SW_4KB_S:
 954                         case DC_SW_4KB_S_X:
 955                                 block_size_log2 = 12;
 956                                 break;
 957                         case DC_SW_64KB_S:
 958                         case DC_SW_64KB_S_T:
 959                         case DC_SW_64KB_S_X:
 960                                 block_size_log2 = 16;
 961                                 break;
 962                         default:
 963                                 drm_dbg_kms(rfb->base.dev,
 964                                             "Swizzle mode with unknown block size: %d\n", swizzle);
 965                                 return -EINVAL;
 966                         }
 967
 968                         get_block_dimensions(block_size_log2, format_info->cpp[i],
 969                                              &block_width, &block_height);
 970                 }
 971
 972                 ret = amdgpu_display_verify_plane(rfb, i, format_info,
 973                                                   block_width, block_height, block_size_log2);
 974                 if (ret)
 975                         return ret;
 976         }
 977
 978         if (AMD_FMT_MOD_GET(DCC, modifier)) {
 979                 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
 980                         block_size_log2 = get_dcc_block_size(modifier, false, false);
 981                         get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
 982                                              &block_width, &block_height);
 983                         ret = amdgpu_display_verify_plane(rfb, i, format_info,
 984                                                           block_width, block_height,
 985                                                           block_size_log2);
 986                         if (ret)
 987                                 return ret;
 988
 989                         ++i;
 990                         block_size_log2 = get_dcc_block_size(modifier, true, true);
 991                 } else {
 992                         bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);
 993
 994                         block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);
 995                 }
 996                 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
 997                                      &block_width, &block_height);
 998                 ret = amdgpu_display_verify_plane(rfb, i, format_info,
 999                                                   block_width, block_height, block_size_log2);
1000                 if (ret)
1001                         return ret;
1002         }
1003
1004         return 0;
1005 }
1006
1007 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1008                                       uint64_t *tiling_flags, bool *tmz_surface)
1009 {
1010         struct amdgpu_bo *rbo;
1011         int r;
1012
1013         if (!amdgpu_fb) {
1014                 *tiling_flags = 0;
1015                 *tmz_surface = false;
1016                 return 0;
1017         }
1018
1019         rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
1020         r = amdgpu_bo_reserve(rbo, false);
1021
1022         if (unlikely(r)) {
1023                 /* Don't show error message when returning -ERESTARTSYS */
1024                 if (r != -ERESTARTSYS)
1025                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
1026                 return r;
1027         }
1028
1029         if (tiling_flags)
1030                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1031
1032         if (tmz_surface)
1033                 *tmz_surface = amdgpu_bo_encrypted(rbo);
1034
1035         amdgpu_bo_unreserve(rbo);
1036
1037         return r;
1038 }
1039
1040 int amdgpu_display_gem_fb_init(struct drm_device *dev,
1041                                struct amdgpu_framebuffer *rfb,
1042                                const struct drm_mode_fb_cmd2 *mode_cmd,
1043                                struct drm_gem_object *obj)
1044 {
1045         int ret;
1046
1047         rfb->base.obj[0] = obj;
1048         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1049         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1050         if (ret)
1051                 goto err;
1052
1053         ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1054         if (ret)
1055                 goto err;
1056
1057         return 0;
1058 err:
1059         drm_err(dev, "Failed to init gem fb: %d\n", ret);
1060         rfb->base.obj[0] = NULL;
1061         return ret;
1062 }
1063
1064 int amdgpu_display_gem_fb_verify_and_init(
1065         struct drm_device *dev, struct amdgpu_framebuffer *rfb,
1066         struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd,
1067         struct drm_gem_object *obj)
1068 {
1069         int ret;
1070
1071         rfb->base.obj[0] = obj;
1072         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
1073         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
1074         if (ret)
1075                 goto err;
1076         /* Verify that the modifier is supported. */
1077         if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format,
1078                                       mode_cmd->modifier[0])) {
1079                 drm_dbg_kms(dev,
1080                             "unsupported pixel format %p4cc / modifier 0x%llx\n",
1081                             &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1082
1083                 ret = -EINVAL;
1084                 goto err;
1085         }
1086
1087         ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj);
1088         if (ret)
1089                 goto err;
1090
1091         return 0;
1092 err:
1093         drm_err(dev, "Failed to verify and init gem fb: %d\n", ret);
1094         rfb->base.obj[0] = NULL;
1095         return ret;
1096 }
1097
1098 int amdgpu_display_framebuffer_init(struct drm_device *dev,
1099                                     struct amdgpu_framebuffer *rfb,
1100                                     const struct drm_mode_fb_cmd2 *mode_cmd,
1101                                     struct drm_gem_object *obj)
1102 {
1103         int ret, i;
1104
1105         /*
1106          * This needs to happen before modifier conversion as that might change
1107          * the number of planes.
1108          */
1109         for (i = 1; i < rfb->base.format->num_planes; ++i) {
1110                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
1111                         drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n",
1112                                     i, mode_cmd->handles[0], mode_cmd->handles[i]);
1113                         ret = -EINVAL;
1114                         return ret;
1115                 }
1116         }
1117
1118         ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1119         if (ret)
1120                 return ret;
1121
1122         if (dev->mode_config.allow_fb_modifiers &&
1123             !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1124                 ret = convert_tiling_flags_to_modifier(rfb);
1125                 if (ret) {
1126                         drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
1127                                     rfb->tiling_flags);
1128                         return ret;
1129                 }
1130         }
1131
1132         ret = amdgpu_display_verify_sizes(rfb);
1133         if (ret)
1134                 return ret;
1135
1136         for (i = 0; i < rfb->base.format->num_planes; ++i) {
1137                 drm_gem_object_get(rfb->base.obj[0]);
1138                 rfb->base.obj[i] = rfb->base.obj[0];
1139         }
1140
1141         return 0;
1142 }
1143
1144 struct drm_framebuffer *
1145 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
1146                                        struct drm_file *file_priv,
1147                                        const struct drm_mode_fb_cmd2 *mode_cmd)
1148 {
1149         struct amdgpu_framebuffer *amdgpu_fb;
1150         struct drm_gem_object *obj;
1151         struct amdgpu_bo *bo;
1152         uint32_t domains;
1153         int ret;
1154
1155         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1156         if (obj ==  NULL) {
1157                 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, "
1158                             "can't create framebuffer\n", mode_cmd->handles[0]);
1159                 return ERR_PTR(-ENOENT);
1160         }
1161
1162         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1163         bo = gem_to_amdgpu_bo(obj);
1164         domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
1165         if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
1166                 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
1167                 drm_gem_object_put(obj);
1168                 return ERR_PTR(-EINVAL);
1169         }
1170
1171         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
1172         if (amdgpu_fb == NULL) {
1173                 drm_gem_object_put(obj);
1174                 return ERR_PTR(-ENOMEM);
1175         }
1176
1177         ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv,
1178                                                     mode_cmd, obj);
1179         if (ret) {
1180                 kfree(amdgpu_fb);
1181                 drm_gem_object_put(obj);
1182                 return ERR_PTR(ret);
1183         }
1184
1185         drm_gem_object_put(obj);
1186         return &amdgpu_fb->base;
1187 }
1188
1189 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
1190         .fb_create = amdgpu_display_user_framebuffer_create,
1191         .output_poll_changed = drm_fb_helper_output_poll_changed,
1192 };
1193
1194 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
1195 {       { UNDERSCAN_OFF, "off" },
1196         { UNDERSCAN_ON, "on" },
1197         { UNDERSCAN_AUTO, "auto" },
1198 };
1199
1200 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
1201 {       { AMDGPU_AUDIO_DISABLE, "off" },
1202         { AMDGPU_AUDIO_ENABLE, "on" },
1203         { AMDGPU_AUDIO_AUTO, "auto" },
1204 };
1205
1206 /* XXX support different dither options? spatial, temporal, both, etc. */
1207 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
1208 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
1209         { AMDGPU_FMT_DITHER_ENABLE, "on" },
1210 };
1211
1212 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
1213 {
1214         int sz;
1215
1216         adev->mode_info.coherent_mode_property =
1217                 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
1218         if (!adev->mode_info.coherent_mode_property)
1219                 return -ENOMEM;
1220
1221         adev->mode_info.load_detect_property =
1222                 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
1223         if (!adev->mode_info.load_detect_property)
1224                 return -ENOMEM;
1225
1226         drm_mode_create_scaling_mode_property(adev_to_drm(adev));
1227
1228         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
1229         adev->mode_info.underscan_property =
1230                 drm_property_create_enum(adev_to_drm(adev), 0,
1231                                          "underscan",
1232                                          amdgpu_underscan_enum_list, sz);
1233
1234         adev->mode_info.underscan_hborder_property =
1235                 drm_property_create_range(adev_to_drm(adev), 0,
1236                                           "underscan hborder", 0, 128);
1237         if (!adev->mode_info.underscan_hborder_property)
1238                 return -ENOMEM;
1239
1240         adev->mode_info.underscan_vborder_property =
1241                 drm_property_create_range(adev_to_drm(adev), 0,
1242                                           "underscan vborder", 0, 128);
1243         if (!adev->mode_info.underscan_vborder_property)
1244                 return -ENOMEM;
1245
1246         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
1247         adev->mode_info.audio_property =
1248                 drm_property_create_enum(adev_to_drm(adev), 0,
1249                                          "audio",
1250                                          amdgpu_audio_enum_list, sz);
1251
1252         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
1253         adev->mode_info.dither_property =
1254                 drm_property_create_enum(adev_to_drm(adev), 0,
1255                                          "dither",
1256                                          amdgpu_dither_enum_list, sz);
1257
1258         if (amdgpu_device_has_dc_support(adev)) {
1259                 adev->mode_info.abm_level_property =
1260                         drm_property_create_range(adev_to_drm(adev), 0,
1261                                                   "abm level", 0, 4);
1262                 if (!adev->mode_info.abm_level_property)
1263                         return -ENOMEM;
1264         }
1265
1266         return 0;
1267 }
1268
1269 void amdgpu_display_update_priority(struct amdgpu_device *adev)
1270 {
1271         /* adjustment options for the display watermarks */
1272         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
1273                 adev->mode_info.disp_priority = 0;
1274         else
1275                 adev->mode_info.disp_priority = amdgpu_disp_priority;
1276
1277 }
1278
1279 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
1280 {
1281         /* try and guess if this is a tv or a monitor */
1282         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1283             (mode->vdisplay == 576) || /* 576p */
1284             (mode->vdisplay == 720) || /* 720p */
1285             (mode->vdisplay == 1080)) /* 1080p */
1286                 return true;
1287         else
1288                 return false;
1289 }
1290
1291 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1292                                         const struct drm_display_mode *mode,
1293                                         struct drm_display_mode *adjusted_mode)
1294 {
1295         struct drm_device *dev = crtc->dev;
1296         struct drm_encoder *encoder;
1297         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1298         struct amdgpu_encoder *amdgpu_encoder;
1299         struct drm_connector *connector;
1300         u32 src_v = 1, dst_v = 1;
1301         u32 src_h = 1, dst_h = 1;
1302
1303         amdgpu_crtc->h_border = 0;
1304         amdgpu_crtc->v_border = 0;
1305
1306         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1307                 if (encoder->crtc != crtc)
1308                         continue;
1309                 amdgpu_encoder = to_amdgpu_encoder(encoder);
1310                 connector = amdgpu_get_connector_for_encoder(encoder);
1311
1312                 /* set scaling */
1313                 if (amdgpu_encoder->rmx_type == RMX_OFF)
1314                         amdgpu_crtc->rmx_type = RMX_OFF;
1315                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
1316                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
1317                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
1318                 else
1319                         amdgpu_crtc->rmx_type = RMX_OFF;
1320                 /* copy native mode */
1321                 memcpy(&amdgpu_crtc->native_mode,
1322                        &amdgpu_encoder->native_mode,
1323                        sizeof(struct drm_display_mode));
1324                 src_v = crtc->mode.vdisplay;
1325                 dst_v = amdgpu_crtc->native_mode.vdisplay;
1326                 src_h = crtc->mode.hdisplay;
1327                 dst_h = amdgpu_crtc->native_mode.hdisplay;
1328
1329                 /* fix up for overscan on hdmi */
1330                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1331                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
1332                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
1333                       drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
1334                       amdgpu_display_is_hdtv_mode(mode)))) {
1335                         if (amdgpu_encoder->underscan_hborder != 0)
1336                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
1337                         else
1338                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
1339                         if (amdgpu_encoder->underscan_vborder != 0)
1340                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
1341                         else
1342                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
1343                         amdgpu_crtc->rmx_type = RMX_FULL;
1344                         src_v = crtc->mode.vdisplay;
1345                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
1346                         src_h = crtc->mode.hdisplay;
1347                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
1348                 }
1349         }
1350         if (amdgpu_crtc->rmx_type != RMX_OFF) {
1351                 fixed20_12 a, b;
1352                 a.full = dfixed_const(src_v);
1353                 b.full = dfixed_const(dst_v);
1354                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
1355                 a.full = dfixed_const(src_h);
1356                 b.full = dfixed_const(dst_h);
1357                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
1358         } else {
1359                 amdgpu_crtc->vsc.full = dfixed_const(1);
1360                 amdgpu_crtc->hsc.full = dfixed_const(1);
1361         }
1362         return true;
1363 }
1364
1365 /*
1366  * Retrieve current video scanout position of crtc on a given gpu, and
1367  * an optional accurate timestamp of when query happened.
1368  *
1369  * \param dev Device to query.
1370  * \param pipe Crtc to query.
1371  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1372  *              For driver internal use only also supports these flags:
1373  *
1374  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1375  *              of a fudged earlier start of vblank.
1376  *
1377  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1378  *              fudged earlier start of vblank in *vpos and the distance
1379  *              to true start of vblank in *hpos.
1380  *
1381  * \param *vpos Location where vertical scanout position should be stored.
1382  * \param *hpos Location where horizontal scanout position should go.
1383  * \param *stime Target location for timestamp taken immediately before
1384  *               scanout position query. Can be NULL to skip timestamp.
1385  * \param *etime Target location for timestamp taken immediately after
1386  *               scanout position query. Can be NULL to skip timestamp.
1387  *
1388  * Returns vpos as a positive number while in active scanout area.
1389  * Returns vpos as a negative number inside vblank, counting the number
1390  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1391  * until start of active scanout / end of vblank."
1392  *
1393  * \return Flags, or'ed together as follows:
1394  *
1395  * DRM_SCANOUTPOS_VALID = Query successful.
1396  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1397  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1398  * this flag means that returned position may be offset by a constant but
1399  * unknown small number of scanlines wrt. real scanout position.
1400  *
1401  */
1402 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
1403                         unsigned int pipe, unsigned int flags, int *vpos,
1404                         int *hpos, ktime_t *stime, ktime_t *etime,
1405                         const struct drm_display_mode *mode)
1406 {
1407         u32 vbl = 0, position = 0;
1408         int vbl_start, vbl_end, vtotal, ret = 0;
1409         bool in_vbl = true;
1410
1411         struct amdgpu_device *adev = drm_to_adev(dev);
1412
1413         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1414
1415         /* Get optional system timestamp before query. */
1416         if (stime)
1417                 *stime = ktime_get();
1418
1419         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
1420                 ret |= DRM_SCANOUTPOS_VALID;
1421
1422         /* Get optional system timestamp after query. */
1423         if (etime)
1424                 *etime = ktime_get();
1425
1426         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1427
1428         /* Decode into vertical and horizontal scanout position. */
1429         *vpos = position & 0x1fff;
1430         *hpos = (position >> 16) & 0x1fff;
1431
1432         /* Valid vblank area boundaries from gpu retrieved? */
1433         if (vbl > 0) {
1434                 /* Yes: Decode. */
1435                 ret |= DRM_SCANOUTPOS_ACCURATE;
1436                 vbl_start = vbl & 0x1fff;
1437                 vbl_end = (vbl >> 16) & 0x1fff;
1438         }
1439         else {
1440                 /* No: Fake something reasonable which gives at least ok results. */
1441                 vbl_start = mode->crtc_vdisplay;
1442                 vbl_end = 0;
1443         }
1444
1445         /* Called from driver internal vblank counter query code? */
1446         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1447             /* Caller wants distance from real vbl_start in *hpos */
1448             *hpos = *vpos - vbl_start;
1449         }
1450
1451         /* Fudge vblank to start a few scanlines earlier to handle the
1452          * problem that vblank irqs fire a few scanlines before start
1453          * of vblank. Some driver internal callers need the true vblank
1454          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1455          *
1456          * The cause of the "early" vblank irq is that the irq is triggered
1457          * by the line buffer logic when the line buffer read position enters
1458          * the vblank, whereas our crtc scanout position naturally lags the
1459          * line buffer read position.
1460          */
1461         if (!(flags & USE_REAL_VBLANKSTART))
1462                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1463
1464         /* Test scanout position against vblank region. */
1465         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1466                 in_vbl = false;
1467
1468         /* In vblank? */
1469         if (in_vbl)
1470             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1471
1472         /* Called from driver internal vblank counter query code? */
1473         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1474                 /* Caller wants distance from fudged earlier vbl_start */
1475                 *vpos -= vbl_start;
1476                 return ret;
1477         }
1478
1479         /* Check if inside vblank area and apply corrective offsets:
1480          * vpos will then be >=0 in video scanout area, but negative
1481          * within vblank area, counting down the number of lines until
1482          * start of scanout.
1483          */
1484
1485         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1486         if (in_vbl && (*vpos >= vbl_start)) {
1487                 vtotal = mode->crtc_vtotal;
1488
1489                 /* With variable refresh rate displays the vpos can exceed
1490                  * the vtotal value. Clamp to 0 to return -vbl_end instead
1491                  * of guessing the remaining number of lines until scanout.
1492                  */
1493                 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1494         }
1495
1496         /* Correct for shifted end of vbl at vbl_end. */
1497         *vpos = *vpos - vbl_end;
1498
1499         return ret;
1500 }
1501
1502 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1503 {
1504         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1505                 return AMDGPU_CRTC_IRQ_NONE;
1506
1507         switch (crtc) {
1508         case 0:
1509                 return AMDGPU_CRTC_IRQ_VBLANK1;
1510         case 1:
1511                 return AMDGPU_CRTC_IRQ_VBLANK2;
1512         case 2:
1513                 return AMDGPU_CRTC_IRQ_VBLANK3;
1514         case 3:
1515                 return AMDGPU_CRTC_IRQ_VBLANK4;
1516         case 4:
1517                 return AMDGPU_CRTC_IRQ_VBLANK5;
1518         case 5:
1519                 return AMDGPU_CRTC_IRQ_VBLANK6;
1520         default:
1521                 return AMDGPU_CRTC_IRQ_NONE;
1522         }
1523 }
1524
1525 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1526                         bool in_vblank_irq, int *vpos,
1527                         int *hpos, ktime_t *stime, ktime_t *etime,
1528                         const struct drm_display_mode *mode)
1529 {
1530         struct drm_device *dev = crtc->dev;
1531         unsigned int pipe = crtc->index;
1532
1533         return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1534                                                   stime, etime, mode);
1535 }
1536
1537 int amdgpu_display_suspend_helper(struct amdgpu_device *adev)
1538 {
1539         struct drm_device *dev = adev_to_drm(adev);
1540         struct drm_crtc *crtc;
1541         struct drm_connector *connector;
1542         struct drm_connector_list_iter iter;
1543         int r;
1544
1545         /* turn off display hw */
1546         drm_modeset_lock_all(dev);
1547         drm_connector_list_iter_begin(dev, &iter);
1548         drm_for_each_connector_iter(connector, &iter)
1549                 drm_helper_connector_dpms(connector,
1550                                           DRM_MODE_DPMS_OFF);
1551         drm_connector_list_iter_end(&iter);
1552         drm_modeset_unlock_all(dev);
1553         /* unpin the front buffers and cursors */
1554         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1555                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1556                 struct drm_framebuffer *fb = crtc->primary->fb;
1557                 struct amdgpu_bo *robj;
1558
1559                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1560                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1561                         r = amdgpu_bo_reserve(aobj, true);
1562                         if (r == 0) {
1563                                 amdgpu_bo_unpin(aobj);
1564                                 amdgpu_bo_unreserve(aobj);
1565                         }
1566                 }
1567
1568                 if (fb == NULL || fb->obj[0] == NULL) {
1569                         continue;
1570                 }
1571                 robj = gem_to_amdgpu_bo(fb->obj[0]);
1572                 /* don't unpin kernel fb objects */
1573                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1574                         r = amdgpu_bo_reserve(robj, true);
1575                         if (r == 0) {
1576                                 amdgpu_bo_unpin(robj);
1577                                 amdgpu_bo_unreserve(robj);
1578                         }
1579                 }
1580         }
1581         return 0;
1582 }
1583
1584 int amdgpu_display_resume_helper(struct amdgpu_device *adev)
1585 {
1586         struct drm_device *dev = adev_to_drm(adev);
1587         struct drm_connector *connector;
1588         struct drm_connector_list_iter iter;
1589         struct drm_crtc *crtc;
1590         int r;
1591
1592         /* pin cursors */
1593         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1594                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1595
1596                 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
1597                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1598                         r = amdgpu_bo_reserve(aobj, true);
1599                         if (r == 0) {
1600                                 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
1601                                 if (r != 0)
1602                                         dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r);
1603                                 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
1604                                 amdgpu_bo_unreserve(aobj);
1605                         }
1606                 }
1607         }
1608
1609         drm_helper_resume_force_mode(dev);
1610
1611         /* turn on display hw */
1612         drm_modeset_lock_all(dev);
1613
1614         drm_connector_list_iter_begin(dev, &iter);
1615         drm_for_each_connector_iter(connector, &iter)
1616                 drm_helper_connector_dpms(connector,
1617                                           DRM_MODE_DPMS_ON);
1618         drm_connector_list_iter_end(&iter);
1619
1620         drm_modeset_unlock_all(dev);
1621
1622         return 0;
1623 }
1624