drivers/gpu/drm/omapdrm/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <[email protected]>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/sizes.h>
  39 #include <linux/mfd/syscon.h>
  40 #include <linux/regmap.h>
  41 #include <linux/of.h>
  42 #include <linux/component.h>
  43
  44 #include "omapdss.h"
  45 #include "dss.h"
  46 #include "dss_features.h"
  47 #include "dispc.h"
  48
  49 /* DISPC */
  50 #define DISPC_SZ_REGS                   SZ_4K
  51
  52 enum omap_burst_size {
  53         BURST_SIZE_X2 = 0,
  54         BURST_SIZE_X4 = 1,
  55         BURST_SIZE_X8 = 2,
  56 };
  57
  58 #define REG_GET(idx, start, end) \
  59         FLD_GET(dispc_read_reg(idx), start, end)
  60
  61 #define REG_FLD_MOD(idx, val, start, end)                               \
  62         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  63
  64 struct dispc_features {
  65         u8 sw_start;
  66         u8 fp_start;
  67         u8 bp_start;
  68         u16 sw_max;
  69         u16 vp_max;
  70         u16 hp_max;
  71         u8 mgr_width_start;
  72         u8 mgr_height_start;
  73         u16 mgr_width_max;
  74         u16 mgr_height_max;
  75         unsigned long max_lcd_pclk;
  76         unsigned long max_tv_pclk;
  77         int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
  78                 const struct omap_video_timings *mgr_timings,
  79                 u16 width, u16 height, u16 out_width, u16 out_height,
  80                 enum omap_color_mode color_mode, bool *five_taps,
  81                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  82                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
  83         unsigned long (*calc_core_clk) (unsigned long pclk,
  84                 u16 width, u16 height, u16 out_width, u16 out_height,
  85                 bool mem_to_mem);
  86         u8 num_fifos;
  87
  88         /* swap GFX & WB fifos */
  89         bool gfx_fifo_workaround:1;
  90
  91         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
  92         bool no_framedone_tv:1;
  93
  94         /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
  95         bool mstandby_workaround:1;
  96
  97         bool set_max_preload:1;
  98
  99         /* PIXEL_INC is not added to the last pixel of a line */
 100         bool last_pixel_inc_missing:1;
 101
 102         /* POL_FREQ has ALIGN bit */
 103         bool supports_sync_align:1;
 104
 105         bool has_writeback:1;
 106
 107         bool supports_double_pixel:1;
 108
 109         /*
 110          * Field order for VENC is different than HDMI. We should handle this in
 111          * some intelligent manner, but as the SoCs have either HDMI or VENC,
 112          * never both, we can just use this flag for now.
 113          */
 114         bool reverse_ilace_field_order:1;
 115 };
 116
 117 #define DISPC_MAX_NR_FIFOS 5
 118
 119 static struct {
 120         struct platform_device *pdev;
 121         void __iomem    *base;
 122
 123         int irq;
 124         irq_handler_t user_handler;
 125         void *user_data;
 126
 127         unsigned long core_clk_rate;
 128         unsigned long tv_pclk_rate;
 129
 130         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 131         /* maps which plane is using a fifo. fifo-id -> plane-id */
 132         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 133
 134         bool            ctx_valid;
 135         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 136
 137         const struct dispc_features *feat;
 138
 139         bool is_enabled;
 140
 141         struct regmap *syscon_pol;
 142         u32 syscon_pol_offset;
 143
 144         /* DISPC_CONTROL & DISPC_CONFIG lock*/
 145         spinlock_t control_lock;
 146 } dispc;
 147
 148 enum omap_color_component {
 149         /* used for all color formats for OMAP3 and earlier
 150          * and for RGB and Y color component on OMAP4
 151          */
 152         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 153         /* used for UV component for
 154          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 155          * color formats on OMAP4
 156          */
 157         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 158 };
 159
 160 enum mgr_reg_fields {
 161         DISPC_MGR_FLD_ENABLE,
 162         DISPC_MGR_FLD_STNTFT,
 163         DISPC_MGR_FLD_GO,
 164         DISPC_MGR_FLD_TFTDATALINES,
 165         DISPC_MGR_FLD_STALLMODE,
 166         DISPC_MGR_FLD_TCKENABLE,
 167         DISPC_MGR_FLD_TCKSELECTION,
 168         DISPC_MGR_FLD_CPR,
 169         DISPC_MGR_FLD_FIFOHANDCHECK,
 170         /* used to maintain a count of the above fields */
 171         DISPC_MGR_FLD_NUM,
 172 };
 173
 174 struct dispc_reg_field {
 175         u16 reg;
 176         u8 high;
 177         u8 low;
 178 };
 179
 180 static const struct {
 181         const char *name;
 182         u32 vsync_irq;
 183         u32 framedone_irq;
 184         u32 sync_lost_irq;
 185         struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
 186 } mgr_desc[] = {
 187         [OMAP_DSS_CHANNEL_LCD] = {
 188                 .name           = "LCD",
 189                 .vsync_irq      = DISPC_IRQ_VSYNC,
 190                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 191                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 192                 .reg_desc       = {
 193                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 194                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 195                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 196                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 197                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 198                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 199                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 200                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 201                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 202                 },
 203         },
 204         [OMAP_DSS_CHANNEL_DIGIT] = {
 205                 .name           = "DIGIT",
 206                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 207                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
 208                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 209                 .reg_desc       = {
 210                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 211                         [DISPC_MGR_FLD_STNTFT]          = { },
 212                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 213                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 214                         [DISPC_MGR_FLD_STALLMODE]       = { },
 215                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 216                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 217                         [DISPC_MGR_FLD_CPR]             = { },
 218                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 219                 },
 220         },
 221         [OMAP_DSS_CHANNEL_LCD2] = {
 222                 .name           = "LCD2",
 223                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 224                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 225                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 226                 .reg_desc       = {
 227                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 228                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 229                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 230                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 231                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 232                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 233                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 234                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 235                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 236                 },
 237         },
 238         [OMAP_DSS_CHANNEL_LCD3] = {
 239                 .name           = "LCD3",
 240                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 241                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 242                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 243                 .reg_desc       = {
 244                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 245                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 246                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 247                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 248                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 249                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 250                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 251                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 252                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 253                 },
 254         },
 255 };
 256
 257 struct color_conv_coef {
 258         int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
 259         int full_range;
 260 };
 261
 262 static unsigned long dispc_fclk_rate(void);
 263 static unsigned long dispc_core_clk_rate(void);
 264 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 265 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 266
 267 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
 268 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 269
 270 static inline void dispc_write_reg(const u16 idx, u32 val)
 271 {
 272         __raw_writel(val, dispc.base + idx);
 273 }
 274
 275 static inline u32 dispc_read_reg(const u16 idx)
 276 {
 277         return __raw_readl(dispc.base + idx);
 278 }
 279
 280 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 281 {
 282         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 283         return REG_GET(rfld.reg, rfld.high, rfld.low);
 284 }
 285
 286 static void mgr_fld_write(enum omap_channel channel,
 287                                         enum mgr_reg_fields regfld, int val) {
 288         const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 289         const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
 290         unsigned long flags;
 291
 292         if (need_lock)
 293                 spin_lock_irqsave(&dispc.control_lock, flags);
 294
 295         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 296
 297         if (need_lock)
 298                 spin_unlock_irqrestore(&dispc.control_lock, flags);
 299 }
 300
 301 #define SR(reg) \
 302         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 303 #define RR(reg) \
 304         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 305
 306 static void dispc_save_context(void)
 307 {
 308         int i, j;
 309
 310         DSSDBG("dispc_save_context\n");
 311
 312         SR(IRQENABLE);
 313         SR(CONTROL);
 314         SR(CONFIG);
 315         SR(LINE_NUMBER);
 316         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 317                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 318                 SR(GLOBAL_ALPHA);
 319         if (dss_has_feature(FEAT_MGR_LCD2)) {
 320                 SR(CONTROL2);
 321                 SR(CONFIG2);
 322         }
 323         if (dss_has_feature(FEAT_MGR_LCD3)) {
 324                 SR(CONTROL3);
 325                 SR(CONFIG3);
 326         }
 327
 328         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 329                 SR(DEFAULT_COLOR(i));
 330                 SR(TRANS_COLOR(i));
 331                 SR(SIZE_MGR(i));
 332                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 333                         continue;
 334                 SR(TIMING_H(i));
 335                 SR(TIMING_V(i));
 336                 SR(POL_FREQ(i));
 337                 SR(DIVISORo(i));
 338
 339                 SR(DATA_CYCLE1(i));
 340                 SR(DATA_CYCLE2(i));
 341                 SR(DATA_CYCLE3(i));
 342
 343                 if (dss_has_feature(FEAT_CPR)) {
 344                         SR(CPR_COEF_R(i));
 345                         SR(CPR_COEF_G(i));
 346                         SR(CPR_COEF_B(i));
 347                 }
 348         }
 349
 350         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 351                 SR(OVL_BA0(i));
 352                 SR(OVL_BA1(i));
 353                 SR(OVL_POSITION(i));
 354                 SR(OVL_SIZE(i));
 355                 SR(OVL_ATTRIBUTES(i));
 356                 SR(OVL_FIFO_THRESHOLD(i));
 357                 SR(OVL_ROW_INC(i));
 358                 SR(OVL_PIXEL_INC(i));
 359                 if (dss_has_feature(FEAT_PRELOAD))
 360                         SR(OVL_PRELOAD(i));
 361                 if (i == OMAP_DSS_GFX) {
 362                         SR(OVL_WINDOW_SKIP(i));
 363                         SR(OVL_TABLE_BA(i));
 364                         continue;
 365                 }
 366                 SR(OVL_FIR(i));
 367                 SR(OVL_PICTURE_SIZE(i));
 368                 SR(OVL_ACCU0(i));
 369                 SR(OVL_ACCU1(i));
 370
 371                 for (j = 0; j < 8; j++)
 372                         SR(OVL_FIR_COEF_H(i, j));
 373
 374                 for (j = 0; j < 8; j++)
 375                         SR(OVL_FIR_COEF_HV(i, j));
 376
 377                 for (j = 0; j < 5; j++)
 378                         SR(OVL_CONV_COEF(i, j));
 379
 380                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 381                         for (j = 0; j < 8; j++)
 382                                 SR(OVL_FIR_COEF_V(i, j));
 383                 }
 384
 385                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 386                         SR(OVL_BA0_UV(i));
 387                         SR(OVL_BA1_UV(i));
 388                         SR(OVL_FIR2(i));
 389                         SR(OVL_ACCU2_0(i));
 390                         SR(OVL_ACCU2_1(i));
 391
 392                         for (j = 0; j < 8; j++)
 393                                 SR(OVL_FIR_COEF_H2(i, j));
 394
 395                         for (j = 0; j < 8; j++)
 396                                 SR(OVL_FIR_COEF_HV2(i, j));
 397
 398                         for (j = 0; j < 8; j++)
 399                                 SR(OVL_FIR_COEF_V2(i, j));
 400                 }
 401                 if (dss_has_feature(FEAT_ATTR2))
 402                         SR(OVL_ATTRIBUTES2(i));
 403         }
 404
 405         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 406                 SR(DIVISOR);
 407
 408         dispc.ctx_valid = true;
 409
 410         DSSDBG("context saved\n");
 411 }
 412
 413 static void dispc_restore_context(void)
 414 {
 415         int i, j;
 416
 417         DSSDBG("dispc_restore_context\n");
 418
 419         if (!dispc.ctx_valid)
 420                 return;
 421
 422         /*RR(IRQENABLE);*/
 423         /*RR(CONTROL);*/
 424         RR(CONFIG);
 425         RR(LINE_NUMBER);
 426         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 427                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 428                 RR(GLOBAL_ALPHA);
 429         if (dss_has_feature(FEAT_MGR_LCD2))
 430                 RR(CONFIG2);
 431         if (dss_has_feature(FEAT_MGR_LCD3))
 432                 RR(CONFIG3);
 433
 434         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 435                 RR(DEFAULT_COLOR(i));
 436                 RR(TRANS_COLOR(i));
 437                 RR(SIZE_MGR(i));
 438                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 439                         continue;
 440                 RR(TIMING_H(i));
 441                 RR(TIMING_V(i));
 442                 RR(POL_FREQ(i));
 443                 RR(DIVISORo(i));
 444
 445                 RR(DATA_CYCLE1(i));
 446                 RR(DATA_CYCLE2(i));
 447                 RR(DATA_CYCLE3(i));
 448
 449                 if (dss_has_feature(FEAT_CPR)) {
 450                         RR(CPR_COEF_R(i));
 451                         RR(CPR_COEF_G(i));
 452                         RR(CPR_COEF_B(i));
 453                 }
 454         }
 455
 456         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 457                 RR(OVL_BA0(i));
 458                 RR(OVL_BA1(i));
 459                 RR(OVL_POSITION(i));
 460                 RR(OVL_SIZE(i));
 461                 RR(OVL_ATTRIBUTES(i));
 462                 RR(OVL_FIFO_THRESHOLD(i));
 463                 RR(OVL_ROW_INC(i));
 464                 RR(OVL_PIXEL_INC(i));
 465                 if (dss_has_feature(FEAT_PRELOAD))
 466                         RR(OVL_PRELOAD(i));
 467                 if (i == OMAP_DSS_GFX) {
 468                         RR(OVL_WINDOW_SKIP(i));
 469                         RR(OVL_TABLE_BA(i));
 470                         continue;
 471                 }
 472                 RR(OVL_FIR(i));
 473                 RR(OVL_PICTURE_SIZE(i));
 474                 RR(OVL_ACCU0(i));
 475                 RR(OVL_ACCU1(i));
 476
 477                 for (j = 0; j < 8; j++)
 478                         RR(OVL_FIR_COEF_H(i, j));
 479
 480                 for (j = 0; j < 8; j++)
 481                         RR(OVL_FIR_COEF_HV(i, j));
 482
 483                 for (j = 0; j < 5; j++)
 484                         RR(OVL_CONV_COEF(i, j));
 485
 486                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 487                         for (j = 0; j < 8; j++)
 488                                 RR(OVL_FIR_COEF_V(i, j));
 489                 }
 490
 491                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 492                         RR(OVL_BA0_UV(i));
 493                         RR(OVL_BA1_UV(i));
 494                         RR(OVL_FIR2(i));
 495                         RR(OVL_ACCU2_0(i));
 496                         RR(OVL_ACCU2_1(i));
 497
 498                         for (j = 0; j < 8; j++)
 499                                 RR(OVL_FIR_COEF_H2(i, j));
 500
 501                         for (j = 0; j < 8; j++)
 502                                 RR(OVL_FIR_COEF_HV2(i, j));
 503
 504                         for (j = 0; j < 8; j++)
 505                                 RR(OVL_FIR_COEF_V2(i, j));
 506                 }
 507                 if (dss_has_feature(FEAT_ATTR2))
 508                         RR(OVL_ATTRIBUTES2(i));
 509         }
 510
 511         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 512                 RR(DIVISOR);
 513
 514         /* enable last, because LCD & DIGIT enable are here */
 515         RR(CONTROL);
 516         if (dss_has_feature(FEAT_MGR_LCD2))
 517                 RR(CONTROL2);
 518         if (dss_has_feature(FEAT_MGR_LCD3))
 519                 RR(CONTROL3);
 520         /* clear spurious SYNC_LOST_DIGIT interrupts */
 521         dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
 522
 523         /*
 524          * enable last so IRQs won't trigger before
 525          * the context is fully restored
 526          */
 527         RR(IRQENABLE);
 528
 529         DSSDBG("context restored\n");
 530 }
 531
 532 #undef SR
 533 #undef RR
 534
 535 int dispc_runtime_get(void)
 536 {
 537         int r;
 538
 539         DSSDBG("dispc_runtime_get\n");
 540
 541         r = pm_runtime_get_sync(&dispc.pdev->dev);
 542         WARN_ON(r < 0);
 543         return r < 0 ? r : 0;
 544 }
 545 EXPORT_SYMBOL(dispc_runtime_get);
 546
 547 void dispc_runtime_put(void)
 548 {
 549         int r;
 550
 551         DSSDBG("dispc_runtime_put\n");
 552
 553         r = pm_runtime_put_sync(&dispc.pdev->dev);
 554         WARN_ON(r < 0 && r != -ENOSYS);
 555 }
 556 EXPORT_SYMBOL(dispc_runtime_put);
 557
 558 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 559 {
 560         return mgr_desc[channel].vsync_irq;
 561 }
 562 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
 563
 564 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 565 {
 566         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
 567                 return 0;
 568
 569         return mgr_desc[channel].framedone_irq;
 570 }
 571 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
 572
 573 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
 574 {
 575         return mgr_desc[channel].sync_lost_irq;
 576 }
 577 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
 578
 579 u32 dispc_wb_get_framedone_irq(void)
 580 {
 581         return DISPC_IRQ_FRAMEDONEWB;
 582 }
 583
 584 bool dispc_mgr_go_busy(enum omap_channel channel)
 585 {
 586         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 587 }
 588 EXPORT_SYMBOL(dispc_mgr_go_busy);
 589
 590 void dispc_mgr_go(enum omap_channel channel)
 591 {
 592         WARN_ON(!dispc_mgr_is_enabled(channel));
 593         WARN_ON(dispc_mgr_go_busy(channel));
 594
 595         DSSDBG("GO %s\n", mgr_desc[channel].name);
 596
 597         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 598 }
 599 EXPORT_SYMBOL(dispc_mgr_go);
 600
 601 bool dispc_wb_go_busy(void)
 602 {
 603         return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 604 }
 605
 606 void dispc_wb_go(void)
 607 {
 608         enum omap_plane plane = OMAP_DSS_WB;
 609         bool enable, go;
 610
 611         enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
 612
 613         if (!enable)
 614                 return;
 615
 616         go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 617         if (go) {
 618                 DSSERR("GO bit not down for WB\n");
 619                 return;
 620         }
 621
 622         REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
 623 }
 624
 625 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 626 {
 627         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 628 }
 629
 630 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 631 {
 632         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 633 }
 634
 635 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 636 {
 637         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 638 }
 639
 640 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 641 {
 642         BUG_ON(plane == OMAP_DSS_GFX);
 643
 644         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 645 }
 646
 647 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 648                 u32 value)
 649 {
 650         BUG_ON(plane == OMAP_DSS_GFX);
 651
 652         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 653 }
 654
 655 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 656 {
 657         BUG_ON(plane == OMAP_DSS_GFX);
 658
 659         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 660 }
 661
 662 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 663                                 int fir_vinc, int five_taps,
 664                                 enum omap_color_component color_comp)
 665 {
 666         const struct dispc_coef *h_coef, *v_coef;
 667         int i;
 668
 669         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 670         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 671
 672         for (i = 0; i < 8; i++) {
 673                 u32 h, hv;
 674
 675                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 676                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 677                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 678                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 679                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 680                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 681                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 682                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 683
 684                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 685                         dispc_ovl_write_firh_reg(plane, i, h);
 686                         dispc_ovl_write_firhv_reg(plane, i, hv);
 687                 } else {
 688                         dispc_ovl_write_firh2_reg(plane, i, h);
 689                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 690                 }
 691
 692         }
 693
 694         if (five_taps) {
 695                 for (i = 0; i < 8; i++) {
 696                         u32 v;
 697                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 698                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 699                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 700                                 dispc_ovl_write_firv_reg(plane, i, v);
 701                         else
 702                                 dispc_ovl_write_firv2_reg(plane, i, v);
 703                 }
 704         }
 705 }
 706
 707
 708 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
 709                 const struct color_conv_coef *ct)
 710 {
 711 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 712
 713         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
 714         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
 715         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
 716         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
 717         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 718
 719         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 720
 721 #undef CVAL
 722 }
 723
 724 static void dispc_setup_color_conv_coef(void)
 725 {
 726         int i;
 727         int num_ovl = dss_feat_get_num_ovls();
 728         const struct color_conv_coef ctbl_bt601_5_ovl = {
 729                 /* YUV -> RGB */
 730                 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
 731         };
 732         const struct color_conv_coef ctbl_bt601_5_wb = {
 733                 /* RGB -> YUV */
 734                 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
 735         };
 736
 737         for (i = 1; i < num_ovl; i++)
 738                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
 739
 740         if (dispc.feat->has_writeback)
 741                 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
 742 }
 743
 744 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 745 {
 746         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 747 }
 748
 749 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 750 {
 751         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 752 }
 753
 754 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 755 {
 756         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 757 }
 758
 759 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 760 {
 761         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 762 }
 763
 764 static void dispc_ovl_set_pos(enum omap_plane plane,
 765                 enum omap_overlay_caps caps, int x, int y)
 766 {
 767         u32 val;
 768
 769         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 770                 return;
 771
 772         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 773
 774         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 775 }
 776
 777 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 778                 int height)
 779 {
 780         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 781
 782         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 783                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 784         else
 785                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 786 }
 787
 788 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 789                 int height)
 790 {
 791         u32 val;
 792
 793         BUG_ON(plane == OMAP_DSS_GFX);
 794
 795         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 796
 797         if (plane == OMAP_DSS_WB)
 798                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 799         else
 800                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 801 }
 802
 803 static void dispc_ovl_set_zorder(enum omap_plane plane,
 804                 enum omap_overlay_caps caps, u8 zorder)
 805 {
 806         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 807                 return;
 808
 809         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 810 }
 811
 812 static void dispc_ovl_enable_zorder_planes(void)
 813 {
 814         int i;
 815
 816         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 817                 return;
 818
 819         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 820                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 821 }
 822
 823 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 824                 enum omap_overlay_caps caps, bool enable)
 825 {
 826         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 827                 return;
 828
 829         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 830 }
 831
 832 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 833                 enum omap_overlay_caps caps, u8 global_alpha)
 834 {
 835         static const unsigned shifts[] = { 0, 8, 16, 24, };
 836         int shift;
 837
 838         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 839                 return;
 840
 841         shift = shifts[plane];
 842         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 843 }
 844
 845 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 846 {
 847         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 848 }
 849
 850 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 851 {
 852         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 853 }
 854
 855 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 856                 enum omap_color_mode color_mode)
 857 {
 858         u32 m = 0;
 859         if (plane != OMAP_DSS_GFX) {
 860                 switch (color_mode) {
 861                 case OMAP_DSS_COLOR_NV12:
 862                         m = 0x0; break;
 863                 case OMAP_DSS_COLOR_RGBX16:
 864                         m = 0x1; break;
 865                 case OMAP_DSS_COLOR_RGBA16:
 866                         m = 0x2; break;
 867                 case OMAP_DSS_COLOR_RGB12U:
 868                         m = 0x4; break;
 869                 case OMAP_DSS_COLOR_ARGB16:
 870                         m = 0x5; break;
 871                 case OMAP_DSS_COLOR_RGB16:
 872                         m = 0x6; break;
 873                 case OMAP_DSS_COLOR_ARGB16_1555:
 874                         m = 0x7; break;
 875                 case OMAP_DSS_COLOR_RGB24U:
 876                         m = 0x8; break;
 877                 case OMAP_DSS_COLOR_RGB24P:
 878                         m = 0x9; break;
 879                 case OMAP_DSS_COLOR_YUV2:
 880                         m = 0xa; break;
 881                 case OMAP_DSS_COLOR_UYVY:
 882                         m = 0xb; break;
 883                 case OMAP_DSS_COLOR_ARGB32:
 884                         m = 0xc; break;
 885                 case OMAP_DSS_COLOR_RGBA32:
 886                         m = 0xd; break;
 887                 case OMAP_DSS_COLOR_RGBX32:
 888                         m = 0xe; break;
 889                 case OMAP_DSS_COLOR_XRGB16_1555:
 890                         m = 0xf; break;
 891                 default:
 892                         BUG(); return;
 893                 }
 894         } else {
 895                 switch (color_mode) {
 896                 case OMAP_DSS_COLOR_CLUT1:
 897                         m = 0x0; break;
 898                 case OMAP_DSS_COLOR_CLUT2:
 899                         m = 0x1; break;
 900                 case OMAP_DSS_COLOR_CLUT4:
 901                         m = 0x2; break;
 902                 case OMAP_DSS_COLOR_CLUT8:
 903                         m = 0x3; break;
 904                 case OMAP_DSS_COLOR_RGB12U:
 905                         m = 0x4; break;
 906                 case OMAP_DSS_COLOR_ARGB16:
 907                         m = 0x5; break;
 908                 case OMAP_DSS_COLOR_RGB16:
 909                         m = 0x6; break;
 910                 case OMAP_DSS_COLOR_ARGB16_1555:
 911                         m = 0x7; break;
 912                 case OMAP_DSS_COLOR_RGB24U:
 913                         m = 0x8; break;
 914                 case OMAP_DSS_COLOR_RGB24P:
 915                         m = 0x9; break;
 916                 case OMAP_DSS_COLOR_RGBX16:
 917                         m = 0xa; break;
 918                 case OMAP_DSS_COLOR_RGBA16:
 919                         m = 0xb; break;
 920                 case OMAP_DSS_COLOR_ARGB32:
 921                         m = 0xc; break;
 922                 case OMAP_DSS_COLOR_RGBA32:
 923                         m = 0xd; break;
 924                 case OMAP_DSS_COLOR_RGBX32:
 925                         m = 0xe; break;
 926                 case OMAP_DSS_COLOR_XRGB16_1555:
 927                         m = 0xf; break;
 928                 default:
 929                         BUG(); return;
 930                 }
 931         }
 932
 933         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 934 }
 935
 936 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 937                 enum omap_dss_rotation_type rotation_type)
 938 {
 939         if (dss_has_feature(FEAT_BURST_2D) == 0)
 940                 return;
 941
 942         if (rotation_type == OMAP_DSS_ROT_TILER)
 943                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 944         else
 945                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 946 }
 947
 948 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 949 {
 950         int shift;
 951         u32 val;
 952         int chan = 0, chan2 = 0;
 953
 954         switch (plane) {
 955         case OMAP_DSS_GFX:
 956                 shift = 8;
 957                 break;
 958         case OMAP_DSS_VIDEO1:
 959         case OMAP_DSS_VIDEO2:
 960         case OMAP_DSS_VIDEO3:
 961                 shift = 16;
 962                 break;
 963         default:
 964                 BUG();
 965                 return;
 966         }
 967
 968         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 969         if (dss_has_feature(FEAT_MGR_LCD2)) {
 970                 switch (channel) {
 971                 case OMAP_DSS_CHANNEL_LCD:
 972                         chan = 0;
 973                         chan2 = 0;
 974                         break;
 975                 case OMAP_DSS_CHANNEL_DIGIT:
 976                         chan = 1;
 977                         chan2 = 0;
 978                         break;
 979                 case OMAP_DSS_CHANNEL_LCD2:
 980                         chan = 0;
 981                         chan2 = 1;
 982                         break;
 983                 case OMAP_DSS_CHANNEL_LCD3:
 984                         if (dss_has_feature(FEAT_MGR_LCD3)) {
 985                                 chan = 0;
 986                                 chan2 = 2;
 987                         } else {
 988                                 BUG();
 989                                 return;
 990                         }
 991                         break;
 992                 case OMAP_DSS_CHANNEL_WB:
 993                         chan = 0;
 994                         chan2 = 3;
 995                         break;
 996                 default:
 997                         BUG();
 998                         return;
 999                 }
1000
1001                 val = FLD_MOD(val, chan, shift, shift);
1002                 val = FLD_MOD(val, chan2, 31, 30);
1003         } else {
1004                 val = FLD_MOD(val, channel, shift, shift);
1005         }
1006         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1007 }
1008 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1009
1010 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1011 {
1012         int shift;
1013         u32 val;
1014
1015         switch (plane) {
1016         case OMAP_DSS_GFX:
1017                 shift = 8;
1018                 break;
1019         case OMAP_DSS_VIDEO1:
1020         case OMAP_DSS_VIDEO2:
1021         case OMAP_DSS_VIDEO3:
1022                 shift = 16;
1023                 break;
1024         default:
1025                 BUG();
1026                 return 0;
1027         }
1028
1029         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1030
1031         if (FLD_GET(val, shift, shift) == 1)
1032                 return OMAP_DSS_CHANNEL_DIGIT;
1033
1034         if (!dss_has_feature(FEAT_MGR_LCD2))
1035                 return OMAP_DSS_CHANNEL_LCD;
1036
1037         switch (FLD_GET(val, 31, 30)) {
1038         case 0:
1039         default:
1040                 return OMAP_DSS_CHANNEL_LCD;
1041         case 1:
1042                 return OMAP_DSS_CHANNEL_LCD2;
1043         case 2:
1044                 return OMAP_DSS_CHANNEL_LCD3;
1045         case 3:
1046                 return OMAP_DSS_CHANNEL_WB;
1047         }
1048 }
1049
1050 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1051 {
1052         enum omap_plane plane = OMAP_DSS_WB;
1053
1054         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1055 }
1056
1057 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1058                 enum omap_burst_size burst_size)
1059 {
1060         static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1061         int shift;
1062
1063         shift = shifts[plane];
1064         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1065 }
1066
1067 static void dispc_configure_burst_sizes(void)
1068 {
1069         int i;
1070         const int burst_size = BURST_SIZE_X8;
1071
1072         /* Configure burst size always to maximum size */
1073         for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1074                 dispc_ovl_set_burst_size(i, burst_size);
1075         if (dispc.feat->has_writeback)
1076                 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1077 }
1078
1079 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1080 {
1081         unsigned unit = dss_feat_get_burst_size_unit();
1082         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1083         return unit * 8;
1084 }
1085
1086 void dispc_enable_gamma_table(bool enable)
1087 {
1088         /*
1089          * This is partially implemented to support only disabling of
1090          * the gamma table.
1091          */
1092         if (enable) {
1093                 DSSWARN("Gamma table enabling for TV not yet supported");
1094                 return;
1095         }
1096
1097         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1098 }
1099
1100 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1101 {
1102         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1103                 return;
1104
1105         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1106 }
1107
1108 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1109                 const struct omap_dss_cpr_coefs *coefs)
1110 {
1111         u32 coef_r, coef_g, coef_b;
1112
1113         if (!dss_mgr_is_lcd(channel))
1114                 return;
1115
1116         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1117                 FLD_VAL(coefs->rb, 9, 0);
1118         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1119                 FLD_VAL(coefs->gb, 9, 0);
1120         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1121                 FLD_VAL(coefs->bb, 9, 0);
1122
1123         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1124         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1125         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1126 }
1127
1128 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1129 {
1130         u32 val;
1131
1132         BUG_ON(plane == OMAP_DSS_GFX);
1133
1134         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1135         val = FLD_MOD(val, enable, 9, 9);
1136         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1137 }
1138
1139 static void dispc_ovl_enable_replication(enum omap_plane plane,
1140                 enum omap_overlay_caps caps, bool enable)
1141 {
1142         static const unsigned shifts[] = { 5, 10, 10, 10 };
1143         int shift;
1144
1145         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1146                 return;
1147
1148         shift = shifts[plane];
1149         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1150 }
1151
1152 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1153                 u16 height)
1154 {
1155         u32 val;
1156
1157         val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1158                 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1159
1160         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1161 }
1162
1163 static void dispc_init_fifos(void)
1164 {
1165         u32 size;
1166         int fifo;
1167         u8 start, end;
1168         u32 unit;
1169         int i;
1170
1171         unit = dss_feat_get_buffer_size_unit();
1172
1173         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1174
1175         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1176                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1177                 size *= unit;
1178                 dispc.fifo_size[fifo] = size;
1179
1180                 /*
1181                  * By default fifos are mapped directly to overlays, fifo 0 to
1182                  * ovl 0, fifo 1 to ovl 1, etc.
1183                  */
1184                 dispc.fifo_assignment[fifo] = fifo;
1185         }
1186
1187         /*
1188          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1189          * causes problems with certain use cases, like using the tiler in 2D
1190          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1191          * giving GFX plane a larger fifo. WB but should work fine with a
1192          * smaller fifo.
1193          */
1194         if (dispc.feat->gfx_fifo_workaround) {
1195                 u32 v;
1196
1197                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1198
1199                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1200                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1201                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1202                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1203
1204                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1205
1206                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1207                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1208         }
1209
1210         /*
1211          * Setup default fifo thresholds.
1212          */
1213         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1214                 u32 low, high;
1215                 const bool use_fifomerge = false;
1216                 const bool manual_update = false;
1217
1218                 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1219                         use_fifomerge, manual_update);
1220
1221                 dispc_ovl_set_fifo_threshold(i, low, high);
1222         }
1223
1224         if (dispc.feat->has_writeback) {
1225                 u32 low, high;
1226                 const bool use_fifomerge = false;
1227                 const bool manual_update = false;
1228
1229                 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1230                         use_fifomerge, manual_update);
1231
1232                 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1233         }
1234 }
1235
1236 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1237 {
1238         int fifo;
1239         u32 size = 0;
1240
1241         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1242                 if (dispc.fifo_assignment[fifo] == plane)
1243                         size += dispc.fifo_size[fifo];
1244         }
1245
1246         return size;
1247 }
1248
1249 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1250 {
1251         u8 hi_start, hi_end, lo_start, lo_end;
1252         u32 unit;
1253
1254         unit = dss_feat_get_buffer_size_unit();
1255
1256         WARN_ON(low % unit != 0);
1257         WARN_ON(high % unit != 0);
1258
1259         low /= unit;
1260         high /= unit;
1261
1262         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1263         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1264
1265         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1266                         plane,
1267                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1268                                 lo_start, lo_end) * unit,
1269                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1270                                 hi_start, hi_end) * unit,
1271                         low * unit, high * unit);
1272
1273         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1274                         FLD_VAL(high, hi_start, hi_end) |
1275                         FLD_VAL(low, lo_start, lo_end));
1276
1277         /*
1278          * configure the preload to the pipeline's high threhold, if HT it's too
1279          * large for the preload field, set the threshold to the maximum value
1280          * that can be held by the preload register
1281          */
1282         if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1283                         plane != OMAP_DSS_WB)
1284                 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1285 }
1286
1287 void dispc_enable_fifomerge(bool enable)
1288 {
1289         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1290                 WARN_ON(enable);
1291                 return;
1292         }
1293
1294         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1295         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1296 }
1297
1298 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1299                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1300                 bool manual_update)
1301 {
1302         /*
1303          * All sizes are in bytes. Both the buffer and burst are made of
1304          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1305          */
1306
1307         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1308         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1309         int i;
1310
1311         burst_size = dispc_ovl_get_burst_size(plane);
1312         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1313
1314         if (use_fifomerge) {
1315                 total_fifo_size = 0;
1316                 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1317                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1318         } else {
1319                 total_fifo_size = ovl_fifo_size;
1320         }
1321
1322         /*
1323          * We use the same low threshold for both fifomerge and non-fifomerge
1324          * cases, but for fifomerge we calculate the high threshold using the
1325          * combined fifo size
1326          */
1327
1328         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1329                 *fifo_low = ovl_fifo_size - burst_size * 2;
1330                 *fifo_high = total_fifo_size - burst_size;
1331         } else if (plane == OMAP_DSS_WB) {
1332                 /*
1333                  * Most optimal configuration for writeback is to push out data
1334                  * to the interconnect the moment writeback pushes enough pixels
1335                  * in the FIFO to form a burst
1336                  */
1337                 *fifo_low = 0;
1338                 *fifo_high = burst_size;
1339         } else {
1340                 *fifo_low = ovl_fifo_size - burst_size;
1341                 *fifo_high = total_fifo_size - buf_unit;
1342         }
1343 }
1344
1345 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1346 {
1347         int bit;
1348
1349         if (plane == OMAP_DSS_GFX)
1350                 bit = 14;
1351         else
1352                 bit = 23;
1353
1354         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1355 }
1356
1357 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1358         int low, int high)
1359 {
1360         dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1361                 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1362 }
1363
1364 static void dispc_init_mflag(void)
1365 {
1366         int i;
1367
1368         /*
1369          * HACK: NV12 color format and MFLAG seem to have problems working
1370          * together: using two displays, and having an NV12 overlay on one of
1371          * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1372          * Changing MFLAG thresholds and PRELOAD to certain values seem to
1373          * remove the errors, but there doesn't seem to be a clear logic on
1374          * which values work and which not.
1375          *
1376          * As a work-around, set force MFLAG to always on.
1377          */
1378         dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1379                 (1 << 0) |      /* MFLAG_CTRL = force always on */
1380                 (0 << 2));      /* MFLAG_START = disable */
1381
1382         for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1383                 u32 size = dispc_ovl_get_fifo_size(i);
1384                 u32 unit = dss_feat_get_buffer_size_unit();
1385                 u32 low, high;
1386
1387                 dispc_ovl_set_mflag(i, true);
1388
1389                 /*
1390                  * Simulation team suggests below thesholds:
1391                  * HT = fifosize * 5 / 8;
1392                  * LT = fifosize * 4 / 8;
1393                  */
1394
1395                 low = size * 4 / 8 / unit;
1396                 high = size * 5 / 8 / unit;
1397
1398                 dispc_ovl_set_mflag_threshold(i, low, high);
1399         }
1400
1401         if (dispc.feat->has_writeback) {
1402                 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1403                 u32 unit = dss_feat_get_buffer_size_unit();
1404                 u32 low, high;
1405
1406                 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1407
1408                 /*
1409                  * Simulation team suggests below thesholds:
1410                  * HT = fifosize * 5 / 8;
1411                  * LT = fifosize * 4 / 8;
1412                  */
1413
1414                 low = size * 4 / 8 / unit;
1415                 high = size * 5 / 8 / unit;
1416
1417                 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1418         }
1419 }
1420
1421 static void dispc_ovl_set_fir(enum omap_plane plane,
1422                                 int hinc, int vinc,
1423                                 enum omap_color_component color_comp)
1424 {
1425         u32 val;
1426
1427         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1428                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1429
1430                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1431                                         &hinc_start, &hinc_end);
1432                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1433                                         &vinc_start, &vinc_end);
1434                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1435                                 FLD_VAL(hinc, hinc_start, hinc_end);
1436
1437                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1438         } else {
1439                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1440                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1441         }
1442 }
1443
1444 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1445 {
1446         u32 val;
1447         u8 hor_start, hor_end, vert_start, vert_end;
1448
1449         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1450         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1451
1452         val = FLD_VAL(vaccu, vert_start, vert_end) |
1453                         FLD_VAL(haccu, hor_start, hor_end);
1454
1455         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1456 }
1457
1458 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1459 {
1460         u32 val;
1461         u8 hor_start, hor_end, vert_start, vert_end;
1462
1463         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1464         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1465
1466         val = FLD_VAL(vaccu, vert_start, vert_end) |
1467                         FLD_VAL(haccu, hor_start, hor_end);
1468
1469         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1470 }
1471
1472 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1473                 int vaccu)
1474 {
1475         u32 val;
1476
1477         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1478         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1479 }
1480
1481 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1482                 int vaccu)
1483 {
1484         u32 val;
1485
1486         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1487         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1488 }
1489
1490 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1491                 u16 orig_width, u16 orig_height,
1492                 u16 out_width, u16 out_height,
1493                 bool five_taps, u8 rotation,
1494                 enum omap_color_component color_comp)
1495 {
1496         int fir_hinc, fir_vinc;
1497
1498         fir_hinc = 1024 * orig_width / out_width;
1499         fir_vinc = 1024 * orig_height / out_height;
1500
1501         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1502                                 color_comp);
1503         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1504 }
1505
1506 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1507                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1508                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1509 {
1510         int h_accu2_0, h_accu2_1;
1511         int v_accu2_0, v_accu2_1;
1512         int chroma_hinc, chroma_vinc;
1513         int idx;
1514
1515         struct accu {
1516                 s8 h0_m, h0_n;
1517                 s8 h1_m, h1_n;
1518                 s8 v0_m, v0_n;
1519                 s8 v1_m, v1_n;
1520         };
1521
1522         const struct accu *accu_table;
1523         const struct accu *accu_val;
1524
1525         static const struct accu accu_nv12[4] = {
1526                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1527                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1528                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1529                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1530         };
1531
1532         static const struct accu accu_nv12_ilace[4] = {
1533                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1534                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1535                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1536                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1537         };
1538
1539         static const struct accu accu_yuv[4] = {
1540                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1541                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1542                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1543                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1544         };
1545
1546         switch (rotation) {
1547         case OMAP_DSS_ROT_0:
1548                 idx = 0;
1549                 break;
1550         case OMAP_DSS_ROT_90:
1551                 idx = 1;
1552                 break;
1553         case OMAP_DSS_ROT_180:
1554                 idx = 2;
1555                 break;
1556         case OMAP_DSS_ROT_270:
1557                 idx = 3;
1558                 break;
1559         default:
1560                 BUG();
1561                 return;
1562         }
1563
1564         switch (color_mode) {
1565         case OMAP_DSS_COLOR_NV12:
1566                 if (ilace)
1567                         accu_table = accu_nv12_ilace;
1568                 else
1569                         accu_table = accu_nv12;
1570                 break;
1571         case OMAP_DSS_COLOR_YUV2:
1572         case OMAP_DSS_COLOR_UYVY:
1573                 accu_table = accu_yuv;
1574                 break;
1575         default:
1576                 BUG();
1577                 return;
1578         }
1579
1580         accu_val = &accu_table[idx];
1581
1582         chroma_hinc = 1024 * orig_width / out_width;
1583         chroma_vinc = 1024 * orig_height / out_height;
1584
1585         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1586         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1587         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1588         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1589
1590         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1591         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1592 }
1593
1594 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1595                 u16 orig_width, u16 orig_height,
1596                 u16 out_width, u16 out_height,
1597                 bool ilace, bool five_taps,
1598                 bool fieldmode, enum omap_color_mode color_mode,
1599                 u8 rotation)
1600 {
1601         int accu0 = 0;
1602         int accu1 = 0;
1603         u32 l;
1604
1605         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1606                                 out_width, out_height, five_taps,
1607                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1608         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1609
1610         /* RESIZEENABLE and VERTICALTAPS */
1611         l &= ~((0x3 << 5) | (0x1 << 21));
1612         l |= (orig_width != out_width) ? (1 << 5) : 0;
1613         l |= (orig_height != out_height) ? (1 << 6) : 0;
1614         l |= five_taps ? (1 << 21) : 0;
1615
1616         /* VRESIZECONF and HRESIZECONF */
1617         if (dss_has_feature(FEAT_RESIZECONF)) {
1618                 l &= ~(0x3 << 7);
1619                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1620                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1621         }
1622
1623         /* LINEBUFFERSPLIT */
1624         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1625                 l &= ~(0x1 << 22);
1626                 l |= five_taps ? (1 << 22) : 0;
1627         }
1628
1629         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1630
1631         /*
1632          * field 0 = even field = bottom field
1633          * field 1 = odd field = top field
1634          */
1635         if (ilace && !fieldmode) {
1636                 accu1 = 0;
1637                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1638                 if (accu0 >= 1024/2) {
1639                         accu1 = 1024/2;
1640                         accu0 -= accu1;
1641                 }
1642         }
1643
1644         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1645         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1646 }
1647
1648 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1649                 u16 orig_width, u16 orig_height,
1650                 u16 out_width, u16 out_height,
1651                 bool ilace, bool five_taps,
1652                 bool fieldmode, enum omap_color_mode color_mode,
1653                 u8 rotation)
1654 {
1655         int scale_x = out_width != orig_width;
1656         int scale_y = out_height != orig_height;
1657         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1658
1659         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1660                 return;
1661         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1662                         color_mode != OMAP_DSS_COLOR_UYVY &&
1663                         color_mode != OMAP_DSS_COLOR_NV12)) {
1664                 /* reset chroma resampling for RGB formats  */
1665                 if (plane != OMAP_DSS_WB)
1666                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1667                 return;
1668         }
1669
1670         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1671                         out_height, ilace, color_mode, rotation);
1672
1673         switch (color_mode) {
1674         case OMAP_DSS_COLOR_NV12:
1675                 if (chroma_upscale) {
1676                         /* UV is subsampled by 2 horizontally and vertically */
1677                         orig_height >>= 1;
1678                         orig_width >>= 1;
1679                 } else {
1680                         /* UV is downsampled by 2 horizontally and vertically */
1681                         orig_height <<= 1;
1682                         orig_width <<= 1;
1683                 }
1684
1685                 break;
1686         case OMAP_DSS_COLOR_YUV2:
1687         case OMAP_DSS_COLOR_UYVY:
1688                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1689                 if (rotation == OMAP_DSS_ROT_0 ||
1690                                 rotation == OMAP_DSS_ROT_180) {
1691                         if (chroma_upscale)
1692                                 /* UV is subsampled by 2 horizontally */
1693                                 orig_width >>= 1;
1694                         else
1695                                 /* UV is downsampled by 2 horizontally */
1696                                 orig_width <<= 1;
1697                 }
1698
1699                 /* must use FIR for YUV422 if rotated */
1700                 if (rotation != OMAP_DSS_ROT_0)
1701                         scale_x = scale_y = true;
1702
1703                 break;
1704         default:
1705                 BUG();
1706                 return;
1707         }
1708
1709         if (out_width != orig_width)
1710                 scale_x = true;
1711         if (out_height != orig_height)
1712                 scale_y = true;
1713
1714         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1715                         out_width, out_height, five_taps,
1716                                 rotation, DISPC_COLOR_COMPONENT_UV);
1717
1718         if (plane != OMAP_DSS_WB)
1719                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1720                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1721
1722         /* set H scaling */
1723         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1724         /* set V scaling */
1725         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1726 }
1727
1728 static void dispc_ovl_set_scaling(enum omap_plane plane,
1729                 u16 orig_width, u16 orig_height,
1730                 u16 out_width, u16 out_height,
1731                 bool ilace, bool five_taps,
1732                 bool fieldmode, enum omap_color_mode color_mode,
1733                 u8 rotation)
1734 {
1735         BUG_ON(plane == OMAP_DSS_GFX);
1736
1737         dispc_ovl_set_scaling_common(plane,
1738                         orig_width, orig_height,
1739                         out_width, out_height,
1740                         ilace, five_taps,
1741                         fieldmode, color_mode,
1742                         rotation);
1743
1744         dispc_ovl_set_scaling_uv(plane,
1745                 orig_width, orig_height,
1746                 out_width, out_height,
1747                 ilace, five_taps,
1748                 fieldmode, color_mode,
1749                 rotation);
1750 }
1751
1752 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1753                 enum omap_dss_rotation_type rotation_type,
1754                 bool mirroring, enum omap_color_mode color_mode)
1755 {
1756         bool row_repeat = false;
1757         int vidrot = 0;
1758
1759         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1760                         color_mode == OMAP_DSS_COLOR_UYVY) {
1761
1762                 if (mirroring) {
1763                         switch (rotation) {
1764                         case OMAP_DSS_ROT_0:
1765                                 vidrot = 2;
1766                                 break;
1767                         case OMAP_DSS_ROT_90:
1768                                 vidrot = 1;
1769                                 break;
1770                         case OMAP_DSS_ROT_180:
1771                                 vidrot = 0;
1772                                 break;
1773                         case OMAP_DSS_ROT_270:
1774                                 vidrot = 3;
1775                                 break;
1776                         }
1777                 } else {
1778                         switch (rotation) {
1779                         case OMAP_DSS_ROT_0:
1780                                 vidrot = 0;
1781                                 break;
1782                         case OMAP_DSS_ROT_90:
1783                                 vidrot = 1;
1784                                 break;
1785                         case OMAP_DSS_ROT_180:
1786                                 vidrot = 2;
1787                                 break;
1788                         case OMAP_DSS_ROT_270:
1789                                 vidrot = 3;
1790                                 break;
1791                         }
1792                 }
1793
1794                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1795                         row_repeat = true;
1796                 else
1797                         row_repeat = false;
1798         }
1799
1800         /*
1801          * OMAP4/5 Errata i631:
1802          * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1803          * rows beyond the framebuffer, which may cause OCP error.
1804          */
1805         if (color_mode == OMAP_DSS_COLOR_NV12 &&
1806                         rotation_type != OMAP_DSS_ROT_TILER)
1807                 vidrot = 1;
1808
1809         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1810         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1811                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1812                         row_repeat ? 1 : 0, 18, 18);
1813
1814         if (color_mode == OMAP_DSS_COLOR_NV12) {
1815                 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1816                                         (rotation == OMAP_DSS_ROT_0 ||
1817                                         rotation == OMAP_DSS_ROT_180);
1818                 /* DOUBLESTRIDE */
1819                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1820         }
1821
1822 }
1823
1824 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1825 {
1826         switch (color_mode) {
1827         case OMAP_DSS_COLOR_CLUT1:
1828                 return 1;
1829         case OMAP_DSS_COLOR_CLUT2:
1830                 return 2;
1831         case OMAP_DSS_COLOR_CLUT4:
1832                 return 4;
1833         case OMAP_DSS_COLOR_CLUT8:
1834         case OMAP_DSS_COLOR_NV12:
1835                 return 8;
1836         case OMAP_DSS_COLOR_RGB12U:
1837         case OMAP_DSS_COLOR_RGB16:
1838         case OMAP_DSS_COLOR_ARGB16:
1839         case OMAP_DSS_COLOR_YUV2:
1840         case OMAP_DSS_COLOR_UYVY:
1841         case OMAP_DSS_COLOR_RGBA16:
1842         case OMAP_DSS_COLOR_RGBX16:
1843         case OMAP_DSS_COLOR_ARGB16_1555:
1844         case OMAP_DSS_COLOR_XRGB16_1555:
1845                 return 16;
1846         case OMAP_DSS_COLOR_RGB24P:
1847                 return 24;
1848         case OMAP_DSS_COLOR_RGB24U:
1849         case OMAP_DSS_COLOR_ARGB32:
1850         case OMAP_DSS_COLOR_RGBA32:
1851         case OMAP_DSS_COLOR_RGBX32:
1852                 return 32;
1853         default:
1854                 BUG();
1855                 return 0;
1856         }
1857 }
1858
1859 static s32 pixinc(int pixels, u8 ps)
1860 {
1861         if (pixels == 1)
1862                 return 1;
1863         else if (pixels > 1)
1864                 return 1 + (pixels - 1) * ps;
1865         else if (pixels < 0)
1866                 return 1 - (-pixels + 1) * ps;
1867         else
1868                 BUG();
1869                 return 0;
1870 }
1871
1872 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1873                 u16 screen_width,
1874                 u16 width, u16 height,
1875                 enum omap_color_mode color_mode, bool fieldmode,
1876                 unsigned int field_offset,
1877                 unsigned *offset0, unsigned *offset1,
1878                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1879 {
1880         u8 ps;
1881
1882         /* FIXME CLUT formats */
1883         switch (color_mode) {
1884         case OMAP_DSS_COLOR_CLUT1:
1885         case OMAP_DSS_COLOR_CLUT2:
1886         case OMAP_DSS_COLOR_CLUT4:
1887         case OMAP_DSS_COLOR_CLUT8:
1888                 BUG();
1889                 return;
1890         case OMAP_DSS_COLOR_YUV2:
1891         case OMAP_DSS_COLOR_UYVY:
1892                 ps = 4;
1893                 break;
1894         default:
1895                 ps = color_mode_to_bpp(color_mode) / 8;
1896                 break;
1897         }
1898
1899         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1900                         width, height);
1901
1902         /*
1903          * field 0 = even field = bottom field
1904          * field 1 = odd field = top field
1905          */
1906         switch (rotation + mirror * 4) {
1907         case OMAP_DSS_ROT_0:
1908         case OMAP_DSS_ROT_180:
1909                 /*
1910                  * If the pixel format is YUV or UYVY divide the width
1911                  * of the image by 2 for 0 and 180 degree rotation.
1912                  */
1913                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1914                         color_mode == OMAP_DSS_COLOR_UYVY)
1915                         width = width >> 1;
1916         case OMAP_DSS_ROT_90:
1917         case OMAP_DSS_ROT_270:
1918                 *offset1 = 0;
1919                 if (field_offset)
1920                         *offset0 = field_offset * screen_width * ps;
1921                 else
1922                         *offset0 = 0;
1923
1924                 *row_inc = pixinc(1 +
1925                         (y_predecim * screen_width - x_predecim * width) +
1926                         (fieldmode ? screen_width : 0), ps);
1927                 *pix_inc = pixinc(x_predecim, ps);
1928                 break;
1929
1930         case OMAP_DSS_ROT_0 + 4:
1931         case OMAP_DSS_ROT_180 + 4:
1932                 /* If the pixel format is YUV or UYVY divide the width
1933                  * of the image by 2  for 0 degree and 180 degree
1934                  */
1935                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1936                         color_mode == OMAP_DSS_COLOR_UYVY)
1937                         width = width >> 1;
1938         case OMAP_DSS_ROT_90 + 4:
1939         case OMAP_DSS_ROT_270 + 4:
1940                 *offset1 = 0;
1941                 if (field_offset)
1942                         *offset0 = field_offset * screen_width * ps;
1943                 else
1944                         *offset0 = 0;
1945                 *row_inc = pixinc(1 -
1946                         (y_predecim * screen_width + x_predecim * width) -
1947                         (fieldmode ? screen_width : 0), ps);
1948                 *pix_inc = pixinc(x_predecim, ps);
1949                 break;
1950
1951         default:
1952                 BUG();
1953                 return;
1954         }
1955 }
1956
1957 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1958                 u16 screen_width,
1959                 u16 width, u16 height,
1960                 enum omap_color_mode color_mode, bool fieldmode,
1961                 unsigned int field_offset,
1962                 unsigned *offset0, unsigned *offset1,
1963                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1964 {
1965         u8 ps;
1966         u16 fbw, fbh;
1967
1968         /* FIXME CLUT formats */
1969         switch (color_mode) {
1970         case OMAP_DSS_COLOR_CLUT1:
1971         case OMAP_DSS_COLOR_CLUT2:
1972         case OMAP_DSS_COLOR_CLUT4:
1973         case OMAP_DSS_COLOR_CLUT8:
1974                 BUG();
1975                 return;
1976         default:
1977                 ps = color_mode_to_bpp(color_mode) / 8;
1978                 break;
1979         }
1980
1981         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1982                         width, height);
1983
1984         /* width & height are overlay sizes, convert to fb sizes */
1985
1986         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1987                 fbw = width;
1988                 fbh = height;
1989         } else {
1990                 fbw = height;
1991                 fbh = width;
1992         }
1993
1994         /*
1995          * field 0 = even field = bottom field
1996          * field 1 = odd field = top field
1997          */
1998         switch (rotation + mirror * 4) {
1999         case OMAP_DSS_ROT_0:
2000                 *offset1 = 0;
2001                 if (field_offset)
2002                         *offset0 = *offset1 + field_offset * screen_width * ps;
2003                 else
2004                         *offset0 = *offset1;
2005                 *row_inc = pixinc(1 +
2006                         (y_predecim * screen_width - fbw * x_predecim) +
2007                         (fieldmode ? screen_width : 0), ps);
2008                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2009                         color_mode == OMAP_DSS_COLOR_UYVY)
2010                         *pix_inc = pixinc(x_predecim, 2 * ps);
2011                 else
2012                         *pix_inc = pixinc(x_predecim, ps);
2013                 break;
2014         case OMAP_DSS_ROT_90:
2015                 *offset1 = screen_width * (fbh - 1) * ps;
2016                 if (field_offset)
2017                         *offset0 = *offset1 + field_offset * ps;
2018                 else
2019                         *offset0 = *offset1;
2020                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2021                                 y_predecim + (fieldmode ? 1 : 0), ps);
2022                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2023                 break;
2024         case OMAP_DSS_ROT_180:
2025                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2026                 if (field_offset)
2027                         *offset0 = *offset1 - field_offset * screen_width * ps;
2028                 else
2029                         *offset0 = *offset1;
2030                 *row_inc = pixinc(-1 -
2031                         (y_predecim * screen_width - fbw * x_predecim) -
2032                         (fieldmode ? screen_width : 0), ps);
2033                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2034                         color_mode == OMAP_DSS_COLOR_UYVY)
2035                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2036                 else
2037                         *pix_inc = pixinc(-x_predecim, ps);
2038                 break;
2039         case OMAP_DSS_ROT_270:
2040                 *offset1 = (fbw - 1) * ps;
2041                 if (field_offset)
2042                         *offset0 = *offset1 - field_offset * ps;
2043                 else
2044                         *offset0 = *offset1;
2045                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2046                                 y_predecim - (fieldmode ? 1 : 0), ps);
2047                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2048                 break;
2049
2050         /* mirroring */
2051         case OMAP_DSS_ROT_0 + 4:
2052                 *offset1 = (fbw - 1) * ps;
2053                 if (field_offset)
2054                         *offset0 = *offset1 + field_offset * screen_width * ps;
2055                 else
2056                         *offset0 = *offset1;
2057                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2058                                 (fieldmode ? screen_width : 0),
2059                                 ps);
2060                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2061                         color_mode == OMAP_DSS_COLOR_UYVY)
2062                         *pix_inc = pixinc(-x_predecim, 2 * ps);
2063                 else
2064                         *pix_inc = pixinc(-x_predecim, ps);
2065                 break;
2066
2067         case OMAP_DSS_ROT_90 + 4:
2068                 *offset1 = 0;
2069                 if (field_offset)
2070                         *offset0 = *offset1 + field_offset * ps;
2071                 else
2072                         *offset0 = *offset1;
2073                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2074                                 y_predecim + (fieldmode ? 1 : 0),
2075                                 ps);
2076                 *pix_inc = pixinc(x_predecim * screen_width, ps);
2077                 break;
2078
2079         case OMAP_DSS_ROT_180 + 4:
2080                 *offset1 = screen_width * (fbh - 1) * ps;
2081                 if (field_offset)
2082                         *offset0 = *offset1 - field_offset * screen_width * ps;
2083                 else
2084                         *offset0 = *offset1;
2085                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2086                                 (fieldmode ? screen_width : 0),
2087                                 ps);
2088                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2089                         color_mode == OMAP_DSS_COLOR_UYVY)
2090                         *pix_inc = pixinc(x_predecim, 2 * ps);
2091                 else
2092                         *pix_inc = pixinc(x_predecim, ps);
2093                 break;
2094
2095         case OMAP_DSS_ROT_270 + 4:
2096                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2097                 if (field_offset)
2098                         *offset0 = *offset1 - field_offset * ps;
2099                 else
2100                         *offset0 = *offset1;
2101                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2102                                 y_predecim - (fieldmode ? 1 : 0),
2103                                 ps);
2104                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2105                 break;
2106
2107         default:
2108                 BUG();
2109                 return;
2110         }
2111 }
2112
2113 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2114                 enum omap_color_mode color_mode, bool fieldmode,
2115                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2116                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2117 {
2118         u8 ps;
2119
2120         switch (color_mode) {
2121         case OMAP_DSS_COLOR_CLUT1:
2122         case OMAP_DSS_COLOR_CLUT2:
2123         case OMAP_DSS_COLOR_CLUT4:
2124         case OMAP_DSS_COLOR_CLUT8:
2125                 BUG();
2126                 return;
2127         default:
2128                 ps = color_mode_to_bpp(color_mode) / 8;
2129                 break;
2130         }
2131
2132         DSSDBG("scrw %d, width %d\n", screen_width, width);
2133
2134         /*
2135          * field 0 = even field = bottom field
2136          * field 1 = odd field = top field
2137          */
2138         *offset1 = 0;
2139         if (field_offset)
2140                 *offset0 = *offset1 + field_offset * screen_width * ps;
2141         else
2142                 *offset0 = *offset1;
2143         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2144                         (fieldmode ? screen_width : 0), ps);
2145         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2146                 color_mode == OMAP_DSS_COLOR_UYVY)
2147                 *pix_inc = pixinc(x_predecim, 2 * ps);
2148         else
2149                 *pix_inc = pixinc(x_predecim, ps);
2150 }
2151
2152 /*
2153  * This function is used to avoid synclosts in OMAP3, because of some
2154  * undocumented horizontal position and timing related limitations.
2155  */
2156 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2157                 const struct omap_video_timings *t, u16 pos_x,
2158                 u16 width, u16 height, u16 out_width, u16 out_height,
2159                 bool five_taps)
2160 {
2161         const int ds = DIV_ROUND_UP(height, out_height);
2162         unsigned long nonactive;
2163         static const u8 limits[3] = { 8, 10, 20 };
2164         u64 val, blank;
2165         int i;
2166
2167         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2168
2169         i = 0;
2170         if (out_height < height)
2171                 i++;
2172         if (out_width < width)
2173                 i++;
2174         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2175         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2176         if (blank <= limits[i])
2177                 return -EINVAL;
2178
2179         /* FIXME add checks for 3-tap filter once the limitations are known */
2180         if (!five_taps)
2181                 return 0;
2182
2183         /*
2184          * Pixel data should be prepared before visible display point starts.
2185          * So, atleast DS-2 lines must have already been fetched by DISPC
2186          * during nonactive - pos_x period.
2187          */
2188         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2189         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2190                 val, max(0, ds - 2) * width);
2191         if (val < max(0, ds - 2) * width)
2192                 return -EINVAL;
2193
2194         /*
2195          * All lines need to be refilled during the nonactive period of which
2196          * only one line can be loaded during the active period. So, atleast
2197          * DS - 1 lines should be loaded during nonactive period.
2198          */
2199         val =  div_u64((u64)nonactive * lclk, pclk);
2200         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2201                 val, max(0, ds - 1) * width);
2202         if (val < max(0, ds - 1) * width)
2203                 return -EINVAL;
2204
2205         return 0;
2206 }
2207
2208 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2209                 const struct omap_video_timings *mgr_timings, u16 width,
2210                 u16 height, u16 out_width, u16 out_height,
2211                 enum omap_color_mode color_mode)
2212 {
2213         u32 core_clk = 0;
2214         u64 tmp;
2215
2216         if (height <= out_height && width <= out_width)
2217                 return (unsigned long) pclk;
2218
2219         if (height > out_height) {
2220                 unsigned int ppl = mgr_timings->x_res;
2221
2222                 tmp = (u64)pclk * height * out_width;
2223                 do_div(tmp, 2 * out_height * ppl);
2224                 core_clk = tmp;
2225
2226                 if (height > 2 * out_height) {
2227                         if (ppl == out_width)
2228                                 return 0;
2229
2230                         tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2231                         do_div(tmp, 2 * out_height * (ppl - out_width));
2232                         core_clk = max_t(u32, core_clk, tmp);
2233                 }
2234         }
2235
2236         if (width > out_width) {
2237                 tmp = (u64)pclk * width;
2238                 do_div(tmp, out_width);
2239                 core_clk = max_t(u32, core_clk, tmp);
2240
2241                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2242                         core_clk <<= 1;
2243         }
2244
2245         return core_clk;
2246 }
2247
2248 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2249                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2250 {
2251         if (height > out_height && width > out_width)
2252                 return pclk * 4;
2253         else
2254                 return pclk * 2;
2255 }
2256
2257 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2258                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2259 {
2260         unsigned int hf, vf;
2261
2262         /*
2263          * FIXME how to determine the 'A' factor
2264          * for the no downscaling case ?
2265          */
2266
2267         if (width > 3 * out_width)
2268                 hf = 4;
2269         else if (width > 2 * out_width)
2270                 hf = 3;
2271         else if (width > out_width)
2272                 hf = 2;
2273         else
2274                 hf = 1;
2275         if (height > out_height)
2276                 vf = 2;
2277         else
2278                 vf = 1;
2279
2280         return pclk * vf * hf;
2281 }
2282
2283 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2284                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2285 {
2286         /*
2287          * If the overlay/writeback is in mem to mem mode, there are no
2288          * downscaling limitations with respect to pixel clock, return 1 as
2289          * required core clock to represent that we have sufficient enough
2290          * core clock to do maximum downscaling
2291          */
2292         if (mem_to_mem)
2293                 return 1;
2294
2295         if (width > out_width)
2296                 return DIV_ROUND_UP(pclk, out_width) * width;
2297         else
2298                 return pclk;
2299 }
2300
2301 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2302                 const struct omap_video_timings *mgr_timings,
2303                 u16 width, u16 height, u16 out_width, u16 out_height,
2304                 enum omap_color_mode color_mode, bool *five_taps,
2305                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2306                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2307 {
2308         int error;
2309         u16 in_width, in_height;
2310         int min_factor = min(*decim_x, *decim_y);
2311         const int maxsinglelinewidth =
2312                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2313
2314         *five_taps = false;
2315
2316         do {
2317                 in_height = height / *decim_y;
2318                 in_width = width / *decim_x;
2319                 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2320                                 in_height, out_width, out_height, mem_to_mem);
2321                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2322                         *core_clk > dispc_core_clk_rate());
2323                 if (error) {
2324                         if (*decim_x == *decim_y) {
2325                                 *decim_x = min_factor;
2326                                 ++*decim_y;
2327                         } else {
2328                                 swap(*decim_x, *decim_y);
2329                                 if (*decim_x < *decim_y)
2330                                         ++*decim_x;
2331                         }
2332                 }
2333         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2334
2335         if (error) {
2336                 DSSERR("failed to find scaling settings\n");
2337                 return -EINVAL;
2338         }
2339
2340         if (in_width > maxsinglelinewidth) {
2341                 DSSERR("Cannot scale max input width exceeded");
2342                 return -EINVAL;
2343         }
2344         return 0;
2345 }
2346
2347 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2348                 const struct omap_video_timings *mgr_timings,
2349                 u16 width, u16 height, u16 out_width, u16 out_height,
2350                 enum omap_color_mode color_mode, bool *five_taps,
2351                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2352                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2353 {
2354         int error;
2355         u16 in_width, in_height;
2356         const int maxsinglelinewidth =
2357                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2358
2359         do {
2360                 in_height = height / *decim_y;
2361                 in_width = width / *decim_x;
2362                 *five_taps = in_height > out_height;
2363
2364                 if (in_width > maxsinglelinewidth)
2365                         if (in_height > out_height &&
2366                                                 in_height < out_height * 2)
2367                                 *five_taps = false;
2368 again:
2369                 if (*five_taps)
2370                         *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2371                                                 in_width, in_height, out_width,
2372                                                 out_height, color_mode);
2373                 else
2374                         *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2375                                         in_height, out_width, out_height,
2376                                         mem_to_mem);
2377
2378                 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2379                                 pos_x, in_width, in_height, out_width,
2380                                 out_height, *five_taps);
2381                 if (error && *five_taps) {
2382                         *five_taps = false;
2383                         goto again;
2384                 }
2385
2386                 error = (error || in_width > maxsinglelinewidth * 2 ||
2387                         (in_width > maxsinglelinewidth && *five_taps) ||
2388                         !*core_clk || *core_clk > dispc_core_clk_rate());
2389
2390                 if (!error) {
2391                         /* verify that we're inside the limits of scaler */
2392                         if (in_width / 4 > out_width)
2393                                         error = 1;
2394
2395                         if (*five_taps) {
2396                                 if (in_height / 4 > out_height)
2397                                         error = 1;
2398                         } else {
2399                                 if (in_height / 2 > out_height)
2400                                         error = 1;
2401                         }
2402                 }
2403
2404                 if (error)
2405                         ++*decim_y;
2406         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2407
2408         if (error) {
2409                 DSSERR("failed to find scaling settings\n");
2410                 return -EINVAL;
2411         }
2412
2413         if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2414                                 in_height, out_width, out_height, *five_taps)) {
2415                         DSSERR("horizontal timing too tight\n");
2416                         return -EINVAL;
2417         }
2418
2419         if (in_width > (maxsinglelinewidth * 2)) {
2420                 DSSERR("Cannot setup scaling");
2421                 DSSERR("width exceeds maximum width possible");
2422                 return -EINVAL;
2423         }
2424
2425         if (in_width > maxsinglelinewidth && *five_taps) {
2426                 DSSERR("cannot setup scaling with five taps");
2427                 return -EINVAL;
2428         }
2429         return 0;
2430 }
2431
2432 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2433                 const struct omap_video_timings *mgr_timings,
2434                 u16 width, u16 height, u16 out_width, u16 out_height,
2435                 enum omap_color_mode color_mode, bool *five_taps,
2436                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2437                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2438 {
2439         u16 in_width, in_width_max;
2440         int decim_x_min = *decim_x;
2441         u16 in_height = height / *decim_y;
2442         const int maxsinglelinewidth =
2443                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2444         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2445
2446         if (mem_to_mem) {
2447                 in_width_max = out_width * maxdownscale;
2448         } else {
2449                 in_width_max = dispc_core_clk_rate() /
2450                                         DIV_ROUND_UP(pclk, out_width);
2451         }
2452
2453         *decim_x = DIV_ROUND_UP(width, in_width_max);
2454
2455         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2456         if (*decim_x > *x_predecim)
2457                 return -EINVAL;
2458
2459         do {
2460                 in_width = width / *decim_x;
2461         } while (*decim_x <= *x_predecim &&
2462                         in_width > maxsinglelinewidth && ++*decim_x);
2463
2464         if (in_width > maxsinglelinewidth) {
2465                 DSSERR("Cannot scale width exceeds max line width");
2466                 return -EINVAL;
2467         }
2468
2469         *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2470                                 out_width, out_height, mem_to_mem);
2471         return 0;
2472 }
2473
2474 #define DIV_FRAC(dividend, divisor) \
2475         ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2476
2477 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2478                 enum omap_overlay_caps caps,
2479                 const struct omap_video_timings *mgr_timings,
2480                 u16 width, u16 height, u16 out_width, u16 out_height,
2481                 enum omap_color_mode color_mode, bool *five_taps,
2482                 int *x_predecim, int *y_predecim, u16 pos_x,
2483                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2484 {
2485         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2486         const int max_decim_limit = 16;
2487         unsigned long core_clk = 0;
2488         int decim_x, decim_y, ret;
2489
2490         if (width == out_width && height == out_height)
2491                 return 0;
2492
2493         if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2494                 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2495                 return -EINVAL;
2496         }
2497
2498         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2499                 return -EINVAL;
2500
2501         if (mem_to_mem) {
2502                 *x_predecim = *y_predecim = 1;
2503         } else {
2504                 *x_predecim = max_decim_limit;
2505                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2506                                 dss_has_feature(FEAT_BURST_2D)) ?
2507                                 2 : max_decim_limit;
2508         }
2509
2510         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2511             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2512             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2513             color_mode == OMAP_DSS_COLOR_CLUT8) {
2514                 *x_predecim = 1;
2515                 *y_predecim = 1;
2516                 *five_taps = false;
2517                 return 0;
2518         }
2519
2520         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2521         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2522
2523         if (decim_x > *x_predecim || out_width > width * 8)
2524                 return -EINVAL;
2525
2526         if (decim_y > *y_predecim || out_height > height * 8)
2527                 return -EINVAL;
2528
2529         ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2530                 out_width, out_height, color_mode, five_taps,
2531                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2532                 mem_to_mem);
2533         if (ret)
2534                 return ret;
2535
2536         DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2537                 width, height,
2538                 out_width, out_height,
2539                 out_width / width, DIV_FRAC(out_width, width),
2540                 out_height / height, DIV_FRAC(out_height, height),
2541
2542                 decim_x, decim_y,
2543                 width / decim_x, height / decim_y,
2544                 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2545                 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2546
2547                 *five_taps ? 5 : 3,
2548                 core_clk, dispc_core_clk_rate());
2549
2550         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2551                 DSSERR("failed to set up scaling, "
2552                         "required core clk rate = %lu Hz, "
2553                         "current core clk rate = %lu Hz\n",
2554                         core_clk, dispc_core_clk_rate());
2555                 return -EINVAL;
2556         }
2557
2558         *x_predecim = decim_x;
2559         *y_predecim = decim_y;
2560         return 0;
2561 }
2562
2563 static int dispc_ovl_setup_common(enum omap_plane plane,
2564                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2565                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2566                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2567                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2568                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2569                 bool replication, const struct omap_video_timings *mgr_timings,
2570                 bool mem_to_mem)
2571 {
2572         bool five_taps = true;
2573         bool fieldmode = false;
2574         int r, cconv = 0;
2575         unsigned offset0, offset1;
2576         s32 row_inc;
2577         s32 pix_inc;
2578         u16 frame_width, frame_height;
2579         unsigned int field_offset = 0;
2580         u16 in_height = height;
2581         u16 in_width = width;
2582         int x_predecim = 1, y_predecim = 1;
2583         bool ilace = mgr_timings->interlace;
2584         unsigned long pclk = dispc_plane_pclk_rate(plane);
2585         unsigned long lclk = dispc_plane_lclk_rate(plane);
2586
2587         if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2588                 return -EINVAL;
2589
2590         switch (color_mode) {
2591         case OMAP_DSS_COLOR_YUV2:
2592         case OMAP_DSS_COLOR_UYVY:
2593         case OMAP_DSS_COLOR_NV12:
2594                 if (in_width & 1) {
2595                         DSSERR("input width %d is not even for YUV format\n",
2596                                 in_width);
2597                         return -EINVAL;
2598                 }
2599                 break;
2600
2601         default:
2602                 break;
2603         }
2604
2605         out_width = out_width == 0 ? width : out_width;
2606         out_height = out_height == 0 ? height : out_height;
2607
2608         if (ilace && height == out_height)
2609                 fieldmode = true;
2610
2611         if (ilace) {
2612                 if (fieldmode)
2613                         in_height /= 2;
2614                 pos_y /= 2;
2615                 out_height /= 2;
2616
2617                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2618                         "out_height %d\n", in_height, pos_y,
2619                         out_height);
2620         }
2621
2622         if (!dss_feat_color_mode_supported(plane, color_mode))
2623                 return -EINVAL;
2624
2625         r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2626                         in_height, out_width, out_height, color_mode,
2627                         &five_taps, &x_predecim, &y_predecim, pos_x,
2628                         rotation_type, mem_to_mem);
2629         if (r)
2630                 return r;
2631
2632         in_width = in_width / x_predecim;
2633         in_height = in_height / y_predecim;
2634
2635         if (x_predecim > 1 || y_predecim > 1)
2636                 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2637                         x_predecim, y_predecim, in_width, in_height);
2638
2639         switch (color_mode) {
2640         case OMAP_DSS_COLOR_YUV2:
2641         case OMAP_DSS_COLOR_UYVY:
2642         case OMAP_DSS_COLOR_NV12:
2643                 if (in_width & 1) {
2644                         DSSDBG("predecimated input width is not even for YUV format\n");
2645                         DSSDBG("adjusting input width %d -> %d\n",
2646                                 in_width, in_width & ~1);
2647
2648                         in_width &= ~1;
2649                 }
2650                 break;
2651
2652         default:
2653                 break;
2654         }
2655
2656         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2657                         color_mode == OMAP_DSS_COLOR_UYVY ||
2658                         color_mode == OMAP_DSS_COLOR_NV12)
2659                 cconv = 1;
2660
2661         if (ilace && !fieldmode) {
2662                 /*
2663                  * when downscaling the bottom field may have to start several
2664                  * source lines below the top field. Unfortunately ACCUI
2665                  * registers will only hold the fractional part of the offset
2666                  * so the integer part must be added to the base address of the
2667                  * bottom field.
2668                  */
2669                 if (!in_height || in_height == out_height)
2670                         field_offset = 0;
2671                 else
2672                         field_offset = in_height / out_height / 2;
2673         }
2674
2675         /* Fields are independent but interleaved in memory. */
2676         if (fieldmode)
2677                 field_offset = 1;
2678
2679         offset0 = 0;
2680         offset1 = 0;
2681         row_inc = 0;
2682         pix_inc = 0;
2683
2684         if (plane == OMAP_DSS_WB) {
2685                 frame_width = out_width;
2686                 frame_height = out_height;
2687         } else {
2688                 frame_width = in_width;
2689                 frame_height = height;
2690         }
2691
2692         if (rotation_type == OMAP_DSS_ROT_TILER)
2693                 calc_tiler_rotation_offset(screen_width, frame_width,
2694                                 color_mode, fieldmode, field_offset,
2695                                 &offset0, &offset1, &row_inc, &pix_inc,
2696                                 x_predecim, y_predecim);
2697         else if (rotation_type == OMAP_DSS_ROT_DMA)
2698                 calc_dma_rotation_offset(rotation, mirror, screen_width,
2699                                 frame_width, frame_height,
2700                                 color_mode, fieldmode, field_offset,
2701                                 &offset0, &offset1, &row_inc, &pix_inc,
2702                                 x_predecim, y_predecim);
2703         else
2704                 calc_vrfb_rotation_offset(rotation, mirror,
2705                                 screen_width, frame_width, frame_height,
2706                                 color_mode, fieldmode, field_offset,
2707                                 &offset0, &offset1, &row_inc, &pix_inc,
2708                                 x_predecim, y_predecim);
2709
2710         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2711                         offset0, offset1, row_inc, pix_inc);
2712
2713         dispc_ovl_set_color_mode(plane, color_mode);
2714
2715         dispc_ovl_configure_burst_type(plane, rotation_type);
2716
2717         if (dispc.feat->reverse_ilace_field_order)
2718                 swap(offset0, offset1);
2719
2720         dispc_ovl_set_ba0(plane, paddr + offset0);
2721         dispc_ovl_set_ba1(plane, paddr + offset1);
2722
2723         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2724                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2725                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2726         }
2727
2728         if (dispc.feat->last_pixel_inc_missing)
2729                 row_inc += pix_inc - 1;
2730
2731         dispc_ovl_set_row_inc(plane, row_inc);
2732         dispc_ovl_set_pix_inc(plane, pix_inc);
2733
2734         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2735                         in_height, out_width, out_height);
2736
2737         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2738
2739         dispc_ovl_set_input_size(plane, in_width, in_height);
2740
2741         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2742                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2743                                    out_height, ilace, five_taps, fieldmode,
2744                                    color_mode, rotation);
2745                 dispc_ovl_set_output_size(plane, out_width, out_height);
2746                 dispc_ovl_set_vid_color_conv(plane, cconv);
2747         }
2748
2749         dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2750                         color_mode);
2751
2752         dispc_ovl_set_zorder(plane, caps, zorder);
2753         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2754         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2755
2756         dispc_ovl_enable_replication(plane, caps, replication);
2757
2758         return 0;
2759 }
2760
2761 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2762                 bool replication, const struct omap_video_timings *mgr_timings,
2763                 bool mem_to_mem)
2764 {
2765         int r;
2766         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2767         enum omap_channel channel;
2768
2769         channel = dispc_ovl_get_channel_out(plane);
2770
2771         DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2772                 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2773                 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2774                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2775                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2776
2777         r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2778                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2779                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2780                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2781                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2782
2783         return r;
2784 }
2785 EXPORT_SYMBOL(dispc_ovl_setup);
2786
2787 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2788                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2789 {
2790         int r;
2791         u32 l;
2792         enum omap_plane plane = OMAP_DSS_WB;
2793         const int pos_x = 0, pos_y = 0;
2794         const u8 zorder = 0, global_alpha = 0;
2795         const bool replication = false;
2796         bool truncation;
2797         int in_width = mgr_timings->x_res;
2798         int in_height = mgr_timings->y_res;
2799         enum omap_overlay_caps caps =
2800                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2801
2802         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2803                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2804                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2805                 wi->mirror);
2806
2807         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2808                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2809                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2810                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2811                 replication, mgr_timings, mem_to_mem);
2812
2813         switch (wi->color_mode) {
2814         case OMAP_DSS_COLOR_RGB16:
2815         case OMAP_DSS_COLOR_RGB24P:
2816         case OMAP_DSS_COLOR_ARGB16:
2817         case OMAP_DSS_COLOR_RGBA16:
2818         case OMAP_DSS_COLOR_RGB12U:
2819         case OMAP_DSS_COLOR_ARGB16_1555:
2820         case OMAP_DSS_COLOR_XRGB16_1555:
2821         case OMAP_DSS_COLOR_RGBX16:
2822                 truncation = true;
2823                 break;
2824         default:
2825                 truncation = false;
2826                 break;
2827         }
2828
2829         /* setup extra DISPC_WB_ATTRIBUTES */
2830         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2831         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2832         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2833         if (mem_to_mem)
2834                 l = FLD_MOD(l, 1, 26, 24);      /* CAPTUREMODE */
2835         else
2836                 l = FLD_MOD(l, 0, 26, 24);      /* CAPTUREMODE */
2837         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2838
2839         if (mem_to_mem) {
2840                 /* WBDELAYCOUNT */
2841                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2842         } else {
2843                 int wbdelay;
2844
2845                 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2846                         mgr_timings->vbp, 255);
2847
2848                 /* WBDELAYCOUNT */
2849                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2850         }
2851
2852         return r;
2853 }
2854
2855 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2856 {
2857         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2858
2859         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2860
2861         return 0;
2862 }
2863 EXPORT_SYMBOL(dispc_ovl_enable);
2864
2865 bool dispc_ovl_enabled(enum omap_plane plane)
2866 {
2867         return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2868 }
2869 EXPORT_SYMBOL(dispc_ovl_enabled);
2870
2871 enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel)
2872 {
2873         return dss_feat_get_supported_outputs(channel);
2874 }
2875 EXPORT_SYMBOL(dispc_mgr_get_supported_outputs);
2876
2877 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2878 {
2879         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2880         /* flush posted write */
2881         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2882 }
2883 EXPORT_SYMBOL(dispc_mgr_enable);
2884
2885 bool dispc_mgr_is_enabled(enum omap_channel channel)
2886 {
2887         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2888 }
2889 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2890
2891 void dispc_wb_enable(bool enable)
2892 {
2893         dispc_ovl_enable(OMAP_DSS_WB, enable);
2894 }
2895
2896 bool dispc_wb_is_enabled(void)
2897 {
2898         return dispc_ovl_enabled(OMAP_DSS_WB);
2899 }
2900
2901 static void dispc_lcd_enable_signal_polarity(bool act_high)
2902 {
2903         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2904                 return;
2905
2906         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2907 }
2908
2909 void dispc_lcd_enable_signal(bool enable)
2910 {
2911         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2912                 return;
2913
2914         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2915 }
2916
2917 void dispc_pck_free_enable(bool enable)
2918 {
2919         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2920                 return;
2921
2922         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2923 }
2924
2925 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2926 {
2927         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2928 }
2929
2930
2931 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2932 {
2933         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2934 }
2935
2936 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2937 {
2938         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2939 }
2940
2941
2942 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2943 {
2944         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2945 }
2946
2947 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2948                 enum omap_dss_trans_key_type type,
2949                 u32 trans_key)
2950 {
2951         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2952
2953         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2954 }
2955
2956 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2957 {
2958         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2959 }
2960
2961 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2962                 bool enable)
2963 {
2964         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2965                 return;
2966
2967         if (ch == OMAP_DSS_CHANNEL_LCD)
2968                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2969         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2970                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2971 }
2972
2973 void dispc_mgr_setup(enum omap_channel channel,
2974                 const struct omap_overlay_manager_info *info)
2975 {
2976         dispc_mgr_set_default_color(channel, info->default_color);
2977         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2978         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2979         dispc_mgr_enable_alpha_fixed_zorder(channel,
2980                         info->partial_alpha_enabled);
2981         if (dss_has_feature(FEAT_CPR)) {
2982                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2983                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2984         }
2985 }
2986 EXPORT_SYMBOL(dispc_mgr_setup);
2987
2988 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2989 {
2990         int code;
2991
2992         switch (data_lines) {
2993         case 12:
2994                 code = 0;
2995                 break;
2996         case 16:
2997                 code = 1;
2998                 break;
2999         case 18:
3000                 code = 2;
3001                 break;
3002         case 24:
3003                 code = 3;
3004                 break;
3005         default:
3006                 BUG();
3007                 return;
3008         }
3009
3010         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3011 }
3012
3013 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3014 {
3015         u32 l;
3016         int gpout0, gpout1;
3017
3018         switch (mode) {
3019         case DSS_IO_PAD_MODE_RESET:
3020                 gpout0 = 0;
3021                 gpout1 = 0;
3022                 break;
3023         case DSS_IO_PAD_MODE_RFBI:
3024                 gpout0 = 1;
3025                 gpout1 = 0;
3026                 break;
3027         case DSS_IO_PAD_MODE_BYPASS:
3028                 gpout0 = 1;
3029                 gpout1 = 1;
3030                 break;
3031         default:
3032                 BUG();
3033                 return;
3034         }
3035
3036         l = dispc_read_reg(DISPC_CONTROL);
3037         l = FLD_MOD(l, gpout0, 15, 15);
3038         l = FLD_MOD(l, gpout1, 16, 16);
3039         dispc_write_reg(DISPC_CONTROL, l);
3040 }
3041
3042 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3043 {
3044         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3045 }
3046
3047 void dispc_mgr_set_lcd_config(enum omap_channel channel,
3048                 const struct dss_lcd_mgr_config *config)
3049 {
3050         dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3051
3052         dispc_mgr_enable_stallmode(channel, config->stallmode);
3053         dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3054
3055         dispc_mgr_set_clock_div(channel, &config->clock_info);
3056
3057         dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3058
3059         dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3060
3061         dispc_mgr_set_lcd_type_tft(channel);
3062 }
3063 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3064
3065 static bool _dispc_mgr_size_ok(u16 width, u16 height)
3066 {
3067         return width <= dispc.feat->mgr_width_max &&
3068                 height <= dispc.feat->mgr_height_max;
3069 }
3070
3071 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3072                 int vsw, int vfp, int vbp)
3073 {
3074         if (hsw < 1 || hsw > dispc.feat->sw_max ||
3075                         hfp < 1 || hfp > dispc.feat->hp_max ||
3076                         hbp < 1 || hbp > dispc.feat->hp_max ||
3077                         vsw < 1 || vsw > dispc.feat->sw_max ||
3078                         vfp < 0 || vfp > dispc.feat->vp_max ||
3079                         vbp < 0 || vbp > dispc.feat->vp_max)
3080                 return false;
3081         return true;
3082 }
3083
3084 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3085                 unsigned long pclk)
3086 {
3087         if (dss_mgr_is_lcd(channel))
3088                 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3089         else
3090                 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3091 }
3092
3093 bool dispc_mgr_timings_ok(enum omap_channel channel,
3094                 const struct omap_video_timings *timings)
3095 {
3096         if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3097                 return false;
3098
3099         if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3100                 return false;
3101
3102         if (dss_mgr_is_lcd(channel)) {
3103                 /* TODO: OMAP4+ supports interlace for LCD outputs */
3104                 if (timings->interlace)
3105                         return false;
3106
3107                 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3108                                 timings->hbp, timings->vsw, timings->vfp,
3109                                 timings->vbp))
3110                         return false;
3111         }
3112
3113         return true;
3114 }
3115
3116 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3117                 int hfp, int hbp, int vsw, int vfp, int vbp,
3118                 enum omap_dss_signal_level vsync_level,
3119                 enum omap_dss_signal_level hsync_level,
3120                 enum omap_dss_signal_edge data_pclk_edge,
3121                 enum omap_dss_signal_level de_level,
3122                 enum omap_dss_signal_edge sync_pclk_edge)
3123
3124 {
3125         u32 timing_h, timing_v, l;
3126         bool onoff, rf, ipc, vs, hs, de;
3127
3128         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3129                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3130                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3131         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3132                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3133                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
3134
3135         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3136         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3137
3138         switch (vsync_level) {
3139         case OMAPDSS_SIG_ACTIVE_LOW:
3140                 vs = true;
3141                 break;
3142         case OMAPDSS_SIG_ACTIVE_HIGH:
3143                 vs = false;
3144                 break;
3145         default:
3146                 BUG();
3147         }
3148
3149         switch (hsync_level) {
3150         case OMAPDSS_SIG_ACTIVE_LOW:
3151                 hs = true;
3152                 break;
3153         case OMAPDSS_SIG_ACTIVE_HIGH:
3154                 hs = false;
3155                 break;
3156         default:
3157                 BUG();
3158         }
3159
3160         switch (de_level) {
3161         case OMAPDSS_SIG_ACTIVE_LOW:
3162                 de = true;
3163                 break;
3164         case OMAPDSS_SIG_ACTIVE_HIGH:
3165                 de = false;
3166                 break;
3167         default:
3168                 BUG();
3169         }
3170
3171         switch (data_pclk_edge) {
3172         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3173                 ipc = false;
3174                 break;
3175         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3176                 ipc = true;
3177                 break;
3178         default:
3179                 BUG();
3180         }
3181
3182         /* always use the 'rf' setting */
3183         onoff = true;
3184
3185         switch (sync_pclk_edge) {
3186         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3187                 rf = false;
3188                 break;
3189         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3190                 rf = true;
3191                 break;
3192         default:
3193                 BUG();
3194         }
3195
3196         l = FLD_VAL(onoff, 17, 17) |
3197                 FLD_VAL(rf, 16, 16) |
3198                 FLD_VAL(de, 15, 15) |
3199                 FLD_VAL(ipc, 14, 14) |
3200                 FLD_VAL(hs, 13, 13) |
3201                 FLD_VAL(vs, 12, 12);
3202
3203         /* always set ALIGN bit when available */
3204         if (dispc.feat->supports_sync_align)
3205                 l |= (1 << 18);
3206
3207         dispc_write_reg(DISPC_POL_FREQ(channel), l);
3208
3209         if (dispc.syscon_pol) {
3210                 const int shifts[] = {
3211                         [OMAP_DSS_CHANNEL_LCD] = 0,
3212                         [OMAP_DSS_CHANNEL_LCD2] = 1,
3213                         [OMAP_DSS_CHANNEL_LCD3] = 2,
3214                 };
3215
3216                 u32 mask, val;
3217
3218                 mask = (1 << 0) | (1 << 3) | (1 << 6);
3219                 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3220
3221                 mask <<= 16 + shifts[channel];
3222                 val <<= 16 + shifts[channel];
3223
3224                 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3225                         mask, val);
3226         }
3227 }
3228
3229 /* change name to mode? */
3230 void dispc_mgr_set_timings(enum omap_channel channel,
3231                 const struct omap_video_timings *timings)
3232 {
3233         unsigned xtot, ytot;
3234         unsigned long ht, vt;
3235         struct omap_video_timings t = *timings;
3236
3237         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3238
3239         if (!dispc_mgr_timings_ok(channel, &t)) {
3240                 BUG();
3241                 return;
3242         }
3243
3244         if (dss_mgr_is_lcd(channel)) {
3245                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3246                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3247                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3248
3249                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3250                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3251
3252                 ht = timings->pixelclock / xtot;
3253                 vt = timings->pixelclock / xtot / ytot;
3254
3255                 DSSDBG("pck %u\n", timings->pixelclock);
3256                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3257                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3258                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3259                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
3260                         t.de_level, t.sync_pclk_edge);
3261
3262                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3263         } else {
3264                 if (t.interlace)
3265                         t.y_res /= 2;
3266
3267                 if (dispc.feat->supports_double_pixel)
3268                         REG_FLD_MOD(DISPC_CONTROL, t.double_pixel ? 1 : 0,
3269                                 19, 17);
3270         }
3271
3272         dispc_mgr_set_size(channel, t.x_res, t.y_res);
3273 }
3274 EXPORT_SYMBOL(dispc_mgr_set_timings);
3275
3276 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3277                 u16 pck_div)
3278 {
3279         BUG_ON(lck_div < 1);
3280         BUG_ON(pck_div < 1);
3281
3282         dispc_write_reg(DISPC_DIVISORo(channel),
3283                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3284
3285         if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3286                         channel == OMAP_DSS_CHANNEL_LCD)
3287                 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3288 }
3289
3290 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3291                 int *pck_div)
3292 {
3293         u32 l;
3294         l = dispc_read_reg(DISPC_DIVISORo(channel));
3295         *lck_div = FLD_GET(l, 23, 16);
3296         *pck_div = FLD_GET(l, 7, 0);
3297 }
3298
3299 static unsigned long dispc_fclk_rate(void)
3300 {
3301         unsigned long r;
3302         enum dss_clk_source src;
3303
3304         src = dss_get_dispc_clk_source();
3305
3306         if (src == DSS_CLK_SRC_FCK) {
3307                 r = dss_get_dispc_clk_rate();
3308         } else {
3309                 struct dss_pll *pll;
3310                 unsigned clkout_idx;
3311
3312                 pll = dss_pll_find_by_src(src);
3313                 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3314
3315                 r = pll->cinfo.clkout[clkout_idx];
3316         }
3317
3318         return r;
3319 }
3320
3321 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3322 {
3323         int lcd;
3324         unsigned long r;
3325         enum dss_clk_source src;
3326
3327         /* for TV, LCLK rate is the FCLK rate */
3328         if (!dss_mgr_is_lcd(channel))
3329                 return dispc_fclk_rate();
3330
3331         src = dss_get_lcd_clk_source(channel);
3332
3333         if (src == DSS_CLK_SRC_FCK) {
3334                 r = dss_get_dispc_clk_rate();
3335         } else {
3336                 struct dss_pll *pll;
3337                 unsigned clkout_idx;
3338
3339                 pll = dss_pll_find_by_src(src);
3340                 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3341
3342                 r = pll->cinfo.clkout[clkout_idx];
3343         }
3344
3345         lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3346
3347         return r / lcd;
3348 }
3349
3350 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3351 {
3352         unsigned long r;
3353
3354         if (dss_mgr_is_lcd(channel)) {
3355                 int pcd;
3356                 u32 l;
3357
3358                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3359
3360                 pcd = FLD_GET(l, 7, 0);
3361
3362                 r = dispc_mgr_lclk_rate(channel);
3363
3364                 return r / pcd;
3365         } else {
3366                 return dispc.tv_pclk_rate;
3367         }
3368 }
3369
3370 void dispc_set_tv_pclk(unsigned long pclk)
3371 {
3372         dispc.tv_pclk_rate = pclk;
3373 }
3374
3375 static unsigned long dispc_core_clk_rate(void)
3376 {
3377         return dispc.core_clk_rate;
3378 }
3379
3380 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3381 {
3382         enum omap_channel channel;
3383
3384         if (plane == OMAP_DSS_WB)
3385                 return 0;
3386
3387         channel = dispc_ovl_get_channel_out(plane);
3388
3389         return dispc_mgr_pclk_rate(channel);
3390 }
3391
3392 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3393 {
3394         enum omap_channel channel;
3395
3396         if (plane == OMAP_DSS_WB)
3397                 return 0;
3398
3399         channel = dispc_ovl_get_channel_out(plane);
3400
3401         return dispc_mgr_lclk_rate(channel);
3402 }
3403
3404 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3405 {
3406         int lcd, pcd;
3407         enum dss_clk_source lcd_clk_src;
3408
3409         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3410
3411         lcd_clk_src = dss_get_lcd_clk_source(channel);
3412
3413         seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
3414                 dss_get_clk_source_name(lcd_clk_src));
3415
3416         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3417
3418         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3419                 dispc_mgr_lclk_rate(channel), lcd);
3420         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3421                 dispc_mgr_pclk_rate(channel), pcd);
3422 }
3423
3424 void dispc_dump_clocks(struct seq_file *s)
3425 {
3426         int lcd;
3427         u32 l;
3428         enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3429
3430         if (dispc_runtime_get())
3431                 return;
3432
3433         seq_printf(s, "- DISPC -\n");
3434
3435         seq_printf(s, "dispc fclk source = %s\n",
3436                         dss_get_clk_source_name(dispc_clk_src));
3437
3438         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3439
3440         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3441                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3442                 l = dispc_read_reg(DISPC_DIVISOR);
3443                 lcd = FLD_GET(l, 23, 16);
3444
3445                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3446                                 (dispc_fclk_rate()/lcd), lcd);
3447         }
3448
3449         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3450
3451         if (dss_has_feature(FEAT_MGR_LCD2))
3452                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3453         if (dss_has_feature(FEAT_MGR_LCD3))
3454                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3455
3456         dispc_runtime_put();
3457 }
3458
3459 static void dispc_dump_regs(struct seq_file *s)
3460 {
3461         int i, j;
3462         const char *mgr_names[] = {
3463                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3464                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3465                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3466                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3467         };
3468         const char *ovl_names[] = {
3469                 [OMAP_DSS_GFX]          = "GFX",
3470                 [OMAP_DSS_VIDEO1]       = "VID1",
3471                 [OMAP_DSS_VIDEO2]       = "VID2",
3472                 [OMAP_DSS_VIDEO3]       = "VID3",
3473                 [OMAP_DSS_WB]           = "WB",
3474         };
3475         const char **p_names;
3476
3477 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3478
3479         if (dispc_runtime_get())
3480                 return;
3481
3482         /* DISPC common registers */
3483         DUMPREG(DISPC_REVISION);
3484         DUMPREG(DISPC_SYSCONFIG);
3485         DUMPREG(DISPC_SYSSTATUS);
3486         DUMPREG(DISPC_IRQSTATUS);
3487         DUMPREG(DISPC_IRQENABLE);
3488         DUMPREG(DISPC_CONTROL);
3489         DUMPREG(DISPC_CONFIG);
3490         DUMPREG(DISPC_CAPABLE);
3491         DUMPREG(DISPC_LINE_STATUS);
3492         DUMPREG(DISPC_LINE_NUMBER);
3493         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3494                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3495                 DUMPREG(DISPC_GLOBAL_ALPHA);
3496         if (dss_has_feature(FEAT_MGR_LCD2)) {
3497                 DUMPREG(DISPC_CONTROL2);
3498                 DUMPREG(DISPC_CONFIG2);
3499         }
3500         if (dss_has_feature(FEAT_MGR_LCD3)) {
3501                 DUMPREG(DISPC_CONTROL3);
3502                 DUMPREG(DISPC_CONFIG3);
3503         }
3504         if (dss_has_feature(FEAT_MFLAG))
3505                 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3506
3507 #undef DUMPREG
3508
3509 #define DISPC_REG(i, name) name(i)
3510 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3511         (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3512         dispc_read_reg(DISPC_REG(i, r)))
3513
3514         p_names = mgr_names;
3515
3516         /* DISPC channel specific registers */
3517         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3518                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3519                 DUMPREG(i, DISPC_TRANS_COLOR);
3520                 DUMPREG(i, DISPC_SIZE_MGR);
3521
3522                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3523                         continue;
3524
3525                 DUMPREG(i, DISPC_TIMING_H);
3526                 DUMPREG(i, DISPC_TIMING_V);
3527                 DUMPREG(i, DISPC_POL_FREQ);
3528                 DUMPREG(i, DISPC_DIVISORo);
3529
3530                 DUMPREG(i, DISPC_DATA_CYCLE1);
3531                 DUMPREG(i, DISPC_DATA_CYCLE2);
3532                 DUMPREG(i, DISPC_DATA_CYCLE3);
3533
3534                 if (dss_has_feature(FEAT_CPR)) {
3535                         DUMPREG(i, DISPC_CPR_COEF_R);
3536                         DUMPREG(i, DISPC_CPR_COEF_G);
3537                         DUMPREG(i, DISPC_CPR_COEF_B);
3538                 }
3539         }
3540
3541         p_names = ovl_names;
3542
3543         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3544                 DUMPREG(i, DISPC_OVL_BA0);
3545                 DUMPREG(i, DISPC_OVL_BA1);
3546                 DUMPREG(i, DISPC_OVL_POSITION);
3547                 DUMPREG(i, DISPC_OVL_SIZE);
3548                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3549                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3550                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3551                 DUMPREG(i, DISPC_OVL_ROW_INC);
3552                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3553
3554                 if (dss_has_feature(FEAT_PRELOAD))
3555                         DUMPREG(i, DISPC_OVL_PRELOAD);
3556                 if (dss_has_feature(FEAT_MFLAG))
3557                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3558
3559                 if (i == OMAP_DSS_GFX) {
3560                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3561                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3562                         continue;
3563                 }
3564
3565                 DUMPREG(i, DISPC_OVL_FIR);
3566                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3567                 DUMPREG(i, DISPC_OVL_ACCU0);
3568                 DUMPREG(i, DISPC_OVL_ACCU1);
3569                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3570                         DUMPREG(i, DISPC_OVL_BA0_UV);
3571                         DUMPREG(i, DISPC_OVL_BA1_UV);
3572                         DUMPREG(i, DISPC_OVL_FIR2);
3573                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3574                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3575                 }
3576                 if (dss_has_feature(FEAT_ATTR2))
3577                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3578         }
3579
3580         if (dispc.feat->has_writeback) {
3581                 i = OMAP_DSS_WB;
3582                 DUMPREG(i, DISPC_OVL_BA0);
3583                 DUMPREG(i, DISPC_OVL_BA1);
3584                 DUMPREG(i, DISPC_OVL_SIZE);
3585                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3586                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3587                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3588                 DUMPREG(i, DISPC_OVL_ROW_INC);
3589                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3590
3591                 if (dss_has_feature(FEAT_MFLAG))
3592                         DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3593
3594                 DUMPREG(i, DISPC_OVL_FIR);
3595                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3596                 DUMPREG(i, DISPC_OVL_ACCU0);
3597                 DUMPREG(i, DISPC_OVL_ACCU1);
3598                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3599                         DUMPREG(i, DISPC_OVL_BA0_UV);
3600                         DUMPREG(i, DISPC_OVL_BA1_UV);
3601                         DUMPREG(i, DISPC_OVL_FIR2);
3602                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3603                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3604                 }
3605                 if (dss_has_feature(FEAT_ATTR2))
3606                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3607         }
3608
3609 #undef DISPC_REG
3610 #undef DUMPREG
3611
3612 #define DISPC_REG(plane, name, i) name(plane, i)
3613 #define DUMPREG(plane, name, i) \
3614         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3615         (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3616         dispc_read_reg(DISPC_REG(plane, name, i)))
3617
3618         /* Video pipeline coefficient registers */
3619
3620         /* start from OMAP_DSS_VIDEO1 */
3621         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3622                 for (j = 0; j < 8; j++)
3623                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3624
3625                 for (j = 0; j < 8; j++)
3626                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3627
3628                 for (j = 0; j < 5; j++)
3629                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3630
3631                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3632                         for (j = 0; j < 8; j++)
3633                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3634                 }
3635
3636                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3637                         for (j = 0; j < 8; j++)
3638                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3639
3640                         for (j = 0; j < 8; j++)
3641                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3642
3643                         for (j = 0; j < 8; j++)
3644                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3645                 }
3646         }
3647
3648         dispc_runtime_put();
3649
3650 #undef DISPC_REG
3651 #undef DUMPREG
3652 }
3653
3654 /* calculate clock rates using dividers in cinfo */
3655 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3656                 struct dispc_clock_info *cinfo)
3657 {
3658         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3659                 return -EINVAL;
3660         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3661                 return -EINVAL;
3662
3663         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3664         cinfo->pck = cinfo->lck / cinfo->pck_div;
3665
3666         return 0;
3667 }
3668
3669 bool dispc_div_calc(unsigned long dispc,
3670                 unsigned long pck_min, unsigned long pck_max,
3671                 dispc_div_calc_func func, void *data)
3672 {
3673         int lckd, lckd_start, lckd_stop;
3674         int pckd, pckd_start, pckd_stop;
3675         unsigned long pck, lck;
3676         unsigned long lck_max;
3677         unsigned long pckd_hw_min, pckd_hw_max;
3678         unsigned min_fck_per_pck;
3679         unsigned long fck;
3680
3681 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3682         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3683 #else
3684         min_fck_per_pck = 0;
3685 #endif
3686
3687         pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3688         pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3689
3690         lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3691
3692         pck_min = pck_min ? pck_min : 1;
3693         pck_max = pck_max ? pck_max : ULONG_MAX;
3694
3695         lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3696         lckd_stop = min(dispc / pck_min, 255ul);
3697
3698         for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3699                 lck = dispc / lckd;
3700
3701                 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3702                 pckd_stop = min(lck / pck_min, pckd_hw_max);
3703
3704                 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3705                         pck = lck / pckd;
3706
3707                         /*
3708                          * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3709                          * clock, which means we're configuring DISPC fclk here
3710                          * also. Thus we need to use the calculated lck. For
3711                          * OMAP4+ the DISPC fclk is a separate clock.
3712                          */
3713                         if (dss_has_feature(FEAT_CORE_CLK_DIV))
3714                                 fck = dispc_core_clk_rate();
3715                         else
3716                                 fck = lck;
3717
3718                         if (fck < pck * min_fck_per_pck)
3719                                 continue;
3720
3721                         if (func(lckd, pckd, lck, pck, data))
3722                                 return true;
3723                 }
3724         }
3725
3726         return false;
3727 }
3728
3729 void dispc_mgr_set_clock_div(enum omap_channel channel,
3730                 const struct dispc_clock_info *cinfo)
3731 {
3732         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3733         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3734
3735         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3736 }
3737
3738 int dispc_mgr_get_clock_div(enum omap_channel channel,
3739                 struct dispc_clock_info *cinfo)
3740 {
3741         unsigned long fck;
3742
3743         fck = dispc_fclk_rate();
3744
3745         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3746         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3747
3748         cinfo->lck = fck / cinfo->lck_div;
3749         cinfo->pck = cinfo->lck / cinfo->pck_div;
3750
3751         return 0;
3752 }
3753
3754 u32 dispc_read_irqstatus(void)
3755 {
3756         return dispc_read_reg(DISPC_IRQSTATUS);
3757 }
3758 EXPORT_SYMBOL(dispc_read_irqstatus);
3759
3760 void dispc_clear_irqstatus(u32 mask)
3761 {
3762         dispc_write_reg(DISPC_IRQSTATUS, mask);
3763 }
3764 EXPORT_SYMBOL(dispc_clear_irqstatus);
3765
3766 u32 dispc_read_irqenable(void)
3767 {
3768         return dispc_read_reg(DISPC_IRQENABLE);
3769 }
3770 EXPORT_SYMBOL(dispc_read_irqenable);
3771
3772 void dispc_write_irqenable(u32 mask)
3773 {
3774         u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3775
3776         /* clear the irqstatus for newly enabled irqs */
3777         dispc_clear_irqstatus((mask ^ old_mask) & mask);
3778
3779         dispc_write_reg(DISPC_IRQENABLE, mask);
3780 }
3781 EXPORT_SYMBOL(dispc_write_irqenable);
3782
3783 void dispc_enable_sidle(void)
3784 {
3785         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3786 }
3787
3788 void dispc_disable_sidle(void)
3789 {
3790         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3791 }
3792
3793 static void _omap_dispc_initial_config(void)
3794 {
3795         u32 l;
3796
3797         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3798         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3799                 l = dispc_read_reg(DISPC_DIVISOR);
3800                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3801                 l = FLD_MOD(l, 1, 0, 0);
3802                 l = FLD_MOD(l, 1, 23, 16);
3803                 dispc_write_reg(DISPC_DIVISOR, l);
3804
3805                 dispc.core_clk_rate = dispc_fclk_rate();
3806         }
3807
3808         /* FUNCGATED */
3809         if (dss_has_feature(FEAT_FUNCGATED))
3810                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3811
3812         dispc_setup_color_conv_coef();
3813
3814         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3815
3816         dispc_init_fifos();
3817
3818         dispc_configure_burst_sizes();
3819
3820         dispc_ovl_enable_zorder_planes();
3821
3822         if (dispc.feat->mstandby_workaround)
3823                 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3824
3825         if (dss_has_feature(FEAT_MFLAG))
3826                 dispc_init_mflag();
3827 }
3828
3829 static const struct dispc_features omap24xx_dispc_feats = {
3830         .sw_start               =       5,
3831         .fp_start               =       15,
3832         .bp_start               =       27,
3833         .sw_max                 =       64,
3834         .vp_max                 =       255,
3835         .hp_max                 =       256,
3836         .mgr_width_start        =       10,
3837         .mgr_height_start       =       26,
3838         .mgr_width_max          =       2048,
3839         .mgr_height_max         =       2048,
3840         .max_lcd_pclk           =       66500000,
3841         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
3842         .calc_core_clk          =       calc_core_clk_24xx,
3843         .num_fifos              =       3,
3844         .no_framedone_tv        =       true,
3845         .set_max_preload        =       false,
3846         .last_pixel_inc_missing =       true,
3847 };
3848
3849 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3850         .sw_start               =       5,
3851         .fp_start               =       15,
3852         .bp_start               =       27,
3853         .sw_max                 =       64,
3854         .vp_max                 =       255,
3855         .hp_max                 =       256,
3856         .mgr_width_start        =       10,
3857         .mgr_height_start       =       26,
3858         .mgr_width_max          =       2048,
3859         .mgr_height_max         =       2048,
3860         .max_lcd_pclk           =       173000000,
3861         .max_tv_pclk            =       59000000,
3862         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3863         .calc_core_clk          =       calc_core_clk_34xx,
3864         .num_fifos              =       3,
3865         .no_framedone_tv        =       true,
3866         .set_max_preload        =       false,
3867         .last_pixel_inc_missing =       true,
3868 };
3869
3870 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3871         .sw_start               =       7,
3872         .fp_start               =       19,
3873         .bp_start               =       31,
3874         .sw_max                 =       256,
3875         .vp_max                 =       4095,
3876         .hp_max                 =       4096,
3877         .mgr_width_start        =       10,
3878         .mgr_height_start       =       26,
3879         .mgr_width_max          =       2048,
3880         .mgr_height_max         =       2048,
3881         .max_lcd_pclk           =       173000000,
3882         .max_tv_pclk            =       59000000,
3883         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3884         .calc_core_clk          =       calc_core_clk_34xx,
3885         .num_fifos              =       3,
3886         .no_framedone_tv        =       true,
3887         .set_max_preload        =       false,
3888         .last_pixel_inc_missing =       true,
3889 };
3890
3891 static const struct dispc_features omap44xx_dispc_feats = {
3892         .sw_start               =       7,
3893         .fp_start               =       19,
3894         .bp_start               =       31,
3895         .sw_max                 =       256,
3896         .vp_max                 =       4095,
3897         .hp_max                 =       4096,
3898         .mgr_width_start        =       10,
3899         .mgr_height_start       =       26,
3900         .mgr_width_max          =       2048,
3901         .mgr_height_max         =       2048,
3902         .max_lcd_pclk           =       170000000,
3903         .max_tv_pclk            =       185625000,
3904         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3905         .calc_core_clk          =       calc_core_clk_44xx,
3906         .num_fifos              =       5,
3907         .gfx_fifo_workaround    =       true,
3908         .set_max_preload        =       true,
3909         .supports_sync_align    =       true,
3910         .has_writeback          =       true,
3911         .supports_double_pixel  =       true,
3912         .reverse_ilace_field_order =    true,
3913 };
3914
3915 static const struct dispc_features omap54xx_dispc_feats = {
3916         .sw_start               =       7,
3917         .fp_start               =       19,
3918         .bp_start               =       31,
3919         .sw_max                 =       256,
3920         .vp_max                 =       4095,
3921         .hp_max                 =       4096,
3922         .mgr_width_start        =       11,
3923         .mgr_height_start       =       27,
3924         .mgr_width_max          =       4096,
3925         .mgr_height_max         =       4096,
3926         .max_lcd_pclk           =       170000000,
3927         .max_tv_pclk            =       186000000,
3928         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3929         .calc_core_clk          =       calc_core_clk_44xx,
3930         .num_fifos              =       5,
3931         .gfx_fifo_workaround    =       true,
3932         .mstandby_workaround    =       true,
3933         .set_max_preload        =       true,
3934         .supports_sync_align    =       true,
3935         .has_writeback          =       true,
3936         .supports_double_pixel  =       true,
3937         .reverse_ilace_field_order =    true,
3938 };
3939
3940 static int dispc_init_features(struct platform_device *pdev)
3941 {
3942         const struct dispc_features *src;
3943         struct dispc_features *dst;
3944
3945         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3946         if (!dst) {
3947                 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3948                 return -ENOMEM;
3949         }
3950
3951         switch (omapdss_get_version()) {
3952         case OMAPDSS_VER_OMAP24xx:
3953                 src = &omap24xx_dispc_feats;
3954                 break;
3955
3956         case OMAPDSS_VER_OMAP34xx_ES1:
3957                 src = &omap34xx_rev1_0_dispc_feats;
3958                 break;
3959
3960         case OMAPDSS_VER_OMAP34xx_ES3:
3961         case OMAPDSS_VER_OMAP3630:
3962         case OMAPDSS_VER_AM35xx:
3963         case OMAPDSS_VER_AM43xx:
3964                 src = &omap34xx_rev3_0_dispc_feats;
3965                 break;
3966
3967         case OMAPDSS_VER_OMAP4430_ES1:
3968         case OMAPDSS_VER_OMAP4430_ES2:
3969         case OMAPDSS_VER_OMAP4:
3970                 src = &omap44xx_dispc_feats;
3971                 break;
3972
3973         case OMAPDSS_VER_OMAP5:
3974         case OMAPDSS_VER_DRA7xx:
3975                 src = &omap54xx_dispc_feats;
3976                 break;
3977
3978         default:
3979                 return -ENODEV;
3980         }
3981
3982         memcpy(dst, src, sizeof(*dst));
3983         dispc.feat = dst;
3984
3985         return 0;
3986 }
3987
3988 static irqreturn_t dispc_irq_handler(int irq, void *arg)
3989 {
3990         if (!dispc.is_enabled)
3991                 return IRQ_NONE;
3992
3993         return dispc.user_handler(irq, dispc.user_data);
3994 }
3995
3996 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3997 {
3998         int r;
3999
4000         if (dispc.user_handler != NULL)
4001                 return -EBUSY;
4002
4003         dispc.user_handler = handler;
4004         dispc.user_data = dev_id;
4005
4006         /* ensure the dispc_irq_handler sees the values above */
4007         smp_wmb();
4008
4009         r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4010                              IRQF_SHARED, "OMAP DISPC", &dispc);
4011         if (r) {
4012                 dispc.user_handler = NULL;
4013                 dispc.user_data = NULL;
4014         }
4015
4016         return r;
4017 }
4018 EXPORT_SYMBOL(dispc_request_irq);
4019
4020 void dispc_free_irq(void *dev_id)
4021 {
4022         devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4023
4024         dispc.user_handler = NULL;
4025         dispc.user_data = NULL;
4026 }
4027 EXPORT_SYMBOL(dispc_free_irq);
4028
4029 /* DISPC HW IP initialisation */
4030 static int dispc_bind(struct device *dev, struct device *master, void *data)
4031 {
4032         struct platform_device *pdev = to_platform_device(dev);
4033         u32 rev;
4034         int r = 0;
4035         struct resource *dispc_mem;
4036         struct device_node *np = pdev->dev.of_node;
4037
4038         dispc.pdev = pdev;
4039
4040         spin_lock_init(&dispc.control_lock);
4041
4042         r = dispc_init_features(dispc.pdev);
4043         if (r)
4044                 return r;
4045
4046         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4047         if (!dispc_mem) {
4048                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4049                 return -EINVAL;
4050         }
4051
4052         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4053                                   resource_size(dispc_mem));
4054         if (!dispc.base) {
4055                 DSSERR("can't ioremap DISPC\n");
4056                 return -ENOMEM;
4057         }
4058
4059         dispc.irq = platform_get_irq(dispc.pdev, 0);
4060         if (dispc.irq < 0) {
4061                 DSSERR("platform_get_irq failed\n");
4062                 return -ENODEV;
4063         }
4064
4065         if (np && of_property_read_bool(np, "syscon-pol")) {
4066                 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4067                 if (IS_ERR(dispc.syscon_pol)) {
4068                         dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4069                         return PTR_ERR(dispc.syscon_pol);
4070                 }
4071
4072                 if (of_property_read_u32_index(np, "syscon-pol", 1,
4073                                 &dispc.syscon_pol_offset)) {
4074                         dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4075                         return -EINVAL;
4076                 }
4077         }
4078
4079         pm_runtime_enable(&pdev->dev);
4080
4081         r = dispc_runtime_get();
4082         if (r)
4083                 goto err_runtime_get;
4084
4085         _omap_dispc_initial_config();
4086
4087         rev = dispc_read_reg(DISPC_REVISION);
4088         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4089                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4090
4091         dispc_runtime_put();
4092
4093         dss_debugfs_create_file("dispc", dispc_dump_regs);
4094
4095         return 0;
4096
4097 err_runtime_get:
4098         pm_runtime_disable(&pdev->dev);
4099         return r;
4100 }
4101
4102 static void dispc_unbind(struct device *dev, struct device *master,
4103                                void *data)
4104 {
4105         pm_runtime_disable(dev);
4106 }
4107
4108 static const struct component_ops dispc_component_ops = {
4109         .bind   = dispc_bind,
4110         .unbind = dispc_unbind,
4111 };
4112
4113 static int dispc_probe(struct platform_device *pdev)
4114 {
4115         return component_add(&pdev->dev, &dispc_component_ops);
4116 }
4117
4118 static int dispc_remove(struct platform_device *pdev)
4119 {
4120         component_del(&pdev->dev, &dispc_component_ops);
4121         return 0;
4122 }
4123
4124 static int dispc_runtime_suspend(struct device *dev)
4125 {
4126         dispc.is_enabled = false;
4127         /* ensure the dispc_irq_handler sees the is_enabled value */
4128         smp_wmb();
4129         /* wait for current handler to finish before turning the DISPC off */
4130         synchronize_irq(dispc.irq);
4131
4132         dispc_save_context();
4133
4134         return 0;
4135 }
4136
4137 static int dispc_runtime_resume(struct device *dev)
4138 {
4139         /*
4140          * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4141          * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4142          * _omap_dispc_initial_config(). We can thus use it to detect if
4143          * we have lost register context.
4144          */
4145         if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4146                 _omap_dispc_initial_config();
4147
4148                 dispc_restore_context();
4149         }
4150
4151         dispc.is_enabled = true;
4152         /* ensure the dispc_irq_handler sees the is_enabled value */
4153         smp_wmb();
4154
4155         return 0;
4156 }
4157
4158 static const struct dev_pm_ops dispc_pm_ops = {
4159         .runtime_suspend = dispc_runtime_suspend,
4160         .runtime_resume = dispc_runtime_resume,
4161 };
4162
4163 static const struct of_device_id dispc_of_match[] = {
4164         { .compatible = "ti,omap2-dispc", },
4165         { .compatible = "ti,omap3-dispc", },
4166         { .compatible = "ti,omap4-dispc", },
4167         { .compatible = "ti,omap5-dispc", },
4168         { .compatible = "ti,dra7-dispc", },
4169         {},
4170 };
4171
4172 static struct platform_driver omap_dispchw_driver = {
4173         .probe          = dispc_probe,
4174         .remove         = dispc_remove,
4175         .driver         = {
4176                 .name   = "omapdss_dispc",
4177                 .pm     = &dispc_pm_ops,
4178                 .of_match_table = dispc_of_match,
4179                 .suppress_bind_attrs = true,
4180         },
4181 };
4182
4183 int __init dispc_init_platform_driver(void)
4184 {
4185         return platform_driver_register(&omap_dispchw_driver);
4186 }
4187
4188 void dispc_uninit_platform_driver(void)
4189 {
4190         platform_driver_unregister(&omap_dispchw_driver);
4191 }