drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30 #include "soc15_hw_ip.h"
  31
  32 union firmware_info {
  33         struct atom_firmware_info_v3_1 v31;
  34         struct atom_firmware_info_v3_2 v32;
  35         struct atom_firmware_info_v3_3 v33;
  36         struct atom_firmware_info_v3_4 v34;
  37         struct atom_firmware_info_v3_5 v35;
  38 };
  39
  40 /*
  41  * Helper function to query firmware capability
  42  *
  43  * @adev: amdgpu_device pointer
  44  *
  45  * Return firmware_capability in firmwareinfo table on success or 0 if not
  46  */
  47 uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)
  48 {
  49         struct amdgpu_mode_info *mode_info = &adev->mode_info;
  50         int index;
  51         u16 data_offset, size;
  52         union firmware_info *firmware_info;
  53         u8 frev, crev;
  54         u32 fw_cap = 0;
  55
  56         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  57                         firmwareinfo);
  58
  59         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
  60                                 index, &size, &frev, &crev, &data_offset)) {
  61                 /* support firmware_info 3.1 + */
  62                 if ((frev == 3 && crev >= 1) || (frev > 3)) {
  63                         firmware_info = (union firmware_info *)
  64                                 (mode_info->atom_context->bios + data_offset);
  65                         fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
  66                 }
  67         }
  68
  69         return fw_cap;
  70 }
  71
  72 /*
  73  * Helper function to query gpu virtualizaiton capability
  74  *
  75  * @adev: amdgpu_device pointer
  76  *
  77  * Return true if gpu virtualization is supported or false if not
  78  */
  79 bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev)
  80 {
  81         u32 fw_cap;
  82
  83         fw_cap = adev->mode_info.firmware_flags;
  84
  85         return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;
  86 }
  87
  88 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  89 {
  90         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  91                                                 firmwareinfo);
  92         uint16_t data_offset;
  93
  94         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  95                                           NULL, NULL, &data_offset)) {
  96                 struct atom_firmware_info_v3_1 *firmware_info =
  97                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  98                                                            data_offset);
  99
 100                 adev->bios_scratch_reg_offset =
 101                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
 102         }
 103 }
 104
 105 static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
 106         struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes)
 107 {
 108         u32 start_addr, fw_size, drv_size;
 109
 110         start_addr = le32_to_cpu(fw_usage->start_address_in_kb);
 111         fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
 112         drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb);
 113
 114         DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
 115                           start_addr,
 116                           fw_size,
 117                           drv_size);
 118
 119         if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
 120                 (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
 121                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
 122                 /* Firmware request VRAM reservation for SR-IOV */
 123                 adev->mman.fw_vram_usage_start_offset = (start_addr &
 124                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 125                 adev->mman.fw_vram_usage_size = fw_size << 10;
 126                 /* Use the default scratch size */
 127                 *usage_bytes = 0;
 128         } else {
 129                 *usage_bytes = drv_size << 10;
 130         }
 131         return 0;
 132 }
 133
 134 static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
 135                 struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes)
 136 {
 137         u32 fw_start_addr, fw_size, drv_start_addr, drv_size;
 138
 139         fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb);
 140         fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
 141
 142         drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb);
 143         drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb);
 144
 145         DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n",
 146                           fw_start_addr,
 147                           fw_size,
 148                           drv_start_addr,
 149                           drv_size);
 150
 151         if (amdgpu_sriov_vf(adev) &&
 152             ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
 153                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
 154                 /* Firmware request VRAM reservation for SR-IOV */
 155                 adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
 156                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 157                 adev->mman.fw_vram_usage_size = fw_size << 10;
 158         }
 159
 160         if (amdgpu_sriov_vf(adev) &&
 161             ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
 162                 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
 163                 /* driver request VRAM reservation for SR-IOV */
 164                 adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
 165                         (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
 166                 adev->mman.drv_vram_usage_size = drv_size << 10;
 167         }
 168
 169         *usage_bytes = 0;
 170         return 0;
 171 }
 172
 173 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 174 {
 175         struct atom_context *ctx = adev->mode_info.atom_context;
 176         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 177                                                 vram_usagebyfirmware);
 178         struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1;
 179         struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2;
 180         u16 data_offset;
 181         u8 frev, crev;
 182         int usage_bytes = 0;
 183
 184         if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) {
 185                 if (frev == 2 && crev == 1) {
 186                         fw_usage_v2_1 =
 187                                 (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
 188                         amdgpu_atomfirmware_allocate_fb_v2_1(adev,
 189                                         fw_usage_v2_1,
 190                                         &usage_bytes);
 191                 } else if (frev >= 2 && crev >= 2) {
 192                         fw_usage_v2_2 =
 193                                 (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset);
 194                         amdgpu_atomfirmware_allocate_fb_v2_2(adev,
 195                                         fw_usage_v2_2,
 196                                         &usage_bytes);
 197                 }
 198         }
 199
 200         ctx->scratch_size_bytes = 0;
 201         if (usage_bytes == 0)
 202                 usage_bytes = 20 * 1024;
 203         /* allocate some scratch memory */
 204         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 205         if (!ctx->scratch)
 206                 return -ENOMEM;
 207         ctx->scratch_size_bytes = usage_bytes;
 208         return 0;
 209 }
 210
 211 union igp_info {
 212         struct atom_integrated_system_info_v1_11 v11;
 213         struct atom_integrated_system_info_v1_12 v12;
 214         struct atom_integrated_system_info_v2_1 v21;
 215 };
 216
 217 union umc_info {
 218         struct atom_umc_info_v3_1 v31;
 219         struct atom_umc_info_v3_2 v32;
 220         struct atom_umc_info_v3_3 v33;
 221         struct atom_umc_info_v4_0 v40;
 222 };
 223
 224 union vram_info {
 225         struct atom_vram_info_header_v2_3 v23;
 226         struct atom_vram_info_header_v2_4 v24;
 227         struct atom_vram_info_header_v2_5 v25;
 228         struct atom_vram_info_header_v2_6 v26;
 229         struct atom_vram_info_header_v3_0 v30;
 230 };
 231
 232 union vram_module {
 233         struct atom_vram_module_v9 v9;
 234         struct atom_vram_module_v10 v10;
 235         struct atom_vram_module_v11 v11;
 236         struct atom_vram_module_v3_0 v30;
 237 };
 238
 239 static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 240                                               int atom_mem_type)
 241 {
 242         int vram_type;
 243
 244         if (adev->flags & AMD_IS_APU) {
 245                 switch (atom_mem_type) {
 246                 case Ddr2MemType:
 247                 case LpDdr2MemType:
 248                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 249                         break;
 250                 case Ddr3MemType:
 251                 case LpDdr3MemType:
 252                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 253                         break;
 254                 case Ddr4MemType:
 255                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 256                         break;
 257                 case LpDdr4MemType:
 258                         vram_type = AMDGPU_VRAM_TYPE_LPDDR4;
 259                         break;
 260                 case Ddr5MemType:
 261                         vram_type = AMDGPU_VRAM_TYPE_DDR5;
 262                         break;
 263                 case LpDdr5MemType:
 264                         vram_type = AMDGPU_VRAM_TYPE_LPDDR5;
 265                         break;
 266                 default:
 267                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 268                         break;
 269                 }
 270         } else {
 271                 switch (atom_mem_type) {
 272                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 273                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 274                         break;
 275                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 276                 case ATOM_DGPU_VRAM_TYPE_HBM2E:
 277                 case ATOM_DGPU_VRAM_TYPE_HBM3:
 278                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 279                         break;
 280                 case ATOM_DGPU_VRAM_TYPE_GDDR6:
 281                         vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 282                         break;
 283                 default:
 284                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 285                         break;
 286                 }
 287         }
 288
 289         return vram_type;
 290 }
 291
 292
 293 int
 294 amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 295                                   int *vram_width, int *vram_type,
 296                                   int *vram_vendor)
 297 {
 298         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 299         int index, i = 0;
 300         u16 data_offset, size;
 301         union igp_info *igp_info;
 302         union vram_info *vram_info;
 303         union vram_module *vram_module;
 304         u8 frev, crev;
 305         u8 mem_type;
 306         u8 mem_vendor;
 307         u32 mem_channel_number;
 308         u32 mem_channel_width;
 309         u32 module_id;
 310
 311         if (adev->flags & AMD_IS_APU)
 312                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 313                                                     integratedsysteminfo);
 314         else
 315                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 316                                                     vram_info);
 317
 318         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 319                                           index, &size,
 320                                           &frev, &crev, &data_offset)) {
 321                 if (adev->flags & AMD_IS_APU) {
 322                         igp_info = (union igp_info *)
 323                                 (mode_info->atom_context->bios + data_offset);
 324                         switch (frev) {
 325                         case 1:
 326                                 switch (crev) {
 327                                 case 11:
 328                                 case 12:
 329                                         mem_channel_number = igp_info->v11.umachannelnumber;
 330                                         if (!mem_channel_number)
 331                                                 mem_channel_number = 1;
 332                                         mem_type = igp_info->v11.memorytype;
 333                                         if (mem_type == LpDdr5MemType)
 334                                                 mem_channel_width = 32;
 335                                         else
 336                                                 mem_channel_width = 64;
 337                                         if (vram_width)
 338                                                 *vram_width = mem_channel_number * mem_channel_width;
 339                                         if (vram_type)
 340                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 341                                         break;
 342                                 default:
 343                                         return -EINVAL;
 344                                 }
 345                                 break;
 346                         case 2:
 347                                 switch (crev) {
 348                                 case 1:
 349                                 case 2:
 350                                         mem_channel_number = igp_info->v21.umachannelnumber;
 351                                         if (!mem_channel_number)
 352                                                 mem_channel_number = 1;
 353                                         mem_type = igp_info->v21.memorytype;
 354                                         if (mem_type == LpDdr5MemType)
 355                                                 mem_channel_width = 32;
 356                                         else
 357                                                 mem_channel_width = 64;
 358                                         if (vram_width)
 359                                                 *vram_width = mem_channel_number * mem_channel_width;
 360                                         if (vram_type)
 361                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 362                                         break;
 363                                 default:
 364                                         return -EINVAL;
 365                                 }
 366                                 break;
 367                         default:
 368                                 return -EINVAL;
 369                         }
 370                 } else {
 371                         vram_info = (union vram_info *)
 372                                 (mode_info->atom_context->bios + data_offset);
 373                         module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
 374                         if (frev == 3) {
 375                                 switch (crev) {
 376                                 /* v30 */
 377                                 case 0:
 378                                         vram_module = (union vram_module *)vram_info->v30.vram_module;
 379                                         mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
 380                                         if (vram_vendor)
 381                                                 *vram_vendor = mem_vendor;
 382                                         mem_type = vram_info->v30.memory_type;
 383                                         if (vram_type)
 384                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 385                                         mem_channel_number = vram_info->v30.channel_num;
 386                                         mem_channel_width = vram_info->v30.channel_width;
 387                                         if (vram_width)
 388                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 389                                         break;
 390                                 default:
 391                                         return -EINVAL;
 392                                 }
 393                         } else if (frev == 2) {
 394                                 switch (crev) {
 395                                 /* v23 */
 396                                 case 3:
 397                                         if (module_id > vram_info->v23.vram_module_num)
 398                                                 module_id = 0;
 399                                         vram_module = (union vram_module *)vram_info->v23.vram_module;
 400                                         while (i < module_id) {
 401                                                 vram_module = (union vram_module *)
 402                                                         ((u8 *)vram_module + vram_module->v9.vram_module_size);
 403                                                 i++;
 404                                         }
 405                                         mem_type = vram_module->v9.memory_type;
 406                                         if (vram_type)
 407                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 408                                         mem_channel_number = vram_module->v9.channel_num;
 409                                         mem_channel_width = vram_module->v9.channel_width;
 410                                         if (vram_width)
 411                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 412                                         mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 413                                         if (vram_vendor)
 414                                                 *vram_vendor = mem_vendor;
 415                                         break;
 416                                 /* v24 */
 417                                 case 4:
 418                                         if (module_id > vram_info->v24.vram_module_num)
 419                                                 module_id = 0;
 420                                         vram_module = (union vram_module *)vram_info->v24.vram_module;
 421                                         while (i < module_id) {
 422                                                 vram_module = (union vram_module *)
 423                                                         ((u8 *)vram_module + vram_module->v10.vram_module_size);
 424                                                 i++;
 425                                         }
 426                                         mem_type = vram_module->v10.memory_type;
 427                                         if (vram_type)
 428                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 429                                         mem_channel_number = vram_module->v10.channel_num;
 430                                         mem_channel_width = vram_module->v10.channel_width;
 431                                         if (vram_width)
 432                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 433                                         mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
 434                                         if (vram_vendor)
 435                                                 *vram_vendor = mem_vendor;
 436                                         break;
 437                                 /* v25 */
 438                                 case 5:
 439                                         if (module_id > vram_info->v25.vram_module_num)
 440                                                 module_id = 0;
 441                                         vram_module = (union vram_module *)vram_info->v25.vram_module;
 442                                         while (i < module_id) {
 443                                                 vram_module = (union vram_module *)
 444                                                         ((u8 *)vram_module + vram_module->v11.vram_module_size);
 445                                                 i++;
 446                                         }
 447                                         mem_type = vram_module->v11.memory_type;
 448                                         if (vram_type)
 449                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 450                                         mem_channel_number = vram_module->v11.channel_num;
 451                                         mem_channel_width = vram_module->v11.channel_width;
 452                                         if (vram_width)
 453                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 454                                         mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
 455                                         if (vram_vendor)
 456                                                 *vram_vendor = mem_vendor;
 457                                         break;
 458                                 /* v26 */
 459                                 case 6:
 460                                         if (module_id > vram_info->v26.vram_module_num)
 461                                                 module_id = 0;
 462                                         vram_module = (union vram_module *)vram_info->v26.vram_module;
 463                                         while (i < module_id) {
 464                                                 vram_module = (union vram_module *)
 465                                                         ((u8 *)vram_module + vram_module->v9.vram_module_size);
 466                                                 i++;
 467                                         }
 468                                         mem_type = vram_module->v9.memory_type;
 469                                         if (vram_type)
 470                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 471                                         mem_channel_number = vram_module->v9.channel_num;
 472                                         mem_channel_width = vram_module->v9.channel_width;
 473                                         if (vram_width)
 474                                                 *vram_width = mem_channel_number * (1 << mem_channel_width);
 475                                         mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
 476                                         if (vram_vendor)
 477                                                 *vram_vendor = mem_vendor;
 478                                         break;
 479                                 default:
 480                                         return -EINVAL;
 481                                 }
 482                         } else {
 483                                 /* invalid frev */
 484                                 return -EINVAL;
 485                         }
 486                 }
 487
 488         }
 489
 490         return 0;
 491 }
 492
 493 /*
 494  * Return true if vbios enabled ecc by default, if umc info table is available
 495  * or false if ecc is not enabled or umc info table is not available
 496  */
 497 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 498 {
 499         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 500         int index;
 501         u16 data_offset, size;
 502         union umc_info *umc_info;
 503         u8 frev, crev;
 504         bool ecc_default_enabled = false;
 505         u8 umc_config;
 506         u32 umc_config1;
 507
 508         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 509                         umc_info);
 510
 511         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 512                                 index, &size, &frev, &crev, &data_offset)) {
 513                 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
 514                 if (frev == 3) {
 515                         switch (crev) {
 516                         case 1:
 517                                 umc_config = le32_to_cpu(umc_info->v31.umc_config);
 518                                 ecc_default_enabled =
 519                                         (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 520                                 break;
 521                         case 2:
 522                                 umc_config = le32_to_cpu(umc_info->v32.umc_config);
 523                                 ecc_default_enabled =
 524                                         (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 525                                 break;
 526                         case 3:
 527                                 umc_config = le32_to_cpu(umc_info->v33.umc_config);
 528                                 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
 529                                 ecc_default_enabled =
 530                                         ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||
 531                                          (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
 532                                 break;
 533                         default:
 534                                 /* unsupported crev */
 535                                 return false;
 536                         }
 537                 } else if (frev == 4) {
 538                         switch (crev) {
 539                         case 0:
 540                                 umc_config1 = le32_to_cpu(umc_info->v40.umc_config1);
 541                                 ecc_default_enabled =
 542                                         (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;
 543                                 break;
 544                         default:
 545                                 /* unsupported crev */
 546                                 return false;
 547                         }
 548                 } else {
 549                         /* unsupported frev */
 550                         return false;
 551                 }
 552         }
 553
 554         return ecc_default_enabled;
 555 }
 556
 557 /*
 558  * Helper function to query sram ecc capablity
 559  *
 560  * @adev: amdgpu_device pointer
 561  *
 562  * Return true if vbios supports sram ecc or false if not
 563  */
 564 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 565 {
 566         u32 fw_cap;
 567
 568         fw_cap = adev->mode_info.firmware_flags;
 569
 570         return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 571 }
 572
 573 /*
 574  * Helper function to query dynamic boot config capability
 575  *
 576  * @adev: amdgpu_device pointer
 577  *
 578  * Return true if vbios supports dynamic boot config or false if not
 579  */
 580 bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev)
 581 {
 582         u32 fw_cap;
 583
 584         fw_cap = adev->mode_info.firmware_flags;
 585
 586         return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
 587 }
 588
 589 /**
 590  * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS
 591  * @adev: amdgpu_device pointer
 592  * @i2c_address: pointer to u8; if not NULL, will contain
 593  *    the RAS EEPROM address if the function returns true
 594  *
 595  * Return true if VBIOS supports RAS EEPROM address reporting,
 596  * else return false. If true and @i2c_address is not NULL,
 597  * will contain the RAS ROM address.
 598  */
 599 bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
 600                                       u8 *i2c_address)
 601 {
 602         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 603         int index;
 604         u16 data_offset, size;
 605         union firmware_info *firmware_info;
 606         u8 frev, crev;
 607
 608         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 609                                             firmwareinfo);
 610
 611         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 612                                           index, &size, &frev, &crev,
 613                                           &data_offset)) {
 614                 /* support firmware_info 3.4 + */
 615                 if ((frev == 3 && crev >= 4) || (frev > 3)) {
 616                         firmware_info = (union firmware_info *)
 617                                 (mode_info->atom_context->bios + data_offset);
 618                         /* The ras_rom_i2c_slave_addr should ideally
 619                          * be a 19-bit EEPROM address, which would be
 620                          * used as is by the driver; see top of
 621                          * amdgpu_eeprom.c.
 622                          *
 623                          * When this is the case, 0 is of course a
 624                          * valid RAS EEPROM address, in which case,
 625                          * we'll drop the first "if (firm...)" and only
 626                          * leave the check for the pointer.
 627                          *
 628                          * The reason this works right now is because
 629                          * ras_rom_i2c_slave_addr contains the EEPROM
 630                          * device type qualifier 1010b in the top 4
 631                          * bits.
 632                          */
 633                         if (firmware_info->v34.ras_rom_i2c_slave_addr) {
 634                                 if (i2c_address)
 635                                         *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
 636                                 return true;
 637                         }
 638                 }
 639         }
 640
 641         return false;
 642 }
 643
 644
 645 union smu_info {
 646         struct atom_smu_info_v3_1 v31;
 647         struct atom_smu_info_v4_0 v40;
 648 };
 649
 650 union gfx_info {
 651         struct atom_gfx_info_v2_2 v22;
 652         struct atom_gfx_info_v2_4 v24;
 653         struct atom_gfx_info_v2_7 v27;
 654         struct atom_gfx_info_v3_0 v30;
 655 };
 656
 657 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 658 {
 659         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 660         struct amdgpu_pll *spll = &adev->clock.spll;
 661         struct amdgpu_pll *mpll = &adev->clock.mpll;
 662         uint8_t frev, crev;
 663         uint16_t data_offset;
 664         int ret = -EINVAL, index;
 665
 666         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 667                                             firmwareinfo);
 668         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 669                                    &frev, &crev, &data_offset)) {
 670                 union firmware_info *firmware_info =
 671                         (union firmware_info *)(mode_info->atom_context->bios +
 672                                                 data_offset);
 673
 674                 adev->clock.default_sclk =
 675                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 676                 adev->clock.default_mclk =
 677                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 678
 679                 adev->pm.current_sclk = adev->clock.default_sclk;
 680                 adev->pm.current_mclk = adev->clock.default_mclk;
 681
 682                 ret = 0;
 683         }
 684
 685         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 686                                             smu_info);
 687         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 688                                    &frev, &crev, &data_offset)) {
 689                 union smu_info *smu_info =
 690                         (union smu_info *)(mode_info->atom_context->bios +
 691                                            data_offset);
 692
 693                 /* system clock */
 694                 if (frev == 3)
 695                         spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 696                 else if (frev == 4)
 697                         spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz);
 698
 699                 spll->reference_div = 0;
 700                 spll->min_post_div = 1;
 701                 spll->max_post_div = 1;
 702                 spll->min_ref_div = 2;
 703                 spll->max_ref_div = 0xff;
 704                 spll->min_feedback_div = 4;
 705                 spll->max_feedback_div = 0xff;
 706                 spll->best_vco = 0;
 707
 708                 ret = 0;
 709         }
 710
 711         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 712                                             umc_info);
 713         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 714                                    &frev, &crev, &data_offset)) {
 715                 union umc_info *umc_info =
 716                         (union umc_info *)(mode_info->atom_context->bios +
 717                                            data_offset);
 718
 719                 /* memory clock */
 720                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 721
 722                 mpll->reference_div = 0;
 723                 mpll->min_post_div = 1;
 724                 mpll->max_post_div = 1;
 725                 mpll->min_ref_div = 2;
 726                 mpll->max_ref_div = 0xff;
 727                 mpll->min_feedback_div = 4;
 728                 mpll->max_feedback_div = 0xff;
 729                 mpll->best_vco = 0;
 730
 731                 ret = 0;
 732         }
 733
 734         /* if asic is Navi+, the rlc reference clock is used for system clock
 735          * from vbios gfx_info table */
 736         if (adev->asic_type >= CHIP_NAVI10) {
 737                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 738                                                    gfx_info);
 739                 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 740                                           &frev, &crev, &data_offset)) {
 741                         union gfx_info *gfx_info = (union gfx_info *)
 742                                 (mode_info->atom_context->bios + data_offset);
 743                         if ((frev == 3) ||
 744                             (frev == 2 && crev == 6)) {
 745                                 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);
 746                                 ret = 0;
 747                         } else if ((frev == 2) &&
 748                                    (crev >= 2) &&
 749                                    (crev != 6)) {
 750                                 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);
 751                                 ret = 0;
 752                         } else {
 753                                 BUG();
 754                         }
 755                 }
 756         }
 757
 758         return ret;
 759 }
 760
 761 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 762 {
 763         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 764         int index;
 765         uint8_t frev, crev;
 766         uint16_t data_offset;
 767
 768         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 769                                             gfx_info);
 770         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 771                                    &frev, &crev, &data_offset)) {
 772                 union gfx_info *gfx_info = (union gfx_info *)
 773                         (mode_info->atom_context->bios + data_offset);
 774                 if (frev == 2) {
 775                         switch (crev) {
 776                         case 4:
 777                                 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 778                                 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 779                                 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 780                                 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 781                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 782                                 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 783                                 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 784                                 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 785                                 adev->gfx.config.gs_prim_buffer_depth =
 786                                         le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 787                                 adev->gfx.config.double_offchip_lds_buf =
 788                                         gfx_info->v24.gc_double_offchip_lds_buffer;
 789                                 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 790                                 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 791                                 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 792                                 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 793                                 return 0;
 794                         case 7:
 795                                 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
 796                                 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
 797                                 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
 798                                 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
 799                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
 800                                 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
 801                                 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
 802                                 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
 803                                 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
 804                                 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
 805                                 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
 806                                 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
 807                                 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
 808                                 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
 809                                 return 0;
 810                         default:
 811                                 return -EINVAL;
 812                         }
 813                 } else if (frev == 3) {
 814                         switch (crev) {
 815                         case 0:
 816                                 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;
 817                                 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;
 818                                 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;
 819                                 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;
 820                                 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;
 821                                 return 0;
 822                         default:
 823                                 return -EINVAL;
 824                         }
 825                 } else {
 826                         return -EINVAL;
 827                 }
 828
 829         }
 830         return -EINVAL;
 831 }
 832
 833 /*
 834  * Helper function to query two stage mem training capability
 835  *
 836  * @adev: amdgpu_device pointer
 837  *
 838  * Return true if two stage mem training is supported or false if not
 839  */
 840 bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev)
 841 {
 842         u32 fw_cap;
 843
 844         fw_cap = adev->mode_info.firmware_flags;
 845
 846         return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;
 847 }
 848
 849 int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
 850 {
 851         struct atom_context *ctx = adev->mode_info.atom_context;
 852         union firmware_info *firmware_info;
 853         int index;
 854         u16 data_offset, size;
 855         u8 frev, crev;
 856         int fw_reserved_fb_size;
 857
 858         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 859                         firmwareinfo);
 860
 861         if (!amdgpu_atom_parse_data_header(ctx, index, &size,
 862                                 &frev, &crev, &data_offset))
 863                 /* fail to parse data_header */
 864                 return 0;
 865
 866         firmware_info = (union firmware_info *)(ctx->bios + data_offset);
 867
 868         if (frev != 3)
 869                 return -EINVAL;
 870
 871         switch (crev) {
 872         case 4:
 873                 fw_reserved_fb_size =
 874                         (firmware_info->v34.fw_reserved_size_in_kb << 10);
 875                 break;
 876         case 5:
 877                 fw_reserved_fb_size =
 878                         (firmware_info->v35.fw_reserved_size_in_kb << 10);
 879                 break;
 880         default:
 881                 fw_reserved_fb_size = 0;
 882                 break;
 883         }
 884
 885         return fw_reserved_fb_size;
 886 }
 887
 888 /*
 889  * Helper function to execute asic_init table
 890  *
 891  * @adev: amdgpu_device pointer
 892  * @fb_reset: flag to indicate whether fb is reset or not
 893  *
 894  * Return 0 if succeed, otherwise failed
 895  */
 896 int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)
 897 {
 898         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 899         struct atom_context *ctx;
 900         uint8_t frev, crev;
 901         uint16_t data_offset;
 902         uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz;
 903         struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1;
 904         int index;
 905
 906         if (!mode_info)
 907                 return -EINVAL;
 908
 909         ctx = mode_info->atom_context;
 910         if (!ctx)
 911                 return -EINVAL;
 912
 913         /* query bootup sclk/mclk from firmware_info table */
 914         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 915                                             firmwareinfo);
 916         if (amdgpu_atom_parse_data_header(ctx, index, NULL,
 917                                 &frev, &crev, &data_offset)) {
 918                 union firmware_info *firmware_info =
 919                         (union firmware_info *)(ctx->bios +
 920                                                 data_offset);
 921
 922                 bootup_sclk_in10khz =
 923                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 924                 bootup_mclk_in10khz =
 925                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 926         } else {
 927                 return -EINVAL;
 928         }
 929
 930         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 931                                         asic_init);
 932         if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) {
 933                 if (frev == 2 && crev >= 1) {
 934                         memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1));
 935                         asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz;
 936                         asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz;
 937                         asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT;
 938                         if (!fb_reset)
 939                                 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT;
 940                         else
 941                                 asic_init_ps_v2_1.param.memparam.memflag = 0;
 942                 } else {
 943                         return -EINVAL;
 944                 }
 945         } else {
 946                 return -EINVAL;
 947         }
 948
 949         return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, (uint32_t *)&asic_init_ps_v2_1,
 950                 sizeof(asic_init_ps_v2_1));
 951 }