drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *    Daniel Vetter <[email protected]>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 const char *
  69 intel_display_power_domain_str(enum intel_display_power_domain domain)
  70 {
  71         switch (domain) {
  72         case POWER_DOMAIN_PIPE_A:
  73                 return "PIPE_A";
  74         case POWER_DOMAIN_PIPE_B:
  75                 return "PIPE_B";
  76         case POWER_DOMAIN_PIPE_C:
  77                 return "PIPE_C";
  78         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  79                 return "PIPE_A_PANEL_FITTER";
  80         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  81                 return "PIPE_B_PANEL_FITTER";
  82         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  83                 return "PIPE_C_PANEL_FITTER";
  84         case POWER_DOMAIN_TRANSCODER_A:
  85                 return "TRANSCODER_A";
  86         case POWER_DOMAIN_TRANSCODER_B:
  87                 return "TRANSCODER_B";
  88         case POWER_DOMAIN_TRANSCODER_C:
  89                 return "TRANSCODER_C";
  90         case POWER_DOMAIN_TRANSCODER_EDP:
  91                 return "TRANSCODER_EDP";
  92         case POWER_DOMAIN_TRANSCODER_DSI_A:
  93                 return "TRANSCODER_DSI_A";
  94         case POWER_DOMAIN_TRANSCODER_DSI_C:
  95                 return "TRANSCODER_DSI_C";
  96         case POWER_DOMAIN_PORT_DDI_A_LANES:
  97                 return "PORT_DDI_A_LANES";
  98         case POWER_DOMAIN_PORT_DDI_B_LANES:
  99                 return "PORT_DDI_B_LANES";
 100         case POWER_DOMAIN_PORT_DDI_C_LANES:
 101                 return "PORT_DDI_C_LANES";
 102         case POWER_DOMAIN_PORT_DDI_D_LANES:
 103                 return "PORT_DDI_D_LANES";
 104         case POWER_DOMAIN_PORT_DDI_E_LANES:
 105                 return "PORT_DDI_E_LANES";
 106         case POWER_DOMAIN_PORT_DSI:
 107                 return "PORT_DSI";
 108         case POWER_DOMAIN_PORT_CRT:
 109                 return "PORT_CRT";
 110         case POWER_DOMAIN_PORT_OTHER:
 111                 return "PORT_OTHER";
 112         case POWER_DOMAIN_VGA:
 113                 return "VGA";
 114         case POWER_DOMAIN_AUDIO:
 115                 return "AUDIO";
 116         case POWER_DOMAIN_PLLS:
 117                 return "PLLS";
 118         case POWER_DOMAIN_AUX_A:
 119                 return "AUX_A";
 120         case POWER_DOMAIN_AUX_B:
 121                 return "AUX_B";
 122         case POWER_DOMAIN_AUX_C:
 123                 return "AUX_C";
 124         case POWER_DOMAIN_AUX_D:
 125                 return "AUX_D";
 126         case POWER_DOMAIN_GMBUS:
 127                 return "GMBUS";
 128         case POWER_DOMAIN_INIT:
 129                 return "INIT";
 130         case POWER_DOMAIN_MODESET:
 131                 return "MODESET";
 132         default:
 133                 MISSING_CASE(domain);
 134                 return "?";
 135         }
 136 }
 137
 138 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 139                                     struct i915_power_well *power_well)
 140 {
 141         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 142         power_well->ops->enable(dev_priv, power_well);
 143         power_well->hw_enabled = true;
 144 }
 145
 146 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 147                                      struct i915_power_well *power_well)
 148 {
 149         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 150         power_well->hw_enabled = false;
 151         power_well->ops->disable(dev_priv, power_well);
 152 }
 153
 154 /*
 155  * We should only use the power well if we explicitly asked the hardware to
 156  * enable it, so check if it's enabled and also check if we've requested it to
 157  * be enabled.
 158  */
 159 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 160                                    struct i915_power_well *power_well)
 161 {
 162         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 163                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 164 }
 165
 166 /**
 167  * __intel_display_power_is_enabled - unlocked check for a power domain
 168  * @dev_priv: i915 device instance
 169  * @domain: power domain to check
 170  *
 171  * This is the unlocked version of intel_display_power_is_enabled() and should
 172  * only be used from error capture and recovery code where deadlocks are
 173  * possible.
 174  *
 175  * Returns:
 176  * True when the power domain is enabled, false otherwise.
 177  */
 178 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 179                                       enum intel_display_power_domain domain)
 180 {
 181         struct i915_power_domains *power_domains;
 182         struct i915_power_well *power_well;
 183         bool is_enabled;
 184         int i;
 185
 186         if (dev_priv->pm.suspended)
 187                 return false;
 188
 189         power_domains = &dev_priv->power_domains;
 190
 191         is_enabled = true;
 192
 193         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 194                 if (power_well->always_on)
 195                         continue;
 196
 197                 if (!power_well->hw_enabled) {
 198                         is_enabled = false;
 199                         break;
 200                 }
 201         }
 202
 203         return is_enabled;
 204 }
 205
 206 /**
 207  * intel_display_power_is_enabled - check for a power domain
 208  * @dev_priv: i915 device instance
 209  * @domain: power domain to check
 210  *
 211  * This function can be used to check the hw power domain state. It is mostly
 212  * used in hardware state readout functions. Everywhere else code should rely
 213  * upon explicit power domain reference counting to ensure that the hardware
 214  * block is powered up before accessing it.
 215  *
 216  * Callers must hold the relevant modesetting locks to ensure that concurrent
 217  * threads can't disable the power well while the caller tries to read a few
 218  * registers.
 219  *
 220  * Returns:
 221  * True when the power domain is enabled, false otherwise.
 222  */
 223 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 224                                     enum intel_display_power_domain domain)
 225 {
 226         struct i915_power_domains *power_domains;
 227         bool ret;
 228
 229         power_domains = &dev_priv->power_domains;
 230
 231         mutex_lock(&power_domains->lock);
 232         ret = __intel_display_power_is_enabled(dev_priv, domain);
 233         mutex_unlock(&power_domains->lock);
 234
 235         return ret;
 236 }
 237
 238 /**
 239  * intel_display_set_init_power - set the initial power domain state
 240  * @dev_priv: i915 device instance
 241  * @enable: whether to enable or disable the initial power domain state
 242  *
 243  * For simplicity our driver load/unload and system suspend/resume code assumes
 244  * that all power domains are always enabled. This functions controls the state
 245  * of this little hack. While the initial power domain state is enabled runtime
 246  * pm is effectively disabled.
 247  */
 248 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 249                                   bool enable)
 250 {
 251         if (dev_priv->power_domains.init_power_on == enable)
 252                 return;
 253
 254         if (enable)
 255                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 256         else
 257                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 258
 259         dev_priv->power_domains.init_power_on = enable;
 260 }
 261
 262 /*
 263  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 264  * when not needed anymore. We have 4 registers that can request the power well
 265  * to be enabled, and it will only be disabled if none of the registers is
 266  * requesting it to be enabled.
 267  */
 268 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 269 {
 270         struct drm_device *dev = dev_priv->dev;
 271
 272         /*
 273          * After we re-enable the power well, if we touch VGA register 0x3d5
 274          * we'll get unclaimed register interrupts. This stops after we write
 275          * anything to the VGA MSR register. The vgacon module uses this
 276          * register all the time, so if we unbind our driver and, as a
 277          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 278          * console_unlock(). So make here we touch the VGA MSR register, making
 279          * sure vgacon can keep working normally without triggering interrupts
 280          * and error messages.
 281          */
 282         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 283         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 284         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 285
 286         if (IS_BROADWELL(dev))
 287                 gen8_irq_power_well_post_enable(dev_priv,
 288                                                 1 << PIPE_C | 1 << PIPE_B);
 289 }
 290
 291 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 292 {
 293         if (IS_BROADWELL(dev_priv))
 294                 gen8_irq_power_well_pre_disable(dev_priv,
 295                                                 1 << PIPE_C | 1 << PIPE_B);
 296 }
 297
 298 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 299                                        struct i915_power_well *power_well)
 300 {
 301         struct drm_device *dev = dev_priv->dev;
 302
 303         /*
 304          * After we re-enable the power well, if we touch VGA register 0x3d5
 305          * we'll get unclaimed register interrupts. This stops after we write
 306          * anything to the VGA MSR register. The vgacon module uses this
 307          * register all the time, so if we unbind our driver and, as a
 308          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 309          * console_unlock(). So make here we touch the VGA MSR register, making
 310          * sure vgacon can keep working normally without triggering interrupts
 311          * and error messages.
 312          */
 313         if (power_well->data == SKL_DISP_PW_2) {
 314                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 315                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 316                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 317
 318                 gen8_irq_power_well_post_enable(dev_priv,
 319                                                 1 << PIPE_C | 1 << PIPE_B);
 320         }
 321 }
 322
 323 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 324                                        struct i915_power_well *power_well)
 325 {
 326         if (power_well->data == SKL_DISP_PW_2)
 327                 gen8_irq_power_well_pre_disable(dev_priv,
 328                                                 1 << PIPE_C | 1 << PIPE_B);
 329 }
 330
 331 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 332                                struct i915_power_well *power_well, bool enable)
 333 {
 334         bool is_enabled, enable_requested;
 335         uint32_t tmp;
 336
 337         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 338         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 339         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 340
 341         if (enable) {
 342                 if (!enable_requested)
 343                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 344                                    HSW_PWR_WELL_ENABLE_REQUEST);
 345
 346                 if (!is_enabled) {
 347                         DRM_DEBUG_KMS("Enabling power well\n");
 348                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 349                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 350                                 DRM_ERROR("Timeout enabling power well\n");
 351                         hsw_power_well_post_enable(dev_priv);
 352                 }
 353
 354         } else {
 355                 if (enable_requested) {
 356                         hsw_power_well_pre_disable(dev_priv);
 357                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 358                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 359                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 360                 }
 361         }
 362 }
 363
 364 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 365         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 366         BIT(POWER_DOMAIN_PIPE_B) |                      \
 367         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 368         BIT(POWER_DOMAIN_PIPE_C) |                      \
 369         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 370         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 371         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 372         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 373         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 374         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 375         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 376         BIT(POWER_DOMAIN_AUX_B) |                       \
 377         BIT(POWER_DOMAIN_AUX_C) |                       \
 378         BIT(POWER_DOMAIN_AUX_D) |                       \
 379         BIT(POWER_DOMAIN_AUDIO) |                       \
 380         BIT(POWER_DOMAIN_VGA) |                         \
 381         BIT(POWER_DOMAIN_INIT))
 382 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 383         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 384         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 385         BIT(POWER_DOMAIN_INIT))
 386 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 387         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 388         BIT(POWER_DOMAIN_INIT))
 389 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 390         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 391         BIT(POWER_DOMAIN_INIT))
 392 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 393         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 394         BIT(POWER_DOMAIN_INIT))
 395 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 396         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 397         BIT(POWER_DOMAIN_MODESET) |                     \
 398         BIT(POWER_DOMAIN_AUX_A) |                       \
 399         BIT(POWER_DOMAIN_INIT))
 400
 401 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 402         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 403         BIT(POWER_DOMAIN_PIPE_B) |                      \
 404         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 405         BIT(POWER_DOMAIN_PIPE_C) |                      \
 406         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 407         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 408         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 409         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 410         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 411         BIT(POWER_DOMAIN_AUX_B) |                       \
 412         BIT(POWER_DOMAIN_AUX_C) |                       \
 413         BIT(POWER_DOMAIN_AUDIO) |                       \
 414         BIT(POWER_DOMAIN_VGA) |                         \
 415         BIT(POWER_DOMAIN_GMBUS) |                       \
 416         BIT(POWER_DOMAIN_INIT))
 417 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 418         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 419         BIT(POWER_DOMAIN_MODESET) |                     \
 420         BIT(POWER_DOMAIN_AUX_A) |                       \
 421         BIT(POWER_DOMAIN_INIT))
 422
 423 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 424 {
 425         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 426                   "DC9 already programmed to be enabled.\n");
 427         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 428                   "DC5 still not disabled to enable DC9.\n");
 429         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 430         WARN_ONCE(intel_irqs_enabled(dev_priv),
 431                   "Interrupts not disabled yet.\n");
 432
 433          /*
 434           * TODO: check for the following to verify the conditions to enter DC9
 435           * state are satisfied:
 436           * 1] Check relevant display engine registers to verify if mode set
 437           * disable sequence was followed.
 438           * 2] Check if display uninitialize sequence is initialized.
 439           */
 440 }
 441
 442 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 443 {
 444         WARN_ONCE(intel_irqs_enabled(dev_priv),
 445                   "Interrupts not disabled yet.\n");
 446         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 447                   "DC5 still not disabled.\n");
 448
 449          /*
 450           * TODO: check for the following to verify DC9 state was indeed
 451           * entered before programming to disable it:
 452           * 1] Check relevant display engine registers to verify if mode
 453           *  set disable sequence was followed.
 454           * 2] Check if display uninitialize sequence is initialized.
 455           */
 456 }
 457
 458 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 459                                 u32 state)
 460 {
 461         int rewrites = 0;
 462         int rereads = 0;
 463         u32 v;
 464
 465         I915_WRITE(DC_STATE_EN, state);
 466
 467         /* It has been observed that disabling the dc6 state sometimes
 468          * doesn't stick and dmc keeps returning old value. Make sure
 469          * the write really sticks enough times and also force rewrite until
 470          * we are confident that state is exactly what we want.
 471          */
 472         do  {
 473                 v = I915_READ(DC_STATE_EN);
 474
 475                 if (v != state) {
 476                         I915_WRITE(DC_STATE_EN, state);
 477                         rewrites++;
 478                         rereads = 0;
 479                 } else if (rereads++ > 5) {
 480                         break;
 481                 }
 482
 483         } while (rewrites < 100);
 484
 485         if (v != state)
 486                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 487                           state, v);
 488
 489         /* Most of the times we need one retry, avoid spam */
 490         if (rewrites > 1)
 491                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 492                               state, rewrites);
 493 }
 494
 495 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 496 {
 497         u32 mask;
 498
 499         mask = DC_STATE_EN_UPTO_DC5;
 500         if (IS_BROXTON(dev_priv))
 501                 mask |= DC_STATE_EN_DC9;
 502         else
 503                 mask |= DC_STATE_EN_UPTO_DC6;
 504
 505         return mask;
 506 }
 507
 508 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 509 {
 510         u32 val;
 511
 512         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 513
 514         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
 515                       dev_priv->csr.dc_state, val);
 516         dev_priv->csr.dc_state = val;
 517 }
 518
 519 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 520 {
 521         uint32_t val;
 522         uint32_t mask;
 523
 524         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 525                 state &= dev_priv->csr.allowed_dc_mask;
 526
 527         val = I915_READ(DC_STATE_EN);
 528         mask = gen9_dc_mask(dev_priv);
 529         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 530                       val & mask, state);
 531
 532         /* Check if DMC is ignoring our DC state requests */
 533         if ((val & mask) != dev_priv->csr.dc_state)
 534                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 535                           dev_priv->csr.dc_state, val & mask);
 536
 537         val &= ~mask;
 538         val |= state;
 539
 540         gen9_write_dc_state(dev_priv, val);
 541
 542         dev_priv->csr.dc_state = val & mask;
 543 }
 544
 545 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 546 {
 547         assert_can_enable_dc9(dev_priv);
 548
 549         DRM_DEBUG_KMS("Enabling DC9\n");
 550
 551         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 552 }
 553
 554 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 555 {
 556         assert_can_disable_dc9(dev_priv);
 557
 558         DRM_DEBUG_KMS("Disabling DC9\n");
 559
 560         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 561 }
 562
 563 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 564 {
 565         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 566                   "CSR program storage start is NULL\n");
 567         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 568         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 569 }
 570
 571 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 572 {
 573         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 574                                         SKL_DISP_PW_2);
 575
 576         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 577
 578         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 579                   "DC5 already programmed to be enabled.\n");
 580         assert_rpm_wakelock_held(dev_priv);
 581
 582         assert_csr_loaded(dev_priv);
 583 }
 584
 585 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 586 {
 587         assert_can_enable_dc5(dev_priv);
 588
 589         DRM_DEBUG_KMS("Enabling DC5\n");
 590
 591         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 592 }
 593
 594 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 595 {
 596         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 597                   "Backlight is not disabled.\n");
 598         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 599                   "DC6 already programmed to be enabled.\n");
 600
 601         assert_csr_loaded(dev_priv);
 602 }
 603
 604 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 605 {
 606         assert_can_enable_dc6(dev_priv);
 607
 608         DRM_DEBUG_KMS("Enabling DC6\n");
 609
 610         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 611
 612 }
 613
 614 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 615 {
 616         DRM_DEBUG_KMS("Disabling DC6\n");
 617
 618         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 619 }
 620
 621 static void
 622 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 623                                   struct i915_power_well *power_well)
 624 {
 625         enum skl_disp_power_wells power_well_id = power_well->data;
 626         u32 val;
 627         u32 mask;
 628
 629         mask = SKL_POWER_WELL_REQ(power_well_id);
 630
 631         val = I915_READ(HSW_PWR_WELL_KVMR);
 632         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 633                       power_well->name))
 634                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 635
 636         val = I915_READ(HSW_PWR_WELL_BIOS);
 637         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 638
 639         if (!(val & mask))
 640                 return;
 641
 642         /*
 643          * DMC is known to force on the request bits for power well 1 on SKL
 644          * and BXT and the misc IO power well on SKL but we don't expect any
 645          * other request bits to be set, so WARN for those.
 646          */
 647         if (power_well_id == SKL_DISP_PW_1 ||
 648             ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 649              power_well_id == SKL_DISP_PW_MISC_IO))
 650                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 651                                  "by DMC\n", power_well->name);
 652         else
 653                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 654                           power_well->name);
 655
 656         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 657         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 658 }
 659
 660 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 661                         struct i915_power_well *power_well, bool enable)
 662 {
 663         uint32_t tmp, fuse_status;
 664         uint32_t req_mask, state_mask;
 665         bool is_enabled, enable_requested, check_fuse_status = false;
 666
 667         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 668         fuse_status = I915_READ(SKL_FUSE_STATUS);
 669
 670         switch (power_well->data) {
 671         case SKL_DISP_PW_1:
 672                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 673                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 674                         DRM_ERROR("PG0 not enabled\n");
 675                         return;
 676                 }
 677                 break;
 678         case SKL_DISP_PW_2:
 679                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 680                         DRM_ERROR("PG1 in disabled state\n");
 681                         return;
 682                 }
 683                 break;
 684         case SKL_DISP_PW_DDI_A_E:
 685         case SKL_DISP_PW_DDI_B:
 686         case SKL_DISP_PW_DDI_C:
 687         case SKL_DISP_PW_DDI_D:
 688         case SKL_DISP_PW_MISC_IO:
 689                 break;
 690         default:
 691                 WARN(1, "Unknown power well %lu\n", power_well->data);
 692                 return;
 693         }
 694
 695         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 696         enable_requested = tmp & req_mask;
 697         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 698         is_enabled = tmp & state_mask;
 699
 700         if (!enable && enable_requested)
 701                 skl_power_well_pre_disable(dev_priv, power_well);
 702
 703         if (enable) {
 704                 if (!enable_requested) {
 705                         WARN((tmp & state_mask) &&
 706                                 !I915_READ(HSW_PWR_WELL_BIOS),
 707                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 708                                 when request is to disable!\n");
 709                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 710                 }
 711
 712                 if (!is_enabled) {
 713                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 714                         check_fuse_status = true;
 715                 }
 716         } else {
 717                 if (enable_requested) {
 718                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 719                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 720                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 721                 }
 722
 723                 if (IS_GEN9(dev_priv))
 724                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 725         }
 726
 727         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 728                      1))
 729                 DRM_ERROR("%s %s timeout\n",
 730                           power_well->name, enable ? "enable" : "disable");
 731
 732         if (check_fuse_status) {
 733                 if (power_well->data == SKL_DISP_PW_1) {
 734                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 735                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 736                                 DRM_ERROR("PG1 distributing status timeout\n");
 737                 } else if (power_well->data == SKL_DISP_PW_2) {
 738                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 739                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 740                                 DRM_ERROR("PG2 distributing status timeout\n");
 741                 }
 742         }
 743
 744         if (enable && !is_enabled)
 745                 skl_power_well_post_enable(dev_priv, power_well);
 746 }
 747
 748 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 749                                    struct i915_power_well *power_well)
 750 {
 751         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 752
 753         /*
 754          * We're taking over the BIOS, so clear any requests made by it since
 755          * the driver is in charge now.
 756          */
 757         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 758                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 759 }
 760
 761 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 762                                   struct i915_power_well *power_well)
 763 {
 764         hsw_set_power_well(dev_priv, power_well, true);
 765 }
 766
 767 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 768                                    struct i915_power_well *power_well)
 769 {
 770         hsw_set_power_well(dev_priv, power_well, false);
 771 }
 772
 773 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 774                                         struct i915_power_well *power_well)
 775 {
 776         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 777                 SKL_POWER_WELL_STATE(power_well->data);
 778
 779         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 780 }
 781
 782 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 783                                 struct i915_power_well *power_well)
 784 {
 785         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 786
 787         /* Clear any request made by BIOS as driver is taking over */
 788         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 789 }
 790
 791 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 792                                 struct i915_power_well *power_well)
 793 {
 794         skl_set_power_well(dev_priv, power_well, true);
 795 }
 796
 797 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 798                                 struct i915_power_well *power_well)
 799 {
 800         skl_set_power_well(dev_priv, power_well, false);
 801 }
 802
 803 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 804                                            struct i915_power_well *power_well)
 805 {
 806         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 807 }
 808
 809 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 810                                           struct i915_power_well *power_well)
 811 {
 812         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 813
 814         if (IS_BROXTON(dev_priv)) {
 815                 broxton_cdclk_verify_state(dev_priv);
 816                 broxton_ddi_phy_verify_state(dev_priv);
 817         }
 818 }
 819
 820 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 821                                            struct i915_power_well *power_well)
 822 {
 823         if (!dev_priv->csr.dmc_payload)
 824                 return;
 825
 826         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 827                 skl_enable_dc6(dev_priv);
 828         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 829                 gen9_enable_dc5(dev_priv);
 830 }
 831
 832 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 833                                            struct i915_power_well *power_well)
 834 {
 835         if (power_well->count > 0)
 836                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 837         else
 838                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 839 }
 840
 841 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 842                                            struct i915_power_well *power_well)
 843 {
 844 }
 845
 846 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 847                                              struct i915_power_well *power_well)
 848 {
 849         return true;
 850 }
 851
 852 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 853                                struct i915_power_well *power_well, bool enable)
 854 {
 855         enum punit_power_well power_well_id = power_well->data;
 856         u32 mask;
 857         u32 state;
 858         u32 ctrl;
 859
 860         mask = PUNIT_PWRGT_MASK(power_well_id);
 861         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 862                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 863
 864         mutex_lock(&dev_priv->rps.hw_lock);
 865
 866 #define COND \
 867         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 868
 869         if (COND)
 870                 goto out;
 871
 872         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 873         ctrl &= ~mask;
 874         ctrl |= state;
 875         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 876
 877         if (wait_for(COND, 100))
 878                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 879                           state,
 880                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 881
 882 #undef COND
 883
 884 out:
 885         mutex_unlock(&dev_priv->rps.hw_lock);
 886 }
 887
 888 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 889                                    struct i915_power_well *power_well)
 890 {
 891         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 892 }
 893
 894 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 895                                   struct i915_power_well *power_well)
 896 {
 897         vlv_set_power_well(dev_priv, power_well, true);
 898 }
 899
 900 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 901                                    struct i915_power_well *power_well)
 902 {
 903         vlv_set_power_well(dev_priv, power_well, false);
 904 }
 905
 906 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 907                                    struct i915_power_well *power_well)
 908 {
 909         int power_well_id = power_well->data;
 910         bool enabled = false;
 911         u32 mask;
 912         u32 state;
 913         u32 ctrl;
 914
 915         mask = PUNIT_PWRGT_MASK(power_well_id);
 916         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 917
 918         mutex_lock(&dev_priv->rps.hw_lock);
 919
 920         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 921         /*
 922          * We only ever set the power-on and power-gate states, anything
 923          * else is unexpected.
 924          */
 925         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 926                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 927         if (state == ctrl)
 928                 enabled = true;
 929
 930         /*
 931          * A transient state at this point would mean some unexpected party
 932          * is poking at the power controls too.
 933          */
 934         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 935         WARN_ON(ctrl != state);
 936
 937         mutex_unlock(&dev_priv->rps.hw_lock);
 938
 939         return enabled;
 940 }
 941
 942 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 943 {
 944         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 945
 946         /*
 947          * Disable trickle feed and enable pnd deadline calculation
 948          */
 949         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 950         I915_WRITE(CBR1_VLV, 0);
 951 }
 952
 953 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 954 {
 955         enum pipe pipe;
 956
 957         /*
 958          * Enable the CRI clock source so we can get at the
 959          * display and the reference clock for VGA
 960          * hotplug / manual detection. Supposedly DSI also
 961          * needs the ref clock up and running.
 962          *
 963          * CHV DPLL B/C have some issues if VGA mode is enabled.
 964          */
 965         for_each_pipe(dev_priv->dev, pipe) {
 966                 u32 val = I915_READ(DPLL(pipe));
 967
 968                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 969                 if (pipe != PIPE_A)
 970                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 971
 972                 I915_WRITE(DPLL(pipe), val);
 973         }
 974
 975         vlv_init_display_clock_gating(dev_priv);
 976
 977         spin_lock_irq(&dev_priv->irq_lock);
 978         valleyview_enable_display_irqs(dev_priv);
 979         spin_unlock_irq(&dev_priv->irq_lock);
 980
 981         /*
 982          * During driver initialization/resume we can avoid restoring the
 983          * part of the HW/SW state that will be inited anyway explicitly.
 984          */
 985         if (dev_priv->power_domains.initializing)
 986                 return;
 987
 988         intel_hpd_init(dev_priv);
 989
 990         i915_redisable_vga_power_on(dev_priv->dev);
 991 }
 992
 993 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 994 {
 995         spin_lock_irq(&dev_priv->irq_lock);
 996         valleyview_disable_display_irqs(dev_priv);
 997         spin_unlock_irq(&dev_priv->irq_lock);
 998
 999         /* make sure we're done processing display irqs */
1000         synchronize_irq(dev_priv->dev->irq);
1001
1002         vlv_power_sequencer_reset(dev_priv);
1003 }
1004
1005 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1006                                           struct i915_power_well *power_well)
1007 {
1008         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1009
1010         vlv_set_power_well(dev_priv, power_well, true);
1011
1012         vlv_display_power_well_init(dev_priv);
1013 }
1014
1015 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1016                                            struct i915_power_well *power_well)
1017 {
1018         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1019
1020         vlv_display_power_well_deinit(dev_priv);
1021
1022         vlv_set_power_well(dev_priv, power_well, false);
1023 }
1024
1025 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1026                                            struct i915_power_well *power_well)
1027 {
1028         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1029
1030         /* since ref/cri clock was enabled */
1031         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1032
1033         vlv_set_power_well(dev_priv, power_well, true);
1034
1035         /*
1036          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1037          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1038          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1039          *   b. The other bits such as sfr settings / modesel may all
1040          *      be set to 0.
1041          *
1042          * This should only be done on init and resume from S3 with
1043          * both PLLs disabled, or we risk losing DPIO and PLL
1044          * synchronization.
1045          */
1046         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1047 }
1048
1049 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1050                                             struct i915_power_well *power_well)
1051 {
1052         enum pipe pipe;
1053
1054         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1055
1056         for_each_pipe(dev_priv, pipe)
1057                 assert_pll_disabled(dev_priv, pipe);
1058
1059         /* Assert common reset */
1060         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1061
1062         vlv_set_power_well(dev_priv, power_well, false);
1063 }
1064
1065 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1066
1067 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1068                                                  int power_well_id)
1069 {
1070         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1071         int i;
1072
1073         for (i = 0; i < power_domains->power_well_count; i++) {
1074                 struct i915_power_well *power_well;
1075
1076                 power_well = &power_domains->power_wells[i];
1077                 if (power_well->data == power_well_id)
1078                         return power_well;
1079         }
1080
1081         return NULL;
1082 }
1083
1084 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1085
1086 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1087 {
1088         struct i915_power_well *cmn_bc =
1089                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1090         struct i915_power_well *cmn_d =
1091                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1092         u32 phy_control = dev_priv->chv_phy_control;
1093         u32 phy_status = 0;
1094         u32 phy_status_mask = 0xffffffff;
1095         u32 tmp;
1096
1097         /*
1098          * The BIOS can leave the PHY is some weird state
1099          * where it doesn't fully power down some parts.
1100          * Disable the asserts until the PHY has been fully
1101          * reset (ie. the power well has been disabled at
1102          * least once).
1103          */
1104         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1105                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1106                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1107                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1108                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1109                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1110                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1111
1112         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1113                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1114                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1115                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1116
1117         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1118                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1119
1120                 /* this assumes override is only used to enable lanes */
1121                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1122                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1123
1124                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1125                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1126
1127                 /* CL1 is on whenever anything is on in either channel */
1128                 if (BITS_SET(phy_control,
1129                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1130                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1131                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1132
1133                 /*
1134                  * The DPLLB check accounts for the pipe B + port A usage
1135                  * with CL2 powered up but all the lanes in the second channel
1136                  * powered down.
1137                  */
1138                 if (BITS_SET(phy_control,
1139                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1140                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1141                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1142
1143                 if (BITS_SET(phy_control,
1144                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1145                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1146                 if (BITS_SET(phy_control,
1147                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1148                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1149
1150                 if (BITS_SET(phy_control,
1151                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1152                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1153                 if (BITS_SET(phy_control,
1154                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1155                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1156         }
1157
1158         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1159                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1160
1161                 /* this assumes override is only used to enable lanes */
1162                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1163                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1164
1165                 if (BITS_SET(phy_control,
1166                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1167                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1168
1169                 if (BITS_SET(phy_control,
1170                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1171                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1172                 if (BITS_SET(phy_control,
1173                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1174                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1175         }
1176
1177         phy_status &= phy_status_mask;
1178
1179         /*
1180          * The PHY may be busy with some initial calibration and whatnot,
1181          * so the power state can take a while to actually change.
1182          */
1183         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1184                 WARN(phy_status != tmp,
1185                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1186                      tmp, phy_status, dev_priv->chv_phy_control);
1187 }
1188
1189 #undef BITS_SET
1190
1191 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1192                                            struct i915_power_well *power_well)
1193 {
1194         enum dpio_phy phy;
1195         enum pipe pipe;
1196         uint32_t tmp;
1197
1198         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1199                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1200
1201         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1202                 pipe = PIPE_A;
1203                 phy = DPIO_PHY0;
1204         } else {
1205                 pipe = PIPE_C;
1206                 phy = DPIO_PHY1;
1207         }
1208
1209         /* since ref/cri clock was enabled */
1210         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1211         vlv_set_power_well(dev_priv, power_well, true);
1212
1213         /* Poll for phypwrgood signal */
1214         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1215                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1216
1217         mutex_lock(&dev_priv->sb_lock);
1218
1219         /* Enable dynamic power down */
1220         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1221         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1222                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1223         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1224
1225         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1226                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1227                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1228                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1229         } else {
1230                 /*
1231                  * Force the non-existing CL2 off. BXT does this
1232                  * too, so maybe it saves some power even though
1233                  * CL2 doesn't exist?
1234                  */
1235                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1236                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1237                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1238         }
1239
1240         mutex_unlock(&dev_priv->sb_lock);
1241
1242         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1243         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1244
1245         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1246                       phy, dev_priv->chv_phy_control);
1247
1248         assert_chv_phy_status(dev_priv);
1249 }
1250
1251 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1252                                             struct i915_power_well *power_well)
1253 {
1254         enum dpio_phy phy;
1255
1256         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1257                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1258
1259         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1260                 phy = DPIO_PHY0;
1261                 assert_pll_disabled(dev_priv, PIPE_A);
1262                 assert_pll_disabled(dev_priv, PIPE_B);
1263         } else {
1264                 phy = DPIO_PHY1;
1265                 assert_pll_disabled(dev_priv, PIPE_C);
1266         }
1267
1268         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1269         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1270
1271         vlv_set_power_well(dev_priv, power_well, false);
1272
1273         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1274                       phy, dev_priv->chv_phy_control);
1275
1276         /* PHY is fully reset now, so we can enable the PHY state asserts */
1277         dev_priv->chv_phy_assert[phy] = true;
1278
1279         assert_chv_phy_status(dev_priv);
1280 }
1281
1282 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1283                                      enum dpio_channel ch, bool override, unsigned int mask)
1284 {
1285         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1286         u32 reg, val, expected, actual;
1287
1288         /*
1289          * The BIOS can leave the PHY is some weird state
1290          * where it doesn't fully power down some parts.
1291          * Disable the asserts until the PHY has been fully
1292          * reset (ie. the power well has been disabled at
1293          * least once).
1294          */
1295         if (!dev_priv->chv_phy_assert[phy])
1296                 return;
1297
1298         if (ch == DPIO_CH0)
1299                 reg = _CHV_CMN_DW0_CH0;
1300         else
1301                 reg = _CHV_CMN_DW6_CH1;
1302
1303         mutex_lock(&dev_priv->sb_lock);
1304         val = vlv_dpio_read(dev_priv, pipe, reg);
1305         mutex_unlock(&dev_priv->sb_lock);
1306
1307         /*
1308          * This assumes !override is only used when the port is disabled.
1309          * All lanes should power down even without the override when
1310          * the port is disabled.
1311          */
1312         if (!override || mask == 0xf) {
1313                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1314                 /*
1315                  * If CH1 common lane is not active anymore
1316                  * (eg. for pipe B DPLL) the entire channel will
1317                  * shut down, which causes the common lane registers
1318                  * to read as 0. That means we can't actually check
1319                  * the lane power down status bits, but as the entire
1320                  * register reads as 0 it's a good indication that the
1321                  * channel is indeed entirely powered down.
1322                  */
1323                 if (ch == DPIO_CH1 && val == 0)
1324                         expected = 0;
1325         } else if (mask != 0x0) {
1326                 expected = DPIO_ANYDL_POWERDOWN;
1327         } else {
1328                 expected = 0;
1329         }
1330
1331         if (ch == DPIO_CH0)
1332                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1333         else
1334                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1335         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1336
1337         WARN(actual != expected,
1338              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1339              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1340              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1341              reg, val);
1342 }
1343
1344 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1345                           enum dpio_channel ch, bool override)
1346 {
1347         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1348         bool was_override;
1349
1350         mutex_lock(&power_domains->lock);
1351
1352         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1353
1354         if (override == was_override)
1355                 goto out;
1356
1357         if (override)
1358                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1359         else
1360                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1361
1362         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1363
1364         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1365                       phy, ch, dev_priv->chv_phy_control);
1366
1367         assert_chv_phy_status(dev_priv);
1368
1369 out:
1370         mutex_unlock(&power_domains->lock);
1371
1372         return was_override;
1373 }
1374
1375 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1376                              bool override, unsigned int mask)
1377 {
1378         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1379         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1380         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1381         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1382
1383         mutex_lock(&power_domains->lock);
1384
1385         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1386         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1387
1388         if (override)
1389                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1390         else
1391                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1392
1393         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1394
1395         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1396                       phy, ch, mask, dev_priv->chv_phy_control);
1397
1398         assert_chv_phy_status(dev_priv);
1399
1400         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1401
1402         mutex_unlock(&power_domains->lock);
1403 }
1404
1405 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1406                                         struct i915_power_well *power_well)
1407 {
1408         enum pipe pipe = power_well->data;
1409         bool enabled;
1410         u32 state, ctrl;
1411
1412         mutex_lock(&dev_priv->rps.hw_lock);
1413
1414         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1415         /*
1416          * We only ever set the power-on and power-gate states, anything
1417          * else is unexpected.
1418          */
1419         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1420         enabled = state == DP_SSS_PWR_ON(pipe);
1421
1422         /*
1423          * A transient state at this point would mean some unexpected party
1424          * is poking at the power controls too.
1425          */
1426         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1427         WARN_ON(ctrl << 16 != state);
1428
1429         mutex_unlock(&dev_priv->rps.hw_lock);
1430
1431         return enabled;
1432 }
1433
1434 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1435                                     struct i915_power_well *power_well,
1436                                     bool enable)
1437 {
1438         enum pipe pipe = power_well->data;
1439         u32 state;
1440         u32 ctrl;
1441
1442         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1443
1444         mutex_lock(&dev_priv->rps.hw_lock);
1445
1446 #define COND \
1447         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1448
1449         if (COND)
1450                 goto out;
1451
1452         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1453         ctrl &= ~DP_SSC_MASK(pipe);
1454         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1455         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1456
1457         if (wait_for(COND, 100))
1458                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1459                           state,
1460                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1461
1462 #undef COND
1463
1464 out:
1465         mutex_unlock(&dev_priv->rps.hw_lock);
1466 }
1467
1468 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1469                                         struct i915_power_well *power_well)
1470 {
1471         WARN_ON_ONCE(power_well->data != PIPE_A);
1472
1473         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1474 }
1475
1476 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1477                                        struct i915_power_well *power_well)
1478 {
1479         WARN_ON_ONCE(power_well->data != PIPE_A);
1480
1481         chv_set_pipe_power_well(dev_priv, power_well, true);
1482
1483         vlv_display_power_well_init(dev_priv);
1484 }
1485
1486 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1487                                         struct i915_power_well *power_well)
1488 {
1489         WARN_ON_ONCE(power_well->data != PIPE_A);
1490
1491         vlv_display_power_well_deinit(dev_priv);
1492
1493         chv_set_pipe_power_well(dev_priv, power_well, false);
1494 }
1495
1496 static void
1497 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1498                                  enum intel_display_power_domain domain)
1499 {
1500         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1501         struct i915_power_well *power_well;
1502         int i;
1503
1504         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1505                 if (!power_well->count++)
1506                         intel_power_well_enable(dev_priv, power_well);
1507         }
1508
1509         power_domains->domain_use_count[domain]++;
1510 }
1511
1512 /**
1513  * intel_display_power_get - grab a power domain reference
1514  * @dev_priv: i915 device instance
1515  * @domain: power domain to reference
1516  *
1517  * This function grabs a power domain reference for @domain and ensures that the
1518  * power domain and all its parents are powered up. Therefore users should only
1519  * grab a reference to the innermost power domain they need.
1520  *
1521  * Any power domain reference obtained by this function must have a symmetric
1522  * call to intel_display_power_put() to release the reference again.
1523  */
1524 void intel_display_power_get(struct drm_i915_private *dev_priv,
1525                              enum intel_display_power_domain domain)
1526 {
1527         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1528
1529         intel_runtime_pm_get(dev_priv);
1530
1531         mutex_lock(&power_domains->lock);
1532
1533         __intel_display_power_get_domain(dev_priv, domain);
1534
1535         mutex_unlock(&power_domains->lock);
1536 }
1537
1538 /**
1539  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1540  * @dev_priv: i915 device instance
1541  * @domain: power domain to reference
1542  *
1543  * This function grabs a power domain reference for @domain and ensures that the
1544  * power domain and all its parents are powered up. Therefore users should only
1545  * grab a reference to the innermost power domain they need.
1546  *
1547  * Any power domain reference obtained by this function must have a symmetric
1548  * call to intel_display_power_put() to release the reference again.
1549  */
1550 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1551                                         enum intel_display_power_domain domain)
1552 {
1553         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1554         bool is_enabled;
1555
1556         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1557                 return false;
1558
1559         mutex_lock(&power_domains->lock);
1560
1561         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1562                 __intel_display_power_get_domain(dev_priv, domain);
1563                 is_enabled = true;
1564         } else {
1565                 is_enabled = false;
1566         }
1567
1568         mutex_unlock(&power_domains->lock);
1569
1570         if (!is_enabled)
1571                 intel_runtime_pm_put(dev_priv);
1572
1573         return is_enabled;
1574 }
1575
1576 /**
1577  * intel_display_power_put - release a power domain reference
1578  * @dev_priv: i915 device instance
1579  * @domain: power domain to reference
1580  *
1581  * This function drops the power domain reference obtained by
1582  * intel_display_power_get() and might power down the corresponding hardware
1583  * block right away if this is the last reference.
1584  */
1585 void intel_display_power_put(struct drm_i915_private *dev_priv,
1586                              enum intel_display_power_domain domain)
1587 {
1588         struct i915_power_domains *power_domains;
1589         struct i915_power_well *power_well;
1590         int i;
1591
1592         power_domains = &dev_priv->power_domains;
1593
1594         mutex_lock(&power_domains->lock);
1595
1596         WARN(!power_domains->domain_use_count[domain],
1597              "Use count on domain %s is already zero\n",
1598              intel_display_power_domain_str(domain));
1599         power_domains->domain_use_count[domain]--;
1600
1601         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1602                 WARN(!power_well->count,
1603                      "Use count on power well %s is already zero",
1604                      power_well->name);
1605
1606                 if (!--power_well->count)
1607                         intel_power_well_disable(dev_priv, power_well);
1608         }
1609
1610         mutex_unlock(&power_domains->lock);
1611
1612         intel_runtime_pm_put(dev_priv);
1613 }
1614
1615 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1616         BIT(POWER_DOMAIN_PIPE_B) |                      \
1617         BIT(POWER_DOMAIN_PIPE_C) |                      \
1618         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
1619         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1620         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1621         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1622         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1623         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1624         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1625         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1626         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1627         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1628         BIT(POWER_DOMAIN_VGA) |                         \
1629         BIT(POWER_DOMAIN_AUDIO) |                       \
1630         BIT(POWER_DOMAIN_INIT))
1631
1632 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1633         BIT(POWER_DOMAIN_PIPE_B) |                      \
1634         BIT(POWER_DOMAIN_PIPE_C) |                      \
1635         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1636         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1637         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1638         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1639         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1640         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1641         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1642         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1643         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1644         BIT(POWER_DOMAIN_VGA) |                         \
1645         BIT(POWER_DOMAIN_AUDIO) |                       \
1646         BIT(POWER_DOMAIN_INIT))
1647
1648 #define VLV_DISPLAY_POWER_DOMAINS (             \
1649         BIT(POWER_DOMAIN_PIPE_A) |              \
1650         BIT(POWER_DOMAIN_PIPE_B) |              \
1651         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1652         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1653         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1654         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1655         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1656         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1657         BIT(POWER_DOMAIN_PORT_DSI) |            \
1658         BIT(POWER_DOMAIN_PORT_CRT) |            \
1659         BIT(POWER_DOMAIN_VGA) |                 \
1660         BIT(POWER_DOMAIN_AUDIO) |               \
1661         BIT(POWER_DOMAIN_AUX_B) |               \
1662         BIT(POWER_DOMAIN_AUX_C) |               \
1663         BIT(POWER_DOMAIN_GMBUS) |               \
1664         BIT(POWER_DOMAIN_INIT))
1665
1666 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1667         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1668         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1669         BIT(POWER_DOMAIN_PORT_CRT) |            \
1670         BIT(POWER_DOMAIN_AUX_B) |               \
1671         BIT(POWER_DOMAIN_AUX_C) |               \
1672         BIT(POWER_DOMAIN_INIT))
1673
1674 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1675         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1676         BIT(POWER_DOMAIN_AUX_B) |               \
1677         BIT(POWER_DOMAIN_INIT))
1678
1679 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1680         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1681         BIT(POWER_DOMAIN_AUX_B) |               \
1682         BIT(POWER_DOMAIN_INIT))
1683
1684 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1685         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1686         BIT(POWER_DOMAIN_AUX_C) |               \
1687         BIT(POWER_DOMAIN_INIT))
1688
1689 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1690         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1691         BIT(POWER_DOMAIN_AUX_C) |               \
1692         BIT(POWER_DOMAIN_INIT))
1693
1694 #define CHV_DISPLAY_POWER_DOMAINS (             \
1695         BIT(POWER_DOMAIN_PIPE_A) |              \
1696         BIT(POWER_DOMAIN_PIPE_B) |              \
1697         BIT(POWER_DOMAIN_PIPE_C) |              \
1698         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1699         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1700         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1701         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1702         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1703         BIT(POWER_DOMAIN_TRANSCODER_C) |        \
1704         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1705         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1706         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1707         BIT(POWER_DOMAIN_PORT_DSI) |            \
1708         BIT(POWER_DOMAIN_VGA) |                 \
1709         BIT(POWER_DOMAIN_AUDIO) |               \
1710         BIT(POWER_DOMAIN_AUX_B) |               \
1711         BIT(POWER_DOMAIN_AUX_C) |               \
1712         BIT(POWER_DOMAIN_AUX_D) |               \
1713         BIT(POWER_DOMAIN_GMBUS) |               \
1714         BIT(POWER_DOMAIN_INIT))
1715
1716 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1717         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1718         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1719         BIT(POWER_DOMAIN_AUX_B) |               \
1720         BIT(POWER_DOMAIN_AUX_C) |               \
1721         BIT(POWER_DOMAIN_INIT))
1722
1723 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1724         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1725         BIT(POWER_DOMAIN_AUX_D) |               \
1726         BIT(POWER_DOMAIN_INIT))
1727
1728 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1729         .sync_hw = i9xx_always_on_power_well_noop,
1730         .enable = i9xx_always_on_power_well_noop,
1731         .disable = i9xx_always_on_power_well_noop,
1732         .is_enabled = i9xx_always_on_power_well_enabled,
1733 };
1734
1735 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1736         .sync_hw = chv_pipe_power_well_sync_hw,
1737         .enable = chv_pipe_power_well_enable,
1738         .disable = chv_pipe_power_well_disable,
1739         .is_enabled = chv_pipe_power_well_enabled,
1740 };
1741
1742 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1743         .sync_hw = vlv_power_well_sync_hw,
1744         .enable = chv_dpio_cmn_power_well_enable,
1745         .disable = chv_dpio_cmn_power_well_disable,
1746         .is_enabled = vlv_power_well_enabled,
1747 };
1748
1749 static struct i915_power_well i9xx_always_on_power_well[] = {
1750         {
1751                 .name = "always-on",
1752                 .always_on = 1,
1753                 .domains = POWER_DOMAIN_MASK,
1754                 .ops = &i9xx_always_on_power_well_ops,
1755         },
1756 };
1757
1758 static const struct i915_power_well_ops hsw_power_well_ops = {
1759         .sync_hw = hsw_power_well_sync_hw,
1760         .enable = hsw_power_well_enable,
1761         .disable = hsw_power_well_disable,
1762         .is_enabled = hsw_power_well_enabled,
1763 };
1764
1765 static const struct i915_power_well_ops skl_power_well_ops = {
1766         .sync_hw = skl_power_well_sync_hw,
1767         .enable = skl_power_well_enable,
1768         .disable = skl_power_well_disable,
1769         .is_enabled = skl_power_well_enabled,
1770 };
1771
1772 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1773         .sync_hw = gen9_dc_off_power_well_sync_hw,
1774         .enable = gen9_dc_off_power_well_enable,
1775         .disable = gen9_dc_off_power_well_disable,
1776         .is_enabled = gen9_dc_off_power_well_enabled,
1777 };
1778
1779 static struct i915_power_well hsw_power_wells[] = {
1780         {
1781                 .name = "always-on",
1782                 .always_on = 1,
1783                 .domains = POWER_DOMAIN_MASK,
1784                 .ops = &i9xx_always_on_power_well_ops,
1785         },
1786         {
1787                 .name = "display",
1788                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1789                 .ops = &hsw_power_well_ops,
1790         },
1791 };
1792
1793 static struct i915_power_well bdw_power_wells[] = {
1794         {
1795                 .name = "always-on",
1796                 .always_on = 1,
1797                 .domains = POWER_DOMAIN_MASK,
1798                 .ops = &i9xx_always_on_power_well_ops,
1799         },
1800         {
1801                 .name = "display",
1802                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1803                 .ops = &hsw_power_well_ops,
1804         },
1805 };
1806
1807 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1808         .sync_hw = vlv_power_well_sync_hw,
1809         .enable = vlv_display_power_well_enable,
1810         .disable = vlv_display_power_well_disable,
1811         .is_enabled = vlv_power_well_enabled,
1812 };
1813
1814 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1815         .sync_hw = vlv_power_well_sync_hw,
1816         .enable = vlv_dpio_cmn_power_well_enable,
1817         .disable = vlv_dpio_cmn_power_well_disable,
1818         .is_enabled = vlv_power_well_enabled,
1819 };
1820
1821 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1822         .sync_hw = vlv_power_well_sync_hw,
1823         .enable = vlv_power_well_enable,
1824         .disable = vlv_power_well_disable,
1825         .is_enabled = vlv_power_well_enabled,
1826 };
1827
1828 static struct i915_power_well vlv_power_wells[] = {
1829         {
1830                 .name = "always-on",
1831                 .always_on = 1,
1832                 .domains = POWER_DOMAIN_MASK,
1833                 .ops = &i9xx_always_on_power_well_ops,
1834                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1835         },
1836         {
1837                 .name = "display",
1838                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1839                 .data = PUNIT_POWER_WELL_DISP2D,
1840                 .ops = &vlv_display_power_well_ops,
1841         },
1842         {
1843                 .name = "dpio-tx-b-01",
1844                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1845                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1846                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1847                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1848                 .ops = &vlv_dpio_power_well_ops,
1849                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1850         },
1851         {
1852                 .name = "dpio-tx-b-23",
1853                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1854                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1855                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1856                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1857                 .ops = &vlv_dpio_power_well_ops,
1858                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1859         },
1860         {
1861                 .name = "dpio-tx-c-01",
1862                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1863                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1864                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1865                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1866                 .ops = &vlv_dpio_power_well_ops,
1867                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1868         },
1869         {
1870                 .name = "dpio-tx-c-23",
1871                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1872                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1873                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1874                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1875                 .ops = &vlv_dpio_power_well_ops,
1876                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1877         },
1878         {
1879                 .name = "dpio-common",
1880                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1881                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1882                 .ops = &vlv_dpio_cmn_power_well_ops,
1883         },
1884 };
1885
1886 static struct i915_power_well chv_power_wells[] = {
1887         {
1888                 .name = "always-on",
1889                 .always_on = 1,
1890                 .domains = POWER_DOMAIN_MASK,
1891                 .ops = &i9xx_always_on_power_well_ops,
1892         },
1893         {
1894                 .name = "display",
1895                 /*
1896                  * Pipe A power well is the new disp2d well. Pipe B and C
1897                  * power wells don't actually exist. Pipe A power well is
1898                  * required for any pipe to work.
1899                  */
1900                 .domains = CHV_DISPLAY_POWER_DOMAINS,
1901                 .data = PIPE_A,
1902                 .ops = &chv_pipe_power_well_ops,
1903         },
1904         {
1905                 .name = "dpio-common-bc",
1906                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1907                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1908                 .ops = &chv_dpio_cmn_power_well_ops,
1909         },
1910         {
1911                 .name = "dpio-common-d",
1912                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1913                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1914                 .ops = &chv_dpio_cmn_power_well_ops,
1915         },
1916 };
1917
1918 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1919                                     int power_well_id)
1920 {
1921         struct i915_power_well *power_well;
1922         bool ret;
1923
1924         power_well = lookup_power_well(dev_priv, power_well_id);
1925         ret = power_well->ops->is_enabled(dev_priv, power_well);
1926
1927         return ret;
1928 }
1929
1930 static struct i915_power_well skl_power_wells[] = {
1931         {
1932                 .name = "always-on",
1933                 .always_on = 1,
1934                 .domains = POWER_DOMAIN_MASK,
1935                 .ops = &i9xx_always_on_power_well_ops,
1936                 .data = SKL_DISP_PW_ALWAYS_ON,
1937         },
1938         {
1939                 .name = "power well 1",
1940                 /* Handled by the DMC firmware */
1941                 .domains = 0,
1942                 .ops = &skl_power_well_ops,
1943                 .data = SKL_DISP_PW_1,
1944         },
1945         {
1946                 .name = "MISC IO power well",
1947                 /* Handled by the DMC firmware */
1948                 .domains = 0,
1949                 .ops = &skl_power_well_ops,
1950                 .data = SKL_DISP_PW_MISC_IO,
1951         },
1952         {
1953                 .name = "DC off",
1954                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1955                 .ops = &gen9_dc_off_power_well_ops,
1956                 .data = SKL_DISP_PW_DC_OFF,
1957         },
1958         {
1959                 .name = "power well 2",
1960                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1961                 .ops = &skl_power_well_ops,
1962                 .data = SKL_DISP_PW_2,
1963         },
1964         {
1965                 .name = "DDI A/E power well",
1966                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1967                 .ops = &skl_power_well_ops,
1968                 .data = SKL_DISP_PW_DDI_A_E,
1969         },
1970         {
1971                 .name = "DDI B power well",
1972                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1973                 .ops = &skl_power_well_ops,
1974                 .data = SKL_DISP_PW_DDI_B,
1975         },
1976         {
1977                 .name = "DDI C power well",
1978                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1979                 .ops = &skl_power_well_ops,
1980                 .data = SKL_DISP_PW_DDI_C,
1981         },
1982         {
1983                 .name = "DDI D power well",
1984                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1985                 .ops = &skl_power_well_ops,
1986                 .data = SKL_DISP_PW_DDI_D,
1987         },
1988 };
1989
1990 static struct i915_power_well bxt_power_wells[] = {
1991         {
1992                 .name = "always-on",
1993                 .always_on = 1,
1994                 .domains = POWER_DOMAIN_MASK,
1995                 .ops = &i9xx_always_on_power_well_ops,
1996         },
1997         {
1998                 .name = "power well 1",
1999                 .domains = 0,
2000                 .ops = &skl_power_well_ops,
2001                 .data = SKL_DISP_PW_1,
2002         },
2003         {
2004                 .name = "DC off",
2005                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2006                 .ops = &gen9_dc_off_power_well_ops,
2007                 .data = SKL_DISP_PW_DC_OFF,
2008         },
2009         {
2010                 .name = "power well 2",
2011                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2012                 .ops = &skl_power_well_ops,
2013                 .data = SKL_DISP_PW_2,
2014         },
2015 };
2016
2017 static int
2018 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2019                                    int disable_power_well)
2020 {
2021         if (disable_power_well >= 0)
2022                 return !!disable_power_well;
2023
2024         return 1;
2025 }
2026
2027 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2028                                     int enable_dc)
2029 {
2030         uint32_t mask;
2031         int requested_dc;
2032         int max_dc;
2033
2034         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2035                 max_dc = 2;
2036                 mask = 0;
2037         } else if (IS_BROXTON(dev_priv)) {
2038                 max_dc = 1;
2039                 /*
2040                  * DC9 has a separate HW flow from the rest of the DC states,
2041                  * not depending on the DMC firmware. It's needed by system
2042                  * suspend/resume, so allow it unconditionally.
2043                  */
2044                 mask = DC_STATE_EN_DC9;
2045         } else {
2046                 max_dc = 0;
2047                 mask = 0;
2048         }
2049
2050         if (!i915.disable_power_well)
2051                 max_dc = 0;
2052
2053         if (enable_dc >= 0 && enable_dc <= max_dc) {
2054                 requested_dc = enable_dc;
2055         } else if (enable_dc == -1) {
2056                 requested_dc = max_dc;
2057         } else if (enable_dc > max_dc && enable_dc <= 2) {
2058                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2059                               enable_dc, max_dc);
2060                 requested_dc = max_dc;
2061         } else {
2062                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2063                 requested_dc = max_dc;
2064         }
2065
2066         if (requested_dc > 1)
2067                 mask |= DC_STATE_EN_UPTO_DC6;
2068         if (requested_dc > 0)
2069                 mask |= DC_STATE_EN_UPTO_DC5;
2070
2071         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2072
2073         return mask;
2074 }
2075
2076 #define set_power_wells(power_domains, __power_wells) ({                \
2077         (power_domains)->power_wells = (__power_wells);                 \
2078         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2079 })
2080
2081 /**
2082  * intel_power_domains_init - initializes the power domain structures
2083  * @dev_priv: i915 device instance
2084  *
2085  * Initializes the power domain structures for @dev_priv depending upon the
2086  * supported platform.
2087  */
2088 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2089 {
2090         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2091
2092         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2093                                                      i915.disable_power_well);
2094         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2095                                                             i915.enable_dc);
2096
2097         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2098
2099         mutex_init(&power_domains->lock);
2100
2101         /*
2102          * The enabling order will be from lower to higher indexed wells,
2103          * the disabling order is reversed.
2104          */
2105         if (IS_HASWELL(dev_priv)) {
2106                 set_power_wells(power_domains, hsw_power_wells);
2107         } else if (IS_BROADWELL(dev_priv)) {
2108                 set_power_wells(power_domains, bdw_power_wells);
2109         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2110                 set_power_wells(power_domains, skl_power_wells);
2111         } else if (IS_BROXTON(dev_priv)) {
2112                 set_power_wells(power_domains, bxt_power_wells);
2113         } else if (IS_CHERRYVIEW(dev_priv)) {
2114                 set_power_wells(power_domains, chv_power_wells);
2115         } else if (IS_VALLEYVIEW(dev_priv)) {
2116                 set_power_wells(power_domains, vlv_power_wells);
2117         } else {
2118                 set_power_wells(power_domains, i9xx_always_on_power_well);
2119         }
2120
2121         return 0;
2122 }
2123
2124 /**
2125  * intel_power_domains_fini - finalizes the power domain structures
2126  * @dev_priv: i915 device instance
2127  *
2128  * Finalizes the power domain structures for @dev_priv depending upon the
2129  * supported platform. This function also disables runtime pm and ensures that
2130  * the device stays powered up so that the driver can be reloaded.
2131  */
2132 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2133 {
2134         struct device *device = &dev_priv->dev->pdev->dev;
2135
2136         /*
2137          * The i915.ko module is still not prepared to be loaded when
2138          * the power well is not enabled, so just enable it in case
2139          * we're going to unload/reload.
2140          * The following also reacquires the RPM reference the core passed
2141          * to the driver during loading, which is dropped in
2142          * intel_runtime_pm_enable(). We have to hand back the control of the
2143          * device to the core with this reference held.
2144          */
2145         intel_display_set_init_power(dev_priv, true);
2146
2147         /* Remove the refcount we took to keep power well support disabled. */
2148         if (!i915.disable_power_well)
2149                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2150
2151         /*
2152          * Remove the refcount we took in intel_runtime_pm_enable() in case
2153          * the platform doesn't support runtime PM.
2154          */
2155         if (!HAS_RUNTIME_PM(dev_priv))
2156                 pm_runtime_put(device);
2157 }
2158
2159 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2160 {
2161         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2162         struct i915_power_well *power_well;
2163         int i;
2164
2165         mutex_lock(&power_domains->lock);
2166         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2167                 power_well->ops->sync_hw(dev_priv, power_well);
2168                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2169                                                                      power_well);
2170         }
2171         mutex_unlock(&power_domains->lock);
2172 }
2173
2174 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2175                                    bool resume)
2176 {
2177         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2178         struct i915_power_well *well;
2179         uint32_t val;
2180
2181         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2182
2183         /* enable PCH reset handshake */
2184         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2185         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2186
2187         /* enable PG1 and Misc I/O */
2188         mutex_lock(&power_domains->lock);
2189
2190         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2191         intel_power_well_enable(dev_priv, well);
2192
2193         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2194         intel_power_well_enable(dev_priv, well);
2195
2196         mutex_unlock(&power_domains->lock);
2197
2198         if (!resume)
2199                 return;
2200
2201         skl_init_cdclk(dev_priv);
2202
2203         if (dev_priv->csr.dmc_payload)
2204                 intel_csr_load_program(dev_priv);
2205 }
2206
2207 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2208 {
2209         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2210         struct i915_power_well *well;
2211
2212         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2213
2214         skl_uninit_cdclk(dev_priv);
2215
2216         /* The spec doesn't call for removing the reset handshake flag */
2217         /* disable PG1 and Misc I/O */
2218
2219         mutex_lock(&power_domains->lock);
2220
2221         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2222         intel_power_well_disable(dev_priv, well);
2223
2224         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2225         intel_power_well_disable(dev_priv, well);
2226
2227         mutex_unlock(&power_domains->lock);
2228 }
2229
2230 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2231                            bool resume)
2232 {
2233         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2234         struct i915_power_well *well;
2235         uint32_t val;
2236
2237         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2238
2239         /*
2240          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2241          * or else the reset will hang because there is no PCH to respond.
2242          * Move the handshake programming to initialization sequence.
2243          * Previously was left up to BIOS.
2244          */
2245         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2246         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2247         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2248
2249         /* Enable PG1 */
2250         mutex_lock(&power_domains->lock);
2251
2252         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2253         intel_power_well_enable(dev_priv, well);
2254
2255         mutex_unlock(&power_domains->lock);
2256
2257         broxton_init_cdclk(dev_priv);
2258         broxton_ddi_phy_init(dev_priv);
2259
2260         broxton_cdclk_verify_state(dev_priv);
2261         broxton_ddi_phy_verify_state(dev_priv);
2262
2263         if (resume && dev_priv->csr.dmc_payload)
2264                 intel_csr_load_program(dev_priv);
2265 }
2266
2267 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2268 {
2269         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2270         struct i915_power_well *well;
2271
2272         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2273
2274         broxton_ddi_phy_uninit(dev_priv);
2275         broxton_uninit_cdclk(dev_priv);
2276
2277         /* The spec doesn't call for removing the reset handshake flag */
2278
2279         /* Disable PG1 */
2280         mutex_lock(&power_domains->lock);
2281
2282         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2283         intel_power_well_disable(dev_priv, well);
2284
2285         mutex_unlock(&power_domains->lock);
2286 }
2287
2288 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2289 {
2290         struct i915_power_well *cmn_bc =
2291                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2292         struct i915_power_well *cmn_d =
2293                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2294
2295         /*
2296          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2297          * workaround never ever read DISPLAY_PHY_CONTROL, and
2298          * instead maintain a shadow copy ourselves. Use the actual
2299          * power well state and lane status to reconstruct the
2300          * expected initial value.
2301          */
2302         dev_priv->chv_phy_control =
2303                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2304                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2305                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2306                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2307                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2308
2309         /*
2310          * If all lanes are disabled we leave the override disabled
2311          * with all power down bits cleared to match the state we
2312          * would use after disabling the port. Otherwise enable the
2313          * override and set the lane powerdown bits accding to the
2314          * current lane status.
2315          */
2316         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2317                 uint32_t status = I915_READ(DPLL(PIPE_A));
2318                 unsigned int mask;
2319
2320                 mask = status & DPLL_PORTB_READY_MASK;
2321                 if (mask == 0xf)
2322                         mask = 0x0;
2323                 else
2324                         dev_priv->chv_phy_control |=
2325                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2326
2327                 dev_priv->chv_phy_control |=
2328                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2329
2330                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2331                 if (mask == 0xf)
2332                         mask = 0x0;
2333                 else
2334                         dev_priv->chv_phy_control |=
2335                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2336
2337                 dev_priv->chv_phy_control |=
2338                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2339
2340                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2341
2342                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2343         } else {
2344                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2345         }
2346
2347         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2348                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2349                 unsigned int mask;
2350
2351                 mask = status & DPLL_PORTD_READY_MASK;
2352
2353                 if (mask == 0xf)
2354                         mask = 0x0;
2355                 else
2356                         dev_priv->chv_phy_control |=
2357                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2358
2359                 dev_priv->chv_phy_control |=
2360                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2361
2362                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2363
2364                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2365         } else {
2366                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2367         }
2368
2369         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2370
2371         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2372                       dev_priv->chv_phy_control);
2373 }
2374
2375 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2376 {
2377         struct i915_power_well *cmn =
2378                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2379         struct i915_power_well *disp2d =
2380                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2381
2382         /* If the display might be already active skip this */
2383         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2384             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2385             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2386                 return;
2387
2388         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2389
2390         /* cmnlane needs DPLL registers */
2391         disp2d->ops->enable(dev_priv, disp2d);
2392
2393         /*
2394          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2395          * Need to assert and de-assert PHY SB reset by gating the
2396          * common lane power, then un-gating it.
2397          * Simply ungating isn't enough to reset the PHY enough to get
2398          * ports and lanes running.
2399          */
2400         cmn->ops->disable(dev_priv, cmn);
2401 }
2402
2403 /**
2404  * intel_power_domains_init_hw - initialize hardware power domain state
2405  * @dev_priv: i915 device instance
2406  *
2407  * This function initializes the hardware power domain state and enables all
2408  * power domains using intel_display_set_init_power().
2409  */
2410 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2411 {
2412         struct drm_device *dev = dev_priv->dev;
2413         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2414
2415         power_domains->initializing = true;
2416
2417         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2418                 skl_display_core_init(dev_priv, resume);
2419         } else if (IS_BROXTON(dev)) {
2420                 bxt_display_core_init(dev_priv, resume);
2421         } else if (IS_CHERRYVIEW(dev)) {
2422                 mutex_lock(&power_domains->lock);
2423                 chv_phy_control_init(dev_priv);
2424                 mutex_unlock(&power_domains->lock);
2425         } else if (IS_VALLEYVIEW(dev)) {
2426                 mutex_lock(&power_domains->lock);
2427                 vlv_cmnlane_wa(dev_priv);
2428                 mutex_unlock(&power_domains->lock);
2429         }
2430
2431         /* For now, we need the power well to be always enabled. */
2432         intel_display_set_init_power(dev_priv, true);
2433         /* Disable power support if the user asked so. */
2434         if (!i915.disable_power_well)
2435                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2436         intel_power_domains_sync_hw(dev_priv);
2437         power_domains->initializing = false;
2438 }
2439
2440 /**
2441  * intel_power_domains_suspend - suspend power domain state
2442  * @dev_priv: i915 device instance
2443  *
2444  * This function prepares the hardware power domain state before entering
2445  * system suspend. It must be paired with intel_power_domains_init_hw().
2446  */
2447 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2448 {
2449         /*
2450          * Even if power well support was disabled we still want to disable
2451          * power wells while we are system suspended.
2452          */
2453         if (!i915.disable_power_well)
2454                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2455
2456         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2457                 skl_display_core_uninit(dev_priv);
2458         else if (IS_BROXTON(dev_priv))
2459                 bxt_display_core_uninit(dev_priv);
2460 }
2461
2462 /**
2463  * intel_runtime_pm_get - grab a runtime pm reference
2464  * @dev_priv: i915 device instance
2465  *
2466  * This function grabs a device-level runtime pm reference (mostly used for GEM
2467  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2468  *
2469  * Any runtime pm reference obtained by this function must have a symmetric
2470  * call to intel_runtime_pm_put() to release the reference again.
2471  */
2472 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2473 {
2474         struct drm_device *dev = dev_priv->dev;
2475         struct device *device = &dev->pdev->dev;
2476
2477         pm_runtime_get_sync(device);
2478
2479         atomic_inc(&dev_priv->pm.wakeref_count);
2480         assert_rpm_wakelock_held(dev_priv);
2481 }
2482
2483 /**
2484  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2485  * @dev_priv: i915 device instance
2486  *
2487  * This function grabs a device-level runtime pm reference if the device is
2488  * already in use and ensures that it is powered up.
2489  *
2490  * Any runtime pm reference obtained by this function must have a symmetric
2491  * call to intel_runtime_pm_put() to release the reference again.
2492  */
2493 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2494 {
2495         struct drm_device *dev = dev_priv->dev;
2496         struct device *device = &dev->pdev->dev;
2497
2498         if (IS_ENABLED(CONFIG_PM)) {
2499                 int ret = pm_runtime_get_if_in_use(device);
2500
2501                 /*
2502                  * In cases runtime PM is disabled by the RPM core and we get
2503                  * an -EINVAL return value we are not supposed to call this
2504                  * function, since the power state is undefined. This applies
2505                  * atm to the late/early system suspend/resume handlers.
2506                  */
2507                 WARN_ON_ONCE(ret < 0);
2508                 if (ret <= 0)
2509                         return false;
2510         }
2511
2512         atomic_inc(&dev_priv->pm.wakeref_count);
2513         assert_rpm_wakelock_held(dev_priv);
2514
2515         return true;
2516 }
2517
2518 /**
2519  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2520  * @dev_priv: i915 device instance
2521  *
2522  * This function grabs a device-level runtime pm reference (mostly used for GEM
2523  * code to ensure the GTT or GT is on).
2524  *
2525  * It will _not_ power up the device but instead only check that it's powered
2526  * on.  Therefore it is only valid to call this functions from contexts where
2527  * the device is known to be powered up and where trying to power it up would
2528  * result in hilarity and deadlocks. That pretty much means only the system
2529  * suspend/resume code where this is used to grab runtime pm references for
2530  * delayed setup down in work items.
2531  *
2532  * Any runtime pm reference obtained by this function must have a symmetric
2533  * call to intel_runtime_pm_put() to release the reference again.
2534  */
2535 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2536 {
2537         struct drm_device *dev = dev_priv->dev;
2538         struct device *device = &dev->pdev->dev;
2539
2540         assert_rpm_wakelock_held(dev_priv);
2541         pm_runtime_get_noresume(device);
2542
2543         atomic_inc(&dev_priv->pm.wakeref_count);
2544 }
2545
2546 /**
2547  * intel_runtime_pm_put - release a runtime pm reference
2548  * @dev_priv: i915 device instance
2549  *
2550  * This function drops the device-level runtime pm reference obtained by
2551  * intel_runtime_pm_get() and might power down the corresponding
2552  * hardware block right away if this is the last reference.
2553  */
2554 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2555 {
2556         struct drm_device *dev = dev_priv->dev;
2557         struct device *device = &dev->pdev->dev;
2558
2559         assert_rpm_wakelock_held(dev_priv);
2560         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2561                 atomic_inc(&dev_priv->pm.atomic_seq);
2562
2563         pm_runtime_mark_last_busy(device);
2564         pm_runtime_put_autosuspend(device);
2565 }
2566
2567 /**
2568  * intel_runtime_pm_enable - enable runtime pm
2569  * @dev_priv: i915 device instance
2570  *
2571  * This function enables runtime pm at the end of the driver load sequence.
2572  *
2573  * Note that this function does currently not enable runtime pm for the
2574  * subordinate display power domains. That is only done on the first modeset
2575  * using intel_display_set_init_power().
2576  */
2577 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2578 {
2579         struct drm_device *dev = dev_priv->dev;
2580         struct device *device = &dev->pdev->dev;
2581
2582         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2583         pm_runtime_mark_last_busy(device);
2584
2585         /*
2586          * Take a permanent reference to disable the RPM functionality and drop
2587          * it only when unloading the driver. Use the low level get/put helpers,
2588          * so the driver's own RPM reference tracking asserts also work on
2589          * platforms without RPM support.
2590          */
2591         if (!HAS_RUNTIME_PM(dev)) {
2592                 pm_runtime_dont_use_autosuspend(device);
2593                 pm_runtime_get_sync(device);
2594         } else {
2595                 pm_runtime_use_autosuspend(device);
2596         }
2597
2598         /*
2599          * The core calls the driver load handler with an RPM reference held.
2600          * We drop that here and will reacquire it during unloading in
2601          * intel_power_domains_fini().
2602          */
2603         pm_runtime_put_autosuspend(device);
2604 }
2605