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26 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_
27 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_
29 #include "gpio_regs.h"
31 /****************************** new register headers */
32 /*** following in header */
34 #define DDC_GPIO_REG_LIST_ENTRY(type,cd,id) \
35 .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\
36 .type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\
37 .type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT
39 #define DDC_GPIO_REG_LIST(cd,id) \
41 DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
42 DDC_GPIO_REG_LIST_ENTRY(A,cd,id),\
43 DDC_GPIO_REG_LIST_ENTRY(EN,cd,id),\
44 DDC_GPIO_REG_LIST_ENTRY(Y,cd,id)\
47 #define DDC_REG_LIST(cd,id) \
48 DDC_GPIO_REG_LIST(cd,id),\
49 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
51 #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\
52 .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\
53 .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
54 .type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT
56 #define DDC_GPIO_VGA_REG_LIST(cd) \
58 DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\
59 DDC_GPIO_VGA_REG_LIST_ENTRY(A,cd),\
60 DDC_GPIO_VGA_REG_LIST_ENTRY(EN,cd),\
61 DDC_GPIO_VGA_REG_LIST_ENTRY(Y,cd)\
64 #define DDC_VGA_REG_LIST(cd) \
65 DDC_GPIO_VGA_REG_LIST(cd),\
66 .ddc_setup = mmDC_I2C_DDCVGA_SETUP
68 #define DDC_GPIO_I2C_REG_LIST_ENTRY(type,cd) \
69 .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\
70 .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\
71 .type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT
73 #define DDC_GPIO_I2C_REG_LIST(cd) \
75 DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\
76 DDC_GPIO_I2C_REG_LIST_ENTRY(A,cd),\
77 DDC_GPIO_I2C_REG_LIST_ENTRY(EN,cd),\
78 DDC_GPIO_I2C_REG_LIST_ENTRY(Y,cd)\
81 #define DDC_I2C_REG_LIST(cd) \
82 DDC_GPIO_I2C_REG_LIST(cd),\
85 #define DDC_MASK_SH_LIST(mask_sh) \
86 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
87 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\
88 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_MODE, mask_sh),\
89 SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1DATA_PD_EN, mask_sh),\
90 SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1CLK_PD_EN, mask_sh),\
91 SF_DDC(DC_GPIO_DDC1_MASK, AUX_PAD1_MODE, mask_sh),\
92 SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\
93 SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh)
96 struct ddc_registers {
97 struct gpio_registers gpio;
103 uint32_t DC_I2C_DDC1_ENABLE;
104 uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE;
105 uint32_t DC_I2C_DDC1_EDID_DETECT_MODE;
107 uint32_t DC_GPIO_DDC1DATA_PD_EN;
108 uint32_t DC_GPIO_DDC1CLK_PD_EN;
109 uint32_t AUX_PAD1_MODE;
111 uint32_t DC_GPIO_SDA_PD_DIS;
112 uint32_t DC_GPIO_SCL_PD_DIS;
117 /*** following in dc_resource */
119 #define ddc_data_regs(id) \
121 DDC_REG_LIST(DATA,id)\
124 #define ddc_clk_regs(id) \
126 DDC_REG_LIST(CLK,id)\
129 #define ddc_vga_data_regs \
131 DDC_VGA_REG_LIST(DATA)\
134 #define ddc_vga_clk_regs \
136 DDC_VGA_REG_LIST(CLK)\
139 #define ddc_i2c_data_regs \
141 DDC_I2C_REG_LIST(SDA)\
144 #define ddc_i2c_clk_regs \
146 DDC_I2C_REG_LIST(SCL)\
150 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */