2 * Procfs interface for the PCI bus.
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/proc_fs.h>
12 #include <linux/seq_file.h>
13 #include <linux/capability.h>
14 #include <asm/uaccess.h>
15 #include <asm/byteorder.h>
18 static int proc_initialized; /* = 0 */
21 proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
23 struct pci_dev *dev = PDE_DATA(file_inode(file));
24 return fixed_size_llseek(file, off, whence, dev->cfg_size);
28 proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
30 struct pci_dev *dev = PDE_DATA(file_inode(file));
31 unsigned int pos = *ppos;
32 unsigned int cnt, size;
35 * Normal users can read only the standardized portion of the
36 * configuration space as several chips lock up when trying to read
37 * undefined locations (think of Intel PIIX4 as a typical example).
40 if (capable(CAP_SYS_ADMIN))
42 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
51 if (pos + nbytes > size)
55 if (!access_ok(VERIFY_WRITE, buf, cnt))
58 pci_config_pm_runtime_get(dev);
60 if ((pos & 1) && cnt) {
62 pci_user_read_config_byte(dev, pos, &val);
69 if ((pos & 3) && cnt > 2) {
71 pci_user_read_config_word(dev, pos, &val);
72 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
80 pci_user_read_config_dword(dev, pos, &val);
81 __put_user(cpu_to_le32(val), (__le32 __user *) buf);
89 pci_user_read_config_word(dev, pos, &val);
90 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
98 pci_user_read_config_byte(dev, pos, &val);
105 pci_config_pm_runtime_put(dev);
112 proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, loff_t *ppos)
114 struct inode *ino = file_inode(file);
115 struct pci_dev *dev = PDE_DATA(ino);
117 int size = dev->cfg_size;
124 if (pos + nbytes > size)
128 if (!access_ok(VERIFY_READ, buf, cnt))
131 pci_config_pm_runtime_get(dev);
133 if ((pos & 1) && cnt) {
135 __get_user(val, buf);
136 pci_user_write_config_byte(dev, pos, val);
142 if ((pos & 3) && cnt > 2) {
144 __get_user(val, (__le16 __user *) buf);
145 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
153 __get_user(val, (__le32 __user *) buf);
154 pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
162 __get_user(val, (__le16 __user *) buf);
163 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
171 __get_user(val, buf);
172 pci_user_write_config_byte(dev, pos, val);
178 pci_config_pm_runtime_put(dev);
181 i_size_write(ino, dev->cfg_size);
185 struct pci_filp_private {
186 enum pci_mmap_state mmap_state;
190 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
193 struct pci_dev *dev = PDE_DATA(file_inode(file));
195 struct pci_filp_private *fpriv = file->private_data;
196 #endif /* HAVE_PCI_MMAP */
200 case PCIIOC_CONTROLLER:
201 ret = pci_domain_nr(dev->bus);
205 case PCIIOC_MMAP_IS_IO:
206 fpriv->mmap_state = pci_mmap_io;
209 case PCIIOC_MMAP_IS_MEM:
210 fpriv->mmap_state = pci_mmap_mem;
213 case PCIIOC_WRITE_COMBINE:
215 fpriv->write_combine = 1;
217 fpriv->write_combine = 0;
220 #endif /* HAVE_PCI_MMAP */
231 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
233 struct pci_dev *dev = PDE_DATA(file_inode(file));
234 struct pci_filp_private *fpriv = file->private_data;
237 if (!capable(CAP_SYS_RAWIO))
240 /* Make sure the caller is mapping a real resource for this device */
241 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
242 if (pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
246 if (i >= PCI_ROM_RESOURCE)
249 ret = pci_mmap_page_range(dev, vma,
251 fpriv->write_combine);
258 static int proc_bus_pci_open(struct inode *inode, struct file *file)
260 struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
265 fpriv->mmap_state = pci_mmap_io;
266 fpriv->write_combine = 0;
268 file->private_data = fpriv;
273 static int proc_bus_pci_release(struct inode *inode, struct file *file)
275 kfree(file->private_data);
276 file->private_data = NULL;
280 #endif /* HAVE_PCI_MMAP */
282 static const struct file_operations proc_bus_pci_operations = {
283 .owner = THIS_MODULE,
284 .llseek = proc_bus_pci_lseek,
285 .read = proc_bus_pci_read,
286 .write = proc_bus_pci_write,
287 .unlocked_ioctl = proc_bus_pci_ioctl,
288 .compat_ioctl = proc_bus_pci_ioctl,
290 .open = proc_bus_pci_open,
291 .release = proc_bus_pci_release,
292 .mmap = proc_bus_pci_mmap,
293 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
294 .get_unmapped_area = get_pci_unmapped_area,
295 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
296 #endif /* HAVE_PCI_MMAP */
300 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
302 struct pci_dev *dev = NULL;
305 for_each_pci_dev(dev) {
312 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
314 struct pci_dev *dev = v;
317 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
321 static void pci_seq_stop(struct seq_file *m, void *v)
324 struct pci_dev *dev = v;
329 static int show_device(struct seq_file *m, void *v)
331 const struct pci_dev *dev = v;
332 const struct pci_driver *drv;
338 drv = pci_dev_driver(dev);
339 seq_printf(m, "%02x%02x\t%04x%04x\t%x",
346 /* only print standard and ROM resources to preserve compatibility */
347 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
348 resource_size_t start, end;
349 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
350 seq_printf(m, "\t%16llx",
351 (unsigned long long)(start |
352 (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
354 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
355 resource_size_t start, end;
356 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
357 seq_printf(m, "\t%16llx",
358 dev->resource[i].start < dev->resource[i].end ?
359 (unsigned long long)(end - start) + 1 : 0);
363 seq_printf(m, "%s", drv->name);
368 static const struct seq_operations proc_bus_pci_devices_op = {
369 .start = pci_seq_start,
370 .next = pci_seq_next,
371 .stop = pci_seq_stop,
375 static struct proc_dir_entry *proc_bus_pci_dir;
377 int pci_proc_attach_device(struct pci_dev *dev)
379 struct pci_bus *bus = dev->bus;
380 struct proc_dir_entry *e;
383 if (!proc_initialized)
387 if (pci_proc_domain(bus)) {
388 sprintf(name, "%04x:%02x", pci_domain_nr(bus),
391 sprintf(name, "%02x", bus->number);
393 bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
398 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
399 e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
400 &proc_bus_pci_operations, dev);
403 proc_set_size(e, dev->cfg_size);
409 int pci_proc_detach_device(struct pci_dev *dev)
411 proc_remove(dev->procent);
416 int pci_proc_detach_bus(struct pci_bus* bus)
418 proc_remove(bus->procdir);
422 static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
424 return seq_open(file, &proc_bus_pci_devices_op);
426 static const struct file_operations proc_bus_pci_dev_operations = {
427 .owner = THIS_MODULE,
428 .open = proc_bus_pci_dev_open,
431 .release = seq_release,
434 static int __init pci_proc_init(void)
436 struct pci_dev *dev = NULL;
437 proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
438 proc_create("devices", 0, proc_bus_pci_dir,
439 &proc_bus_pci_dev_operations);
440 proc_initialized = 1;
441 for_each_pci_dev(dev)
442 pci_proc_attach_device(dev);
447 device_initcall(pci_proc_init);