1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
5 // Copyright 2018 Realtek Semiconductor Corp.
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/mutex.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/jack.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 #include <sound/rt5682.h>
33 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
40 EXPORT_SYMBOL_GPL(rt5682_supply_names);
42 static const struct reg_sequence patch_list[] = {
43 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
44 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
45 {RT5682_I2C_CTRL, 0x000f},
46 {RT5682_PLL2_INTERNAL, 0x8266},
47 {RT5682_SAR_IL_CMD_1, 0x22b7},
48 {RT5682_SAR_IL_CMD_3, 0x0365},
49 {RT5682_SAR_IL_CMD_6, 0x0110},
50 {RT5682_CHARGE_PUMP_1, 0x0210},
51 {RT5682_HP_LOGIC_CTRL_2, 0x0007},
52 {RT5682_SAR_IL_CMD_2, 0xac00},
53 {RT5682_CBJ_CTRL_7, 0x0104},
56 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
60 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
61 ARRAY_SIZE(patch_list));
63 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
65 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
67 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
387 EXPORT_SYMBOL_GPL(rt5682_reg);
389 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
393 case RT5682_CBJ_CTRL_2:
394 case RT5682_INT_ST_1:
395 case RT5682_4BTN_IL_CMD_1:
396 case RT5682_AJD1_CTRL:
397 case RT5682_HP_CALIB_CTRL_1:
398 case RT5682_INT_DEVICE_ID:
399 case RT5682_DEVICE_ID:
400 case RT5682_I2C_MODE:
401 case RT5682_HP_CALIB_CTRL_10:
402 case RT5682_EFUSE_CTRL_2:
403 case RT5682_JD_TOP_VC_VTRL:
404 case RT5682_HP_IMP_SENS_CTRL_19:
405 case RT5682_IL_CMD_1:
406 case RT5682_SAR_IL_CMD_2:
407 case RT5682_SAR_IL_CMD_4:
408 case RT5682_SAR_IL_CMD_10:
409 case RT5682_SAR_IL_CMD_11:
410 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
411 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
417 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
419 bool rt5682_readable_register(struct device *dev, unsigned int reg)
423 case RT5682_INT_DEVICE_ID:
424 case RT5682_VERSION_ID:
425 case RT5682_VENDOR_ID:
426 case RT5682_DEVICE_ID:
427 case RT5682_HP_CTRL_1:
428 case RT5682_HP_CTRL_2:
429 case RT5682_HPL_GAIN:
430 case RT5682_HPR_GAIN:
431 case RT5682_I2C_CTRL:
432 case RT5682_CBJ_BST_CTRL:
433 case RT5682_CBJ_CTRL_1:
434 case RT5682_CBJ_CTRL_2:
435 case RT5682_CBJ_CTRL_3:
436 case RT5682_CBJ_CTRL_4:
437 case RT5682_CBJ_CTRL_5:
438 case RT5682_CBJ_CTRL_6:
439 case RT5682_CBJ_CTRL_7:
440 case RT5682_DAC1_DIG_VOL:
441 case RT5682_STO1_ADC_DIG_VOL:
442 case RT5682_STO1_ADC_BOOST:
443 case RT5682_HP_IMP_GAIN_1:
444 case RT5682_HP_IMP_GAIN_2:
445 case RT5682_SIDETONE_CTRL:
446 case RT5682_STO1_ADC_MIXER:
447 case RT5682_AD_DA_MIXER:
448 case RT5682_STO1_DAC_MIXER:
449 case RT5682_A_DAC1_MUX:
450 case RT5682_DIG_INF2_DATA:
451 case RT5682_REC_MIXER:
453 case RT5682_ALC_BACK_GAIN:
454 case RT5682_PWR_DIG_1:
455 case RT5682_PWR_DIG_2:
456 case RT5682_PWR_ANLG_1:
457 case RT5682_PWR_ANLG_2:
458 case RT5682_PWR_ANLG_3:
459 case RT5682_PWR_MIXER:
462 case RT5682_RESET_LPF_CTRL:
463 case RT5682_RESET_HPF_CTRL:
464 case RT5682_DMIC_CTRL_1:
465 case RT5682_I2S1_SDP:
466 case RT5682_I2S2_SDP:
467 case RT5682_ADDA_CLK_1:
468 case RT5682_ADDA_CLK_2:
469 case RT5682_I2S1_F_DIV_CTRL_1:
470 case RT5682_I2S1_F_DIV_CTRL_2:
471 case RT5682_TDM_CTRL:
472 case RT5682_TDM_ADDA_CTRL_1:
473 case RT5682_TDM_ADDA_CTRL_2:
474 case RT5682_DATA_SEL_CTRL_1:
475 case RT5682_TDM_TCON_CTRL:
477 case RT5682_PLL_CTRL_1:
478 case RT5682_PLL_CTRL_2:
479 case RT5682_PLL_TRACK_1:
480 case RT5682_PLL_TRACK_2:
481 case RT5682_PLL_TRACK_3:
482 case RT5682_PLL_TRACK_4:
483 case RT5682_PLL_TRACK_5:
484 case RT5682_PLL_TRACK_6:
485 case RT5682_PLL_TRACK_11:
486 case RT5682_SDW_REF_CLK:
489 case RT5682_HP_CHARGE_PUMP_1:
490 case RT5682_HP_CHARGE_PUMP_2:
491 case RT5682_MICBIAS_1:
492 case RT5682_MICBIAS_2:
493 case RT5682_PLL_TRACK_12:
494 case RT5682_PLL_TRACK_14:
495 case RT5682_PLL2_CTRL_1:
496 case RT5682_PLL2_CTRL_2:
497 case RT5682_PLL2_CTRL_3:
498 case RT5682_PLL2_CTRL_4:
499 case RT5682_RC_CLK_CTRL:
500 case RT5682_I2S_M_CLK_CTRL_1:
501 case RT5682_I2S2_F_DIV_CTRL_1:
502 case RT5682_I2S2_F_DIV_CTRL_2:
503 case RT5682_EQ_CTRL_1:
504 case RT5682_EQ_CTRL_2:
505 case RT5682_IRQ_CTRL_1:
506 case RT5682_IRQ_CTRL_2:
507 case RT5682_IRQ_CTRL_3:
508 case RT5682_IRQ_CTRL_4:
509 case RT5682_INT_ST_1:
510 case RT5682_GPIO_CTRL_1:
511 case RT5682_GPIO_CTRL_2:
512 case RT5682_GPIO_CTRL_3:
513 case RT5682_HP_AMP_DET_CTRL_1:
514 case RT5682_HP_AMP_DET_CTRL_2:
515 case RT5682_MID_HP_AMP_DET:
516 case RT5682_LOW_HP_AMP_DET:
517 case RT5682_DELAY_BUF_CTRL:
518 case RT5682_SV_ZCD_1:
519 case RT5682_SV_ZCD_2:
520 case RT5682_IL_CMD_1:
521 case RT5682_IL_CMD_2:
522 case RT5682_IL_CMD_3:
523 case RT5682_IL_CMD_4:
524 case RT5682_IL_CMD_5:
525 case RT5682_IL_CMD_6:
526 case RT5682_4BTN_IL_CMD_1:
527 case RT5682_4BTN_IL_CMD_2:
528 case RT5682_4BTN_IL_CMD_3:
529 case RT5682_4BTN_IL_CMD_4:
530 case RT5682_4BTN_IL_CMD_5:
531 case RT5682_4BTN_IL_CMD_6:
532 case RT5682_4BTN_IL_CMD_7:
533 case RT5682_ADC_STO1_HP_CTRL_1:
534 case RT5682_ADC_STO1_HP_CTRL_2:
535 case RT5682_AJD1_CTRL:
538 case RT5682_JD_CTRL_1:
542 case RT5682_DAC_ADC_DIG_VOL1:
543 case RT5682_BIAS_CUR_CTRL_2:
544 case RT5682_BIAS_CUR_CTRL_3:
545 case RT5682_BIAS_CUR_CTRL_4:
546 case RT5682_BIAS_CUR_CTRL_5:
547 case RT5682_BIAS_CUR_CTRL_6:
548 case RT5682_BIAS_CUR_CTRL_7:
549 case RT5682_BIAS_CUR_CTRL_8:
550 case RT5682_BIAS_CUR_CTRL_9:
551 case RT5682_BIAS_CUR_CTRL_10:
552 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
553 case RT5682_CHARGE_PUMP_1:
554 case RT5682_DIG_IN_CTRL_1:
555 case RT5682_PAD_DRIVING_CTRL:
556 case RT5682_SOFT_RAMP_DEPOP:
557 case RT5682_CHOP_DAC:
558 case RT5682_CHOP_ADC:
559 case RT5682_CALIB_ADC_CTRL:
560 case RT5682_VOL_TEST:
561 case RT5682_SPKVDD_DET_STA:
562 case RT5682_TEST_MODE_CTRL_1:
563 case RT5682_TEST_MODE_CTRL_2:
564 case RT5682_TEST_MODE_CTRL_3:
565 case RT5682_TEST_MODE_CTRL_4:
566 case RT5682_TEST_MODE_CTRL_5:
567 case RT5682_PLL1_INTERNAL:
568 case RT5682_PLL2_INTERNAL:
569 case RT5682_STO_NG2_CTRL_1:
570 case RT5682_STO_NG2_CTRL_2:
571 case RT5682_STO_NG2_CTRL_3:
572 case RT5682_STO_NG2_CTRL_4:
573 case RT5682_STO_NG2_CTRL_5:
574 case RT5682_STO_NG2_CTRL_6:
575 case RT5682_STO_NG2_CTRL_7:
576 case RT5682_STO_NG2_CTRL_8:
577 case RT5682_STO_NG2_CTRL_9:
578 case RT5682_STO_NG2_CTRL_10:
579 case RT5682_STO1_DAC_SIL_DET:
580 case RT5682_SIL_PSV_CTRL1:
581 case RT5682_SIL_PSV_CTRL2:
582 case RT5682_SIL_PSV_CTRL3:
583 case RT5682_SIL_PSV_CTRL4:
584 case RT5682_SIL_PSV_CTRL5:
585 case RT5682_HP_IMP_SENS_CTRL_01:
586 case RT5682_HP_IMP_SENS_CTRL_02:
587 case RT5682_HP_IMP_SENS_CTRL_03:
588 case RT5682_HP_IMP_SENS_CTRL_04:
589 case RT5682_HP_IMP_SENS_CTRL_05:
590 case RT5682_HP_IMP_SENS_CTRL_06:
591 case RT5682_HP_IMP_SENS_CTRL_07:
592 case RT5682_HP_IMP_SENS_CTRL_08:
593 case RT5682_HP_IMP_SENS_CTRL_09:
594 case RT5682_HP_IMP_SENS_CTRL_10:
595 case RT5682_HP_IMP_SENS_CTRL_11:
596 case RT5682_HP_IMP_SENS_CTRL_12:
597 case RT5682_HP_IMP_SENS_CTRL_13:
598 case RT5682_HP_IMP_SENS_CTRL_14:
599 case RT5682_HP_IMP_SENS_CTRL_15:
600 case RT5682_HP_IMP_SENS_CTRL_16:
601 case RT5682_HP_IMP_SENS_CTRL_17:
602 case RT5682_HP_IMP_SENS_CTRL_18:
603 case RT5682_HP_IMP_SENS_CTRL_19:
604 case RT5682_HP_IMP_SENS_CTRL_20:
605 case RT5682_HP_IMP_SENS_CTRL_21:
606 case RT5682_HP_IMP_SENS_CTRL_22:
607 case RT5682_HP_IMP_SENS_CTRL_23:
608 case RT5682_HP_IMP_SENS_CTRL_24:
609 case RT5682_HP_IMP_SENS_CTRL_25:
610 case RT5682_HP_IMP_SENS_CTRL_26:
611 case RT5682_HP_IMP_SENS_CTRL_27:
612 case RT5682_HP_IMP_SENS_CTRL_28:
613 case RT5682_HP_IMP_SENS_CTRL_29:
614 case RT5682_HP_IMP_SENS_CTRL_30:
615 case RT5682_HP_IMP_SENS_CTRL_31:
616 case RT5682_HP_IMP_SENS_CTRL_32:
617 case RT5682_HP_IMP_SENS_CTRL_33:
618 case RT5682_HP_IMP_SENS_CTRL_34:
619 case RT5682_HP_IMP_SENS_CTRL_35:
620 case RT5682_HP_IMP_SENS_CTRL_36:
621 case RT5682_HP_IMP_SENS_CTRL_37:
622 case RT5682_HP_IMP_SENS_CTRL_38:
623 case RT5682_HP_IMP_SENS_CTRL_39:
624 case RT5682_HP_IMP_SENS_CTRL_40:
625 case RT5682_HP_IMP_SENS_CTRL_41:
626 case RT5682_HP_IMP_SENS_CTRL_42:
627 case RT5682_HP_IMP_SENS_CTRL_43:
628 case RT5682_HP_LOGIC_CTRL_1:
629 case RT5682_HP_LOGIC_CTRL_2:
630 case RT5682_HP_LOGIC_CTRL_3:
631 case RT5682_HP_CALIB_CTRL_1:
632 case RT5682_HP_CALIB_CTRL_2:
633 case RT5682_HP_CALIB_CTRL_3:
634 case RT5682_HP_CALIB_CTRL_4:
635 case RT5682_HP_CALIB_CTRL_5:
636 case RT5682_HP_CALIB_CTRL_6:
637 case RT5682_HP_CALIB_CTRL_7:
638 case RT5682_HP_CALIB_CTRL_9:
639 case RT5682_HP_CALIB_CTRL_10:
640 case RT5682_HP_CALIB_CTRL_11:
641 case RT5682_HP_CALIB_STA_1:
642 case RT5682_HP_CALIB_STA_2:
643 case RT5682_HP_CALIB_STA_3:
644 case RT5682_HP_CALIB_STA_4:
645 case RT5682_HP_CALIB_STA_5:
646 case RT5682_HP_CALIB_STA_6:
647 case RT5682_HP_CALIB_STA_7:
648 case RT5682_HP_CALIB_STA_8:
649 case RT5682_HP_CALIB_STA_9:
650 case RT5682_HP_CALIB_STA_10:
651 case RT5682_HP_CALIB_STA_11:
652 case RT5682_SAR_IL_CMD_1:
653 case RT5682_SAR_IL_CMD_2:
654 case RT5682_SAR_IL_CMD_3:
655 case RT5682_SAR_IL_CMD_4:
656 case RT5682_SAR_IL_CMD_5:
657 case RT5682_SAR_IL_CMD_6:
658 case RT5682_SAR_IL_CMD_7:
659 case RT5682_SAR_IL_CMD_8:
660 case RT5682_SAR_IL_CMD_9:
661 case RT5682_SAR_IL_CMD_10:
662 case RT5682_SAR_IL_CMD_11:
663 case RT5682_SAR_IL_CMD_12:
664 case RT5682_SAR_IL_CMD_13:
665 case RT5682_EFUSE_CTRL_1:
666 case RT5682_EFUSE_CTRL_2:
667 case RT5682_EFUSE_CTRL_3:
668 case RT5682_EFUSE_CTRL_4:
669 case RT5682_EFUSE_CTRL_5:
670 case RT5682_EFUSE_CTRL_6:
671 case RT5682_EFUSE_CTRL_7:
672 case RT5682_EFUSE_CTRL_8:
673 case RT5682_EFUSE_CTRL_9:
674 case RT5682_EFUSE_CTRL_10:
675 case RT5682_EFUSE_CTRL_11:
676 case RT5682_JD_TOP_VC_VTRL:
677 case RT5682_DRC1_CTRL_0:
678 case RT5682_DRC1_CTRL_1:
679 case RT5682_DRC1_CTRL_2:
680 case RT5682_DRC1_CTRL_3:
681 case RT5682_DRC1_CTRL_4:
682 case RT5682_DRC1_CTRL_5:
683 case RT5682_DRC1_CTRL_6:
684 case RT5682_DRC1_HARD_LMT_CTRL_1:
685 case RT5682_DRC1_HARD_LMT_CTRL_2:
686 case RT5682_DRC1_PRIV_1:
687 case RT5682_DRC1_PRIV_2:
688 case RT5682_DRC1_PRIV_3:
689 case RT5682_DRC1_PRIV_4:
690 case RT5682_DRC1_PRIV_5:
691 case RT5682_DRC1_PRIV_6:
692 case RT5682_DRC1_PRIV_7:
693 case RT5682_DRC1_PRIV_8:
694 case RT5682_EQ_AUTO_RCV_CTRL1:
695 case RT5682_EQ_AUTO_RCV_CTRL2:
696 case RT5682_EQ_AUTO_RCV_CTRL3:
697 case RT5682_EQ_AUTO_RCV_CTRL4:
698 case RT5682_EQ_AUTO_RCV_CTRL5:
699 case RT5682_EQ_AUTO_RCV_CTRL6:
700 case RT5682_EQ_AUTO_RCV_CTRL7:
701 case RT5682_EQ_AUTO_RCV_CTRL8:
702 case RT5682_EQ_AUTO_RCV_CTRL9:
703 case RT5682_EQ_AUTO_RCV_CTRL10:
704 case RT5682_EQ_AUTO_RCV_CTRL11:
705 case RT5682_EQ_AUTO_RCV_CTRL12:
706 case RT5682_EQ_AUTO_RCV_CTRL13:
707 case RT5682_ADC_L_EQ_LPF1_A1:
708 case RT5682_R_EQ_LPF1_A1:
709 case RT5682_L_EQ_LPF1_H0:
710 case RT5682_R_EQ_LPF1_H0:
711 case RT5682_L_EQ_BPF1_A1:
712 case RT5682_R_EQ_BPF1_A1:
713 case RT5682_L_EQ_BPF1_A2:
714 case RT5682_R_EQ_BPF1_A2:
715 case RT5682_L_EQ_BPF1_H0:
716 case RT5682_R_EQ_BPF1_H0:
717 case RT5682_L_EQ_BPF2_A1:
718 case RT5682_R_EQ_BPF2_A1:
719 case RT5682_L_EQ_BPF2_A2:
720 case RT5682_R_EQ_BPF2_A2:
721 case RT5682_L_EQ_BPF2_H0:
722 case RT5682_R_EQ_BPF2_H0:
723 case RT5682_L_EQ_BPF3_A1:
724 case RT5682_R_EQ_BPF3_A1:
725 case RT5682_L_EQ_BPF3_A2:
726 case RT5682_R_EQ_BPF3_A2:
727 case RT5682_L_EQ_BPF3_H0:
728 case RT5682_R_EQ_BPF3_H0:
729 case RT5682_L_EQ_BPF4_A1:
730 case RT5682_R_EQ_BPF4_A1:
731 case RT5682_L_EQ_BPF4_A2:
732 case RT5682_R_EQ_BPF4_A2:
733 case RT5682_L_EQ_BPF4_H0:
734 case RT5682_R_EQ_BPF4_H0:
735 case RT5682_L_EQ_HPF1_A1:
736 case RT5682_R_EQ_HPF1_A1:
737 case RT5682_L_EQ_HPF1_H0:
738 case RT5682_R_EQ_HPF1_H0:
739 case RT5682_L_EQ_PRE_VOL:
740 case RT5682_R_EQ_PRE_VOL:
741 case RT5682_L_EQ_POST_VOL:
742 case RT5682_R_EQ_POST_VOL:
743 case RT5682_I2C_MODE:
749 EXPORT_SYMBOL_GPL(rt5682_readable_register);
751 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
752 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
753 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
755 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
756 static const DECLARE_TLV_DB_RANGE(bst_tlv,
757 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
758 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
759 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
760 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
761 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
762 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
763 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
766 /* Interface data select */
767 static const char * const rt5682_data_select[] = {
768 "L/R", "R/L", "L/L", "R/R"
771 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
772 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
774 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
775 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
777 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
778 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
780 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
781 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
783 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
784 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
786 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
787 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
789 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
790 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
792 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
793 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
795 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
796 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
798 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
799 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
801 static const char * const rt5682_dac_select[] = {
805 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
806 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
808 static const struct snd_kcontrol_new rt5682_dac_l_mux =
809 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
811 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
812 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
814 static const struct snd_kcontrol_new rt5682_dac_r_mux =
815 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
817 void rt5682_reset(struct rt5682_priv *rt5682)
819 regmap_write(rt5682->regmap, RT5682_RESET, 0);
821 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
823 EXPORT_SYMBOL_GPL(rt5682_reset);
826 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
827 * @component: SoC audio component device.
828 * @filter_mask: mask of filters.
829 * @clk_src: clock source
831 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
832 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
833 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
834 * ASRC function will track i2s clock and generate a corresponding system clock
835 * for codec. This function provides an API to select the clock source for a
836 * set of filters specified by the mask. And the component driver will turn on
837 * ASRC for these filters if ASRC is selected as their clock source.
839 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
840 unsigned int filter_mask, unsigned int clk_src)
843 case RT5682_CLK_SEL_SYS:
844 case RT5682_CLK_SEL_I2S1_ASRC:
845 case RT5682_CLK_SEL_I2S2_ASRC:
852 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
853 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
854 RT5682_FILTER_CLK_SEL_MASK,
855 clk_src << RT5682_FILTER_CLK_SEL_SFT);
858 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
859 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
860 RT5682_FILTER_CLK_SEL_MASK,
861 clk_src << RT5682_FILTER_CLK_SEL_SFT);
866 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
868 static int rt5682_button_detect(struct snd_soc_component *component)
872 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
873 btn_type = val & 0xfff0;
874 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
875 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
876 snd_soc_component_update_bits(component,
877 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
882 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
885 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
888 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
889 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
890 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
891 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
892 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
893 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
894 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
895 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
897 snd_soc_component_update_bits(component,
899 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
900 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
902 snd_soc_component_update_bits(component,
903 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
906 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
907 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
908 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
909 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
910 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
911 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
912 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
913 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
914 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
915 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
920 * rt5682_headset_detect - Detect headset.
921 * @component: SoC audio component device.
922 * @jack_insert: Jack insert or not.
924 * Detect whether is headset or not when jack inserted.
926 * Returns detect status.
928 static int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
930 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
931 struct snd_soc_dapm_context *dapm = &component->dapm;
932 unsigned int val, count;
935 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
936 RT5682_PWR_VREF2 | RT5682_PWR_MB,
937 RT5682_PWR_VREF2 | RT5682_PWR_MB);
938 snd_soc_component_update_bits(component,
939 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
940 usleep_range(15000, 20000);
941 snd_soc_component_update_bits(component,
942 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
943 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
944 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
945 snd_soc_component_update_bits(component,
946 RT5682_HP_CHARGE_PUMP_1,
947 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
948 rt5682_enable_push_button_irq(component, false);
949 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
950 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
951 usleep_range(55000, 60000);
952 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
953 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
956 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
957 & RT5682_JACK_TYPE_MASK;
958 while (val == 0 && count < 50) {
959 usleep_range(10000, 15000);
960 val = snd_soc_component_read(component,
961 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
968 rt5682->jack_type = SND_JACK_HEADSET;
969 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
970 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
971 rt5682_enable_push_button_irq(component, true);
974 rt5682->jack_type = SND_JACK_HEADPHONE;
978 snd_soc_component_update_bits(component,
979 RT5682_HP_CHARGE_PUMP_1,
980 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
981 RT5682_OSW_L_EN | RT5682_OSW_R_EN);
982 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
983 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
984 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
986 rt5682_enable_push_button_irq(component, false);
987 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
988 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
989 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
990 !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
991 !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
992 snd_soc_component_update_bits(component,
993 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
994 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
995 !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
996 !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
997 snd_soc_component_update_bits(component,
998 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
999 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
1001 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
1002 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
1003 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
1004 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
1005 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
1007 rt5682->jack_type = 0;
1010 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
1011 return rt5682->jack_type;
1014 static int rt5682_set_jack_detect(struct snd_soc_component *component,
1015 struct snd_soc_jack *hs_jack, void *data)
1017 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1019 rt5682->hs_jack = hs_jack;
1021 if (rt5682->is_sdw && !rt5682->first_hw_init)
1025 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1026 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1027 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1028 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1029 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1034 if (!rt5682->is_sdw) {
1035 switch (rt5682->pdata.jd_src) {
1037 snd_soc_component_update_bits(component,
1038 RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
1039 snd_soc_component_update_bits(component,
1040 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1041 RT5682_EXT_JD_SRC_MANUAL);
1042 snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1044 snd_soc_component_update_bits(component,
1045 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1046 RT5682_CBJ_IN_BUF_EN);
1047 snd_soc_component_update_bits(component,
1048 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1050 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1051 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1052 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1053 RT5682_POW_IRQ | RT5682_POW_JDH |
1054 RT5682_POW_ANA, RT5682_POW_IRQ |
1055 RT5682_POW_JDH | RT5682_POW_ANA);
1056 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1057 RT5682_PWR_JDH, RT5682_PWR_JDH);
1058 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1059 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1060 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1061 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1062 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1063 rt5682->pdata.btndet_delay));
1064 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1065 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1066 rt5682->pdata.btndet_delay));
1067 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1068 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1069 rt5682->pdata.btndet_delay));
1070 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1071 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1072 rt5682->pdata.btndet_delay));
1073 mod_delayed_work(system_power_efficient_wq,
1074 &rt5682->jack_detect_work,
1075 msecs_to_jiffies(250));
1078 case RT5682_JD_NULL:
1079 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1080 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1081 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1082 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1086 dev_warn(component->dev, "Wrong JD source\n");
1094 void rt5682_jack_detect_handler(struct work_struct *work)
1096 struct rt5682_priv *rt5682 =
1097 container_of(work, struct rt5682_priv, jack_detect_work.work);
1098 struct snd_soc_dapm_context *dapm;
1101 if (!rt5682->component ||
1102 !snd_soc_card_is_instantiated(rt5682->component->card)) {
1103 /* card not yet ready, try later */
1104 mod_delayed_work(system_power_efficient_wq,
1105 &rt5682->jack_detect_work, msecs_to_jiffies(15));
1109 if (rt5682->is_sdw) {
1110 if (pm_runtime_status_suspended(rt5682->slave->dev.parent)) {
1111 dev_dbg(&rt5682->slave->dev,
1112 "%s: parent device is pm_runtime_status_suspended, skipping jack detection\n",
1118 dapm = snd_soc_component_get_dapm(rt5682->component);
1120 snd_soc_dapm_mutex_lock(dapm);
1121 mutex_lock(&rt5682->calibrate_mutex);
1123 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1124 & RT5682_JDH_RS_MASK;
1127 if (rt5682->jack_type == 0) {
1128 /* jack was out, report jack type */
1130 rt5682_headset_detect(rt5682->component, 1);
1131 rt5682->irq_work_delay_time = 0;
1132 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1134 /* jack is already in, report button event */
1135 rt5682->jack_type = SND_JACK_HEADSET;
1136 btn_type = rt5682_button_detect(rt5682->component);
1138 * rt5682 can report three kinds of button behavior,
1139 * one click, double click and hold. However,
1140 * currently we will report button pressed/released
1141 * event. So all the three button behaviors are
1142 * treated as button pressed.
1148 rt5682->jack_type |= SND_JACK_BTN_0;
1153 rt5682->jack_type |= SND_JACK_BTN_1;
1158 rt5682->jack_type |= SND_JACK_BTN_2;
1163 rt5682->jack_type |= SND_JACK_BTN_3;
1165 case 0x0000: /* unpressed */
1168 dev_err(rt5682->component->dev,
1169 "Unexpected button code 0x%04x\n",
1176 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1177 rt5682->irq_work_delay_time = 50;
1180 mutex_unlock(&rt5682->calibrate_mutex);
1181 snd_soc_dapm_mutex_unlock(dapm);
1183 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1185 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1186 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1188 if (!rt5682->is_sdw) {
1189 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1190 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1191 schedule_delayed_work(&rt5682->jd_check_work, 0);
1193 cancel_delayed_work_sync(&rt5682->jd_check_work);
1196 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1198 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1199 /* DAC Digital Volume */
1200 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1201 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1203 /* IN Boost Volume */
1204 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1205 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1207 /* ADC Digital Volume Control */
1208 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1209 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1210 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1211 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1213 /* ADC Boost Volume Control */
1214 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1215 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1219 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1220 int target, const int div[], int size)
1224 if (rt5682->sysclk < target) {
1225 dev_err(rt5682->component->dev,
1226 "sysclk rate %d is too low\n", rt5682->sysclk);
1230 for (i = 0; i < size - 1; i++) {
1231 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1232 if (target * div[i] == rt5682->sysclk)
1234 if (target * div[i + 1] > rt5682->sysclk) {
1235 dev_dbg(rt5682->component->dev,
1236 "can't find div for sysclk %d\n",
1242 if (target * div[i] < rt5682->sysclk)
1243 dev_err(rt5682->component->dev,
1244 "sysclk rate %d is too high\n", rt5682->sysclk);
1250 * set_dmic_clk - Set parameter of dmic.
1253 * @kcontrol: The kcontrol of this widget.
1256 * Choose dmic clock between 1MHz and 3MHz.
1257 * It is better for clock to approximate 3MHz.
1259 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1260 struct snd_kcontrol *kcontrol, int event)
1262 struct snd_soc_component *component =
1263 snd_soc_dapm_to_component(w->dapm);
1264 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1265 int idx, dmic_clk_rate = 3072000;
1266 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1268 if (rt5682->pdata.dmic_clk_rate)
1269 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1271 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1273 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1274 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1279 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1280 struct snd_kcontrol *kcontrol, int event)
1282 struct snd_soc_component *component =
1283 snd_soc_dapm_to_component(w->dapm);
1284 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1285 int ref, val, reg, idx;
1286 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1287 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1292 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1293 RT5682_GP4_PIN_MASK;
1294 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1295 val == RT5682_GP4_PIN_ADCDAT2)
1296 ref = 256 * rt5682->lrck[RT5682_AIF2];
1298 ref = 256 * rt5682->lrck[RT5682_AIF1];
1300 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1302 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1303 reg = RT5682_PLL_TRACK_3;
1305 reg = RT5682_PLL_TRACK_2;
1307 snd_soc_component_update_bits(component, reg,
1308 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1310 /* select over sample rate */
1311 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1312 if (rt5682->sysclk <= 12288000 * div_o[idx])
1316 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1317 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1318 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1323 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1324 struct snd_soc_dapm_widget *sink)
1327 struct snd_soc_component *component =
1328 snd_soc_dapm_to_component(w->dapm);
1330 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1331 val &= RT5682_SCLK_SRC_MASK;
1332 if (val == RT5682_SCLK_SRC_PLL1)
1338 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1339 struct snd_soc_dapm_widget *sink)
1342 struct snd_soc_component *component =
1343 snd_soc_dapm_to_component(w->dapm);
1345 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1346 val &= RT5682_SCLK_SRC_MASK;
1347 if (val == RT5682_SCLK_SRC_PLL2)
1353 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1354 struct snd_soc_dapm_widget *sink)
1356 unsigned int reg, shift, val;
1357 struct snd_soc_component *component =
1358 snd_soc_dapm_to_component(w->dapm);
1361 case RT5682_ADC_STO1_ASRC_SFT:
1362 reg = RT5682_PLL_TRACK_3;
1363 shift = RT5682_FILTER_CLK_SEL_SFT;
1365 case RT5682_DAC_STO1_ASRC_SFT:
1366 reg = RT5682_PLL_TRACK_2;
1367 shift = RT5682_FILTER_CLK_SEL_SFT;
1373 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1375 case RT5682_CLK_SEL_I2S1_ASRC:
1376 case RT5682_CLK_SEL_I2S2_ASRC:
1384 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1385 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1386 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1387 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1388 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1391 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1392 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1393 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1394 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1395 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1398 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1399 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1400 RT5682_M_ADCMIX_L_SFT, 1, 1),
1401 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1402 RT5682_M_DAC1_L_SFT, 1, 1),
1405 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1406 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1407 RT5682_M_ADCMIX_R_SFT, 1, 1),
1408 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1409 RT5682_M_DAC1_R_SFT, 1, 1),
1412 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1413 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1414 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1415 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1416 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1419 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1420 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1421 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1422 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1423 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1426 /* Analog Input Mixer */
1427 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1428 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1429 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1432 /* STO1 ADC1 Source */
1433 /* MX-26 [13] [5] */
1434 static const char * const rt5682_sto1_adc1_src[] = {
1438 static SOC_ENUM_SINGLE_DECL(
1439 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1440 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1442 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1443 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1445 static SOC_ENUM_SINGLE_DECL(
1446 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1447 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1449 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1450 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1452 /* STO1 ADC Source */
1453 /* MX-26 [11:10] [3:2] */
1454 static const char * const rt5682_sto1_adc_src[] = {
1458 static SOC_ENUM_SINGLE_DECL(
1459 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1460 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1462 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1463 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1465 static SOC_ENUM_SINGLE_DECL(
1466 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1467 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1469 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1470 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1472 /* STO1 ADC2 Source */
1473 /* MX-26 [12] [4] */
1474 static const char * const rt5682_sto1_adc2_src[] = {
1478 static SOC_ENUM_SINGLE_DECL(
1479 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1480 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1482 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1483 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1485 static SOC_ENUM_SINGLE_DECL(
1486 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1487 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1489 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1490 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1492 /* MX-79 [6:4] I2S1 ADC data location */
1493 static const unsigned int rt5682_if1_adc_slot_values[] = {
1500 static const char * const rt5682_if1_adc_slot_src[] = {
1501 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1504 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1505 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1506 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1508 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1509 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1511 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1512 /* MX-2B [4], MX-2B [0]*/
1513 static const char * const rt5682_alg_dac1_src[] = {
1514 "Stereo1 DAC Mixer", "DAC1"
1517 static SOC_ENUM_SINGLE_DECL(
1518 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1519 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1521 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1522 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1524 static SOC_ENUM_SINGLE_DECL(
1525 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1526 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1528 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1529 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1532 static const struct snd_kcontrol_new hpol_switch =
1533 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1534 RT5682_L_MUTE_SFT, 1, 1);
1535 static const struct snd_kcontrol_new hpor_switch =
1536 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1537 RT5682_R_MUTE_SFT, 1, 1);
1539 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1540 struct snd_kcontrol *kcontrol, int event)
1542 struct snd_soc_component *component =
1543 snd_soc_dapm_to_component(w->dapm);
1546 case SND_SOC_DAPM_PRE_PMU:
1547 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1548 RT5682_HP_C2_DAC_AMP_MUTE, 0);
1549 snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2,
1550 RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG);
1551 snd_soc_component_update_bits(component,
1552 RT5682_DEPOP_1, 0x60, 0x60);
1553 snd_soc_component_update_bits(component,
1554 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1555 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1556 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN,
1557 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN);
1558 usleep_range(5000, 10000);
1559 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1560 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L);
1563 case SND_SOC_DAPM_POST_PMD:
1564 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1565 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0);
1566 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1567 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M);
1568 snd_soc_component_update_bits(component,
1569 RT5682_DEPOP_1, 0x60, 0x0);
1570 snd_soc_component_update_bits(component,
1571 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1578 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1579 struct snd_kcontrol *kcontrol, int event)
1581 struct snd_soc_component *component =
1582 snd_soc_dapm_to_component(w->dapm);
1583 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1584 unsigned int delay = 50, val;
1586 if (rt5682->pdata.dmic_delay)
1587 delay = rt5682->pdata.dmic_delay;
1590 case SND_SOC_DAPM_POST_PMU:
1591 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1592 val &= RT5682_SCLK_SRC_MASK;
1593 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1594 snd_soc_component_update_bits(component,
1596 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1597 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1599 /*Add delay to avoid pop noise*/
1603 case SND_SOC_DAPM_POST_PMD:
1604 if (!rt5682->jack_type) {
1605 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1606 snd_soc_component_update_bits(component,
1607 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1608 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1609 snd_soc_component_update_bits(component,
1610 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1618 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1619 struct snd_kcontrol *kcontrol, int event)
1621 struct snd_soc_component *component =
1622 snd_soc_dapm_to_component(w->dapm);
1625 case SND_SOC_DAPM_PRE_PMU:
1627 case RT5682_PWR_VREF1_BIT:
1628 snd_soc_component_update_bits(component,
1629 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1632 case RT5682_PWR_VREF2_BIT:
1633 snd_soc_component_update_bits(component,
1634 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1639 case SND_SOC_DAPM_POST_PMU:
1640 usleep_range(15000, 20000);
1642 case RT5682_PWR_VREF1_BIT:
1643 snd_soc_component_update_bits(component,
1644 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1648 case RT5682_PWR_VREF2_BIT:
1649 snd_soc_component_update_bits(component,
1650 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1660 static const unsigned int rt5682_adcdat_pin_values[] = {
1665 static const char * const rt5682_adcdat_pin_select[] = {
1670 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1671 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1672 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1674 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1675 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1677 static const unsigned int rt5682_hpo_sig_out_values[] = {
1682 static const char * const rt5682_hpo_sig_out_mode[] = {
1687 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum,
1688 RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK,
1689 rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values);
1691 static const struct snd_kcontrol_new rt5682_hpo_sig_demux =
1692 SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum);
1694 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1695 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1697 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1699 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1701 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1702 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1703 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1704 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1705 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1706 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1709 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1710 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1711 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1712 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1713 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1714 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1715 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1716 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1717 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1718 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1721 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1723 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1727 SND_SOC_DAPM_INPUT("DMIC L1"),
1728 SND_SOC_DAPM_INPUT("DMIC R1"),
1730 SND_SOC_DAPM_INPUT("IN1P"),
1732 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1733 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1734 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1735 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1736 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1739 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1743 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1744 ARRAY_SIZE(rt5682_rec1_l_mix)),
1745 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1746 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1749 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1750 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1752 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1753 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1754 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1755 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1756 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1757 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1760 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1761 &rt5682_sto1_adc1l_mux),
1762 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1763 &rt5682_sto1_adc1r_mux),
1764 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1765 &rt5682_sto1_adc2l_mux),
1766 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1767 &rt5682_sto1_adc2r_mux),
1768 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1769 &rt5682_sto1_adcl_mux),
1770 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1771 &rt5682_sto1_adcr_mux),
1772 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1773 &rt5682_if1_adc_slot_mux),
1776 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1777 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1778 SND_SOC_DAPM_PRE_PMU),
1779 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1780 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1781 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1782 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1783 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1784 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1787 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1789 /* Digital Interface */
1790 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1792 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1794 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1795 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1796 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1797 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1798 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1800 /* Digital Interface Select */
1801 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1802 &rt5682_if1_01_adc_swap_mux),
1803 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1804 &rt5682_if1_23_adc_swap_mux),
1805 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1806 &rt5682_if1_45_adc_swap_mux),
1807 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1808 &rt5682_if1_67_adc_swap_mux),
1809 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1810 &rt5682_if2_adc_swap_mux),
1812 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1813 &rt5682_adcdat_pin_ctrl),
1815 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1817 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1820 /* Audio Interface */
1821 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1822 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1823 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1824 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1825 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1826 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1827 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1830 /* DAC mixer before sound effect */
1831 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1832 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1833 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1834 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1836 /* DAC channel Mux */
1837 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1838 &rt5682_alg_dac_l1_mux),
1839 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1840 &rt5682_alg_dac_r1_mux),
1843 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1844 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1845 SND_SOC_DAPM_PRE_PMU),
1846 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1847 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1848 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1849 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1852 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1853 RT5682_PWR_DAC_L1_BIT, 0),
1854 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1855 RT5682_PWR_DAC_R1_BIT, 0),
1856 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1857 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1860 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1861 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1863 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1864 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1865 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1866 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1867 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1868 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1869 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1870 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1872 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1874 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1877 SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0),
1878 SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0),
1879 SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux),
1882 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1883 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1884 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1885 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1886 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1887 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1888 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1889 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1892 SND_SOC_DAPM_OUTPUT("HPOL"),
1893 SND_SOC_DAPM_OUTPUT("HPOR"),
1896 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1898 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1899 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1900 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1901 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1902 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1903 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1906 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1907 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1908 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1909 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1910 {"ADC STO1 ASRC", NULL, "CLKDET"},
1911 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1912 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1913 {"DAC STO1 ASRC", NULL, "CLKDET"},
1916 {"MICBIAS1", NULL, "Vref1"},
1917 {"MICBIAS2", NULL, "Vref1"},
1919 {"CLKDET SYS", NULL, "CLKDET"},
1921 {"BST1 CBJ", NULL, "IN1P"},
1923 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1924 {"RECMIX1L", NULL, "RECMIX1L Power"},
1926 {"ADC1 L", NULL, "RECMIX1L"},
1927 {"ADC1 L", NULL, "ADC1 L Power"},
1928 {"ADC1 L", NULL, "ADC1 clock"},
1930 {"DMIC L1", NULL, "DMIC CLK"},
1931 {"DMIC L1", NULL, "DMIC1 Power"},
1932 {"DMIC R1", NULL, "DMIC CLK"},
1933 {"DMIC R1", NULL, "DMIC1 Power"},
1934 {"DMIC CLK", NULL, "DMIC ASRC"},
1936 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1937 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1938 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1939 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1941 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1942 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1943 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1944 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1946 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1947 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1948 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1949 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1951 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1952 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1953 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1955 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1956 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1957 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1959 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1960 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1962 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1963 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1964 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1965 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1966 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1967 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1968 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1969 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1970 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1971 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1972 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1973 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1974 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1975 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1976 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1977 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1979 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1980 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1981 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1982 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1983 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1984 {"AIF1TX", NULL, "I2S1"},
1985 {"AIF1TX", NULL, "ADCDAT Mux"},
1986 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1987 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1988 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1989 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1990 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1991 {"AIF2TX", NULL, "ADCDAT Mux"},
1993 {"SDWTX", NULL, "PLL2B"},
1994 {"SDWTX", NULL, "PLL2F"},
1995 {"SDWTX", NULL, "ADCDAT Mux"},
1997 {"IF1 DAC1 L", NULL, "AIF1RX"},
1998 {"IF1 DAC1 L", NULL, "I2S1"},
1999 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
2000 {"IF1 DAC1 R", NULL, "AIF1RX"},
2001 {"IF1 DAC1 R", NULL, "I2S1"},
2002 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
2004 {"SOUND DAC L", NULL, "SDWRX"},
2005 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
2006 {"SOUND DAC L", NULL, "PLL2B"},
2007 {"SOUND DAC L", NULL, "PLL2F"},
2008 {"SOUND DAC R", NULL, "SDWRX"},
2009 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
2010 {"SOUND DAC R", NULL, "PLL2B"},
2011 {"SOUND DAC R", NULL, "PLL2F"},
2013 {"DAC L Mux", "IF1", "IF1 DAC1 L"},
2014 {"DAC L Mux", "SOUND", "SOUND DAC L"},
2015 {"DAC R Mux", "IF1", "IF1 DAC1 R"},
2016 {"DAC R Mux", "SOUND", "SOUND DAC R"},
2018 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
2019 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
2020 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
2021 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
2023 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
2024 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
2026 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
2027 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
2029 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
2030 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
2031 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
2032 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
2034 {"DAC L1", NULL, "DAC L1 Source"},
2035 {"DAC R1", NULL, "DAC R1 Source"},
2037 {"DAC L1", NULL, "DAC 1 Clock"},
2038 {"DAC R1", NULL, "DAC 1 Clock"},
2040 {"HP Amp", NULL, "DAC L1"},
2041 {"HP Amp", NULL, "DAC R1"},
2042 {"HP Amp", NULL, "HP Amp L"},
2043 {"HP Amp", NULL, "HP Amp R"},
2044 {"HP Amp", NULL, "Capless"},
2045 {"HP Amp", NULL, "Charge Pump"},
2046 {"HP Amp", NULL, "CLKDET SYS"},
2047 {"HP Amp", NULL, "Vref1"},
2049 {"HPO Signal Demux", NULL, "HP Amp"},
2051 {"HPO Legacy", "Legacy", "HPO Signal Demux"},
2052 {"HPO OneBit", "OneBit", "HPO Signal Demux"},
2054 {"HPOL Playback", "Switch", "HPO Legacy"},
2055 {"HPOR Playback", "Switch", "HPO Legacy"},
2057 {"HPOL", NULL, "HPOL Playback"},
2058 {"HPOR", NULL, "HPOR Playback"},
2059 {"HPOL", NULL, "HPO OneBit"},
2060 {"HPOR", NULL, "HPO OneBit"},
2063 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2064 unsigned int rx_mask, int slots, int slot_width)
2066 struct snd_soc_component *component = dai->component;
2067 unsigned int cl, val = 0;
2069 if (tx_mask || rx_mask)
2070 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2071 RT5682_TDM_EN, RT5682_TDM_EN);
2073 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2078 val |= RT5682_TDM_TX_CH_4;
2079 val |= RT5682_TDM_RX_CH_4;
2082 val |= RT5682_TDM_TX_CH_6;
2083 val |= RT5682_TDM_RX_CH_6;
2086 val |= RT5682_TDM_TX_CH_8;
2087 val |= RT5682_TDM_RX_CH_8;
2095 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2096 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2098 switch (slot_width) {
2100 if (tx_mask || rx_mask)
2102 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2105 val = RT5682_TDM_CL_16;
2106 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2109 val = RT5682_TDM_CL_20;
2110 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2113 val = RT5682_TDM_CL_24;
2114 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2117 val = RT5682_TDM_CL_32;
2118 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2124 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2125 RT5682_TDM_CL_MASK, val);
2126 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2127 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2132 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2133 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2135 struct snd_soc_component *component = dai->component;
2136 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2137 unsigned int len_1 = 0, len_2 = 0;
2138 int pre_div, frame_size;
2140 rt5682->lrck[dai->id] = params_rate(params);
2141 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2143 frame_size = snd_soc_params_to_frame_size(params);
2144 if (frame_size < 0) {
2145 dev_err(component->dev, "Unsupported frame size: %d\n",
2150 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2151 rt5682->lrck[dai->id], pre_div, dai->id);
2153 switch (params_width(params)) {
2157 len_1 |= RT5682_I2S1_DL_20;
2158 len_2 |= RT5682_I2S2_DL_20;
2161 len_1 |= RT5682_I2S1_DL_24;
2162 len_2 |= RT5682_I2S2_DL_24;
2165 len_1 |= RT5682_I2S1_DL_32;
2166 len_2 |= RT5682_I2S2_DL_24;
2169 len_1 |= RT5682_I2S2_DL_8;
2170 len_2 |= RT5682_I2S2_DL_8;
2178 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2179 RT5682_I2S1_DL_MASK, len_1);
2180 if (rt5682->master[RT5682_AIF1]) {
2181 snd_soc_component_update_bits(component,
2182 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2183 RT5682_I2S_CLK_SRC_MASK,
2184 pre_div << RT5682_I2S_M_DIV_SFT |
2185 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2187 if (params_channels(params) == 1) /* mono mode */
2188 snd_soc_component_update_bits(component,
2189 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2190 RT5682_I2S1_MONO_EN);
2192 snd_soc_component_update_bits(component,
2193 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2194 RT5682_I2S1_MONO_DIS);
2197 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2198 RT5682_I2S2_DL_MASK, len_2);
2199 if (rt5682->master[RT5682_AIF2]) {
2200 snd_soc_component_update_bits(component,
2201 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2202 pre_div << RT5682_I2S2_M_PD_SFT);
2204 if (params_channels(params) == 1) /* mono mode */
2205 snd_soc_component_update_bits(component,
2206 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2207 RT5682_I2S2_MONO_EN);
2209 snd_soc_component_update_bits(component,
2210 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2211 RT5682_I2S2_MONO_DIS);
2214 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2221 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2223 struct snd_soc_component *component = dai->component;
2224 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2225 unsigned int reg_val = 0, tdm_ctrl = 0;
2227 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2228 case SND_SOC_DAIFMT_CBM_CFM:
2229 rt5682->master[dai->id] = 1;
2231 case SND_SOC_DAIFMT_CBS_CFS:
2232 rt5682->master[dai->id] = 0;
2238 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2239 case SND_SOC_DAIFMT_NB_NF:
2241 case SND_SOC_DAIFMT_IB_NF:
2242 reg_val |= RT5682_I2S_BP_INV;
2243 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2245 case SND_SOC_DAIFMT_NB_IF:
2246 if (dai->id == RT5682_AIF1)
2247 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2251 case SND_SOC_DAIFMT_IB_IF:
2252 if (dai->id == RT5682_AIF1)
2253 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2254 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2262 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2263 case SND_SOC_DAIFMT_I2S:
2265 case SND_SOC_DAIFMT_LEFT_J:
2266 reg_val |= RT5682_I2S_DF_LEFT;
2267 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2269 case SND_SOC_DAIFMT_DSP_A:
2270 reg_val |= RT5682_I2S_DF_PCM_A;
2271 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2273 case SND_SOC_DAIFMT_DSP_B:
2274 reg_val |= RT5682_I2S_DF_PCM_B;
2275 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2283 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2284 RT5682_I2S_DF_MASK, reg_val);
2285 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2286 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2287 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2288 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2289 tdm_ctrl | rt5682->master[dai->id]);
2292 if (rt5682->master[dai->id] == 0)
2293 reg_val |= RT5682_I2S2_MS_S;
2294 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2295 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2296 RT5682_I2S_DF_MASK, reg_val);
2299 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2305 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2306 int clk_id, int source, unsigned int freq, int dir)
2308 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2309 unsigned int reg_val = 0, src = 0;
2311 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2315 case RT5682_SCLK_S_MCLK:
2316 reg_val |= RT5682_SCLK_SRC_MCLK;
2317 src = RT5682_CLK_SRC_MCLK;
2319 case RT5682_SCLK_S_PLL1:
2320 reg_val |= RT5682_SCLK_SRC_PLL1;
2321 src = RT5682_CLK_SRC_PLL1;
2323 case RT5682_SCLK_S_PLL2:
2324 reg_val |= RT5682_SCLK_SRC_PLL2;
2325 src = RT5682_CLK_SRC_PLL2;
2327 case RT5682_SCLK_S_RCCLK:
2328 reg_val |= RT5682_SCLK_SRC_RCCLK;
2329 src = RT5682_CLK_SRC_RCCLK;
2332 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2335 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2336 RT5682_SCLK_SRC_MASK, reg_val);
2338 if (rt5682->master[RT5682_AIF2]) {
2339 snd_soc_component_update_bits(component,
2340 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2341 src << RT5682_I2S2_SRC_SFT);
2344 rt5682->sysclk = freq;
2345 rt5682->sysclk_src = clk_id;
2347 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2353 static int rt5682_set_component_pll(struct snd_soc_component *component,
2354 int pll_id, int source, unsigned int freq_in,
2355 unsigned int freq_out)
2357 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2358 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2359 unsigned int pll2_fout1, pll2_ps_val;
2362 if (source == rt5682->pll_src[pll_id] &&
2363 freq_in == rt5682->pll_in[pll_id] &&
2364 freq_out == rt5682->pll_out[pll_id])
2367 if (!freq_in || !freq_out) {
2368 dev_dbg(component->dev, "PLL disabled\n");
2370 rt5682->pll_in[pll_id] = 0;
2371 rt5682->pll_out[pll_id] = 0;
2372 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2373 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2377 if (pll_id == RT5682_PLL2) {
2379 case RT5682_PLL2_S_MCLK:
2380 snd_soc_component_update_bits(component,
2381 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2382 RT5682_PLL2_SRC_MCLK);
2385 dev_err(component->dev, "Unknown PLL2 Source %d\n",
2391 * PLL2 concatenates 2 PLL units.
2392 * We suggest the Fout of the front PLL is 3.84MHz.
2394 pll2_fout1 = 3840000;
2395 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2397 dev_err(component->dev, "Unsupported input clock %d\n",
2401 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2402 freq_in, pll2_fout1,
2404 (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2405 pll2f_code.n_code, pll2f_code.k_code);
2407 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2409 dev_err(component->dev, "Unsupported input clock %d\n",
2413 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2414 pll2_fout1, freq_out,
2416 (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2417 pll2b_code.n_code, pll2b_code.k_code);
2419 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2420 pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2421 pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2423 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2424 pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2426 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2427 pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2429 if (freq_out == 22579200)
2430 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2432 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2433 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2434 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2435 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2437 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2438 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2442 case RT5682_PLL1_S_MCLK:
2443 snd_soc_component_update_bits(component,
2444 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2445 RT5682_PLL1_SRC_MCLK);
2447 case RT5682_PLL1_S_BCLK1:
2448 snd_soc_component_update_bits(component,
2449 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2450 RT5682_PLL1_SRC_BCLK1);
2453 dev_err(component->dev, "Unknown PLL1 Source %d\n",
2458 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2460 dev_err(component->dev, "Unsupported input clock %d\n",
2465 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2466 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2467 pll_code.n_code, pll_code.k_code);
2469 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2470 (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
2471 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2472 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
2473 ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
2476 rt5682->pll_in[pll_id] = freq_in;
2477 rt5682->pll_out[pll_id] = freq_out;
2478 rt5682->pll_src[pll_id] = source;
2483 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2485 struct snd_soc_component *component = dai->component;
2486 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2488 rt5682->bclk[dai->id] = ratio;
2492 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2493 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2496 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2497 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2500 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2501 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2504 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2505 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2508 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2515 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2517 struct snd_soc_component *component = dai->component;
2518 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2520 rt5682->bclk[dai->id] = ratio;
2524 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2525 RT5682_I2S2_BCLK_MS2_MASK,
2526 RT5682_I2S2_BCLK_MS2_64);
2529 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2530 RT5682_I2S2_BCLK_MS2_MASK,
2531 RT5682_I2S2_BCLK_MS2_32);
2534 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2541 static int rt5682_set_bias_level(struct snd_soc_component *component,
2542 enum snd_soc_bias_level level)
2544 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2547 case SND_SOC_BIAS_PREPARE:
2548 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2549 RT5682_PWR_BG, RT5682_PWR_BG);
2550 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2551 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2552 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2555 case SND_SOC_BIAS_STANDBY:
2556 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2557 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2559 case SND_SOC_BIAS_OFF:
2560 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2561 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2562 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2565 case SND_SOC_BIAS_ON:
2572 #ifdef CONFIG_COMMON_CLK
2573 #define CLK_PLL2_FIN 48000000
2574 #define CLK_48 48000
2575 #define CLK_44 44100
2577 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2579 if (!rt5682->master[RT5682_AIF1]) {
2580 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n");
2586 static int rt5682_wclk_prepare(struct clk_hw *hw)
2588 struct rt5682_priv *rt5682 =
2589 container_of(hw, struct rt5682_priv,
2590 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2591 struct snd_soc_component *component;
2592 struct snd_soc_dapm_context *dapm;
2594 if (!rt5682_clk_check(rt5682))
2597 component = rt5682->component;
2598 dapm = snd_soc_component_get_dapm(component);
2600 snd_soc_dapm_mutex_lock(dapm);
2602 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2603 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2604 RT5682_PWR_MB, RT5682_PWR_MB);
2606 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2607 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2608 RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2610 usleep_range(55000, 60000);
2611 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2612 RT5682_PWR_FV2, RT5682_PWR_FV2);
2614 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2615 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2616 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2617 snd_soc_dapm_sync_unlocked(dapm);
2619 snd_soc_dapm_mutex_unlock(dapm);
2624 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2626 struct rt5682_priv *rt5682 =
2627 container_of(hw, struct rt5682_priv,
2628 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2629 struct snd_soc_component *component;
2630 struct snd_soc_dapm_context *dapm;
2632 if (!rt5682_clk_check(rt5682))
2635 component = rt5682->component;
2636 dapm = snd_soc_component_get_dapm(component);
2638 snd_soc_dapm_mutex_lock(dapm);
2640 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2641 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2642 if (!rt5682->jack_type)
2643 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2644 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2647 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2648 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2649 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2650 snd_soc_dapm_sync_unlocked(dapm);
2652 snd_soc_dapm_mutex_unlock(dapm);
2655 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2656 unsigned long parent_rate)
2658 struct rt5682_priv *rt5682 =
2659 container_of(hw, struct rt5682_priv,
2660 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2661 const char * const clk_name = clk_hw_get_name(hw);
2663 if (!rt5682_clk_check(rt5682))
2666 * Only accept to set wclk rate to 44.1k or 48kHz.
2668 if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2669 rt5682->lrck[RT5682_AIF1] != CLK_44) {
2670 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2671 __func__, clk_name, CLK_44, CLK_48);
2675 return rt5682->lrck[RT5682_AIF1];
2678 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2679 unsigned long *parent_rate)
2681 struct rt5682_priv *rt5682 =
2682 container_of(hw, struct rt5682_priv,
2683 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2684 const char * const clk_name = clk_hw_get_name(hw);
2686 if (!rt5682_clk_check(rt5682))
2689 * Only accept to set wclk rate to 44.1k or 48kHz.
2690 * It will force to 48kHz if not both.
2692 if (rate != CLK_48 && rate != CLK_44) {
2693 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2694 __func__, clk_name, CLK_44, CLK_48);
2701 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2702 unsigned long parent_rate)
2704 struct rt5682_priv *rt5682 =
2705 container_of(hw, struct rt5682_priv,
2706 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2707 struct snd_soc_component *component;
2708 struct clk_hw *parent_hw;
2709 const char * const clk_name = clk_hw_get_name(hw);
2711 unsigned int clk_pll2_out;
2713 if (!rt5682_clk_check(rt5682))
2716 component = rt5682->component;
2719 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2720 * it is fixed or set to 48MHz before setting wclk rate. It's a
2721 * temporary limitation. Only accept 48MHz clk as the clk provider.
2723 * It will set the codec anyway by assuming mclk is 48MHz.
2725 parent_hw = clk_hw_get_parent(hw);
2727 dev_warn(rt5682->i2c_dev,
2728 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2731 if (parent_rate != CLK_PLL2_FIN)
2732 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n",
2733 clk_name, CLK_PLL2_FIN);
2736 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2739 clk_pll2_out = rate * 512;
2740 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2741 CLK_PLL2_FIN, clk_pll2_out);
2743 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2744 clk_pll2_out, SND_SOC_CLOCK_IN);
2746 rt5682->lrck[RT5682_AIF1] = rate;
2748 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2750 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2751 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2752 pre_div << RT5682_I2S_M_DIV_SFT |
2753 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2758 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2759 unsigned long parent_rate)
2761 struct rt5682_priv *rt5682 =
2762 container_of(hw, struct rt5682_priv,
2763 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2764 unsigned int bclks_per_wclk;
2766 regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk);
2768 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2769 case RT5682_TDM_BCLK_MS1_256:
2770 return parent_rate * 256;
2771 case RT5682_TDM_BCLK_MS1_128:
2772 return parent_rate * 128;
2773 case RT5682_TDM_BCLK_MS1_64:
2774 return parent_rate * 64;
2775 case RT5682_TDM_BCLK_MS1_32:
2776 return parent_rate * 32;
2782 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2783 unsigned long parent_rate)
2785 unsigned long factor;
2787 factor = rate / parent_rate;
2790 else if (factor < 128)
2792 else if (factor < 256)
2798 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2799 unsigned long *parent_rate)
2801 struct rt5682_priv *rt5682 =
2802 container_of(hw, struct rt5682_priv,
2803 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2804 unsigned long factor;
2806 if (!*parent_rate || !rt5682_clk_check(rt5682))
2810 * BCLK rates are set as a multiplier of WCLK in HW.
2811 * We don't allow changing the parent WCLK. We just do
2812 * some rounding down based on the parent WCLK rate
2813 * and find the appropriate multiplier of BCLK to
2814 * get the rounded down BCLK value.
2816 factor = rt5682_bclk_get_factor(rate, *parent_rate);
2818 return *parent_rate * factor;
2821 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2822 unsigned long parent_rate)
2824 struct rt5682_priv *rt5682 =
2825 container_of(hw, struct rt5682_priv,
2826 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2827 struct snd_soc_component *component;
2828 struct snd_soc_dai *dai;
2829 unsigned long factor;
2831 if (!rt5682_clk_check(rt5682))
2834 component = rt5682->component;
2836 factor = rt5682_bclk_get_factor(rate, parent_rate);
2838 for_each_component_dais(component, dai)
2839 if (dai->id == RT5682_AIF1)
2840 return rt5682_set_bclk1_ratio(dai, factor);
2842 dev_err(rt5682->i2c_dev, "dai %d not found in component\n",
2847 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2848 [RT5682_DAI_WCLK_IDX] = {
2849 .prepare = rt5682_wclk_prepare,
2850 .unprepare = rt5682_wclk_unprepare,
2851 .recalc_rate = rt5682_wclk_recalc_rate,
2852 .round_rate = rt5682_wclk_round_rate,
2853 .set_rate = rt5682_wclk_set_rate,
2855 [RT5682_DAI_BCLK_IDX] = {
2856 .recalc_rate = rt5682_bclk_recalc_rate,
2857 .round_rate = rt5682_bclk_round_rate,
2858 .set_rate = rt5682_bclk_set_rate,
2862 int rt5682_register_dai_clks(struct rt5682_priv *rt5682)
2864 struct device *dev = rt5682->i2c_dev;
2865 struct rt5682_platform_data *pdata = &rt5682->pdata;
2866 struct clk_hw *dai_clk_hw;
2869 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2870 struct clk_init_data init = { };
2871 const struct clk_hw *parent;
2873 dai_clk_hw = &rt5682->dai_clks_hw[i];
2876 case RT5682_DAI_WCLK_IDX:
2877 /* Make MCLK the parent of WCLK */
2879 parent = __clk_get_hw(rt5682->mclk);
2880 init.parent_hws = &parent;
2881 init.num_parents = 1;
2884 case RT5682_DAI_BCLK_IDX:
2885 /* Make WCLK the parent of BCLK */
2886 parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
2887 init.parent_hws = &parent;
2888 init.num_parents = 1;
2891 dev_err(dev, "Invalid clock index\n");
2895 init.name = pdata->dai_clk_names[i];
2896 init.ops = &rt5682_dai_clk_ops[i];
2897 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2898 dai_clk_hw->init = &init;
2900 ret = devm_clk_hw_register(dev, dai_clk_hw);
2902 dev_warn(dev, "Failed to register %s: %d\n",
2908 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2913 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2923 EXPORT_SYMBOL_GPL(rt5682_register_dai_clks);
2924 #endif /* CONFIG_COMMON_CLK */
2926 static int rt5682_probe(struct snd_soc_component *component)
2928 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2929 struct sdw_slave *slave;
2931 struct snd_soc_dapm_context *dapm = &component->dapm;
2933 rt5682->component = component;
2935 if (rt5682->is_sdw) {
2936 slave = rt5682->slave;
2937 time = wait_for_completion_timeout(
2938 &slave->initialization_complete,
2939 msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2941 dev_err(&slave->dev, "Initialization not complete, timed out\n");
2946 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2947 snd_soc_dapm_disable_pin(dapm, "Vref2");
2948 snd_soc_dapm_sync(dapm);
2952 static void rt5682_remove(struct snd_soc_component *component)
2954 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2956 rt5682_reset(rt5682);
2960 static int rt5682_suspend(struct snd_soc_component *component)
2962 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2969 disable_irq(rt5682->irq);
2971 cancel_delayed_work_sync(&rt5682->jack_detect_work);
2972 cancel_delayed_work_sync(&rt5682->jd_check_work);
2973 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
2974 val = snd_soc_component_read(component,
2975 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
2979 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2980 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2981 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL);
2984 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2985 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2986 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL);
2992 /* enter SAR ADC power saving mode */
2993 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2994 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK |
2995 RT5682_SAR_SEL_MB1_MB2_MASK, 0);
2996 usleep_range(5000, 6000);
2997 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
2998 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
2999 RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG);
3000 usleep_range(10000, 12000);
3001 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
3002 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK,
3003 RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV);
3004 snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1,
3005 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
3008 regcache_cache_only(rt5682->regmap, true);
3009 regcache_mark_dirty(rt5682->regmap);
3013 static int rt5682_resume(struct snd_soc_component *component)
3015 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
3020 regcache_cache_only(rt5682->regmap, false);
3021 regcache_sync(rt5682->regmap);
3023 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
3024 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
3025 RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK,
3026 RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO);
3027 usleep_range(5000, 6000);
3028 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
3029 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
3030 RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM);
3031 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
3032 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
3035 rt5682->jack_type = 0;
3036 mod_delayed_work(system_power_efficient_wq,
3037 &rt5682->jack_detect_work, msecs_to_jiffies(0));
3040 enable_irq(rt5682->irq);
3045 #define rt5682_suspend NULL
3046 #define rt5682_resume NULL
3049 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
3050 .hw_params = rt5682_hw_params,
3051 .set_fmt = rt5682_set_dai_fmt,
3052 .set_tdm_slot = rt5682_set_tdm_slot,
3053 .set_bclk_ratio = rt5682_set_bclk1_ratio,
3055 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
3057 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
3058 .hw_params = rt5682_hw_params,
3059 .set_fmt = rt5682_set_dai_fmt,
3060 .set_bclk_ratio = rt5682_set_bclk2_ratio,
3062 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
3064 const struct snd_soc_component_driver rt5682_soc_component_dev = {
3065 .probe = rt5682_probe,
3066 .remove = rt5682_remove,
3067 .suspend = rt5682_suspend,
3068 .resume = rt5682_resume,
3069 .set_bias_level = rt5682_set_bias_level,
3070 .controls = rt5682_snd_controls,
3071 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
3072 .dapm_widgets = rt5682_dapm_widgets,
3073 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
3074 .dapm_routes = rt5682_dapm_routes,
3075 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
3076 .set_sysclk = rt5682_set_component_sysclk,
3077 .set_pll = rt5682_set_component_pll,
3078 .set_jack = rt5682_set_jack_detect,
3079 .use_pmdown_time = 1,
3082 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
3084 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
3087 device_property_read_u32(dev, "realtek,dmic1-data-pin",
3088 &rt5682->pdata.dmic1_data_pin);
3089 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
3090 &rt5682->pdata.dmic1_clk_pin);
3091 device_property_read_u32(dev, "realtek,jd-src",
3092 &rt5682->pdata.jd_src);
3093 device_property_read_u32(dev, "realtek,btndet-delay",
3094 &rt5682->pdata.btndet_delay);
3095 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
3096 &rt5682->pdata.dmic_clk_rate);
3097 device_property_read_u32(dev, "realtek,dmic-delay-ms",
3098 &rt5682->pdata.dmic_delay);
3100 if (device_property_read_string_array(dev, "clock-output-names",
3101 rt5682->pdata.dai_clk_names,
3102 RT5682_DAI_NUM_CLKS) < 0)
3103 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3104 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3105 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3107 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
3108 "realtek,dmic-clk-driving-high");
3112 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3114 int rt5682_get_ldo1(struct rt5682_priv *rt5682, struct device *dev)
3116 rt5682->ldo1_en = devm_gpiod_get_optional(dev,
3119 if (IS_ERR(rt5682->ldo1_en)) {
3120 dev_err(dev, "Fail gpio request ldo1_en\n");
3121 return PTR_ERR(rt5682->ldo1_en);
3126 EXPORT_SYMBOL_GPL(rt5682_get_ldo1);
3128 void rt5682_calibrate(struct rt5682_priv *rt5682)
3132 mutex_lock(&rt5682->calibrate_mutex);
3134 rt5682_reset(rt5682);
3135 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3136 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3137 usleep_range(15000, 20000);
3138 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3139 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3140 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3141 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3142 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3143 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3145 regmap_write(rt5682->regmap, RT5682_CHOP_ADC, 0x7005);
3147 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3148 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3149 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3150 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3151 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3152 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3153 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3154 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3155 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3157 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3159 for (count = 0; count < 60; count++) {
3160 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3161 if (!(value & 0x8000))
3164 usleep_range(10000, 10005);
3168 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3170 /* restore settings */
3171 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3172 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3173 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3174 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3175 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3177 regmap_write(rt5682->regmap, RT5682_CHOP_ADC, 0x2005);
3179 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3180 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3181 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3183 mutex_unlock(&rt5682->calibrate_mutex);
3185 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3187 MODULE_DESCRIPTION("ASoC RT5682 driver");
3189 MODULE_LICENSE("GPL v2");
projects / linux.git / blob