include/dt-bindings/clock/qcom,sm4450-dispcc.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2 /*
   3  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
   7 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H
   8
   9 /* DISP_CC clocks */
  10 #define DISP_CC_MDSS_AHB1_CLK                                   0
  11 #define DISP_CC_MDSS_AHB_CLK                                    1
  12 #define DISP_CC_MDSS_AHB_CLK_SRC                                2
  13 #define DISP_CC_MDSS_BYTE0_CLK                                  3
  14 #define DISP_CC_MDSS_BYTE0_CLK_SRC                              4
  15 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC                          5
  16 #define DISP_CC_MDSS_BYTE0_INTF_CLK                             6
  17 #define DISP_CC_MDSS_ESC0_CLK                                   7
  18 #define DISP_CC_MDSS_ESC0_CLK_SRC                               8
  19 #define DISP_CC_MDSS_MDP1_CLK                                   9
  20 #define DISP_CC_MDSS_MDP_CLK                                    10
  21 #define DISP_CC_MDSS_MDP_CLK_SRC                                11
  22 #define DISP_CC_MDSS_MDP_LUT1_CLK                               12
  23 #define DISP_CC_MDSS_MDP_LUT_CLK                                13
  24 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK                           14
  25 #define DISP_CC_MDSS_PCLK0_CLK                                  15
  26 #define DISP_CC_MDSS_PCLK0_CLK_SRC                              16
  27 #define DISP_CC_MDSS_ROT1_CLK                                   17
  28 #define DISP_CC_MDSS_ROT_CLK                                    18
  29 #define DISP_CC_MDSS_ROT_CLK_SRC                                19
  30 #define DISP_CC_MDSS_RSCC_AHB_CLK                               20
  31 #define DISP_CC_MDSS_RSCC_VSYNC_CLK                             21
  32 #define DISP_CC_MDSS_VSYNC1_CLK                                 22
  33 #define DISP_CC_MDSS_VSYNC_CLK                                  23
  34 #define DISP_CC_MDSS_VSYNC_CLK_SRC                              24
  35 #define DISP_CC_PLL0                                            25
  36 #define DISP_CC_PLL1                                            26
  37 #define DISP_CC_SLEEP_CLK                                       27
  38 #define DISP_CC_SLEEP_CLK_SRC                                   28
  39 #define DISP_CC_XO_CLK                                          29
  40 #define DISP_CC_XO_CLK_SRC                                      30
  41
  42 /* DISP_CC power domains */
  43 #define DISP_CC_MDSS_CORE_GDSC                                  0
  44 #define DISP_CC_MDSS_CORE_INT2_GDSC                             1
  45
  46 /* DISP_CC resets */
  47 #define DISP_CC_MDSS_CORE_BCR                                   0
  48 #define DISP_CC_MDSS_CORE_INT2_BCR                              1
  49 #define DISP_CC_MDSS_RSCC_BCR                                   2
  50
  51 #endif