drivers/spi/spi-sun4i.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2012 - 2014 Allwinner Tech
   4  * Pan Nan <[email protected]>
   5  *
   6  * Copyright (C) 2014 Maxime Ripard
   7  * Maxime Ripard <[email protected]>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/device.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18
  19 #include <linux/spi/spi.h>
  20
  21 #define SUN4I_FIFO_DEPTH                64
  22
  23 #define SUN4I_RXDATA_REG                0x00
  24
  25 #define SUN4I_TXDATA_REG                0x04
  26
  27 #define SUN4I_CTL_REG                   0x08
  28 #define SUN4I_CTL_ENABLE                        BIT(0)
  29 #define SUN4I_CTL_MASTER                        BIT(1)
  30 #define SUN4I_CTL_CPHA                          BIT(2)
  31 #define SUN4I_CTL_CPOL                          BIT(3)
  32 #define SUN4I_CTL_CS_ACTIVE_LOW                 BIT(4)
  33 #define SUN4I_CTL_LMTF                          BIT(6)
  34 #define SUN4I_CTL_TF_RST                        BIT(8)
  35 #define SUN4I_CTL_RF_RST                        BIT(9)
  36 #define SUN4I_CTL_XCH                           BIT(10)
  37 #define SUN4I_CTL_CS_MASK                       0x3000
  38 #define SUN4I_CTL_CS(cs)                        (((cs) << 12) & SUN4I_CTL_CS_MASK)
  39 #define SUN4I_CTL_DHB                           BIT(15)
  40 #define SUN4I_CTL_CS_MANUAL                     BIT(16)
  41 #define SUN4I_CTL_CS_LEVEL                      BIT(17)
  42 #define SUN4I_CTL_TP                            BIT(18)
  43
  44 #define SUN4I_INT_CTL_REG               0x0c
  45 #define SUN4I_INT_CTL_RF_F34                    BIT(4)
  46 #define SUN4I_INT_CTL_TF_E34                    BIT(12)
  47 #define SUN4I_INT_CTL_TC                        BIT(16)
  48
  49 #define SUN4I_INT_STA_REG               0x10
  50
  51 #define SUN4I_DMA_CTL_REG               0x14
  52
  53 #define SUN4I_WAIT_REG                  0x18
  54
  55 #define SUN4I_CLK_CTL_REG               0x1c
  56 #define SUN4I_CLK_CTL_CDR2_MASK                 0xff
  57 #define SUN4I_CLK_CTL_CDR2(div)                 ((div) & SUN4I_CLK_CTL_CDR2_MASK)
  58 #define SUN4I_CLK_CTL_CDR1_MASK                 0xf
  59 #define SUN4I_CLK_CTL_CDR1(div)                 (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
  60 #define SUN4I_CLK_CTL_DRS                       BIT(12)
  61
  62 #define SUN4I_MAX_XFER_SIZE                     0xffffff
  63
  64 #define SUN4I_BURST_CNT_REG             0x20
  65 #define SUN4I_BURST_CNT(cnt)                    ((cnt) & SUN4I_MAX_XFER_SIZE)
  66
  67 #define SUN4I_XMIT_CNT_REG              0x24
  68 #define SUN4I_XMIT_CNT(cnt)                     ((cnt) & SUN4I_MAX_XFER_SIZE)
  69
  70
  71 #define SUN4I_FIFO_STA_REG              0x28
  72 #define SUN4I_FIFO_STA_RF_CNT_MASK              0x7f
  73 #define SUN4I_FIFO_STA_RF_CNT_BITS              0
  74 #define SUN4I_FIFO_STA_TF_CNT_MASK              0x7f
  75 #define SUN4I_FIFO_STA_TF_CNT_BITS              16
  76
  77 struct sun4i_spi {
  78         struct spi_controller   *host;
  79         void __iomem            *base_addr;
  80         struct clk              *hclk;
  81         struct clk              *mclk;
  82
  83         struct completion       done;
  84
  85         const u8                *tx_buf;
  86         u8                      *rx_buf;
  87         int                     len;
  88 };
  89
  90 static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
  91 {
  92         return readl(sspi->base_addr + reg);
  93 }
  94
  95 static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
  96 {
  97         writel(value, sspi->base_addr + reg);
  98 }
  99
 100 static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
 101 {
 102         u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
 103
 104         reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;
 105
 106         return reg & SUN4I_FIFO_STA_TF_CNT_MASK;
 107 }
 108
 109 static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
 110 {
 111         u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
 112
 113         reg |= mask;
 114         sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
 115 }
 116
 117 static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)
 118 {
 119         u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
 120
 121         reg &= ~mask;
 122         sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
 123 }
 124
 125 static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
 126 {
 127         u32 reg, cnt;
 128         u8 byte;
 129
 130         /* See how much data is available */
 131         reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
 132         reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
 133         cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
 134
 135         if (len > cnt)
 136                 len = cnt;
 137
 138         while (len--) {
 139                 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
 140                 if (sspi->rx_buf)
 141                         *sspi->rx_buf++ = byte;
 142         }
 143 }
 144
 145 static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
 146 {
 147         u32 cnt;
 148         u8 byte;
 149
 150         /* See how much data we can fit */
 151         cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
 152
 153         len = min3(len, (int)cnt, sspi->len);
 154
 155         while (len--) {
 156                 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
 157                 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
 158                 sspi->len--;
 159         }
 160 }
 161
 162 static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
 163 {
 164         struct sun4i_spi *sspi = spi_controller_get_devdata(spi->controller);
 165         u32 reg;
 166
 167         reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 168
 169         reg &= ~SUN4I_CTL_CS_MASK;
 170         reg |= SUN4I_CTL_CS(spi_get_chipselect(spi, 0));
 171
 172         /* We want to control the chip select manually */
 173         reg |= SUN4I_CTL_CS_MANUAL;
 174
 175         if (enable)
 176                 reg |= SUN4I_CTL_CS_LEVEL;
 177         else
 178                 reg &= ~SUN4I_CTL_CS_LEVEL;
 179
 180         /*
 181          * Even though this looks irrelevant since we are supposed to
 182          * be controlling the chip select manually, this bit also
 183          * controls the levels of the chip select for inactive
 184          * devices.
 185          *
 186          * If we don't set it, the chip select level will go low by
 187          * default when the device is idle, which is not really
 188          * expected in the common case where the chip select is active
 189          * low.
 190          */
 191         if (spi->mode & SPI_CS_HIGH)
 192                 reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
 193         else
 194                 reg |= SUN4I_CTL_CS_ACTIVE_LOW;
 195
 196         sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
 197 }
 198
 199 static size_t sun4i_spi_max_transfer_size(struct spi_device *spi)
 200 {
 201         return SUN4I_MAX_XFER_SIZE - 1;
 202 }
 203
 204 static int sun4i_spi_transfer_one(struct spi_controller *host,
 205                                   struct spi_device *spi,
 206                                   struct spi_transfer *tfr)
 207 {
 208         struct sun4i_spi *sspi = spi_controller_get_devdata(host);
 209         unsigned int mclk_rate, div;
 210         unsigned long time_left;
 211         unsigned int start, end, tx_time;
 212         unsigned int tx_len = 0;
 213         int ret = 0;
 214         u32 reg;
 215
 216         /* We don't support transfer larger than the FIFO */
 217         if (tfr->len > SUN4I_MAX_XFER_SIZE)
 218                 return -EMSGSIZE;
 219
 220         if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE)
 221                 return -EMSGSIZE;
 222
 223         reinit_completion(&sspi->done);
 224         sspi->tx_buf = tfr->tx_buf;
 225         sspi->rx_buf = tfr->rx_buf;
 226         sspi->len = tfr->len;
 227
 228         /* Clear pending interrupts */
 229         sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
 230
 231
 232         reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 233
 234         /* Reset FIFOs */
 235         sun4i_spi_write(sspi, SUN4I_CTL_REG,
 236                         reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
 237
 238         /*
 239          * Setup the transfer control register: Chip Select,
 240          * polarities, etc.
 241          */
 242         if (spi->mode & SPI_CPOL)
 243                 reg |= SUN4I_CTL_CPOL;
 244         else
 245                 reg &= ~SUN4I_CTL_CPOL;
 246
 247         if (spi->mode & SPI_CPHA)
 248                 reg |= SUN4I_CTL_CPHA;
 249         else
 250                 reg &= ~SUN4I_CTL_CPHA;
 251
 252         if (spi->mode & SPI_LSB_FIRST)
 253                 reg |= SUN4I_CTL_LMTF;
 254         else
 255                 reg &= ~SUN4I_CTL_LMTF;
 256
 257
 258         /*
 259          * If it's a TX only transfer, we don't want to fill the RX
 260          * FIFO with bogus data
 261          */
 262         if (sspi->rx_buf)
 263                 reg &= ~SUN4I_CTL_DHB;
 264         else
 265                 reg |= SUN4I_CTL_DHB;
 266
 267         sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
 268
 269         /* Ensure that we have a parent clock fast enough */
 270         mclk_rate = clk_get_rate(sspi->mclk);
 271         if (mclk_rate < (2 * tfr->speed_hz)) {
 272                 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
 273                 mclk_rate = clk_get_rate(sspi->mclk);
 274         }
 275
 276         /*
 277          * Setup clock divider.
 278          *
 279          * We have two choices there. Either we can use the clock
 280          * divide rate 1, which is calculated thanks to this formula:
 281          * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
 282          * Or we can use CDR2, which is calculated with the formula:
 283          * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 284          * Whether we use the former or the latter is set through the
 285          * DRS bit.
 286          *
 287          * First try CDR2, and if we can't reach the expected
 288          * frequency, fall back to CDR1.
 289          */
 290         div = mclk_rate / (2 * tfr->speed_hz);
 291         if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
 292                 if (div > 0)
 293                         div--;
 294
 295                 reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
 296         } else {
 297                 div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
 298                 reg = SUN4I_CLK_CTL_CDR1(div);
 299         }
 300
 301         sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
 302
 303         /* Setup the transfer now... */
 304         if (sspi->tx_buf)
 305                 tx_len = tfr->len;
 306
 307         /* Setup the counters */
 308         sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
 309         sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
 310
 311         /*
 312          * Fill the TX FIFO
 313          * Filling the FIFO fully causes timeout for some reason
 314          * at least on spi2 on A10s
 315          */
 316         sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
 317
 318         /* Enable the interrupts */
 319         sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |
 320                                          SUN4I_INT_CTL_RF_F34);
 321         /* Only enable Tx FIFO interrupt if we really need it */
 322         if (tx_len > SUN4I_FIFO_DEPTH)
 323                 sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
 324
 325         /* Start the transfer */
 326         reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
 327         sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
 328
 329         tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
 330         start = jiffies;
 331         time_left = wait_for_completion_timeout(&sspi->done,
 332                                                 msecs_to_jiffies(tx_time));
 333         end = jiffies;
 334         if (!time_left) {
 335                 dev_warn(&host->dev,
 336                          "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
 337                          dev_name(&spi->dev), tfr->len, tfr->speed_hz,
 338                          jiffies_to_msecs(end - start), tx_time);
 339                 ret = -ETIMEDOUT;
 340                 goto out;
 341         }
 342
 343
 344 out:
 345         sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
 346
 347         return ret;
 348 }
 349
 350 static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
 351 {
 352         struct sun4i_spi *sspi = dev_id;
 353         u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
 354
 355         /* Transfer complete */
 356         if (status & SUN4I_INT_CTL_TC) {
 357                 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
 358                 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
 359                 complete(&sspi->done);
 360                 return IRQ_HANDLED;
 361         }
 362
 363         /* Receive FIFO 3/4 full */
 364         if (status & SUN4I_INT_CTL_RF_F34) {
 365                 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
 366                 /* Only clear the interrupt _after_ draining the FIFO */
 367                 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);
 368                 return IRQ_HANDLED;
 369         }
 370
 371         /* Transmit FIFO 3/4 empty */
 372         if (status & SUN4I_INT_CTL_TF_E34) {
 373                 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
 374
 375                 if (!sspi->len)
 376                         /* nothing left to transmit */
 377                         sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
 378
 379                 /* Only clear the interrupt _after_ re-seeding the FIFO */
 380                 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);
 381
 382                 return IRQ_HANDLED;
 383         }
 384
 385         return IRQ_NONE;
 386 }
 387
 388 static int sun4i_spi_runtime_resume(struct device *dev)
 389 {
 390         struct spi_controller *host = dev_get_drvdata(dev);
 391         struct sun4i_spi *sspi = spi_controller_get_devdata(host);
 392         int ret;
 393
 394         ret = clk_prepare_enable(sspi->hclk);
 395         if (ret) {
 396                 dev_err(dev, "Couldn't enable AHB clock\n");
 397                 goto out;
 398         }
 399
 400         ret = clk_prepare_enable(sspi->mclk);
 401         if (ret) {
 402                 dev_err(dev, "Couldn't enable module clock\n");
 403                 goto err;
 404         }
 405
 406         sun4i_spi_write(sspi, SUN4I_CTL_REG,
 407                         SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
 408
 409         return 0;
 410
 411 err:
 412         clk_disable_unprepare(sspi->hclk);
 413 out:
 414         return ret;
 415 }
 416
 417 static int sun4i_spi_runtime_suspend(struct device *dev)
 418 {
 419         struct spi_controller *host = dev_get_drvdata(dev);
 420         struct sun4i_spi *sspi = spi_controller_get_devdata(host);
 421
 422         clk_disable_unprepare(sspi->mclk);
 423         clk_disable_unprepare(sspi->hclk);
 424
 425         return 0;
 426 }
 427
 428 static int sun4i_spi_probe(struct platform_device *pdev)
 429 {
 430         struct spi_controller *host;
 431         struct sun4i_spi *sspi;
 432         int ret = 0, irq;
 433
 434         host = spi_alloc_host(&pdev->dev, sizeof(struct sun4i_spi));
 435         if (!host) {
 436                 dev_err(&pdev->dev, "Unable to allocate SPI Host\n");
 437                 return -ENOMEM;
 438         }
 439
 440         platform_set_drvdata(pdev, host);
 441         sspi = spi_controller_get_devdata(host);
 442
 443         sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
 444         if (IS_ERR(sspi->base_addr)) {
 445                 ret = PTR_ERR(sspi->base_addr);
 446                 goto err_free_host;
 447         }
 448
 449         irq = platform_get_irq(pdev, 0);
 450         if (irq < 0) {
 451                 ret = -ENXIO;
 452                 goto err_free_host;
 453         }
 454
 455         ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
 456                                0, "sun4i-spi", sspi);
 457         if (ret) {
 458                 dev_err(&pdev->dev, "Cannot request IRQ\n");
 459                 goto err_free_host;
 460         }
 461
 462         sspi->host = host;
 463         host->max_speed_hz = 100 * 1000 * 1000;
 464         host->min_speed_hz = 3 * 1000;
 465         host->set_cs = sun4i_spi_set_cs;
 466         host->transfer_one = sun4i_spi_transfer_one;
 467         host->num_chipselect = 4;
 468         host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 469         host->bits_per_word_mask = SPI_BPW_MASK(8);
 470         host->dev.of_node = pdev->dev.of_node;
 471         host->auto_runtime_pm = true;
 472         host->max_transfer_size = sun4i_spi_max_transfer_size;
 473
 474         sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
 475         if (IS_ERR(sspi->hclk)) {
 476                 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
 477                 ret = PTR_ERR(sspi->hclk);
 478                 goto err_free_host;
 479         }
 480
 481         sspi->mclk = devm_clk_get(&pdev->dev, "mod");
 482         if (IS_ERR(sspi->mclk)) {
 483                 dev_err(&pdev->dev, "Unable to acquire module clock\n");
 484                 ret = PTR_ERR(sspi->mclk);
 485                 goto err_free_host;
 486         }
 487
 488         init_completion(&sspi->done);
 489
 490         /*
 491          * This wake-up/shutdown pattern is to be able to have the
 492          * device woken up, even if runtime_pm is disabled
 493          */
 494         ret = sun4i_spi_runtime_resume(&pdev->dev);
 495         if (ret) {
 496                 dev_err(&pdev->dev, "Couldn't resume the device\n");
 497                 goto err_free_host;
 498         }
 499
 500         pm_runtime_set_active(&pdev->dev);
 501         pm_runtime_enable(&pdev->dev);
 502         pm_runtime_idle(&pdev->dev);
 503
 504         ret = devm_spi_register_controller(&pdev->dev, host);
 505         if (ret) {
 506                 dev_err(&pdev->dev, "cannot register SPI host\n");
 507                 goto err_pm_disable;
 508         }
 509
 510         return 0;
 511
 512 err_pm_disable:
 513         pm_runtime_disable(&pdev->dev);
 514         sun4i_spi_runtime_suspend(&pdev->dev);
 515 err_free_host:
 516         spi_controller_put(host);
 517         return ret;
 518 }
 519
 520 static void sun4i_spi_remove(struct platform_device *pdev)
 521 {
 522         pm_runtime_force_suspend(&pdev->dev);
 523 }
 524
 525 static const struct of_device_id sun4i_spi_match[] = {
 526         { .compatible = "allwinner,sun4i-a10-spi", },
 527         {}
 528 };
 529 MODULE_DEVICE_TABLE(of, sun4i_spi_match);
 530
 531 static const struct dev_pm_ops sun4i_spi_pm_ops = {
 532         .runtime_resume         = sun4i_spi_runtime_resume,
 533         .runtime_suspend        = sun4i_spi_runtime_suspend,
 534 };
 535
 536 static struct platform_driver sun4i_spi_driver = {
 537         .probe  = sun4i_spi_probe,
 538         .remove = sun4i_spi_remove,
 539         .driver = {
 540                 .name           = "sun4i-spi",
 541                 .of_match_table = sun4i_spi_match,
 542                 .pm             = &sun4i_spi_pm_ops,
 543         },
 544 };
 545 module_platform_driver(sun4i_spi_driver);
 546
 547 MODULE_AUTHOR("Pan Nan <[email protected]>");
 548 MODULE_AUTHOR("Maxime Ripard <[email protected]>");
 549 MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
 550 MODULE_LICENSE("GPL");