drivers/scsi/mpi3mr/mpi3mr_fw.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for Broadcom MPI3 Storage Controllers
   4  *
   5  * Copyright (C) 2017-2023 Broadcom Inc.
   6  *  (mailto: [email protected])
   7  *
   8  */
   9
  10 #include "mpi3mr.h"
  11 #include <linux/io-64-nonatomic-lo-hi.h>
  12
  13 static int
  14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u16 reset_reason);
  15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
  16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
  17         struct mpi3_ioc_facts_data *facts_data);
  18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
  19         struct mpi3mr_drv_cmd *drv_cmd);
  20
  21 static int poll_queues;
  22 module_param(poll_queues, int, 0444);
  23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
  24
  25 #if defined(writeq) && defined(CONFIG_64BIT)
  26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
  27 {
  28         writeq(b, addr);
  29 }
  30 #else
  31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
  32 {
  33         __u64 data_out = b;
  34
  35         writel((u32)(data_out), addr);
  36         writel((u32)(data_out >> 32), (addr + 4));
  37 }
  38 #endif
  39
  40 static inline bool
  41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
  42 {
  43         u16 pi, ci, max_entries;
  44         bool is_qfull = false;
  45
  46         pi = op_req_q->pi;
  47         ci = READ_ONCE(op_req_q->ci);
  48         max_entries = op_req_q->num_requests;
  49
  50         if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
  51                 is_qfull = true;
  52
  53         return is_qfull;
  54 }
  55
  56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
  57 {
  58         u16 i, max_vectors;
  59
  60         max_vectors = mrioc->intr_info_count;
  61
  62         for (i = 0; i < max_vectors; i++)
  63                 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
  64 }
  65
  66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
  67 {
  68         mrioc->intr_enabled = 0;
  69         mpi3mr_sync_irqs(mrioc);
  70 }
  71
  72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
  73 {
  74         mrioc->intr_enabled = 1;
  75 }
  76
  77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
  78 {
  79         u16 i;
  80
  81         mpi3mr_ioc_disable_intr(mrioc);
  82
  83         if (!mrioc->intr_info)
  84                 return;
  85
  86         for (i = 0; i < mrioc->intr_info_count; i++)
  87                 free_irq(pci_irq_vector(mrioc->pdev, i),
  88                     (mrioc->intr_info + i));
  89
  90         kfree(mrioc->intr_info);
  91         mrioc->intr_info = NULL;
  92         mrioc->intr_info_count = 0;
  93         mrioc->is_intr_info_set = false;
  94         pci_free_irq_vectors(mrioc->pdev);
  95 }
  96
  97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
  98         dma_addr_t dma_addr)
  99 {
 100         struct mpi3_sge_common *sgel = paddr;
 101
 102         sgel->flags = flags;
 103         sgel->length = cpu_to_le32(length);
 104         sgel->address = cpu_to_le64(dma_addr);
 105 }
 106
 107 void mpi3mr_build_zero_len_sge(void *paddr)
 108 {
 109         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
 110
 111         mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
 112 }
 113
 114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
 115         dma_addr_t phys_addr)
 116 {
 117         if (!phys_addr)
 118                 return NULL;
 119
 120         if ((phys_addr < mrioc->reply_buf_dma) ||
 121             (phys_addr > mrioc->reply_buf_dma_max_address))
 122                 return NULL;
 123
 124         return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
 125 }
 126
 127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
 128         dma_addr_t phys_addr)
 129 {
 130         if (!phys_addr)
 131                 return NULL;
 132
 133         return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
 134 }
 135
 136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
 137         u64 reply_dma)
 138 {
 139         u32 old_idx = 0;
 140         unsigned long flags;
 141
 142         spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
 143         old_idx  =  mrioc->reply_free_queue_host_index;
 144         mrioc->reply_free_queue_host_index = (
 145             (mrioc->reply_free_queue_host_index ==
 146             (mrioc->reply_free_qsz - 1)) ? 0 :
 147             (mrioc->reply_free_queue_host_index + 1));
 148         mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
 149         writel(mrioc->reply_free_queue_host_index,
 150             &mrioc->sysif_regs->reply_free_host_index);
 151         spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
 152 }
 153
 154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
 155         u64 sense_buf_dma)
 156 {
 157         u32 old_idx = 0;
 158         unsigned long flags;
 159
 160         spin_lock_irqsave(&mrioc->sbq_lock, flags);
 161         old_idx  =  mrioc->sbq_host_index;
 162         mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
 163             (mrioc->sense_buf_q_sz - 1)) ? 0 :
 164             (mrioc->sbq_host_index + 1));
 165         mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
 166         writel(mrioc->sbq_host_index,
 167             &mrioc->sysif_regs->sense_buffer_free_host_index);
 168         spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
 169 }
 170
 171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
 172         struct mpi3_event_notification_reply *event_reply)
 173 {
 174         char *desc = NULL;
 175         u16 event;
 176
 177         event = event_reply->event;
 178
 179         switch (event) {
 180         case MPI3_EVENT_LOG_DATA:
 181                 desc = "Log Data";
 182                 break;
 183         case MPI3_EVENT_CHANGE:
 184                 desc = "Event Change";
 185                 break;
 186         case MPI3_EVENT_GPIO_INTERRUPT:
 187                 desc = "GPIO Interrupt";
 188                 break;
 189         case MPI3_EVENT_CABLE_MGMT:
 190                 desc = "Cable Management";
 191                 break;
 192         case MPI3_EVENT_ENERGY_PACK_CHANGE:
 193                 desc = "Energy Pack Change";
 194                 break;
 195         case MPI3_EVENT_DEVICE_ADDED:
 196         {
 197                 struct mpi3_device_page0 *event_data =
 198                     (struct mpi3_device_page0 *)event_reply->event_data;
 199                 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
 200                     event_data->dev_handle, event_data->device_form);
 201                 return;
 202         }
 203         case MPI3_EVENT_DEVICE_INFO_CHANGED:
 204         {
 205                 struct mpi3_device_page0 *event_data =
 206                     (struct mpi3_device_page0 *)event_reply->event_data;
 207                 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
 208                     event_data->dev_handle, event_data->device_form);
 209                 return;
 210         }
 211         case MPI3_EVENT_DEVICE_STATUS_CHANGE:
 212         {
 213                 struct mpi3_event_data_device_status_change *event_data =
 214                     (struct mpi3_event_data_device_status_change *)event_reply->event_data;
 215                 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
 216                     event_data->dev_handle, event_data->reason_code);
 217                 return;
 218         }
 219         case MPI3_EVENT_SAS_DISCOVERY:
 220         {
 221                 struct mpi3_event_data_sas_discovery *event_data =
 222                     (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
 223                 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
 224                     (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
 225                     "start" : "stop",
 226                     le32_to_cpu(event_data->discovery_status));
 227                 return;
 228         }
 229         case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
 230                 desc = "SAS Broadcast Primitive";
 231                 break;
 232         case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
 233                 desc = "SAS Notify Primitive";
 234                 break;
 235         case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
 236                 desc = "SAS Init Device Status Change";
 237                 break;
 238         case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
 239                 desc = "SAS Init Table Overflow";
 240                 break;
 241         case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
 242                 desc = "SAS Topology Change List";
 243                 break;
 244         case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
 245                 desc = "Enclosure Device Status Change";
 246                 break;
 247         case MPI3_EVENT_ENCL_DEVICE_ADDED:
 248                 desc = "Enclosure Added";
 249                 break;
 250         case MPI3_EVENT_HARD_RESET_RECEIVED:
 251                 desc = "Hard Reset Received";
 252                 break;
 253         case MPI3_EVENT_SAS_PHY_COUNTER:
 254                 desc = "SAS PHY Counter";
 255                 break;
 256         case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
 257                 desc = "SAS Device Discovery Error";
 258                 break;
 259         case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
 260                 desc = "PCIE Topology Change List";
 261                 break;
 262         case MPI3_EVENT_PCIE_ENUMERATION:
 263         {
 264                 struct mpi3_event_data_pcie_enumeration *event_data =
 265                     (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
 266                 ioc_info(mrioc, "PCIE Enumeration: (%s)",
 267                     (event_data->reason_code ==
 268                     MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
 269                 if (event_data->enumeration_status)
 270                         ioc_info(mrioc, "enumeration_status(0x%08x)\n",
 271                             le32_to_cpu(event_data->enumeration_status));
 272                 return;
 273         }
 274         case MPI3_EVENT_PREPARE_FOR_RESET:
 275                 desc = "Prepare For Reset";
 276                 break;
 277         case MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE:
 278                 desc = "Diagnostic Buffer Status Change";
 279                 break;
 280         }
 281
 282         if (!desc)
 283                 return;
 284
 285         ioc_info(mrioc, "%s\n", desc);
 286 }
 287
 288 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
 289         struct mpi3_default_reply *def_reply)
 290 {
 291         struct mpi3_event_notification_reply *event_reply =
 292             (struct mpi3_event_notification_reply *)def_reply;
 293
 294         mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
 295         mpi3mr_print_event_data(mrioc, event_reply);
 296         mpi3mr_os_handle_events(mrioc, event_reply);
 297 }
 298
 299 static struct mpi3mr_drv_cmd *
 300 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
 301         struct mpi3_default_reply *def_reply)
 302 {
 303         u16 idx;
 304
 305         switch (host_tag) {
 306         case MPI3MR_HOSTTAG_INITCMDS:
 307                 return &mrioc->init_cmds;
 308         case MPI3MR_HOSTTAG_CFG_CMDS:
 309                 return &mrioc->cfg_cmds;
 310         case MPI3MR_HOSTTAG_BSG_CMDS:
 311                 return &mrioc->bsg_cmds;
 312         case MPI3MR_HOSTTAG_BLK_TMS:
 313                 return &mrioc->host_tm_cmds;
 314         case MPI3MR_HOSTTAG_PEL_ABORT:
 315                 return &mrioc->pel_abort_cmd;
 316         case MPI3MR_HOSTTAG_PEL_WAIT:
 317                 return &mrioc->pel_cmds;
 318         case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
 319                 return &mrioc->transport_cmds;
 320         case MPI3MR_HOSTTAG_INVALID:
 321                 if (def_reply && def_reply->function ==
 322                     MPI3_FUNCTION_EVENT_NOTIFICATION)
 323                         mpi3mr_handle_events(mrioc, def_reply);
 324                 return NULL;
 325         default:
 326                 break;
 327         }
 328         if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
 329             host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
 330                 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
 331                 return &mrioc->dev_rmhs_cmds[idx];
 332         }
 333
 334         if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
 335             host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
 336                 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
 337                 return &mrioc->evtack_cmds[idx];
 338         }
 339
 340         return NULL;
 341 }
 342
 343 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
 344         struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
 345 {
 346         u16 reply_desc_type, host_tag = 0;
 347         u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
 348         u16 masked_ioc_status = MPI3_IOCSTATUS_SUCCESS;
 349         u32 ioc_loginfo = 0, sense_count = 0;
 350         struct mpi3_status_reply_descriptor *status_desc;
 351         struct mpi3_address_reply_descriptor *addr_desc;
 352         struct mpi3_success_reply_descriptor *success_desc;
 353         struct mpi3_default_reply *def_reply = NULL;
 354         struct mpi3mr_drv_cmd *cmdptr = NULL;
 355         struct mpi3_scsi_io_reply *scsi_reply;
 356         struct scsi_sense_hdr sshdr;
 357         u8 *sense_buf = NULL;
 358
 359         *reply_dma = 0;
 360         reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
 361             MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
 362         switch (reply_desc_type) {
 363         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
 364                 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
 365                 host_tag = le16_to_cpu(status_desc->host_tag);
 366                 ioc_status = le16_to_cpu(status_desc->ioc_status);
 367                 if (ioc_status &
 368                     MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
 369                         ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
 370                 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
 371                 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo);
 372                 break;
 373         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
 374                 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
 375                 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
 376                 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
 377                 if (!def_reply)
 378                         goto out;
 379                 host_tag = le16_to_cpu(def_reply->host_tag);
 380                 ioc_status = le16_to_cpu(def_reply->ioc_status);
 381                 if (ioc_status &
 382                     MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
 383                         ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
 384                 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
 385                 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
 386                         scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
 387                         sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
 388                             le64_to_cpu(scsi_reply->sense_data_buffer_address));
 389                         sense_count = le32_to_cpu(scsi_reply->sense_count);
 390                         if (sense_buf) {
 391                                 scsi_normalize_sense(sense_buf, sense_count,
 392                                     &sshdr);
 393                                 mpi3mr_scsisense_trigger(mrioc, sshdr.sense_key,
 394                                     sshdr.asc, sshdr.ascq);
 395                         }
 396                 }
 397                 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo);
 398                 break;
 399         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
 400                 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
 401                 host_tag = le16_to_cpu(success_desc->host_tag);
 402                 break;
 403         default:
 404                 break;
 405         }
 406
 407         cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
 408         if (cmdptr) {
 409                 if (cmdptr->state & MPI3MR_CMD_PENDING) {
 410                         cmdptr->state |= MPI3MR_CMD_COMPLETE;
 411                         cmdptr->ioc_loginfo = ioc_loginfo;
 412                         if (host_tag == MPI3MR_HOSTTAG_BSG_CMDS)
 413                                 cmdptr->ioc_status = ioc_status;
 414                         else
 415                                 cmdptr->ioc_status = masked_ioc_status;
 416                         cmdptr->state &= ~MPI3MR_CMD_PENDING;
 417                         if (def_reply) {
 418                                 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
 419                                 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
 420                                     mrioc->reply_sz);
 421                         }
 422                         if (sense_buf && cmdptr->sensebuf) {
 423                                 cmdptr->is_sense = 1;
 424                                 memcpy(cmdptr->sensebuf, sense_buf,
 425                                        MPI3MR_SENSE_BUF_SZ);
 426                         }
 427                         if (cmdptr->is_waiting) {
 428                                 complete(&cmdptr->done);
 429                                 cmdptr->is_waiting = 0;
 430                         } else if (cmdptr->callback)
 431                                 cmdptr->callback(mrioc, cmdptr);
 432                 }
 433         }
 434 out:
 435         if (sense_buf)
 436                 mpi3mr_repost_sense_buf(mrioc,
 437                     le64_to_cpu(scsi_reply->sense_data_buffer_address));
 438 }
 439
 440 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
 441 {
 442         u32 exp_phase = mrioc->admin_reply_ephase;
 443         u32 admin_reply_ci = mrioc->admin_reply_ci;
 444         u32 num_admin_replies = 0;
 445         u64 reply_dma = 0;
 446         u16 threshold_comps = 0;
 447         struct mpi3_default_reply_descriptor *reply_desc;
 448
 449         if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1))
 450                 return 0;
 451
 452         reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
 453             admin_reply_ci;
 454
 455         if ((le16_to_cpu(reply_desc->reply_flags) &
 456             MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
 457                 atomic_dec(&mrioc->admin_reply_q_in_use);
 458                 return 0;
 459         }
 460
 461         do {
 462                 if (mrioc->unrecoverable)
 463                         break;
 464
 465                 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
 466                 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
 467                 if (reply_dma)
 468                         mpi3mr_repost_reply_buf(mrioc, reply_dma);
 469                 num_admin_replies++;
 470                 threshold_comps++;
 471                 if (++admin_reply_ci == mrioc->num_admin_replies) {
 472                         admin_reply_ci = 0;
 473                         exp_phase ^= 1;
 474                 }
 475                 reply_desc =
 476                     (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
 477                     admin_reply_ci;
 478                 if ((le16_to_cpu(reply_desc->reply_flags) &
 479                     MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 480                         break;
 481                 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
 482                         writel(admin_reply_ci,
 483                             &mrioc->sysif_regs->admin_reply_queue_ci);
 484                         threshold_comps = 0;
 485                 }
 486         } while (1);
 487
 488         writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
 489         mrioc->admin_reply_ci = admin_reply_ci;
 490         mrioc->admin_reply_ephase = exp_phase;
 491         atomic_dec(&mrioc->admin_reply_q_in_use);
 492
 493         return num_admin_replies;
 494 }
 495
 496 /**
 497  * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
 498  *      queue's consumer index from operational reply descriptor queue.
 499  * @op_reply_q: op_reply_qinfo object
 500  * @reply_ci: operational reply descriptor's queue consumer index
 501  *
 502  * Returns: reply descriptor frame address
 503  */
 504 static inline struct mpi3_default_reply_descriptor *
 505 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
 506 {
 507         void *segment_base_addr;
 508         struct segments *segments = op_reply_q->q_segments;
 509         struct mpi3_default_reply_descriptor *reply_desc = NULL;
 510
 511         segment_base_addr =
 512             segments[reply_ci / op_reply_q->segment_qd].segment;
 513         reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
 514             (reply_ci % op_reply_q->segment_qd);
 515         return reply_desc;
 516 }
 517
 518 /**
 519  * mpi3mr_process_op_reply_q - Operational reply queue handler
 520  * @mrioc: Adapter instance reference
 521  * @op_reply_q: Operational reply queue info
 522  *
 523  * Checks the specific operational reply queue and drains the
 524  * reply queue entries until the queue is empty and process the
 525  * individual reply descriptors.
 526  *
 527  * Return: 0 if queue is already processed,or number of reply
 528  *          descriptors processed.
 529  */
 530 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
 531         struct op_reply_qinfo *op_reply_q)
 532 {
 533         struct op_req_qinfo *op_req_q;
 534         u32 exp_phase;
 535         u32 reply_ci;
 536         u32 num_op_reply = 0;
 537         u64 reply_dma = 0;
 538         struct mpi3_default_reply_descriptor *reply_desc;
 539         u16 req_q_idx = 0, reply_qidx, threshold_comps = 0;
 540
 541         reply_qidx = op_reply_q->qid - 1;
 542
 543         if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
 544                 return 0;
 545
 546         exp_phase = op_reply_q->ephase;
 547         reply_ci = op_reply_q->ci;
 548
 549         reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
 550         if ((le16_to_cpu(reply_desc->reply_flags) &
 551             MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
 552                 atomic_dec(&op_reply_q->in_use);
 553                 return 0;
 554         }
 555
 556         do {
 557                 if (mrioc->unrecoverable)
 558                         break;
 559
 560                 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
 561                 op_req_q = &mrioc->req_qinfo[req_q_idx];
 562
 563                 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
 564                 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
 565                     reply_qidx);
 566                 atomic_dec(&op_reply_q->pend_ios);
 567                 if (reply_dma)
 568                         mpi3mr_repost_reply_buf(mrioc, reply_dma);
 569                 num_op_reply++;
 570                 threshold_comps++;
 571
 572                 if (++reply_ci == op_reply_q->num_replies) {
 573                         reply_ci = 0;
 574                         exp_phase ^= 1;
 575                 }
 576
 577                 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
 578
 579                 if ((le16_to_cpu(reply_desc->reply_flags) &
 580                     MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 581                         break;
 582 #ifndef CONFIG_PREEMPT_RT
 583                 /*
 584                  * Exit completion loop to avoid CPU lockup
 585                  * Ensure remaining completion happens from threaded ISR.
 586                  */
 587                 if (num_op_reply > mrioc->max_host_ios) {
 588                         op_reply_q->enable_irq_poll = true;
 589                         break;
 590                 }
 591 #endif
 592                 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
 593                         writel(reply_ci,
 594                             &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
 595                         atomic_sub(threshold_comps, &op_reply_q->pend_ios);
 596                         threshold_comps = 0;
 597                 }
 598         } while (1);
 599
 600         writel(reply_ci,
 601             &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
 602         op_reply_q->ci = reply_ci;
 603         op_reply_q->ephase = exp_phase;
 604         atomic_sub(threshold_comps, &op_reply_q->pend_ios);
 605         atomic_dec(&op_reply_q->in_use);
 606         return num_op_reply;
 607 }
 608
 609 /**
 610  * mpi3mr_blk_mq_poll - Operational reply queue handler
 611  * @shost: SCSI Host reference
 612  * @queue_num: Request queue number (w.r.t OS it is hardware context number)
 613  *
 614  * Checks the specific operational reply queue and drains the
 615  * reply queue entries until the queue is empty and process the
 616  * individual reply descriptors.
 617  *
 618  * Return: 0 if queue is already processed,or number of reply
 619  *          descriptors processed.
 620  */
 621 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
 622 {
 623         int num_entries = 0;
 624         struct mpi3mr_ioc *mrioc;
 625
 626         mrioc = (struct mpi3mr_ioc *)shost->hostdata;
 627
 628         if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
 629             mrioc->unrecoverable || mrioc->pci_err_recovery))
 630                 return 0;
 631
 632         num_entries = mpi3mr_process_op_reply_q(mrioc,
 633                         &mrioc->op_reply_qinfo[queue_num]);
 634
 635         return num_entries;
 636 }
 637
 638 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
 639 {
 640         struct mpi3mr_intr_info *intr_info = privdata;
 641         struct mpi3mr_ioc *mrioc;
 642         u16 midx;
 643         u32 num_admin_replies = 0, num_op_reply = 0;
 644
 645         if (!intr_info)
 646                 return IRQ_NONE;
 647
 648         mrioc = intr_info->mrioc;
 649
 650         if (!mrioc->intr_enabled)
 651                 return IRQ_NONE;
 652
 653         midx = intr_info->msix_index;
 654
 655         if (!midx)
 656                 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
 657         if (intr_info->op_reply_q)
 658                 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
 659                     intr_info->op_reply_q);
 660
 661         if (num_admin_replies || num_op_reply)
 662                 return IRQ_HANDLED;
 663         else
 664                 return IRQ_NONE;
 665 }
 666
 667 #ifndef CONFIG_PREEMPT_RT
 668
 669 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
 670 {
 671         struct mpi3mr_intr_info *intr_info = privdata;
 672         int ret;
 673
 674         if (!intr_info)
 675                 return IRQ_NONE;
 676
 677         /* Call primary ISR routine */
 678         ret = mpi3mr_isr_primary(irq, privdata);
 679
 680         /*
 681          * If more IOs are expected, schedule IRQ polling thread.
 682          * Otherwise exit from ISR.
 683          */
 684         if (!intr_info->op_reply_q)
 685                 return ret;
 686
 687         if (!intr_info->op_reply_q->enable_irq_poll ||
 688             !atomic_read(&intr_info->op_reply_q->pend_ios))
 689                 return ret;
 690
 691         disable_irq_nosync(intr_info->os_irq);
 692
 693         return IRQ_WAKE_THREAD;
 694 }
 695
 696 /**
 697  * mpi3mr_isr_poll - Reply queue polling routine
 698  * @irq: IRQ
 699  * @privdata: Interrupt info
 700  *
 701  * poll for pending I/O completions in a loop until pending I/Os
 702  * present or controller queue depth I/Os are processed.
 703  *
 704  * Return: IRQ_NONE or IRQ_HANDLED
 705  */
 706 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
 707 {
 708         struct mpi3mr_intr_info *intr_info = privdata;
 709         struct mpi3mr_ioc *mrioc;
 710         u16 midx;
 711         u32 num_op_reply = 0;
 712
 713         if (!intr_info || !intr_info->op_reply_q)
 714                 return IRQ_NONE;
 715
 716         mrioc = intr_info->mrioc;
 717         midx = intr_info->msix_index;
 718
 719         /* Poll for pending IOs completions */
 720         do {
 721                 if (!mrioc->intr_enabled || mrioc->unrecoverable)
 722                         break;
 723
 724                 if (!midx)
 725                         mpi3mr_process_admin_reply_q(mrioc);
 726                 if (intr_info->op_reply_q)
 727                         num_op_reply +=
 728                             mpi3mr_process_op_reply_q(mrioc,
 729                                 intr_info->op_reply_q);
 730
 731                 usleep_range(MPI3MR_IRQ_POLL_SLEEP, MPI3MR_IRQ_POLL_SLEEP + 1);
 732
 733         } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
 734             (num_op_reply < mrioc->max_host_ios));
 735
 736         intr_info->op_reply_q->enable_irq_poll = false;
 737         enable_irq(intr_info->os_irq);
 738
 739         return IRQ_HANDLED;
 740 }
 741
 742 #endif
 743
 744 /**
 745  * mpi3mr_request_irq - Request IRQ and register ISR
 746  * @mrioc: Adapter instance reference
 747  * @index: IRQ vector index
 748  *
 749  * Request threaded ISR with primary ISR and secondary
 750  *
 751  * Return: 0 on success and non zero on failures.
 752  */
 753 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
 754 {
 755         struct pci_dev *pdev = mrioc->pdev;
 756         struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
 757         int retval = 0;
 758
 759         intr_info->mrioc = mrioc;
 760         intr_info->msix_index = index;
 761         intr_info->op_reply_q = NULL;
 762
 763         snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
 764             mrioc->driver_name, mrioc->id, index);
 765
 766 #ifndef CONFIG_PREEMPT_RT
 767         retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
 768             mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
 769 #else
 770         retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
 771             NULL, IRQF_SHARED, intr_info->name, intr_info);
 772 #endif
 773         if (retval) {
 774                 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
 775                     intr_info->name, pci_irq_vector(pdev, index));
 776                 return retval;
 777         }
 778
 779         intr_info->os_irq = pci_irq_vector(pdev, index);
 780         return retval;
 781 }
 782
 783 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
 784 {
 785         if (!mrioc->requested_poll_qcount)
 786                 return;
 787
 788         /* Reserved for Admin and Default Queue */
 789         if (max_vectors > 2 &&
 790                 (mrioc->requested_poll_qcount < max_vectors - 2)) {
 791                 ioc_info(mrioc,
 792                     "enabled polled queues (%d) msix (%d)\n",
 793                     mrioc->requested_poll_qcount, max_vectors);
 794         } else {
 795                 ioc_info(mrioc,
 796                     "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
 797                     mrioc->requested_poll_qcount, max_vectors);
 798                 mrioc->requested_poll_qcount = 0;
 799         }
 800 }
 801
 802 /**
 803  * mpi3mr_setup_isr - Setup ISR for the controller
 804  * @mrioc: Adapter instance reference
 805  * @setup_one: Request one IRQ or more
 806  *
 807  * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
 808  *
 809  * Return: 0 on success and non zero on failures.
 810  */
 811 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
 812 {
 813         unsigned int irq_flags = PCI_IRQ_MSIX;
 814         int max_vectors, min_vec;
 815         int retval;
 816         int i;
 817         struct irq_affinity desc = { .pre_vectors =  1, .post_vectors = 1 };
 818
 819         if (mrioc->is_intr_info_set)
 820                 return 0;
 821
 822         mpi3mr_cleanup_isr(mrioc);
 823
 824         if (setup_one || reset_devices) {
 825                 max_vectors = 1;
 826                 retval = pci_alloc_irq_vectors(mrioc->pdev,
 827                     1, max_vectors, irq_flags);
 828                 if (retval < 0) {
 829                         ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
 830                             retval);
 831                         goto out_failed;
 832                 }
 833         } else {
 834                 max_vectors =
 835                     min_t(int, mrioc->cpu_count + 1 +
 836                         mrioc->requested_poll_qcount, mrioc->msix_count);
 837
 838                 mpi3mr_calc_poll_queues(mrioc, max_vectors);
 839
 840                 ioc_info(mrioc,
 841                     "MSI-X vectors supported: %d, no of cores: %d,",
 842                     mrioc->msix_count, mrioc->cpu_count);
 843                 ioc_info(mrioc,
 844                     "MSI-x vectors requested: %d poll_queues %d\n",
 845                     max_vectors, mrioc->requested_poll_qcount);
 846
 847                 desc.post_vectors = mrioc->requested_poll_qcount;
 848                 min_vec = desc.pre_vectors + desc.post_vectors;
 849                 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
 850
 851                 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
 852                         min_vec, max_vectors, irq_flags, &desc);
 853
 854                 if (retval < 0) {
 855                         ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
 856                             retval);
 857                         goto out_failed;
 858                 }
 859
 860
 861                 /*
 862                  * If only one MSI-x is allocated, then MSI-x 0 will be shared
 863                  * between Admin queue and operational queue
 864                  */
 865                 if (retval == min_vec)
 866                         mrioc->op_reply_q_offset = 0;
 867                 else if (retval != (max_vectors)) {
 868                         ioc_info(mrioc,
 869                             "allocated vectors (%d) are less than configured (%d)\n",
 870                             retval, max_vectors);
 871                 }
 872
 873                 max_vectors = retval;
 874                 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
 875
 876                 mpi3mr_calc_poll_queues(mrioc, max_vectors);
 877
 878         }
 879
 880         mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
 881             GFP_KERNEL);
 882         if (!mrioc->intr_info) {
 883                 retval = -ENOMEM;
 884                 pci_free_irq_vectors(mrioc->pdev);
 885                 goto out_failed;
 886         }
 887         for (i = 0; i < max_vectors; i++) {
 888                 retval = mpi3mr_request_irq(mrioc, i);
 889                 if (retval) {
 890                         mrioc->intr_info_count = i;
 891                         goto out_failed;
 892                 }
 893         }
 894         if (reset_devices || !setup_one)
 895                 mrioc->is_intr_info_set = true;
 896         mrioc->intr_info_count = max_vectors;
 897         mpi3mr_ioc_enable_intr(mrioc);
 898         return 0;
 899
 900 out_failed:
 901         mpi3mr_cleanup_isr(mrioc);
 902
 903         return retval;
 904 }
 905
 906 static const struct {
 907         enum mpi3mr_iocstate value;
 908         char *name;
 909 } mrioc_states[] = {
 910         { MRIOC_STATE_READY, "ready" },
 911         { MRIOC_STATE_FAULT, "fault" },
 912         { MRIOC_STATE_RESET, "reset" },
 913         { MRIOC_STATE_BECOMING_READY, "becoming ready" },
 914         { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
 915         { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
 916 };
 917
 918 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
 919 {
 920         int i;
 921         char *name = NULL;
 922
 923         for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
 924                 if (mrioc_states[i].value == mrioc_state) {
 925                         name = mrioc_states[i].name;
 926                         break;
 927                 }
 928         }
 929         return name;
 930 }
 931
 932 /* Reset reason to name mapper structure*/
 933 static const struct {
 934         enum mpi3mr_reset_reason value;
 935         char *name;
 936 } mpi3mr_reset_reason_codes[] = {
 937         { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
 938         { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
 939         { MPI3MR_RESET_FROM_APP, "application invocation" },
 940         { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
 941         { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
 942         { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
 943         { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
 944         { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
 945         { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
 946         { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
 947         { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
 948         { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
 949         { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
 950         {
 951                 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
 952                 "create request queue timeout"
 953         },
 954         {
 955                 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
 956                 "create reply queue timeout"
 957         },
 958         { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
 959         { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
 960         { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
 961         { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
 962         {
 963                 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
 964                 "component image activation timeout"
 965         },
 966         {
 967                 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
 968                 "get package version timeout"
 969         },
 970         { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
 971         { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
 972         {
 973                 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT,
 974                 "diagnostic buffer post timeout"
 975         },
 976         {
 977                 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT,
 978                 "diagnostic buffer release timeout"
 979         },
 980         { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
 981         { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
 982         { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
 983 };
 984
 985 /**
 986  * mpi3mr_reset_rc_name - get reset reason code name
 987  * @reason_code: reset reason code value
 988  *
 989  * Map reset reason to an NULL terminated ASCII string
 990  *
 991  * Return: name corresponding to reset reason value or NULL.
 992  */
 993 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
 994 {
 995         int i;
 996         char *name = NULL;
 997
 998         for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
 999                 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
1000                         name = mpi3mr_reset_reason_codes[i].name;
1001                         break;
1002                 }
1003         }
1004         return name;
1005 }
1006
1007 /* Reset type to name mapper structure*/
1008 static const struct {
1009         u16 reset_type;
1010         char *name;
1011 } mpi3mr_reset_types[] = {
1012         { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
1013         { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
1014 };
1015
1016 /**
1017  * mpi3mr_reset_type_name - get reset type name
1018  * @reset_type: reset type value
1019  *
1020  * Map reset type to an NULL terminated ASCII string
1021  *
1022  * Return: name corresponding to reset type value or NULL.
1023  */
1024 static const char *mpi3mr_reset_type_name(u16 reset_type)
1025 {
1026         int i;
1027         char *name = NULL;
1028
1029         for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
1030                 if (mpi3mr_reset_types[i].reset_type == reset_type) {
1031                         name = mpi3mr_reset_types[i].name;
1032                         break;
1033                 }
1034         }
1035         return name;
1036 }
1037
1038 /**
1039  * mpi3mr_is_fault_recoverable - Read fault code and decide
1040  * whether the controller can be recoverable
1041  * @mrioc: Adapter instance reference
1042  * Return: true if fault is recoverable, false otherwise.
1043  */
1044 static inline bool mpi3mr_is_fault_recoverable(struct mpi3mr_ioc *mrioc)
1045 {
1046         u32 fault;
1047
1048         fault = (readl(&mrioc->sysif_regs->fault) &
1049                       MPI3_SYSIF_FAULT_CODE_MASK);
1050
1051         switch (fault) {
1052         case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
1053         case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
1054                 ioc_warn(mrioc,
1055                     "controller requires system power cycle, marking controller as unrecoverable\n");
1056                 return false;
1057         case MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER:
1058                 ioc_warn(mrioc,
1059                     "controller faulted due to insufficient power,\n"
1060                     " try by connecting it to a different slot\n");
1061                 return false;
1062         default:
1063                 break;
1064         }
1065         return true;
1066 }
1067
1068 /**
1069  * mpi3mr_print_fault_info - Display fault information
1070  * @mrioc: Adapter instance reference
1071  *
1072  * Display the controller fault information if there is a
1073  * controller fault.
1074  *
1075  * Return: Nothing.
1076  */
1077 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1078 {
1079         u32 ioc_status, code, code1, code2, code3;
1080
1081         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1082
1083         if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1084                 code = readl(&mrioc->sysif_regs->fault);
1085                 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1086                 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1087                 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1088
1089                 ioc_info(mrioc,
1090                     "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1091                     code, code1, code2, code3);
1092         }
1093 }
1094
1095 /**
1096  * mpi3mr_get_iocstate - Get IOC State
1097  * @mrioc: Adapter instance reference
1098  *
1099  * Return a proper IOC state enum based on the IOC status and
1100  * IOC configuration and unrcoverable state of the controller.
1101  *
1102  * Return: Current IOC state.
1103  */
1104 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1105 {
1106         u32 ioc_status, ioc_config;
1107         u8 ready, enabled;
1108
1109         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1110         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1111
1112         if (mrioc->unrecoverable)
1113                 return MRIOC_STATE_UNRECOVERABLE;
1114         if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1115                 return MRIOC_STATE_FAULT;
1116
1117         ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1118         enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1119
1120         if (ready && enabled)
1121                 return MRIOC_STATE_READY;
1122         if ((!ready) && (!enabled))
1123                 return MRIOC_STATE_RESET;
1124         if ((!ready) && (enabled))
1125                 return MRIOC_STATE_BECOMING_READY;
1126
1127         return MRIOC_STATE_RESET_REQUESTED;
1128 }
1129
1130 /**
1131  * mpi3mr_free_ioctl_dma_memory - free memory for ioctl dma
1132  * @mrioc: Adapter instance reference
1133  *
1134  * Free the DMA memory allocated for IOCTL handling purpose.
1135  *
1136  * Return: None
1137  */
1138 static void mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc *mrioc)
1139 {
1140         struct dma_memory_desc *mem_desc;
1141         u16 i;
1142
1143         if (!mrioc->ioctl_dma_pool)
1144                 return;
1145
1146         for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) {
1147                 mem_desc = &mrioc->ioctl_sge[i];
1148                 if (mem_desc->addr) {
1149                         dma_pool_free(mrioc->ioctl_dma_pool,
1150                                       mem_desc->addr,
1151                                       mem_desc->dma_addr);
1152                         mem_desc->addr = NULL;
1153                 }
1154         }
1155         dma_pool_destroy(mrioc->ioctl_dma_pool);
1156         mrioc->ioctl_dma_pool = NULL;
1157         mem_desc = &mrioc->ioctl_chain_sge;
1158
1159         if (mem_desc->addr) {
1160                 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
1161                                   mem_desc->addr, mem_desc->dma_addr);
1162                 mem_desc->addr = NULL;
1163         }
1164         mem_desc = &mrioc->ioctl_resp_sge;
1165         if (mem_desc->addr) {
1166                 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
1167                                   mem_desc->addr, mem_desc->dma_addr);
1168                 mem_desc->addr = NULL;
1169         }
1170
1171         mrioc->ioctl_sges_allocated = false;
1172 }
1173
1174 /**
1175  * mpi3mr_alloc_ioctl_dma_memory - Alloc memory for ioctl dma
1176  * @mrioc: Adapter instance reference
1177  *
1178  * This function allocates dmaable memory required to handle the
1179  * application issued MPI3 IOCTL requests.
1180  *
1181  * Return: None
1182  */
1183 static void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc *mrioc)
1184
1185 {
1186         struct dma_memory_desc *mem_desc;
1187         u16 i;
1188
1189         mrioc->ioctl_dma_pool = dma_pool_create("ioctl dma pool",
1190                                                 &mrioc->pdev->dev,
1191                                                 MPI3MR_IOCTL_SGE_SIZE,
1192                                                 MPI3MR_PAGE_SIZE_4K, 0);
1193
1194         if (!mrioc->ioctl_dma_pool) {
1195                 ioc_err(mrioc, "ioctl_dma_pool: dma_pool_create failed\n");
1196                 goto out_failed;
1197         }
1198
1199         for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) {
1200                 mem_desc = &mrioc->ioctl_sge[i];
1201                 mem_desc->size = MPI3MR_IOCTL_SGE_SIZE;
1202                 mem_desc->addr = dma_pool_zalloc(mrioc->ioctl_dma_pool,
1203                                                  GFP_KERNEL,
1204                                                  &mem_desc->dma_addr);
1205                 if (!mem_desc->addr)
1206                         goto out_failed;
1207         }
1208
1209         mem_desc = &mrioc->ioctl_chain_sge;
1210         mem_desc->size = MPI3MR_PAGE_SIZE_4K;
1211         mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
1212                                             mem_desc->size,
1213                                             &mem_desc->dma_addr,
1214                                             GFP_KERNEL);
1215         if (!mem_desc->addr)
1216                 goto out_failed;
1217
1218         mem_desc = &mrioc->ioctl_resp_sge;
1219         mem_desc->size = MPI3MR_PAGE_SIZE_4K;
1220         mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
1221                                             mem_desc->size,
1222                                             &mem_desc->dma_addr,
1223                                             GFP_KERNEL);
1224         if (!mem_desc->addr)
1225                 goto out_failed;
1226
1227         mrioc->ioctl_sges_allocated = true;
1228
1229         return;
1230 out_failed:
1231         ioc_warn(mrioc, "cannot allocate DMA memory for the mpt commands\n"
1232                  "from the applications, application interface for MPT command is disabled\n");
1233         mpi3mr_free_ioctl_dma_memory(mrioc);
1234 }
1235
1236 /**
1237  * mpi3mr_clear_reset_history - clear reset history
1238  * @mrioc: Adapter instance reference
1239  *
1240  * Write the reset history bit in IOC status to clear the bit,
1241  * if it is already set.
1242  *
1243  * Return: Nothing.
1244  */
1245 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1246 {
1247         u32 ioc_status;
1248
1249         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1250         if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1251                 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1252 }
1253
1254 /**
1255  * mpi3mr_issue_and_process_mur - Message unit Reset handler
1256  * @mrioc: Adapter instance reference
1257  * @reset_reason: Reset reason code
1258  *
1259  * Issue Message unit Reset to the controller and wait for it to
1260  * be complete.
1261  *
1262  * Return: 0 on success, -1 on failure.
1263  */
1264 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1265         u32 reset_reason)
1266 {
1267         u32 ioc_config, timeout, ioc_status, scratch_pad0;
1268         int retval = -1;
1269
1270         ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1271         if (mrioc->unrecoverable) {
1272                 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1273                 return retval;
1274         }
1275         mpi3mr_clear_reset_history(mrioc);
1276         scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
1277                          MPI3MR_RESET_REASON_OSTYPE_SHIFT) |
1278                         (mrioc->facts.ioc_num <<
1279                          MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
1280         writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]);
1281         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1282         ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1283         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1284
1285         timeout = MPI3MR_MUR_TIMEOUT * 10;
1286         do {
1287                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1288                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1289                         mpi3mr_clear_reset_history(mrioc);
1290                         break;
1291                 }
1292                 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1293                         mpi3mr_print_fault_info(mrioc);
1294                         break;
1295                 }
1296                 msleep(100);
1297         } while (--timeout);
1298
1299         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1300         if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1301               (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1302               (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1303                 retval = 0;
1304
1305         ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1306             (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1307         return retval;
1308 }
1309
1310 /**
1311  * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1312  * during reset/resume
1313  * @mrioc: Adapter instance reference
1314  *
1315  * Return: zero if the new IOCFacts parameters value is compatible with
1316  * older values else return -EPERM
1317  */
1318 static int
1319 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1320 {
1321         unsigned long *removepend_bitmap;
1322
1323         if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1324                 ioc_err(mrioc,
1325                     "cannot increase reply size from %d to %d\n",
1326                     mrioc->reply_sz, mrioc->facts.reply_sz);
1327                 return -EPERM;
1328         }
1329
1330         if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1331                 ioc_err(mrioc,
1332                     "cannot reduce number of operational reply queues from %d to %d\n",
1333                     mrioc->num_op_reply_q,
1334                     mrioc->facts.max_op_reply_q);
1335                 return -EPERM;
1336         }
1337
1338         if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1339                 ioc_err(mrioc,
1340                     "cannot reduce number of operational request queues from %d to %d\n",
1341                     mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1342                 return -EPERM;
1343         }
1344
1345         if (mrioc->shost->max_sectors != (mrioc->facts.max_data_length / 512))
1346                 ioc_err(mrioc, "Warning: The maximum data transfer length\n"
1347                             "\tchanged after reset: previous(%d), new(%d),\n"
1348                             "the driver cannot change this at run time\n",
1349                             mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length);
1350
1351         if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1352             MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED))
1353                 ioc_err(mrioc,
1354                     "critical error: multipath capability is enabled at the\n"
1355                     "\tcontroller while sas transport support is enabled at the\n"
1356                     "\tdriver, please reboot the system or reload the driver\n");
1357
1358         if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1359                 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1360                                                   GFP_KERNEL);
1361                 if (!removepend_bitmap) {
1362                         ioc_err(mrioc,
1363                                 "failed to increase removepend_bitmap bits from %d to %d\n",
1364                                 mrioc->dev_handle_bitmap_bits,
1365                                 mrioc->facts.max_devhandle);
1366                         return -EPERM;
1367                 }
1368                 bitmap_free(mrioc->removepend_bitmap);
1369                 mrioc->removepend_bitmap = removepend_bitmap;
1370                 ioc_info(mrioc,
1371                          "increased bits of dev_handle_bitmap from %d to %d\n",
1372                          mrioc->dev_handle_bitmap_bits,
1373                          mrioc->facts.max_devhandle);
1374                 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1375         }
1376
1377         return 0;
1378 }
1379
1380 /**
1381  * mpi3mr_bring_ioc_ready - Bring controller to ready state
1382  * @mrioc: Adapter instance reference
1383  *
1384  * Set Enable IOC bit in IOC configuration register and wait for
1385  * the controller to become ready.
1386  *
1387  * Return: 0 on success, appropriate error on failure.
1388  */
1389 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1390 {
1391         u32 ioc_config, ioc_status, timeout, host_diagnostic;
1392         int retval = 0;
1393         enum mpi3mr_iocstate ioc_state;
1394         u64 base_info;
1395         u8 retry = 0;
1396         u64 start_time, elapsed_time_sec;
1397
1398 retry_bring_ioc_ready:
1399
1400         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1401         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1402         base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1403         ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1404             ioc_status, ioc_config, base_info);
1405
1406         if (!mpi3mr_is_fault_recoverable(mrioc)) {
1407                 mrioc->unrecoverable = 1;
1408                 goto out_device_not_present;
1409         }
1410
1411         /*The timeout value is in 2sec unit, changing it to seconds*/
1412         mrioc->ready_timeout =
1413             ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1414             MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1415
1416         ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1417
1418         ioc_state = mpi3mr_get_iocstate(mrioc);
1419         ioc_info(mrioc, "controller is in %s state during detection\n",
1420             mpi3mr_iocstate_name(ioc_state));
1421
1422         timeout = mrioc->ready_timeout * 10;
1423
1424         do {
1425                 ioc_state = mpi3mr_get_iocstate(mrioc);
1426
1427                 if (ioc_state != MRIOC_STATE_BECOMING_READY &&
1428                     ioc_state != MRIOC_STATE_RESET_REQUESTED)
1429                         break;
1430
1431                 if (!pci_device_is_present(mrioc->pdev)) {
1432                         mrioc->unrecoverable = 1;
1433                         ioc_err(mrioc, "controller is not present while waiting to reset\n");
1434                         goto out_device_not_present;
1435                 }
1436
1437                 msleep(100);
1438         } while (--timeout);
1439
1440         if (ioc_state == MRIOC_STATE_READY) {
1441                 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1442                 retval = mpi3mr_issue_and_process_mur(mrioc,
1443                     MPI3MR_RESET_FROM_BRINGUP);
1444                 ioc_state = mpi3mr_get_iocstate(mrioc);
1445                 if (retval)
1446                         ioc_err(mrioc,
1447                             "message unit reset failed with error %d current state %s\n",
1448                             retval, mpi3mr_iocstate_name(ioc_state));
1449         }
1450         if (ioc_state != MRIOC_STATE_RESET) {
1451                 if (ioc_state == MRIOC_STATE_FAULT) {
1452                         timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1453                         mpi3mr_print_fault_info(mrioc);
1454                         do {
1455                                 host_diagnostic =
1456                                         readl(&mrioc->sysif_regs->host_diagnostic);
1457                                 if (!(host_diagnostic &
1458                                       MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1459                                         break;
1460                                 if (!pci_device_is_present(mrioc->pdev)) {
1461                                         mrioc->unrecoverable = 1;
1462                                         ioc_err(mrioc, "controller is not present at the bringup\n");
1463                                         goto out_device_not_present;
1464                                 }
1465                                 msleep(100);
1466                         } while (--timeout);
1467                 }
1468                 mpi3mr_print_fault_info(mrioc);
1469                 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1470                 retval = mpi3mr_issue_reset(mrioc,
1471                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1472                     MPI3MR_RESET_FROM_BRINGUP);
1473                 if (retval) {
1474                         ioc_err(mrioc,
1475                             "soft reset failed with error %d\n", retval);
1476                         goto out_failed;
1477                 }
1478         }
1479         ioc_state = mpi3mr_get_iocstate(mrioc);
1480         if (ioc_state != MRIOC_STATE_RESET) {
1481                 ioc_err(mrioc,
1482                     "cannot bring controller to reset state, current state: %s\n",
1483                     mpi3mr_iocstate_name(ioc_state));
1484                 goto out_failed;
1485         }
1486         mpi3mr_clear_reset_history(mrioc);
1487         retval = mpi3mr_setup_admin_qpair(mrioc);
1488         if (retval) {
1489                 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1490                     retval);
1491                 goto out_failed;
1492         }
1493
1494         ioc_info(mrioc, "bringing controller to ready state\n");
1495         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1496         ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1497         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1498
1499         if (retry == 0)
1500                 start_time = jiffies;
1501
1502         timeout = mrioc->ready_timeout * 10;
1503         do {
1504                 ioc_state = mpi3mr_get_iocstate(mrioc);
1505                 if (ioc_state == MRIOC_STATE_READY) {
1506                         ioc_info(mrioc,
1507                             "successfully transitioned to %s state\n",
1508                             mpi3mr_iocstate_name(ioc_state));
1509                         return 0;
1510                 }
1511                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1512                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
1513                     (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
1514                         mpi3mr_print_fault_info(mrioc);
1515                         goto out_failed;
1516                 }
1517                 if (!pci_device_is_present(mrioc->pdev)) {
1518                         mrioc->unrecoverable = 1;
1519                         ioc_err(mrioc,
1520                             "controller is not present at the bringup\n");
1521                         retval = -1;
1522                         goto out_device_not_present;
1523                 }
1524                 msleep(100);
1525                 elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000;
1526         } while (elapsed_time_sec < mrioc->ready_timeout);
1527
1528 out_failed:
1529         elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000;
1530         if ((retry < 2) && (elapsed_time_sec < (mrioc->ready_timeout - 60))) {
1531                 retry++;
1532
1533                 ioc_warn(mrioc, "retrying to bring IOC ready, retry_count:%d\n"
1534                                 " elapsed time =%llu\n", retry, elapsed_time_sec);
1535
1536                 goto retry_bring_ioc_ready;
1537         }
1538         ioc_state = mpi3mr_get_iocstate(mrioc);
1539         ioc_err(mrioc,
1540             "failed to bring to ready state,  current state: %s\n",
1541             mpi3mr_iocstate_name(ioc_state));
1542 out_device_not_present:
1543         return retval;
1544 }
1545
1546 /**
1547  * mpi3mr_soft_reset_success - Check softreset is success or not
1548  * @ioc_status: IOC status register value
1549  * @ioc_config: IOC config register value
1550  *
1551  * Check whether the soft reset is successful or not based on
1552  * IOC status and IOC config register values.
1553  *
1554  * Return: True when the soft reset is success, false otherwise.
1555  */
1556 static inline bool
1557 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1558 {
1559         if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1560             (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1561                 return true;
1562         return false;
1563 }
1564
1565 /**
1566  * mpi3mr_diagfault_success - Check diag fault is success or not
1567  * @mrioc: Adapter reference
1568  * @ioc_status: IOC status register value
1569  *
1570  * Check whether the controller hit diag reset fault code.
1571  *
1572  * Return: True when there is diag fault, false otherwise.
1573  */
1574 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1575         u32 ioc_status)
1576 {
1577         u32 fault;
1578
1579         if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1580                 return false;
1581         fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1582         if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1583                 mpi3mr_print_fault_info(mrioc);
1584                 return true;
1585         }
1586         return false;
1587 }
1588
1589 /**
1590  * mpi3mr_set_diagsave - Set diag save bit for snapdump
1591  * @mrioc: Adapter reference
1592  *
1593  * Set diag save bit in IOC configuration register to enable
1594  * snapdump.
1595  *
1596  * Return: Nothing.
1597  */
1598 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1599 {
1600         u32 ioc_config;
1601
1602         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1603         ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1604         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1605 }
1606
1607 /**
1608  * mpi3mr_issue_reset - Issue reset to the controller
1609  * @mrioc: Adapter reference
1610  * @reset_type: Reset type
1611  * @reset_reason: Reset reason code
1612  *
1613  * Unlock the host diagnostic registers and write the specific
1614  * reset type to that, wait for reset acknowledgment from the
1615  * controller, if the reset is not successful retry for the
1616  * predefined number of times.
1617  *
1618  * Return: 0 on success, non-zero on failure.
1619  */
1620 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1621         u16 reset_reason)
1622 {
1623         int retval = -1;
1624         u8 unlock_retry_count = 0;
1625         u32 host_diagnostic, ioc_status, ioc_config, scratch_pad0;
1626         u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1627
1628         if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1629             (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1630                 return retval;
1631         if (mrioc->unrecoverable)
1632                 return retval;
1633         if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1634                 retval = 0;
1635                 return retval;
1636         }
1637
1638         ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1639             mpi3mr_reset_type_name(reset_type),
1640             mpi3mr_reset_rc_name(reset_reason), reset_reason);
1641
1642         mpi3mr_clear_reset_history(mrioc);
1643         do {
1644                 ioc_info(mrioc,
1645                     "Write magic sequence to unlock host diag register (retry=%d)\n",
1646                     ++unlock_retry_count);
1647                 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1648                         ioc_err(mrioc,
1649                             "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1650                             mpi3mr_reset_type_name(reset_type),
1651                             host_diagnostic);
1652                         mrioc->unrecoverable = 1;
1653                         return retval;
1654                 }
1655
1656                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1657                     &mrioc->sysif_regs->write_sequence);
1658                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1659                     &mrioc->sysif_regs->write_sequence);
1660                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1661                     &mrioc->sysif_regs->write_sequence);
1662                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1663                     &mrioc->sysif_regs->write_sequence);
1664                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1665                     &mrioc->sysif_regs->write_sequence);
1666                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1667                     &mrioc->sysif_regs->write_sequence);
1668                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1669                     &mrioc->sysif_regs->write_sequence);
1670                 usleep_range(1000, 1100);
1671                 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1672                 ioc_info(mrioc,
1673                     "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1674                     unlock_retry_count, host_diagnostic);
1675         } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1676
1677         scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
1678             MPI3MR_RESET_REASON_OSTYPE_SHIFT) | (mrioc->facts.ioc_num <<
1679             MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
1680         writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1681         writel(host_diagnostic | reset_type,
1682             &mrioc->sysif_regs->host_diagnostic);
1683         switch (reset_type) {
1684         case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1685                 do {
1686                         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1687                         ioc_config =
1688                             readl(&mrioc->sysif_regs->ioc_configuration);
1689                         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1690                             && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1691                             ) {
1692                                 mpi3mr_clear_reset_history(mrioc);
1693                                 retval = 0;
1694                                 break;
1695                         }
1696                         msleep(100);
1697                 } while (--timeout);
1698                 mpi3mr_print_fault_info(mrioc);
1699                 break;
1700         case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1701                 do {
1702                         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1703                         if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1704                                 retval = 0;
1705                                 break;
1706                         }
1707                         msleep(100);
1708                 } while (--timeout);
1709                 break;
1710         default:
1711                 break;
1712         }
1713
1714         writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1715             &mrioc->sysif_regs->write_sequence);
1716
1717         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1718         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1719         ioc_info(mrioc,
1720             "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1721             (!retval)?"successful":"failed", ioc_status,
1722             ioc_config);
1723         if (retval)
1724                 mrioc->unrecoverable = 1;
1725         return retval;
1726 }
1727
1728 /**
1729  * mpi3mr_admin_request_post - Post request to admin queue
1730  * @mrioc: Adapter reference
1731  * @admin_req: MPI3 request
1732  * @admin_req_sz: Request size
1733  * @ignore_reset: Ignore reset in process
1734  *
1735  * Post the MPI3 request into admin request queue and
1736  * inform the controller, if the queue is full return
1737  * appropriate error.
1738  *
1739  * Return: 0 on success, non-zero on failure.
1740  */
1741 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1742         u16 admin_req_sz, u8 ignore_reset)
1743 {
1744         u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1745         int retval = 0;
1746         unsigned long flags;
1747         u8 *areq_entry;
1748
1749         if (mrioc->unrecoverable) {
1750                 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1751                 return -EFAULT;
1752         }
1753
1754         spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1755         areq_pi = mrioc->admin_req_pi;
1756         areq_ci = mrioc->admin_req_ci;
1757         max_entries = mrioc->num_admin_req;
1758         if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1759             (areq_pi == (max_entries - 1)))) {
1760                 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1761                 retval = -EAGAIN;
1762                 goto out;
1763         }
1764         if (!ignore_reset && mrioc->reset_in_progress) {
1765                 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1766                 retval = -EAGAIN;
1767                 goto out;
1768         }
1769         if (mrioc->pci_err_recovery) {
1770                 ioc_err(mrioc, "admin request queue submission failed due to pci error recovery in progress\n");
1771                 retval = -EAGAIN;
1772                 goto out;
1773         }
1774
1775         areq_entry = (u8 *)mrioc->admin_req_base +
1776             (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1777         memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1778         memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1779
1780         if (++areq_pi == max_entries)
1781                 areq_pi = 0;
1782         mrioc->admin_req_pi = areq_pi;
1783
1784         writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1785
1786 out:
1787         spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1788
1789         return retval;
1790 }
1791
1792 /**
1793  * mpi3mr_free_op_req_q_segments - free request memory segments
1794  * @mrioc: Adapter instance reference
1795  * @q_idx: operational request queue index
1796  *
1797  * Free memory segments allocated for operational request queue
1798  *
1799  * Return: Nothing.
1800  */
1801 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1802 {
1803         u16 j;
1804         int size;
1805         struct segments *segments;
1806
1807         segments = mrioc->req_qinfo[q_idx].q_segments;
1808         if (!segments)
1809                 return;
1810
1811         if (mrioc->enable_segqueue) {
1812                 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1813                 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1814                         dma_free_coherent(&mrioc->pdev->dev,
1815                             MPI3MR_MAX_SEG_LIST_SIZE,
1816                             mrioc->req_qinfo[q_idx].q_segment_list,
1817                             mrioc->req_qinfo[q_idx].q_segment_list_dma);
1818                         mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1819                 }
1820         } else
1821                 size = mrioc->req_qinfo[q_idx].segment_qd *
1822                     mrioc->facts.op_req_sz;
1823
1824         for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1825                 if (!segments[j].segment)
1826                         continue;
1827                 dma_free_coherent(&mrioc->pdev->dev,
1828                     size, segments[j].segment, segments[j].segment_dma);
1829                 segments[j].segment = NULL;
1830         }
1831         kfree(mrioc->req_qinfo[q_idx].q_segments);
1832         mrioc->req_qinfo[q_idx].q_segments = NULL;
1833         mrioc->req_qinfo[q_idx].qid = 0;
1834 }
1835
1836 /**
1837  * mpi3mr_free_op_reply_q_segments - free reply memory segments
1838  * @mrioc: Adapter instance reference
1839  * @q_idx: operational reply queue index
1840  *
1841  * Free memory segments allocated for operational reply queue
1842  *
1843  * Return: Nothing.
1844  */
1845 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1846 {
1847         u16 j;
1848         int size;
1849         struct segments *segments;
1850
1851         segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1852         if (!segments)
1853                 return;
1854
1855         if (mrioc->enable_segqueue) {
1856                 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1857                 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1858                         dma_free_coherent(&mrioc->pdev->dev,
1859                             MPI3MR_MAX_SEG_LIST_SIZE,
1860                             mrioc->op_reply_qinfo[q_idx].q_segment_list,
1861                             mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1862                         mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1863                 }
1864         } else
1865                 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1866                     mrioc->op_reply_desc_sz;
1867
1868         for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1869                 if (!segments[j].segment)
1870                         continue;
1871                 dma_free_coherent(&mrioc->pdev->dev,
1872                     size, segments[j].segment, segments[j].segment_dma);
1873                 segments[j].segment = NULL;
1874         }
1875
1876         kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1877         mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1878         mrioc->op_reply_qinfo[q_idx].qid = 0;
1879 }
1880
1881 /**
1882  * mpi3mr_delete_op_reply_q - delete operational reply queue
1883  * @mrioc: Adapter instance reference
1884  * @qidx: operational reply queue index
1885  *
1886  * Delete operatinal reply queue by issuing MPI request
1887  * through admin queue.
1888  *
1889  * Return:  0 on success, non-zero on failure.
1890  */
1891 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1892 {
1893         struct mpi3_delete_reply_queue_request delq_req;
1894         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1895         int retval = 0;
1896         u16 reply_qid = 0, midx;
1897
1898         reply_qid = op_reply_q->qid;
1899
1900         midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1901
1902         if (!reply_qid) {
1903                 retval = -1;
1904                 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1905                 goto out;
1906         }
1907
1908         (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1909             mrioc->active_poll_qcount--;
1910
1911         memset(&delq_req, 0, sizeof(delq_req));
1912         mutex_lock(&mrioc->init_cmds.mutex);
1913         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1914                 retval = -1;
1915                 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1916                 mutex_unlock(&mrioc->init_cmds.mutex);
1917                 goto out;
1918         }
1919         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1920         mrioc->init_cmds.is_waiting = 1;
1921         mrioc->init_cmds.callback = NULL;
1922         delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1923         delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1924         delq_req.queue_id = cpu_to_le16(reply_qid);
1925
1926         init_completion(&mrioc->init_cmds.done);
1927         retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1928             1);
1929         if (retval) {
1930                 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1931                 goto out_unlock;
1932         }
1933         wait_for_completion_timeout(&mrioc->init_cmds.done,
1934             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1935         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1936                 ioc_err(mrioc, "delete reply queue timed out\n");
1937                 mpi3mr_check_rh_fault_ioc(mrioc,
1938                     MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1939                 retval = -1;
1940                 goto out_unlock;
1941         }
1942         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1943             != MPI3_IOCSTATUS_SUCCESS) {
1944                 ioc_err(mrioc,
1945                     "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1946                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1947                     mrioc->init_cmds.ioc_loginfo);
1948                 retval = -1;
1949                 goto out_unlock;
1950         }
1951         mrioc->intr_info[midx].op_reply_q = NULL;
1952
1953         mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1954 out_unlock:
1955         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1956         mutex_unlock(&mrioc->init_cmds.mutex);
1957 out:
1958
1959         return retval;
1960 }
1961
1962 /**
1963  * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1964  * @mrioc: Adapter instance reference
1965  * @qidx: request queue index
1966  *
1967  * Allocate segmented memory pools for operational reply
1968  * queue.
1969  *
1970  * Return: 0 on success, non-zero on failure.
1971  */
1972 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1973 {
1974         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1975         int i, size;
1976         u64 *q_segment_list_entry = NULL;
1977         struct segments *segments;
1978
1979         if (mrioc->enable_segqueue) {
1980                 op_reply_q->segment_qd =
1981                     MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1982
1983                 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1984
1985                 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1986                     MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1987                     GFP_KERNEL);
1988                 if (!op_reply_q->q_segment_list)
1989                         return -ENOMEM;
1990                 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1991         } else {
1992                 op_reply_q->segment_qd = op_reply_q->num_replies;
1993                 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1994         }
1995
1996         op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1997             op_reply_q->segment_qd);
1998
1999         op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
2000             sizeof(struct segments), GFP_KERNEL);
2001         if (!op_reply_q->q_segments)
2002                 return -ENOMEM;
2003
2004         segments = op_reply_q->q_segments;
2005         for (i = 0; i < op_reply_q->num_segments; i++) {
2006                 segments[i].segment =
2007                     dma_alloc_coherent(&mrioc->pdev->dev,
2008                     size, &segments[i].segment_dma, GFP_KERNEL);
2009                 if (!segments[i].segment)
2010                         return -ENOMEM;
2011                 if (mrioc->enable_segqueue)
2012                         q_segment_list_entry[i] =
2013                             (unsigned long)segments[i].segment_dma;
2014         }
2015
2016         return 0;
2017 }
2018
2019 /**
2020  * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
2021  * @mrioc: Adapter instance reference
2022  * @qidx: request queue index
2023  *
2024  * Allocate segmented memory pools for operational request
2025  * queue.
2026  *
2027  * Return: 0 on success, non-zero on failure.
2028  */
2029 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
2030 {
2031         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
2032         int i, size;
2033         u64 *q_segment_list_entry = NULL;
2034         struct segments *segments;
2035
2036         if (mrioc->enable_segqueue) {
2037                 op_req_q->segment_qd =
2038                     MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
2039
2040                 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
2041
2042                 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
2043                     MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
2044                     GFP_KERNEL);
2045                 if (!op_req_q->q_segment_list)
2046                         return -ENOMEM;
2047                 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
2048
2049         } else {
2050                 op_req_q->segment_qd = op_req_q->num_requests;
2051                 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
2052         }
2053
2054         op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
2055             op_req_q->segment_qd);
2056
2057         op_req_q->q_segments = kcalloc(op_req_q->num_segments,
2058             sizeof(struct segments), GFP_KERNEL);
2059         if (!op_req_q->q_segments)
2060                 return -ENOMEM;
2061
2062         segments = op_req_q->q_segments;
2063         for (i = 0; i < op_req_q->num_segments; i++) {
2064                 segments[i].segment =
2065                     dma_alloc_coherent(&mrioc->pdev->dev,
2066                     size, &segments[i].segment_dma, GFP_KERNEL);
2067                 if (!segments[i].segment)
2068                         return -ENOMEM;
2069                 if (mrioc->enable_segqueue)
2070                         q_segment_list_entry[i] =
2071                             (unsigned long)segments[i].segment_dma;
2072         }
2073
2074         return 0;
2075 }
2076
2077 /**
2078  * mpi3mr_create_op_reply_q - create operational reply queue
2079  * @mrioc: Adapter instance reference
2080  * @qidx: operational reply queue index
2081  *
2082  * Create operatinal reply queue by issuing MPI request
2083  * through admin queue.
2084  *
2085  * Return:  0 on success, non-zero on failure.
2086  */
2087 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
2088 {
2089         struct mpi3_create_reply_queue_request create_req;
2090         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
2091         int retval = 0;
2092         u16 reply_qid = 0, midx;
2093
2094         reply_qid = op_reply_q->qid;
2095
2096         midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
2097
2098         if (reply_qid) {
2099                 retval = -1;
2100                 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
2101                     reply_qid);
2102
2103                 return retval;
2104         }
2105
2106         reply_qid = qidx + 1;
2107         op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
2108         if ((mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) &&
2109                 !mrioc->pdev->revision)
2110                 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
2111         op_reply_q->ci = 0;
2112         op_reply_q->ephase = 1;
2113         atomic_set(&op_reply_q->pend_ios, 0);
2114         atomic_set(&op_reply_q->in_use, 0);
2115         op_reply_q->enable_irq_poll = false;
2116
2117         if (!op_reply_q->q_segments) {
2118                 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
2119                 if (retval) {
2120                         mpi3mr_free_op_reply_q_segments(mrioc, qidx);
2121                         goto out;
2122                 }
2123         }
2124
2125         memset(&create_req, 0, sizeof(create_req));
2126         mutex_lock(&mrioc->init_cmds.mutex);
2127         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2128                 retval = -1;
2129                 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
2130                 goto out_unlock;
2131         }
2132         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2133         mrioc->init_cmds.is_waiting = 1;
2134         mrioc->init_cmds.callback = NULL;
2135         create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2136         create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
2137         create_req.queue_id = cpu_to_le16(reply_qid);
2138
2139         if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
2140                 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
2141         else
2142                 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
2143
2144         if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
2145                 create_req.flags =
2146                         MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
2147                 create_req.msix_index =
2148                         cpu_to_le16(mrioc->intr_info[midx].msix_index);
2149         } else {
2150                 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
2151                 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
2152                         reply_qid, midx);
2153                 if (!mrioc->active_poll_qcount)
2154                         disable_irq_nosync(pci_irq_vector(mrioc->pdev,
2155                             mrioc->intr_info_count - 1));
2156         }
2157
2158         if (mrioc->enable_segqueue) {
2159                 create_req.flags |=
2160                     MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2161                 create_req.base_address = cpu_to_le64(
2162                     op_reply_q->q_segment_list_dma);
2163         } else
2164                 create_req.base_address = cpu_to_le64(
2165                     op_reply_q->q_segments[0].segment_dma);
2166
2167         create_req.size = cpu_to_le16(op_reply_q->num_replies);
2168
2169         init_completion(&mrioc->init_cmds.done);
2170         retval = mpi3mr_admin_request_post(mrioc, &create_req,
2171             sizeof(create_req), 1);
2172         if (retval) {
2173                 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
2174                 goto out_unlock;
2175         }
2176         wait_for_completion_timeout(&mrioc->init_cmds.done,
2177             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2178         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2179                 ioc_err(mrioc, "create reply queue timed out\n");
2180                 mpi3mr_check_rh_fault_ioc(mrioc,
2181                     MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
2182                 retval = -1;
2183                 goto out_unlock;
2184         }
2185         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2186             != MPI3_IOCSTATUS_SUCCESS) {
2187                 ioc_err(mrioc,
2188                     "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2189                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2190                     mrioc->init_cmds.ioc_loginfo);
2191                 retval = -1;
2192                 goto out_unlock;
2193         }
2194         op_reply_q->qid = reply_qid;
2195         if (midx < mrioc->intr_info_count)
2196                 mrioc->intr_info[midx].op_reply_q = op_reply_q;
2197
2198         (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
2199             mrioc->active_poll_qcount++;
2200
2201 out_unlock:
2202         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2203         mutex_unlock(&mrioc->init_cmds.mutex);
2204 out:
2205
2206         return retval;
2207 }
2208
2209 /**
2210  * mpi3mr_create_op_req_q - create operational request queue
2211  * @mrioc: Adapter instance reference
2212  * @idx: operational request queue index
2213  * @reply_qid: Reply queue ID
2214  *
2215  * Create operatinal request queue by issuing MPI request
2216  * through admin queue.
2217  *
2218  * Return:  0 on success, non-zero on failure.
2219  */
2220 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
2221         u16 reply_qid)
2222 {
2223         struct mpi3_create_request_queue_request create_req;
2224         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2225         int retval = 0;
2226         u16 req_qid = 0;
2227
2228         req_qid = op_req_q->qid;
2229
2230         if (req_qid) {
2231                 retval = -1;
2232                 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2233                     req_qid);
2234
2235                 return retval;
2236         }
2237         req_qid = idx + 1;
2238
2239         op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2240         op_req_q->ci = 0;
2241         op_req_q->pi = 0;
2242         op_req_q->reply_qid = reply_qid;
2243         spin_lock_init(&op_req_q->q_lock);
2244
2245         if (!op_req_q->q_segments) {
2246                 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2247                 if (retval) {
2248                         mpi3mr_free_op_req_q_segments(mrioc, idx);
2249                         goto out;
2250                 }
2251         }
2252
2253         memset(&create_req, 0, sizeof(create_req));
2254         mutex_lock(&mrioc->init_cmds.mutex);
2255         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2256                 retval = -1;
2257                 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2258                 goto out_unlock;
2259         }
2260         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2261         mrioc->init_cmds.is_waiting = 1;
2262         mrioc->init_cmds.callback = NULL;
2263         create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2264         create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2265         create_req.queue_id = cpu_to_le16(req_qid);
2266         if (mrioc->enable_segqueue) {
2267                 create_req.flags =
2268                     MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2269                 create_req.base_address = cpu_to_le64(
2270                     op_req_q->q_segment_list_dma);
2271         } else
2272                 create_req.base_address = cpu_to_le64(
2273                     op_req_q->q_segments[0].segment_dma);
2274         create_req.reply_queue_id = cpu_to_le16(reply_qid);
2275         create_req.size = cpu_to_le16(op_req_q->num_requests);
2276
2277         init_completion(&mrioc->init_cmds.done);
2278         retval = mpi3mr_admin_request_post(mrioc, &create_req,
2279             sizeof(create_req), 1);
2280         if (retval) {
2281                 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2282                 goto out_unlock;
2283         }
2284         wait_for_completion_timeout(&mrioc->init_cmds.done,
2285             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2286         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2287                 ioc_err(mrioc, "create request queue timed out\n");
2288                 mpi3mr_check_rh_fault_ioc(mrioc,
2289                     MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2290                 retval = -1;
2291                 goto out_unlock;
2292         }
2293         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2294             != MPI3_IOCSTATUS_SUCCESS) {
2295                 ioc_err(mrioc,
2296                     "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2297                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2298                     mrioc->init_cmds.ioc_loginfo);
2299                 retval = -1;
2300                 goto out_unlock;
2301         }
2302         op_req_q->qid = req_qid;
2303
2304 out_unlock:
2305         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2306         mutex_unlock(&mrioc->init_cmds.mutex);
2307 out:
2308
2309         return retval;
2310 }
2311
2312 /**
2313  * mpi3mr_create_op_queues - create operational queue pairs
2314  * @mrioc: Adapter instance reference
2315  *
2316  * Allocate memory for operational queue meta data and call
2317  * create request and reply queue functions.
2318  *
2319  * Return: 0 on success, non-zero on failures.
2320  */
2321 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2322 {
2323         int retval = 0;
2324         u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2325
2326         num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2327             mrioc->facts.max_op_req_q);
2328
2329         msix_count_op_q =
2330             mrioc->intr_info_count - mrioc->op_reply_q_offset;
2331         if (!mrioc->num_queues)
2332                 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2333         /*
2334          * During reset set the num_queues to the number of queues
2335          * that was set before the reset.
2336          */
2337         num_queues = mrioc->num_op_reply_q ?
2338             mrioc->num_op_reply_q : mrioc->num_queues;
2339         ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2340             num_queues);
2341
2342         if (!mrioc->req_qinfo) {
2343                 mrioc->req_qinfo = kcalloc(num_queues,
2344                     sizeof(struct op_req_qinfo), GFP_KERNEL);
2345                 if (!mrioc->req_qinfo) {
2346                         retval = -1;
2347                         goto out_failed;
2348                 }
2349
2350                 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2351                     num_queues, GFP_KERNEL);
2352                 if (!mrioc->op_reply_qinfo) {
2353                         retval = -1;
2354                         goto out_failed;
2355                 }
2356         }
2357
2358         if (mrioc->enable_segqueue)
2359                 ioc_info(mrioc,
2360                     "allocating operational queues through segmented queues\n");
2361
2362         for (i = 0; i < num_queues; i++) {
2363                 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2364                         ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2365                         break;
2366                 }
2367                 if (mpi3mr_create_op_req_q(mrioc, i,
2368                     mrioc->op_reply_qinfo[i].qid)) {
2369                         ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2370                         mpi3mr_delete_op_reply_q(mrioc, i);
2371                         break;
2372                 }
2373         }
2374
2375         if (i == 0) {
2376                 /* Not even one queue is created successfully*/
2377                 retval = -1;
2378                 goto out_failed;
2379         }
2380         mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2381         ioc_info(mrioc,
2382             "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2383             mrioc->num_op_reply_q, mrioc->default_qcount,
2384             mrioc->active_poll_qcount);
2385
2386         return retval;
2387 out_failed:
2388         kfree(mrioc->req_qinfo);
2389         mrioc->req_qinfo = NULL;
2390
2391         kfree(mrioc->op_reply_qinfo);
2392         mrioc->op_reply_qinfo = NULL;
2393
2394         return retval;
2395 }
2396
2397 /**
2398  * mpi3mr_op_request_post - Post request to operational queue
2399  * @mrioc: Adapter reference
2400  * @op_req_q: Operational request queue info
2401  * @req: MPI3 request
2402  *
2403  * Post the MPI3 request into operational request queue and
2404  * inform the controller, if the queue is full return
2405  * appropriate error.
2406  *
2407  * Return: 0 on success, non-zero on failure.
2408  */
2409 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2410         struct op_req_qinfo *op_req_q, u8 *req)
2411 {
2412         u16 pi = 0, max_entries, reply_qidx = 0, midx;
2413         int retval = 0;
2414         unsigned long flags;
2415         u8 *req_entry;
2416         void *segment_base_addr;
2417         u16 req_sz = mrioc->facts.op_req_sz;
2418         struct segments *segments = op_req_q->q_segments;
2419
2420         reply_qidx = op_req_q->reply_qid - 1;
2421
2422         if (mrioc->unrecoverable)
2423                 return -EFAULT;
2424
2425         spin_lock_irqsave(&op_req_q->q_lock, flags);
2426         pi = op_req_q->pi;
2427         max_entries = op_req_q->num_requests;
2428
2429         if (mpi3mr_check_req_qfull(op_req_q)) {
2430                 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2431                     reply_qidx, mrioc->op_reply_q_offset);
2432                 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2433
2434                 if (mpi3mr_check_req_qfull(op_req_q)) {
2435                         retval = -EAGAIN;
2436                         goto out;
2437                 }
2438         }
2439
2440         if (mrioc->reset_in_progress) {
2441                 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2442                 retval = -EAGAIN;
2443                 goto out;
2444         }
2445         if (mrioc->pci_err_recovery) {
2446                 ioc_err(mrioc, "operational request queue submission failed due to pci error recovery in progress\n");
2447                 retval = -EAGAIN;
2448                 goto out;
2449         }
2450
2451         segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2452         req_entry = (u8 *)segment_base_addr +
2453             ((pi % op_req_q->segment_qd) * req_sz);
2454
2455         memset(req_entry, 0, req_sz);
2456         memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2457
2458         if (++pi == max_entries)
2459                 pi = 0;
2460         op_req_q->pi = pi;
2461
2462 #ifndef CONFIG_PREEMPT_RT
2463         if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2464             > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2465                 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2466 #else
2467         atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2468 #endif
2469
2470         writel(op_req_q->pi,
2471             &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2472
2473 out:
2474         spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2475         return retval;
2476 }
2477
2478 /**
2479  * mpi3mr_check_rh_fault_ioc - check reset history and fault
2480  * controller
2481  * @mrioc: Adapter instance reference
2482  * @reason_code: reason code for the fault.
2483  *
2484  * This routine will save snapdump and fault the controller with
2485  * the given reason code if it is not already in the fault or
2486  * not asynchronosuly reset. This will be used to handle
2487  * initilaization time faults/resets/timeout as in those cases
2488  * immediate soft reset invocation is not required.
2489  *
2490  * Return:  None.
2491  */
2492 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2493 {
2494         u32 ioc_status, host_diagnostic, timeout;
2495         union mpi3mr_trigger_data trigger_data;
2496
2497         if (mrioc->unrecoverable) {
2498                 ioc_err(mrioc, "controller is unrecoverable\n");
2499                 return;
2500         }
2501
2502         if (!pci_device_is_present(mrioc->pdev)) {
2503                 mrioc->unrecoverable = 1;
2504                 ioc_err(mrioc, "controller is not present\n");
2505                 return;
2506         }
2507         memset(&trigger_data, 0, sizeof(trigger_data));
2508         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2509
2510         if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2511                 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2512                     MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0);
2513                 return;
2514         } else if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
2515                 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
2516                       MPI3_SYSIF_FAULT_CODE_MASK);
2517
2518                 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2519                     MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
2520                 mpi3mr_print_fault_info(mrioc);
2521                 return;
2522         }
2523
2524         mpi3mr_set_diagsave(mrioc);
2525         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2526             reason_code);
2527         trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
2528                       MPI3_SYSIF_FAULT_CODE_MASK);
2529         mpi3mr_set_trigger_data_in_all_hdb(mrioc, MPI3MR_HDB_TRIGGER_TYPE_FAULT,
2530             &trigger_data, 0);
2531         timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2532         do {
2533                 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2534                 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2535                         break;
2536                 msleep(100);
2537         } while (--timeout);
2538 }
2539
2540 /**
2541  * mpi3mr_sync_timestamp - Issue time stamp sync request
2542  * @mrioc: Adapter reference
2543  *
2544  * Issue IO unit control MPI request to synchornize firmware
2545  * timestamp with host time.
2546  *
2547  * Return: 0 on success, non-zero on failure.
2548  */
2549 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2550 {
2551         ktime_t current_time;
2552         struct mpi3_iounit_control_request iou_ctrl;
2553         int retval = 0;
2554
2555         memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2556         mutex_lock(&mrioc->init_cmds.mutex);
2557         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2558                 retval = -1;
2559                 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2560                 mutex_unlock(&mrioc->init_cmds.mutex);
2561                 goto out;
2562         }
2563         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2564         mrioc->init_cmds.is_waiting = 1;
2565         mrioc->init_cmds.callback = NULL;
2566         iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2567         iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2568         iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2569         current_time = ktime_get_real();
2570         iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2571
2572         init_completion(&mrioc->init_cmds.done);
2573         retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2574             sizeof(iou_ctrl), 0);
2575         if (retval) {
2576                 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2577                 goto out_unlock;
2578         }
2579
2580         wait_for_completion_timeout(&mrioc->init_cmds.done,
2581             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2582         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2583                 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2584                 mrioc->init_cmds.is_waiting = 0;
2585                 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2586                         mpi3mr_check_rh_fault_ioc(mrioc,
2587                             MPI3MR_RESET_FROM_TSU_TIMEOUT);
2588                 retval = -1;
2589                 goto out_unlock;
2590         }
2591         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2592             != MPI3_IOCSTATUS_SUCCESS) {
2593                 ioc_err(mrioc,
2594                     "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2595                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2596                     mrioc->init_cmds.ioc_loginfo);
2597                 retval = -1;
2598                 goto out_unlock;
2599         }
2600
2601 out_unlock:
2602         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2603         mutex_unlock(&mrioc->init_cmds.mutex);
2604
2605 out:
2606         return retval;
2607 }
2608
2609 /**
2610  * mpi3mr_print_pkg_ver - display controller fw package version
2611  * @mrioc: Adapter reference
2612  *
2613  * Retrieve firmware package version from the component image
2614  * header of the controller flash and display it.
2615  *
2616  * Return: 0 on success and non-zero on failure.
2617  */
2618 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2619 {
2620         struct mpi3_ci_upload_request ci_upload;
2621         int retval = -1;
2622         void *data = NULL;
2623         dma_addr_t data_dma;
2624         struct mpi3_ci_manifest_mpi *manifest;
2625         u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2626         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2627
2628         data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2629             GFP_KERNEL);
2630         if (!data)
2631                 return -ENOMEM;
2632
2633         memset(&ci_upload, 0, sizeof(ci_upload));
2634         mutex_lock(&mrioc->init_cmds.mutex);
2635         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2636                 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2637                 mutex_unlock(&mrioc->init_cmds.mutex);
2638                 goto out;
2639         }
2640         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2641         mrioc->init_cmds.is_waiting = 1;
2642         mrioc->init_cmds.callback = NULL;
2643         ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2644         ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2645         ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2646         ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2647         ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2648         ci_upload.segment_size = cpu_to_le32(data_len);
2649
2650         mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2651             data_dma);
2652         init_completion(&mrioc->init_cmds.done);
2653         retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2654             sizeof(ci_upload), 1);
2655         if (retval) {
2656                 ioc_err(mrioc, "posting get package version failed\n");
2657                 goto out_unlock;
2658         }
2659         wait_for_completion_timeout(&mrioc->init_cmds.done,
2660             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2661         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2662                 ioc_err(mrioc, "get package version timed out\n");
2663                 mpi3mr_check_rh_fault_ioc(mrioc,
2664                     MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2665                 retval = -1;
2666                 goto out_unlock;
2667         }
2668         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2669             == MPI3_IOCSTATUS_SUCCESS) {
2670                 manifest = (struct mpi3_ci_manifest_mpi *) data;
2671                 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2672                         ioc_info(mrioc,
2673                             "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2674                             manifest->package_version.gen_major,
2675                             manifest->package_version.gen_minor,
2676                             manifest->package_version.phase_major,
2677                             manifest->package_version.phase_minor,
2678                             manifest->package_version.customer_id,
2679                             manifest->package_version.build_num);
2680                 }
2681         }
2682         retval = 0;
2683 out_unlock:
2684         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2685         mutex_unlock(&mrioc->init_cmds.mutex);
2686
2687 out:
2688         if (data)
2689                 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2690                     data_dma);
2691         return retval;
2692 }
2693
2694 /**
2695  * mpi3mr_watchdog_work - watchdog thread to monitor faults
2696  * @work: work struct
2697  *
2698  * Watch dog work periodically executed (1 second interval) to
2699  * monitor firmware fault and to issue periodic timer sync to
2700  * the firmware.
2701  *
2702  * Return: Nothing.
2703  */
2704 static void mpi3mr_watchdog_work(struct work_struct *work)
2705 {
2706         struct mpi3mr_ioc *mrioc =
2707             container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2708         unsigned long flags;
2709         enum mpi3mr_iocstate ioc_state;
2710         u32 host_diagnostic, ioc_status;
2711         union mpi3mr_trigger_data trigger_data;
2712         u16 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2713
2714         if (mrioc->reset_in_progress || mrioc->pci_err_recovery)
2715                 return;
2716
2717         if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2718                 ioc_err(mrioc, "watchdog could not detect the controller\n");
2719                 mrioc->unrecoverable = 1;
2720         }
2721
2722         if (mrioc->unrecoverable) {
2723                 ioc_err(mrioc,
2724                     "flush pending commands for unrecoverable controller\n");
2725                 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2726                 return;
2727         }
2728
2729         if (mrioc->ts_update_counter++ >= mrioc->ts_update_interval) {
2730                 mrioc->ts_update_counter = 0;
2731                 mpi3mr_sync_timestamp(mrioc);
2732         }
2733
2734         if ((mrioc->prepare_for_reset) &&
2735             ((mrioc->prepare_for_reset_timeout_counter++) >=
2736              MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2737                 mpi3mr_soft_reset_handler(mrioc,
2738                     MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2739                 return;
2740         }
2741
2742         memset(&trigger_data, 0, sizeof(trigger_data));
2743         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2744         if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2745                 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2746                     MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0);
2747                 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2748                 return;
2749         }
2750
2751         /*Check for fault state every one second and issue Soft reset*/
2752         ioc_state = mpi3mr_get_iocstate(mrioc);
2753         if (ioc_state != MRIOC_STATE_FAULT)
2754                 goto schedule_work;
2755
2756         trigger_data.fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2757         mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2758             MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
2759         host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2760         if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2761                 if (!mrioc->diagsave_timeout) {
2762                         mpi3mr_print_fault_info(mrioc);
2763                         ioc_warn(mrioc, "diag save in progress\n");
2764                 }
2765                 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2766                         goto schedule_work;
2767         }
2768
2769         mpi3mr_print_fault_info(mrioc);
2770         mrioc->diagsave_timeout = 0;
2771
2772         if (!mpi3mr_is_fault_recoverable(mrioc)) {
2773                 mrioc->unrecoverable = 1;
2774                 goto schedule_work;
2775         }
2776
2777         switch (trigger_data.fault) {
2778         case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2779         case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2780                 ioc_warn(mrioc,
2781                     "controller requires system power cycle, marking controller as unrecoverable\n");
2782                 mrioc->unrecoverable = 1;
2783                 goto schedule_work;
2784         case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2785                 goto schedule_work;
2786         case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2787                 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2788                 break;
2789         default:
2790                 break;
2791         }
2792         mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2793         return;
2794
2795 schedule_work:
2796         spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2797         if (mrioc->watchdog_work_q)
2798                 queue_delayed_work(mrioc->watchdog_work_q,
2799                     &mrioc->watchdog_work,
2800                     msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2801         spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2802         return;
2803 }
2804
2805 /**
2806  * mpi3mr_start_watchdog - Start watchdog
2807  * @mrioc: Adapter instance reference
2808  *
2809  * Create and start the watchdog thread to monitor controller
2810  * faults.
2811  *
2812  * Return: Nothing.
2813  */
2814 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2815 {
2816         if (mrioc->watchdog_work_q)
2817                 return;
2818
2819         INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2820         snprintf(mrioc->watchdog_work_q_name,
2821             sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2822             mrioc->id);
2823         mrioc->watchdog_work_q = alloc_ordered_workqueue(
2824                 "%s", WQ_MEM_RECLAIM, mrioc->watchdog_work_q_name);
2825         if (!mrioc->watchdog_work_q) {
2826                 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2827                 return;
2828         }
2829
2830         if (mrioc->watchdog_work_q)
2831                 queue_delayed_work(mrioc->watchdog_work_q,
2832                     &mrioc->watchdog_work,
2833                     msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2834 }
2835
2836 /**
2837  * mpi3mr_stop_watchdog - Stop watchdog
2838  * @mrioc: Adapter instance reference
2839  *
2840  * Stop the watchdog thread created to monitor controller
2841  * faults.
2842  *
2843  * Return: Nothing.
2844  */
2845 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2846 {
2847         unsigned long flags;
2848         struct workqueue_struct *wq;
2849
2850         spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2851         wq = mrioc->watchdog_work_q;
2852         mrioc->watchdog_work_q = NULL;
2853         spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2854         if (wq) {
2855                 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2856                         flush_workqueue(wq);
2857                 destroy_workqueue(wq);
2858         }
2859 }
2860
2861 /**
2862  * mpi3mr_setup_admin_qpair - Setup admin queue pair
2863  * @mrioc: Adapter instance reference
2864  *
2865  * Allocate memory for admin queue pair if required and register
2866  * the admin queue with the controller.
2867  *
2868  * Return: 0 on success, non-zero on failures.
2869  */
2870 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2871 {
2872         int retval = 0;
2873         u32 num_admin_entries = 0;
2874
2875         mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2876         mrioc->num_admin_req = mrioc->admin_req_q_sz /
2877             MPI3MR_ADMIN_REQ_FRAME_SZ;
2878         mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2879
2880         mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2881         mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2882             MPI3MR_ADMIN_REPLY_FRAME_SZ;
2883         mrioc->admin_reply_ci = 0;
2884         mrioc->admin_reply_ephase = 1;
2885         atomic_set(&mrioc->admin_reply_q_in_use, 0);
2886
2887         if (!mrioc->admin_req_base) {
2888                 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2889                     mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2890
2891                 if (!mrioc->admin_req_base) {
2892                         retval = -1;
2893                         goto out_failed;
2894                 }
2895
2896                 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2897                     mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2898                     GFP_KERNEL);
2899
2900                 if (!mrioc->admin_reply_base) {
2901                         retval = -1;
2902                         goto out_failed;
2903                 }
2904         }
2905
2906         num_admin_entries = (mrioc->num_admin_replies << 16) |
2907             (mrioc->num_admin_req);
2908         writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2909         mpi3mr_writeq(mrioc->admin_req_dma,
2910             &mrioc->sysif_regs->admin_request_queue_address);
2911         mpi3mr_writeq(mrioc->admin_reply_dma,
2912             &mrioc->sysif_regs->admin_reply_queue_address);
2913         writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2914         writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2915         return retval;
2916
2917 out_failed:
2918
2919         if (mrioc->admin_reply_base) {
2920                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2921                     mrioc->admin_reply_base, mrioc->admin_reply_dma);
2922                 mrioc->admin_reply_base = NULL;
2923         }
2924         if (mrioc->admin_req_base) {
2925                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2926                     mrioc->admin_req_base, mrioc->admin_req_dma);
2927                 mrioc->admin_req_base = NULL;
2928         }
2929         return retval;
2930 }
2931
2932 /**
2933  * mpi3mr_issue_iocfacts - Send IOC Facts
2934  * @mrioc: Adapter instance reference
2935  * @facts_data: Cached IOC facts data
2936  *
2937  * Issue IOC Facts MPI request through admin queue and wait for
2938  * the completion of it or time out.
2939  *
2940  * Return: 0 on success, non-zero on failures.
2941  */
2942 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2943         struct mpi3_ioc_facts_data *facts_data)
2944 {
2945         struct mpi3_ioc_facts_request iocfacts_req;
2946         void *data = NULL;
2947         dma_addr_t data_dma;
2948         u32 data_len = sizeof(*facts_data);
2949         int retval = 0;
2950         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2951
2952         data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2953             GFP_KERNEL);
2954
2955         if (!data) {
2956                 retval = -1;
2957                 goto out;
2958         }
2959
2960         memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2961         mutex_lock(&mrioc->init_cmds.mutex);
2962         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2963                 retval = -1;
2964                 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2965                 mutex_unlock(&mrioc->init_cmds.mutex);
2966                 goto out;
2967         }
2968         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2969         mrioc->init_cmds.is_waiting = 1;
2970         mrioc->init_cmds.callback = NULL;
2971         iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2972         iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2973
2974         mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2975             data_dma);
2976
2977         init_completion(&mrioc->init_cmds.done);
2978         retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2979             sizeof(iocfacts_req), 1);
2980         if (retval) {
2981                 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2982                 goto out_unlock;
2983         }
2984         wait_for_completion_timeout(&mrioc->init_cmds.done,
2985             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2986         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2987                 ioc_err(mrioc, "ioc_facts timed out\n");
2988                 mpi3mr_check_rh_fault_ioc(mrioc,
2989                     MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2990                 retval = -1;
2991                 goto out_unlock;
2992         }
2993         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2994             != MPI3_IOCSTATUS_SUCCESS) {
2995                 ioc_err(mrioc,
2996                     "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2997                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2998                     mrioc->init_cmds.ioc_loginfo);
2999                 retval = -1;
3000                 goto out_unlock;
3001         }
3002         memcpy(facts_data, (u8 *)data, data_len);
3003         mpi3mr_process_factsdata(mrioc, facts_data);
3004 out_unlock:
3005         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3006         mutex_unlock(&mrioc->init_cmds.mutex);
3007
3008 out:
3009         if (data)
3010                 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
3011
3012         return retval;
3013 }
3014
3015 /**
3016  * mpi3mr_check_reset_dma_mask - Process IOC facts data
3017  * @mrioc: Adapter instance reference
3018  *
3019  * Check whether the new DMA mask requested through IOCFacts by
3020  * firmware needs to be set, if so set it .
3021  *
3022  * Return: 0 on success, non-zero on failure.
3023  */
3024 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
3025 {
3026         struct pci_dev *pdev = mrioc->pdev;
3027         int r;
3028         u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
3029
3030         if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
3031                 return 0;
3032
3033         ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
3034             mrioc->dma_mask, facts_dma_mask);
3035
3036         r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
3037         if (r) {
3038                 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
3039                     facts_dma_mask, r);
3040                 return r;
3041         }
3042         mrioc->dma_mask = facts_dma_mask;
3043         return r;
3044 }
3045
3046 /**
3047  * mpi3mr_process_factsdata - Process IOC facts data
3048  * @mrioc: Adapter instance reference
3049  * @facts_data: Cached IOC facts data
3050  *
3051  * Convert IOC facts data into cpu endianness and cache it in
3052  * the driver .
3053  *
3054  * Return: Nothing.
3055  */
3056 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
3057         struct mpi3_ioc_facts_data *facts_data)
3058 {
3059         u32 ioc_config, req_sz, facts_flags;
3060
3061         if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
3062             (sizeof(*facts_data) / 4)) {
3063                 ioc_warn(mrioc,
3064                     "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
3065                     sizeof(*facts_data),
3066                     le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
3067         }
3068
3069         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
3070         req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
3071             MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
3072         if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
3073                 ioc_err(mrioc,
3074                     "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
3075                     req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
3076         }
3077
3078         memset(&mrioc->facts, 0, sizeof(mrioc->facts));
3079
3080         facts_flags = le32_to_cpu(facts_data->flags);
3081         mrioc->facts.op_req_sz = req_sz;
3082         mrioc->op_reply_desc_sz = 1 << ((ioc_config &
3083             MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
3084             MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
3085
3086         mrioc->facts.ioc_num = facts_data->ioc_number;
3087         mrioc->facts.who_init = facts_data->who_init;
3088         mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
3089         mrioc->facts.personality = (facts_flags &
3090             MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
3091         mrioc->facts.dma_mask = (facts_flags &
3092             MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
3093             MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
3094         mrioc->facts.protocol_flags = facts_data->protocol_flags;
3095         mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
3096         mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
3097         mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
3098         mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
3099         mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
3100         mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
3101         mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
3102         mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
3103         mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
3104         mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
3105         mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
3106         mrioc->facts.max_pcie_switches =
3107             le16_to_cpu(facts_data->max_pcie_switches);
3108         mrioc->facts.max_sasexpanders =
3109             le16_to_cpu(facts_data->max_sas_expanders);
3110         mrioc->facts.max_data_length = le16_to_cpu(facts_data->max_data_length);
3111         mrioc->facts.max_sasinitiators =
3112             le16_to_cpu(facts_data->max_sas_initiators);
3113         mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
3114         mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
3115         mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
3116         mrioc->facts.max_op_req_q =
3117             le16_to_cpu(facts_data->max_operational_request_queues);
3118         mrioc->facts.max_op_reply_q =
3119             le16_to_cpu(facts_data->max_operational_reply_queues);
3120         mrioc->facts.ioc_capabilities =
3121             le32_to_cpu(facts_data->ioc_capabilities);
3122         mrioc->facts.fw_ver.build_num =
3123             le16_to_cpu(facts_data->fw_version.build_num);
3124         mrioc->facts.fw_ver.cust_id =
3125             le16_to_cpu(facts_data->fw_version.customer_id);
3126         mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
3127         mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
3128         mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
3129         mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
3130         mrioc->msix_count = min_t(int, mrioc->msix_count,
3131             mrioc->facts.max_msix_vectors);
3132         mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
3133         mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
3134         mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
3135         mrioc->facts.shutdown_timeout =
3136             le16_to_cpu(facts_data->shutdown_timeout);
3137         mrioc->facts.diag_trace_sz =
3138             le32_to_cpu(facts_data->diag_trace_size);
3139         mrioc->facts.diag_fw_sz =
3140             le32_to_cpu(facts_data->diag_fw_size);
3141         mrioc->facts.diag_drvr_sz = le32_to_cpu(facts_data->diag_driver_size);
3142         mrioc->facts.max_dev_per_tg =
3143             facts_data->max_devices_per_throttle_group;
3144         mrioc->facts.io_throttle_data_length =
3145             le16_to_cpu(facts_data->io_throttle_data_length);
3146         mrioc->facts.max_io_throttle_group =
3147             le16_to_cpu(facts_data->max_io_throttle_group);
3148         mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
3149         mrioc->facts.io_throttle_high =
3150             le16_to_cpu(facts_data->io_throttle_high);
3151
3152         if (mrioc->facts.max_data_length ==
3153             MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED)
3154                 mrioc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE;
3155         else
3156                 mrioc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K;
3157         /* Store in 512b block count */
3158         if (mrioc->facts.io_throttle_data_length)
3159                 mrioc->io_throttle_data_length =
3160                     (mrioc->facts.io_throttle_data_length * 2 * 4);
3161         else
3162                 /* set the length to 1MB + 1K to disable throttle */
3163                 mrioc->io_throttle_data_length = (mrioc->facts.max_data_length / 512) + 2;
3164
3165         mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
3166         mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
3167
3168         ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
3169             mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
3170             mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
3171         ioc_info(mrioc,
3172             "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
3173             mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
3174             mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
3175         ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
3176             mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
3177             mrioc->facts.sge_mod_shift);
3178         ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x max_data_len (%d)\n",
3179             mrioc->facts.dma_mask, (facts_flags &
3180             MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK), mrioc->facts.max_data_length);
3181         ioc_info(mrioc,
3182             "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
3183             mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
3184         ioc_info(mrioc,
3185            "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
3186            mrioc->facts.io_throttle_data_length * 4,
3187            mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
3188 }
3189
3190 /**
3191  * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
3192  * @mrioc: Adapter instance reference
3193  *
3194  * Allocate and initialize the reply free buffers, sense
3195  * buffers, reply free queue and sense buffer queue.
3196  *
3197  * Return: 0 on success, non-zero on failures.
3198  */
3199 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
3200 {
3201         int retval = 0;
3202         u32 sz, i;
3203
3204         if (mrioc->init_cmds.reply)
3205                 return retval;
3206
3207         mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3208         if (!mrioc->init_cmds.reply)
3209                 goto out_failed;
3210
3211         mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3212         if (!mrioc->bsg_cmds.reply)
3213                 goto out_failed;
3214
3215         mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3216         if (!mrioc->transport_cmds.reply)
3217                 goto out_failed;
3218
3219         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
3220                 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
3221                     GFP_KERNEL);
3222                 if (!mrioc->dev_rmhs_cmds[i].reply)
3223                         goto out_failed;
3224         }
3225
3226         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
3227                 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
3228                     GFP_KERNEL);
3229                 if (!mrioc->evtack_cmds[i].reply)
3230                         goto out_failed;
3231         }
3232
3233         mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3234         if (!mrioc->host_tm_cmds.reply)
3235                 goto out_failed;
3236
3237         mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3238         if (!mrioc->pel_cmds.reply)
3239                 goto out_failed;
3240
3241         mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3242         if (!mrioc->pel_abort_cmd.reply)
3243                 goto out_failed;
3244
3245         mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
3246         mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
3247                                                  GFP_KERNEL);
3248         if (!mrioc->removepend_bitmap)
3249                 goto out_failed;
3250
3251         mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
3252         if (!mrioc->devrem_bitmap)
3253                 goto out_failed;
3254
3255         mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
3256                                                   GFP_KERNEL);
3257         if (!mrioc->evtack_cmds_bitmap)
3258                 goto out_failed;
3259
3260         mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
3261         mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
3262         mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
3263         mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
3264
3265         /* reply buffer pool, 16 byte align */
3266         sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3267         mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3268             &mrioc->pdev->dev, sz, 16, 0);
3269         if (!mrioc->reply_buf_pool) {
3270                 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3271                 goto out_failed;
3272         }
3273
3274         mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3275             &mrioc->reply_buf_dma);
3276         if (!mrioc->reply_buf)
3277                 goto out_failed;
3278
3279         mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3280
3281         /* reply free queue, 8 byte align */
3282         sz = mrioc->reply_free_qsz * 8;
3283         mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3284             &mrioc->pdev->dev, sz, 8, 0);
3285         if (!mrioc->reply_free_q_pool) {
3286                 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3287                 goto out_failed;
3288         }
3289         mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3290             GFP_KERNEL, &mrioc->reply_free_q_dma);
3291         if (!mrioc->reply_free_q)
3292                 goto out_failed;
3293
3294         /* sense buffer pool,  4 byte align */
3295         sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3296         mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3297             &mrioc->pdev->dev, sz, 4, 0);
3298         if (!mrioc->sense_buf_pool) {
3299                 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3300                 goto out_failed;
3301         }
3302         mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3303             &mrioc->sense_buf_dma);
3304         if (!mrioc->sense_buf)
3305                 goto out_failed;
3306
3307         /* sense buffer queue, 8 byte align */
3308         sz = mrioc->sense_buf_q_sz * 8;
3309         mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3310             &mrioc->pdev->dev, sz, 8, 0);
3311         if (!mrioc->sense_buf_q_pool) {
3312                 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3313                 goto out_failed;
3314         }
3315         mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3316             GFP_KERNEL, &mrioc->sense_buf_q_dma);
3317         if (!mrioc->sense_buf_q)
3318                 goto out_failed;
3319
3320         return retval;
3321
3322 out_failed:
3323         retval = -1;
3324         return retval;
3325 }
3326
3327 /**
3328  * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3329  * buffers
3330  * @mrioc: Adapter instance reference
3331  *
3332  * Helper function to initialize reply and sense buffers along
3333  * with some debug prints.
3334  *
3335  * Return:  None.
3336  */
3337 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3338 {
3339         u32 sz, i;
3340         dma_addr_t phy_addr;
3341
3342         sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3343         ioc_info(mrioc,
3344             "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3345             mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3346             (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3347         sz = mrioc->reply_free_qsz * 8;
3348         ioc_info(mrioc,
3349             "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3350             mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3351             (unsigned long long)mrioc->reply_free_q_dma);
3352         sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3353         ioc_info(mrioc,
3354             "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3355             mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3356             (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3357         sz = mrioc->sense_buf_q_sz * 8;
3358         ioc_info(mrioc,
3359             "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3360             mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3361             (unsigned long long)mrioc->sense_buf_q_dma);
3362
3363         /* initialize Reply buffer Queue */
3364         for (i = 0, phy_addr = mrioc->reply_buf_dma;
3365             i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3366                 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3367         mrioc->reply_free_q[i] = cpu_to_le64(0);
3368
3369         /* initialize Sense Buffer Queue */
3370         for (i = 0, phy_addr = mrioc->sense_buf_dma;
3371             i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3372                 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3373         mrioc->sense_buf_q[i] = cpu_to_le64(0);
3374 }
3375
3376 /**
3377  * mpi3mr_issue_iocinit - Send IOC Init
3378  * @mrioc: Adapter instance reference
3379  *
3380  * Issue IOC Init MPI request through admin queue and wait for
3381  * the completion of it or time out.
3382  *
3383  * Return: 0 on success, non-zero on failures.
3384  */
3385 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3386 {
3387         struct mpi3_ioc_init_request iocinit_req;
3388         struct mpi3_driver_info_layout *drv_info;
3389         dma_addr_t data_dma;
3390         u32 data_len = sizeof(*drv_info);
3391         int retval = 0;
3392         ktime_t current_time;
3393
3394         drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3395             GFP_KERNEL);
3396         if (!drv_info) {
3397                 retval = -1;
3398                 goto out;
3399         }
3400         mpimr_initialize_reply_sbuf_queues(mrioc);
3401
3402         drv_info->information_length = cpu_to_le32(data_len);
3403         strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3404         strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3405         strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3406         strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3407         strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3408         strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3409             sizeof(drv_info->driver_release_date));
3410         drv_info->driver_capabilities = 0;
3411         memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3412             sizeof(mrioc->driver_info));
3413
3414         memset(&iocinit_req, 0, sizeof(iocinit_req));
3415         mutex_lock(&mrioc->init_cmds.mutex);
3416         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3417                 retval = -1;
3418                 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3419                 mutex_unlock(&mrioc->init_cmds.mutex);
3420                 goto out;
3421         }
3422         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3423         mrioc->init_cmds.is_waiting = 1;
3424         mrioc->init_cmds.callback = NULL;
3425         iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3426         iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3427         iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3428         iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3429         iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3430         iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3431         iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3432         iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3433         iocinit_req.reply_free_queue_address =
3434             cpu_to_le64(mrioc->reply_free_q_dma);
3435         iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3436         iocinit_req.sense_buffer_free_queue_depth =
3437             cpu_to_le16(mrioc->sense_buf_q_sz);
3438         iocinit_req.sense_buffer_free_queue_address =
3439             cpu_to_le64(mrioc->sense_buf_q_dma);
3440         iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3441
3442         current_time = ktime_get_real();
3443         iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3444
3445         iocinit_req.msg_flags |=
3446             MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED;
3447         iocinit_req.msg_flags |=
3448                 MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED;
3449
3450         init_completion(&mrioc->init_cmds.done);
3451         retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3452             sizeof(iocinit_req), 1);
3453         if (retval) {
3454                 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3455                 goto out_unlock;
3456         }
3457         wait_for_completion_timeout(&mrioc->init_cmds.done,
3458             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3459         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3460                 mpi3mr_check_rh_fault_ioc(mrioc,
3461                     MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3462                 ioc_err(mrioc, "ioc_init timed out\n");
3463                 retval = -1;
3464                 goto out_unlock;
3465         }
3466         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3467             != MPI3_IOCSTATUS_SUCCESS) {
3468                 ioc_err(mrioc,
3469                     "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3470                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3471                     mrioc->init_cmds.ioc_loginfo);
3472                 retval = -1;
3473                 goto out_unlock;
3474         }
3475
3476         mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3477         writel(mrioc->reply_free_queue_host_index,
3478             &mrioc->sysif_regs->reply_free_host_index);
3479
3480         mrioc->sbq_host_index = mrioc->num_sense_bufs;
3481         writel(mrioc->sbq_host_index,
3482             &mrioc->sysif_regs->sense_buffer_free_host_index);
3483 out_unlock:
3484         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3485         mutex_unlock(&mrioc->init_cmds.mutex);
3486
3487 out:
3488         if (drv_info)
3489                 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3490                     data_dma);
3491
3492         return retval;
3493 }
3494
3495 /**
3496  * mpi3mr_unmask_events - Unmask events in event mask bitmap
3497  * @mrioc: Adapter instance reference
3498  * @event: MPI event ID
3499  *
3500  * Un mask the specific event by resetting the event_mask
3501  * bitmap.
3502  *
3503  * Return: 0 on success, non-zero on failures.
3504  */
3505 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3506 {
3507         u32 desired_event;
3508         u8 word;
3509
3510         if (event >= 128)
3511                 return;
3512
3513         desired_event = (1 << (event % 32));
3514         word = event / 32;
3515
3516         mrioc->event_masks[word] &= ~desired_event;
3517 }
3518
3519 /**
3520  * mpi3mr_issue_event_notification - Send event notification
3521  * @mrioc: Adapter instance reference
3522  *
3523  * Issue event notification MPI request through admin queue and
3524  * wait for the completion of it or time out.
3525  *
3526  * Return: 0 on success, non-zero on failures.
3527  */
3528 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3529 {
3530         struct mpi3_event_notification_request evtnotify_req;
3531         int retval = 0;
3532         u8 i;
3533
3534         memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3535         mutex_lock(&mrioc->init_cmds.mutex);
3536         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3537                 retval = -1;
3538                 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3539                 mutex_unlock(&mrioc->init_cmds.mutex);
3540                 goto out;
3541         }
3542         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3543         mrioc->init_cmds.is_waiting = 1;
3544         mrioc->init_cmds.callback = NULL;
3545         evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3546         evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3547         for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3548                 evtnotify_req.event_masks[i] =
3549                     cpu_to_le32(mrioc->event_masks[i]);
3550         init_completion(&mrioc->init_cmds.done);
3551         retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3552             sizeof(evtnotify_req), 1);
3553         if (retval) {
3554                 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3555                 goto out_unlock;
3556         }
3557         wait_for_completion_timeout(&mrioc->init_cmds.done,
3558             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3559         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3560                 ioc_err(mrioc, "event notification timed out\n");
3561                 mpi3mr_check_rh_fault_ioc(mrioc,
3562                     MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3563                 retval = -1;
3564                 goto out_unlock;
3565         }
3566         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3567             != MPI3_IOCSTATUS_SUCCESS) {
3568                 ioc_err(mrioc,
3569                     "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3570                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3571                     mrioc->init_cmds.ioc_loginfo);
3572                 retval = -1;
3573                 goto out_unlock;
3574         }
3575
3576 out_unlock:
3577         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3578         mutex_unlock(&mrioc->init_cmds.mutex);
3579 out:
3580         return retval;
3581 }
3582
3583 /**
3584  * mpi3mr_process_event_ack - Process event acknowledgment
3585  * @mrioc: Adapter instance reference
3586  * @event: MPI3 event ID
3587  * @event_ctx: event context
3588  *
3589  * Send event acknowledgment through admin queue and wait for
3590  * it to complete.
3591  *
3592  * Return: 0 on success, non-zero on failures.
3593  */
3594 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3595         u32 event_ctx)
3596 {
3597         struct mpi3_event_ack_request evtack_req;
3598         int retval = 0;
3599
3600         memset(&evtack_req, 0, sizeof(evtack_req));
3601         mutex_lock(&mrioc->init_cmds.mutex);
3602         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3603                 retval = -1;
3604                 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3605                 mutex_unlock(&mrioc->init_cmds.mutex);
3606                 goto out;
3607         }
3608         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3609         mrioc->init_cmds.is_waiting = 1;
3610         mrioc->init_cmds.callback = NULL;
3611         evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3612         evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3613         evtack_req.event = event;
3614         evtack_req.event_context = cpu_to_le32(event_ctx);
3615
3616         init_completion(&mrioc->init_cmds.done);
3617         retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3618             sizeof(evtack_req), 1);
3619         if (retval) {
3620                 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3621                 goto out_unlock;
3622         }
3623         wait_for_completion_timeout(&mrioc->init_cmds.done,
3624             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3625         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3626                 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3627                 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3628                         mpi3mr_check_rh_fault_ioc(mrioc,
3629                             MPI3MR_RESET_FROM_EVTACK_TIMEOUT);
3630                 retval = -1;
3631                 goto out_unlock;
3632         }
3633         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3634             != MPI3_IOCSTATUS_SUCCESS) {
3635                 ioc_err(mrioc,
3636                     "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3637                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3638                     mrioc->init_cmds.ioc_loginfo);
3639                 retval = -1;
3640                 goto out_unlock;
3641         }
3642
3643 out_unlock:
3644         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3645         mutex_unlock(&mrioc->init_cmds.mutex);
3646 out:
3647         return retval;
3648 }
3649
3650 /**
3651  * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3652  * @mrioc: Adapter instance reference
3653  *
3654  * Allocate chain buffers and set a bitmap to indicate free
3655  * chain buffers. Chain buffers are used to pass the SGE
3656  * information along with MPI3 SCSI IO requests for host I/O.
3657  *
3658  * Return: 0 on success, non-zero on failure
3659  */
3660 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3661 {
3662         int retval = 0;
3663         u32 sz, i;
3664         u16 num_chains;
3665
3666         if (mrioc->chain_sgl_list)
3667                 return retval;
3668
3669         num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3670
3671         if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3672             | SHOST_DIX_TYPE1_PROTECTION
3673             | SHOST_DIX_TYPE2_PROTECTION
3674             | SHOST_DIX_TYPE3_PROTECTION))
3675                 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3676
3677         mrioc->chain_buf_count = num_chains;
3678         sz = sizeof(struct chain_element) * num_chains;
3679         mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3680         if (!mrioc->chain_sgl_list)
3681                 goto out_failed;
3682
3683         if (mrioc->max_sgl_entries > (mrioc->facts.max_data_length /
3684                 MPI3MR_PAGE_SIZE_4K))
3685                 mrioc->max_sgl_entries = mrioc->facts.max_data_length /
3686                         MPI3MR_PAGE_SIZE_4K;
3687         sz = mrioc->max_sgl_entries * sizeof(struct mpi3_sge_common);
3688         ioc_info(mrioc, "number of sgl entries=%d chain buffer size=%dKB\n",
3689                         mrioc->max_sgl_entries, sz/1024);
3690
3691         mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3692             &mrioc->pdev->dev, sz, 16, 0);
3693         if (!mrioc->chain_buf_pool) {
3694                 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3695                 goto out_failed;
3696         }
3697
3698         for (i = 0; i < num_chains; i++) {
3699                 mrioc->chain_sgl_list[i].addr =
3700                     dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3701                     &mrioc->chain_sgl_list[i].dma_addr);
3702
3703                 if (!mrioc->chain_sgl_list[i].addr)
3704                         goto out_failed;
3705         }
3706         mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3707         if (!mrioc->chain_bitmap)
3708                 goto out_failed;
3709         return retval;
3710 out_failed:
3711         retval = -1;
3712         return retval;
3713 }
3714
3715 /**
3716  * mpi3mr_port_enable_complete - Mark port enable complete
3717  * @mrioc: Adapter instance reference
3718  * @drv_cmd: Internal command tracker
3719  *
3720  * Call back for asynchronous port enable request sets the
3721  * driver command to indicate port enable request is complete.
3722  *
3723  * Return: Nothing
3724  */
3725 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3726         struct mpi3mr_drv_cmd *drv_cmd)
3727 {
3728         drv_cmd->callback = NULL;
3729         mrioc->scan_started = 0;
3730         if (drv_cmd->state & MPI3MR_CMD_RESET)
3731                 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3732         else
3733                 mrioc->scan_failed = drv_cmd->ioc_status;
3734         drv_cmd->state = MPI3MR_CMD_NOTUSED;
3735 }
3736
3737 /**
3738  * mpi3mr_issue_port_enable - Issue Port Enable
3739  * @mrioc: Adapter instance reference
3740  * @async: Flag to wait for completion or not
3741  *
3742  * Issue Port Enable MPI request through admin queue and if the
3743  * async flag is not set wait for the completion of the port
3744  * enable or time out.
3745  *
3746  * Return: 0 on success, non-zero on failures.
3747  */
3748 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3749 {
3750         struct mpi3_port_enable_request pe_req;
3751         int retval = 0;
3752         u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3753
3754         memset(&pe_req, 0, sizeof(pe_req));
3755         mutex_lock(&mrioc->init_cmds.mutex);
3756         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3757                 retval = -1;
3758                 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3759                 mutex_unlock(&mrioc->init_cmds.mutex);
3760                 goto out;
3761         }
3762         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3763         if (async) {
3764                 mrioc->init_cmds.is_waiting = 0;
3765                 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3766         } else {
3767                 mrioc->init_cmds.is_waiting = 1;
3768                 mrioc->init_cmds.callback = NULL;
3769                 init_completion(&mrioc->init_cmds.done);
3770         }
3771         pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3772         pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3773
3774         retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3775         if (retval) {
3776                 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3777                 goto out_unlock;
3778         }
3779         if (async) {
3780                 mutex_unlock(&mrioc->init_cmds.mutex);
3781                 goto out;
3782         }
3783
3784         wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3785         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3786                 ioc_err(mrioc, "port enable timed out\n");
3787                 retval = -1;
3788                 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3789                 goto out_unlock;
3790         }
3791         mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3792
3793 out_unlock:
3794         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3795         mutex_unlock(&mrioc->init_cmds.mutex);
3796 out:
3797         return retval;
3798 }
3799
3800 /* Protocol type to name mapper structure */
3801 static const struct {
3802         u8 protocol;
3803         char *name;
3804 } mpi3mr_protocols[] = {
3805         { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3806         { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3807         { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3808 };
3809
3810 /* Capability to name mapper structure*/
3811 static const struct {
3812         u32 capability;
3813         char *name;
3814 } mpi3mr_capabilities[] = {
3815         { MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED, "RAID" },
3816         { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED, "MultiPath" },
3817 };
3818
3819 /**
3820  * mpi3mr_repost_diag_bufs - repost host diag buffers
3821  * @mrioc: Adapter instance reference
3822  *
3823  * repost firmware and trace diag buffers based on global
3824  * trigger flag from driver page 2
3825  *
3826  * Return: 0 on success, non-zero on failures.
3827  */
3828 static int mpi3mr_repost_diag_bufs(struct mpi3mr_ioc *mrioc)
3829 {
3830         u64 global_trigger;
3831         union mpi3mr_trigger_data prev_trigger_data;
3832         struct diag_buffer_desc *trace_hdb = NULL;
3833         struct diag_buffer_desc *fw_hdb = NULL;
3834         int retval = 0;
3835         bool trace_repost_needed = false;
3836         bool fw_repost_needed = false;
3837         u8 prev_trigger_type;
3838
3839         retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT);
3840         if (retval)
3841                 return -1;
3842
3843         trace_hdb = mpi3mr_diag_buffer_for_type(mrioc,
3844             MPI3_DIAG_BUFFER_TYPE_TRACE);
3845
3846         if (trace_hdb &&
3847             trace_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED &&
3848             trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL &&
3849             trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT)
3850                 trace_repost_needed = true;
3851
3852         fw_hdb = mpi3mr_diag_buffer_for_type(mrioc, MPI3_DIAG_BUFFER_TYPE_FW);
3853
3854         if (fw_hdb && fw_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED &&
3855             fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL &&
3856             fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT)
3857                 fw_repost_needed = true;
3858
3859         if (trace_repost_needed || fw_repost_needed) {
3860                 global_trigger = le64_to_cpu(mrioc->driver_pg2->global_trigger);
3861                 if (global_trigger &
3862                       MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED)
3863                         trace_repost_needed = false;
3864                 if (global_trigger &
3865                      MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED)
3866                         fw_repost_needed = false;
3867         }
3868
3869         if (trace_repost_needed) {
3870                 prev_trigger_type = trace_hdb->trigger_type;
3871                 memcpy(&prev_trigger_data, &trace_hdb->trigger_data,
3872                     sizeof(trace_hdb->trigger_data));
3873                 retval = mpi3mr_issue_diag_buf_post(mrioc, trace_hdb);
3874                 if (!retval) {
3875                         dprint_init(mrioc, "trace diag buffer reposted");
3876                         mpi3mr_set_trigger_data_in_hdb(trace_hdb,
3877                                     MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1);
3878                 } else {
3879                         trace_hdb->trigger_type = prev_trigger_type;
3880                         memcpy(&trace_hdb->trigger_data, &prev_trigger_data,
3881                             sizeof(prev_trigger_data));
3882                         ioc_err(mrioc, "trace diag buffer repost failed");
3883                         return -1;
3884                 }
3885         }
3886
3887         if (fw_repost_needed) {
3888                 prev_trigger_type = fw_hdb->trigger_type;
3889                 memcpy(&prev_trigger_data, &fw_hdb->trigger_data,
3890                     sizeof(fw_hdb->trigger_data));
3891                 retval = mpi3mr_issue_diag_buf_post(mrioc, fw_hdb);
3892                 if (!retval) {
3893                         dprint_init(mrioc, "firmware diag buffer reposted");
3894                         mpi3mr_set_trigger_data_in_hdb(fw_hdb,
3895                                     MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1);
3896                 } else {
3897                         fw_hdb->trigger_type = prev_trigger_type;
3898                         memcpy(&fw_hdb->trigger_data, &prev_trigger_data,
3899                             sizeof(prev_trigger_data));
3900                         ioc_err(mrioc, "firmware diag buffer repost failed");
3901                         return -1;
3902                 }
3903         }
3904         return retval;
3905 }
3906
3907 /**
3908  * mpi3mr_read_tsu_interval - Update time stamp interval
3909  * @mrioc: Adapter instance reference
3910  *
3911  * Update time stamp interval if its defined in driver page 1,
3912  * otherwise use default value.
3913  *
3914  * Return: Nothing
3915  */
3916 static void
3917 mpi3mr_read_tsu_interval(struct mpi3mr_ioc *mrioc)
3918 {
3919         struct mpi3_driver_page1 driver_pg1;
3920         u16 pg_sz = sizeof(driver_pg1);
3921         int retval = 0;
3922
3923         mrioc->ts_update_interval = MPI3MR_TSUPDATE_INTERVAL;
3924
3925         retval = mpi3mr_cfg_get_driver_pg1(mrioc, &driver_pg1, pg_sz);
3926         if (!retval && driver_pg1.time_stamp_update)
3927                 mrioc->ts_update_interval = (driver_pg1.time_stamp_update * 60);
3928 }
3929
3930 /**
3931  * mpi3mr_print_ioc_info - Display controller information
3932  * @mrioc: Adapter instance reference
3933  *
3934  * Display controller personality, capability, supported
3935  * protocols etc.
3936  *
3937  * Return: Nothing
3938  */
3939 static void
3940 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3941 {
3942         int i = 0, bytes_written = 0;
3943         const char *personality;
3944         char protocol[50] = {0};
3945         char capabilities[100] = {0};
3946         struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3947
3948         switch (mrioc->facts.personality) {
3949         case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3950                 personality = "Enhanced HBA";
3951                 break;
3952         case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3953                 personality = "RAID";
3954                 break;
3955         default:
3956                 personality = "Unknown";
3957                 break;
3958         }
3959
3960         ioc_info(mrioc, "Running in %s Personality", personality);
3961
3962         ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3963             fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3964             fwver->ph_minor, fwver->cust_id, fwver->build_num);
3965
3966         for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3967                 if (mrioc->facts.protocol_flags &
3968                     mpi3mr_protocols[i].protocol) {
3969                         bytes_written += scnprintf(protocol + bytes_written,
3970                                     sizeof(protocol) - bytes_written, "%s%s",
3971                                     bytes_written ? "," : "",
3972                                     mpi3mr_protocols[i].name);
3973                 }
3974         }
3975
3976         bytes_written = 0;
3977         for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3978                 if (mrioc->facts.protocol_flags &
3979                     mpi3mr_capabilities[i].capability) {
3980                         bytes_written += scnprintf(capabilities + bytes_written,
3981                                     sizeof(capabilities) - bytes_written, "%s%s",
3982                                     bytes_written ? "," : "",
3983                                     mpi3mr_capabilities[i].name);
3984                 }
3985         }
3986
3987         ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
3988                  protocol, capabilities);
3989 }
3990
3991 /**
3992  * mpi3mr_cleanup_resources - Free PCI resources
3993  * @mrioc: Adapter instance reference
3994  *
3995  * Unmap PCI device memory and disable PCI device.
3996  *
3997  * Return: 0 on success and non-zero on failure.
3998  */
3999 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
4000 {
4001         struct pci_dev *pdev = mrioc->pdev;
4002
4003         mpi3mr_cleanup_isr(mrioc);
4004
4005         if (mrioc->sysif_regs) {
4006                 iounmap((void __iomem *)mrioc->sysif_regs);
4007                 mrioc->sysif_regs = NULL;
4008         }
4009
4010         if (pci_is_enabled(pdev)) {
4011                 if (mrioc->bars)
4012                         pci_release_selected_regions(pdev, mrioc->bars);
4013                 pci_disable_device(pdev);
4014         }
4015 }
4016
4017 /**
4018  * mpi3mr_setup_resources - Enable PCI resources
4019  * @mrioc: Adapter instance reference
4020  *
4021  * Enable PCI device memory, MSI-x registers and set DMA mask.
4022  *
4023  * Return: 0 on success and non-zero on failure.
4024  */
4025 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
4026 {
4027         struct pci_dev *pdev = mrioc->pdev;
4028         u32 memap_sz = 0;
4029         int i, retval = 0, capb = 0;
4030         u16 message_control;
4031         u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
4032             ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
4033
4034         if (pci_enable_device_mem(pdev)) {
4035                 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
4036                 retval = -ENODEV;
4037                 goto out_failed;
4038         }
4039
4040         capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
4041         if (!capb) {
4042                 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
4043                 retval = -ENODEV;
4044                 goto out_failed;
4045         }
4046         mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
4047
4048         if (pci_request_selected_regions(pdev, mrioc->bars,
4049             mrioc->driver_name)) {
4050                 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
4051                 retval = -ENODEV;
4052                 goto out_failed;
4053         }
4054
4055         for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
4056                 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
4057                         mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
4058                         memap_sz = pci_resource_len(pdev, i);
4059                         mrioc->sysif_regs =
4060                             ioremap(mrioc->sysif_regs_phys, memap_sz);
4061                         break;
4062                 }
4063         }
4064
4065         pci_set_master(pdev);
4066
4067         retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
4068         if (retval) {
4069                 if (dma_mask != DMA_BIT_MASK(32)) {
4070                         ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
4071                         dma_mask = DMA_BIT_MASK(32);
4072                         retval = dma_set_mask_and_coherent(&pdev->dev,
4073                             dma_mask);
4074                 }
4075                 if (retval) {
4076                         mrioc->dma_mask = 0;
4077                         ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
4078                         goto out_failed;
4079                 }
4080         }
4081         mrioc->dma_mask = dma_mask;
4082
4083         if (!mrioc->sysif_regs) {
4084                 ioc_err(mrioc,
4085                     "Unable to map adapter memory or resource not found\n");
4086                 retval = -EINVAL;
4087                 goto out_failed;
4088         }
4089
4090         pci_read_config_word(pdev, capb + 2, &message_control);
4091         mrioc->msix_count = (message_control & 0x3FF) + 1;
4092
4093         pci_save_state(pdev);
4094
4095         pci_set_drvdata(pdev, mrioc->shost);
4096
4097         mpi3mr_ioc_disable_intr(mrioc);
4098
4099         ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
4100             (unsigned long long)mrioc->sysif_regs_phys,
4101             mrioc->sysif_regs, memap_sz);
4102         ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
4103             mrioc->msix_count);
4104
4105         if (!reset_devices && poll_queues > 0)
4106                 mrioc->requested_poll_qcount = min_t(int, poll_queues,
4107                                 mrioc->msix_count - 2);
4108         return retval;
4109
4110 out_failed:
4111         mpi3mr_cleanup_resources(mrioc);
4112         return retval;
4113 }
4114
4115 /**
4116  * mpi3mr_enable_events - Enable required events
4117  * @mrioc: Adapter instance reference
4118  *
4119  * This routine unmasks the events required by the driver by
4120  * sennding appropriate event mask bitmapt through an event
4121  * notification request.
4122  *
4123  * Return: 0 on success and non-zero on failure.
4124  */
4125 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
4126 {
4127         int retval = 0;
4128         u32  i;
4129
4130         for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4131                 mrioc->event_masks[i] = -1;
4132
4133         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
4134         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
4135         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
4136         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
4137         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
4138         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
4139         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
4140         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
4141         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
4142         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
4143         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
4144         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
4145         mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
4146         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
4147         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE);
4148
4149         retval = mpi3mr_issue_event_notification(mrioc);
4150         if (retval)
4151                 ioc_err(mrioc, "failed to issue event notification %d\n",
4152                     retval);
4153         return retval;
4154 }
4155
4156 /**
4157  * mpi3mr_init_ioc - Initialize the controller
4158  * @mrioc: Adapter instance reference
4159  *
4160  * This the controller initialization routine, executed either
4161  * after soft reset or from pci probe callback.
4162  * Setup the required resources, memory map the controller
4163  * registers, create admin and operational reply queue pairs,
4164  * allocate required memory for reply pool, sense buffer pool,
4165  * issue IOC init request to the firmware, unmask the events and
4166  * issue port enable to discover SAS/SATA/NVMe devies and RAID
4167  * volumes.
4168  *
4169  * Return: 0 on success and non-zero on failure.
4170  */
4171 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
4172 {
4173         int retval = 0;
4174         u8 retry = 0;
4175         struct mpi3_ioc_facts_data facts_data;
4176         u32 sz;
4177
4178 retry_init:
4179         retval = mpi3mr_bring_ioc_ready(mrioc);
4180         if (retval) {
4181                 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
4182                     retval);
4183                 goto out_failed_noretry;
4184         }
4185
4186         retval = mpi3mr_setup_isr(mrioc, 1);
4187         if (retval) {
4188                 ioc_err(mrioc, "Failed to setup ISR error %d\n",
4189                     retval);
4190                 goto out_failed_noretry;
4191         }
4192
4193         retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4194         if (retval) {
4195                 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
4196                     retval);
4197                 goto out_failed;
4198         }
4199
4200         mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
4201         mrioc->shost->max_sectors = mrioc->facts.max_data_length / 512;
4202         mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
4203         atomic_set(&mrioc->pend_large_data_sz, 0);
4204
4205         if (reset_devices)
4206                 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
4207                     MPI3MR_HOST_IOS_KDUMP);
4208
4209         if (!(mrioc->facts.ioc_capabilities &
4210             MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED)) {
4211                 mrioc->sas_transport_enabled = 1;
4212                 mrioc->scsi_device_channel = 1;
4213                 mrioc->shost->max_channel = 1;
4214                 mrioc->shost->transportt = mpi3mr_transport_template;
4215         }
4216
4217         mrioc->reply_sz = mrioc->facts.reply_sz;
4218
4219         retval = mpi3mr_check_reset_dma_mask(mrioc);
4220         if (retval) {
4221                 ioc_err(mrioc, "Resetting dma mask failed %d\n",
4222                     retval);
4223                 goto out_failed_noretry;
4224         }
4225
4226         mpi3mr_read_tsu_interval(mrioc);
4227         mpi3mr_print_ioc_info(mrioc);
4228
4229         dprint_init(mrioc, "allocating host diag buffers\n");
4230         mpi3mr_alloc_diag_bufs(mrioc);
4231
4232         dprint_init(mrioc, "allocating ioctl dma buffers\n");
4233         mpi3mr_alloc_ioctl_dma_memory(mrioc);
4234
4235         dprint_init(mrioc, "posting host diag buffers\n");
4236         retval = mpi3mr_post_diag_bufs(mrioc);
4237
4238         if (retval)
4239                 ioc_warn(mrioc, "failed to post host diag buffers\n");
4240
4241         if (!mrioc->init_cmds.reply) {
4242                 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
4243                 if (retval) {
4244                         ioc_err(mrioc,
4245                             "%s :Failed to allocated reply sense buffers %d\n",
4246                             __func__, retval);
4247                         goto out_failed_noretry;
4248                 }
4249         }
4250
4251         if (!mrioc->chain_sgl_list) {
4252                 retval = mpi3mr_alloc_chain_bufs(mrioc);
4253                 if (retval) {
4254                         ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
4255                             retval);
4256                         goto out_failed_noretry;
4257                 }
4258         }
4259
4260         retval = mpi3mr_issue_iocinit(mrioc);
4261         if (retval) {
4262                 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
4263                     retval);
4264                 goto out_failed;
4265         }
4266
4267         retval = mpi3mr_print_pkg_ver(mrioc);
4268         if (retval) {
4269                 ioc_err(mrioc, "failed to get package version\n");
4270                 goto out_failed;
4271         }
4272
4273         retval = mpi3mr_setup_isr(mrioc, 0);
4274         if (retval) {
4275                 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
4276                     retval);
4277                 goto out_failed_noretry;
4278         }
4279
4280         retval = mpi3mr_create_op_queues(mrioc);
4281         if (retval) {
4282                 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
4283                     retval);
4284                 goto out_failed;
4285         }
4286
4287         if (!mrioc->pel_seqnum_virt) {
4288                 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
4289                 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4290                 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4291                     mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4292                     GFP_KERNEL);
4293                 if (!mrioc->pel_seqnum_virt) {
4294                         retval = -ENOMEM;
4295                         goto out_failed_noretry;
4296                 }
4297         }
4298
4299         if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
4300                 dprint_init(mrioc, "allocating memory for throttle groups\n");
4301                 sz = sizeof(struct mpi3mr_throttle_group_info);
4302                 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
4303                 if (!mrioc->throttle_groups) {
4304                         retval = -1;
4305                         goto out_failed_noretry;
4306                 }
4307         }
4308
4309         retval = mpi3mr_enable_events(mrioc);
4310         if (retval) {
4311                 ioc_err(mrioc, "failed to enable events %d\n",
4312                     retval);
4313                 goto out_failed;
4314         }
4315
4316         retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT);
4317         if (retval) {
4318                 ioc_err(mrioc, "failed to refresh triggers\n");
4319                 goto out_failed;
4320         }
4321
4322         ioc_info(mrioc, "controller initialization completed successfully\n");
4323         return retval;
4324 out_failed:
4325         if (retry < 2) {
4326                 retry++;
4327                 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
4328                     retry);
4329                 mpi3mr_memset_buffers(mrioc);
4330                 goto retry_init;
4331         }
4332         retval = -1;
4333 out_failed_noretry:
4334         ioc_err(mrioc, "controller initialization failed\n");
4335         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4336             MPI3MR_RESET_FROM_CTLR_CLEANUP);
4337         mrioc->unrecoverable = 1;
4338         return retval;
4339 }
4340
4341 /**
4342  * mpi3mr_reinit_ioc - Re-Initialize the controller
4343  * @mrioc: Adapter instance reference
4344  * @is_resume: Called from resume or reset path
4345  *
4346  * This the controller re-initialization routine, executed from
4347  * the soft reset handler or resume callback. Creates
4348  * operational reply queue pairs, allocate required memory for
4349  * reply pool, sense buffer pool, issue IOC init request to the
4350  * firmware, unmask the events and issue port enable to discover
4351  * SAS/SATA/NVMe devices and RAID volumes.
4352  *
4353  * Return: 0 on success and non-zero on failure.
4354  */
4355 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
4356 {
4357         int retval = 0;
4358         u8 retry = 0;
4359         struct mpi3_ioc_facts_data facts_data;
4360         u32 pe_timeout, ioc_status;
4361
4362 retry_init:
4363         pe_timeout =
4364             (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
4365
4366         dprint_reset(mrioc, "bringing up the controller to ready state\n");
4367         retval = mpi3mr_bring_ioc_ready(mrioc);
4368         if (retval) {
4369                 ioc_err(mrioc, "failed to bring to ready state\n");
4370                 goto out_failed_noretry;
4371         }
4372
4373         if (is_resume || mrioc->block_on_pci_err) {
4374                 dprint_reset(mrioc, "setting up single ISR\n");
4375                 retval = mpi3mr_setup_isr(mrioc, 1);
4376                 if (retval) {
4377                         ioc_err(mrioc, "failed to setup ISR\n");
4378                         goto out_failed_noretry;
4379                 }
4380         } else
4381                 mpi3mr_ioc_enable_intr(mrioc);
4382
4383         dprint_reset(mrioc, "getting ioc_facts\n");
4384         retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4385         if (retval) {
4386                 ioc_err(mrioc, "failed to get ioc_facts\n");
4387                 goto out_failed;
4388         }
4389
4390         dprint_reset(mrioc, "validating ioc_facts\n");
4391         retval = mpi3mr_revalidate_factsdata(mrioc);
4392         if (retval) {
4393                 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
4394                 goto out_failed_noretry;
4395         }
4396
4397         mpi3mr_read_tsu_interval(mrioc);
4398         mpi3mr_print_ioc_info(mrioc);
4399
4400         if (is_resume) {
4401                 dprint_reset(mrioc, "posting host diag buffers\n");
4402                 retval = mpi3mr_post_diag_bufs(mrioc);
4403                 if (retval)
4404                         ioc_warn(mrioc, "failed to post host diag buffers\n");
4405         } else {
4406                 retval = mpi3mr_repost_diag_bufs(mrioc);
4407                 if (retval)
4408                         ioc_warn(mrioc, "failed to re post host diag buffers\n");
4409         }
4410
4411         dprint_reset(mrioc, "sending ioc_init\n");
4412         retval = mpi3mr_issue_iocinit(mrioc);
4413         if (retval) {
4414                 ioc_err(mrioc, "failed to send ioc_init\n");
4415                 goto out_failed;
4416         }
4417
4418         dprint_reset(mrioc, "getting package version\n");
4419         retval = mpi3mr_print_pkg_ver(mrioc);
4420         if (retval) {
4421                 ioc_err(mrioc, "failed to get package version\n");
4422                 goto out_failed;
4423         }
4424
4425         if (is_resume || mrioc->block_on_pci_err) {
4426                 dprint_reset(mrioc, "setting up multiple ISR\n");
4427                 retval = mpi3mr_setup_isr(mrioc, 0);
4428                 if (retval) {
4429                         ioc_err(mrioc, "failed to re-setup ISR\n");
4430                         goto out_failed_noretry;
4431                 }
4432         }
4433
4434         dprint_reset(mrioc, "creating operational queue pairs\n");
4435         retval = mpi3mr_create_op_queues(mrioc);
4436         if (retval) {
4437                 ioc_err(mrioc, "failed to create operational queue pairs\n");
4438                 goto out_failed;
4439         }
4440
4441         if (!mrioc->pel_seqnum_virt) {
4442                 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4443                 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4444                 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4445                     mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4446                     GFP_KERNEL);
4447                 if (!mrioc->pel_seqnum_virt) {
4448                         retval = -ENOMEM;
4449                         goto out_failed_noretry;
4450                 }
4451         }
4452
4453         if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4454                 ioc_err(mrioc,
4455                     "cannot create minimum number of operational queues expected:%d created:%d\n",
4456                     mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4457                 retval = -1;
4458                 goto out_failed_noretry;
4459         }
4460
4461         dprint_reset(mrioc, "enabling events\n");
4462         retval = mpi3mr_enable_events(mrioc);
4463         if (retval) {
4464                 ioc_err(mrioc, "failed to enable events\n");
4465                 goto out_failed;
4466         }
4467
4468         mrioc->device_refresh_on = 1;
4469         mpi3mr_add_event_wait_for_device_refresh(mrioc);
4470
4471         ioc_info(mrioc, "sending port enable\n");
4472         retval = mpi3mr_issue_port_enable(mrioc, 1);
4473         if (retval) {
4474                 ioc_err(mrioc, "failed to issue port enable\n");
4475                 goto out_failed;
4476         }
4477         do {
4478                 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4479                 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4480                         break;
4481                 if (!pci_device_is_present(mrioc->pdev))
4482                         mrioc->unrecoverable = 1;
4483                 if (mrioc->unrecoverable) {
4484                         retval = -1;
4485                         goto out_failed_noretry;
4486                 }
4487                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4488                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4489                     (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4490                         mpi3mr_print_fault_info(mrioc);
4491                         mrioc->init_cmds.is_waiting = 0;
4492                         mrioc->init_cmds.callback = NULL;
4493                         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4494                         goto out_failed;
4495                 }
4496         } while (--pe_timeout);
4497
4498         if (!pe_timeout) {
4499                 ioc_err(mrioc, "port enable timed out\n");
4500                 mpi3mr_check_rh_fault_ioc(mrioc,
4501                     MPI3MR_RESET_FROM_PE_TIMEOUT);
4502                 mrioc->init_cmds.is_waiting = 0;
4503                 mrioc->init_cmds.callback = NULL;
4504                 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4505                 goto out_failed;
4506         } else if (mrioc->scan_failed) {
4507                 ioc_err(mrioc,
4508                     "port enable failed with status=0x%04x\n",
4509                     mrioc->scan_failed);
4510         } else
4511                 ioc_info(mrioc, "port enable completed successfully\n");
4512
4513         ioc_info(mrioc, "controller %s completed successfully\n",
4514             (is_resume)?"resume":"re-initialization");
4515         return retval;
4516 out_failed:
4517         if (retry < 2) {
4518                 retry++;
4519                 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4520                     (is_resume)?"resume":"re-initialization", retry);
4521                 mpi3mr_memset_buffers(mrioc);
4522                 goto retry_init;
4523         }
4524         retval = -1;
4525 out_failed_noretry:
4526         ioc_err(mrioc, "controller %s is failed\n",
4527             (is_resume)?"resume":"re-initialization");
4528         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4529             MPI3MR_RESET_FROM_CTLR_CLEANUP);
4530         mrioc->unrecoverable = 1;
4531         return retval;
4532 }
4533
4534 /**
4535  * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4536  *                                      segments
4537  * @mrioc: Adapter instance reference
4538  * @qidx: Operational reply queue index
4539  *
4540  * Return: Nothing.
4541  */
4542 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4543 {
4544         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4545         struct segments *segments;
4546         int i, size;
4547
4548         if (!op_reply_q->q_segments)
4549                 return;
4550
4551         size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4552         segments = op_reply_q->q_segments;
4553         for (i = 0; i < op_reply_q->num_segments; i++)
4554                 memset(segments[i].segment, 0, size);
4555 }
4556
4557 /**
4558  * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4559  *                                      segments
4560  * @mrioc: Adapter instance reference
4561  * @qidx: Operational request queue index
4562  *
4563  * Return: Nothing.
4564  */
4565 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4566 {
4567         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4568         struct segments *segments;
4569         int i, size;
4570
4571         if (!op_req_q->q_segments)
4572                 return;
4573
4574         size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4575         segments = op_req_q->q_segments;
4576         for (i = 0; i < op_req_q->num_segments; i++)
4577                 memset(segments[i].segment, 0, size);
4578 }
4579
4580 /**
4581  * mpi3mr_memset_buffers - memset memory for a controller
4582  * @mrioc: Adapter instance reference
4583  *
4584  * clear all the memory allocated for a controller, typically
4585  * called post reset to reuse the memory allocated during the
4586  * controller init.
4587  *
4588  * Return: Nothing.
4589  */
4590 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4591 {
4592         u16 i;
4593         struct mpi3mr_throttle_group_info *tg;
4594
4595         mrioc->change_count = 0;
4596         mrioc->active_poll_qcount = 0;
4597         mrioc->default_qcount = 0;
4598         if (mrioc->admin_req_base)
4599                 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4600         if (mrioc->admin_reply_base)
4601                 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4602         atomic_set(&mrioc->admin_reply_q_in_use, 0);
4603
4604         if (mrioc->init_cmds.reply) {
4605                 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4606                 memset(mrioc->bsg_cmds.reply, 0,
4607                     sizeof(*mrioc->bsg_cmds.reply));
4608                 memset(mrioc->host_tm_cmds.reply, 0,
4609                     sizeof(*mrioc->host_tm_cmds.reply));
4610                 memset(mrioc->pel_cmds.reply, 0,
4611                     sizeof(*mrioc->pel_cmds.reply));
4612                 memset(mrioc->pel_abort_cmd.reply, 0,
4613                     sizeof(*mrioc->pel_abort_cmd.reply));
4614                 memset(mrioc->transport_cmds.reply, 0,
4615                     sizeof(*mrioc->transport_cmds.reply));
4616                 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4617                         memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4618                             sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4619                 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4620                         memset(mrioc->evtack_cmds[i].reply, 0,
4621                             sizeof(*mrioc->evtack_cmds[i].reply));
4622                 bitmap_clear(mrioc->removepend_bitmap, 0,
4623                              mrioc->dev_handle_bitmap_bits);
4624                 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4625                 bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4626                              MPI3MR_NUM_EVTACKCMD);
4627         }
4628
4629         for (i = 0; i < mrioc->num_queues; i++) {
4630                 mrioc->op_reply_qinfo[i].qid = 0;
4631                 mrioc->op_reply_qinfo[i].ci = 0;
4632                 mrioc->op_reply_qinfo[i].num_replies = 0;
4633                 mrioc->op_reply_qinfo[i].ephase = 0;
4634                 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4635                 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4636                 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4637
4638                 mrioc->req_qinfo[i].ci = 0;
4639                 mrioc->req_qinfo[i].pi = 0;
4640                 mrioc->req_qinfo[i].num_requests = 0;
4641                 mrioc->req_qinfo[i].qid = 0;
4642                 mrioc->req_qinfo[i].reply_qid = 0;
4643                 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4644                 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4645         }
4646
4647         atomic_set(&mrioc->pend_large_data_sz, 0);
4648         if (mrioc->throttle_groups) {
4649                 tg = mrioc->throttle_groups;
4650                 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4651                         tg->id = 0;
4652                         tg->fw_qd = 0;
4653                         tg->modified_qd = 0;
4654                         tg->io_divert = 0;
4655                         tg->need_qd_reduction = 0;
4656                         tg->high = 0;
4657                         tg->low = 0;
4658                         tg->qd_reduction = 0;
4659                         atomic_set(&tg->pend_large_data_sz, 0);
4660                 }
4661         }
4662 }
4663
4664 /**
4665  * mpi3mr_free_mem - Free memory allocated for a controller
4666  * @mrioc: Adapter instance reference
4667  *
4668  * Free all the memory allocated for a controller.
4669  *
4670  * Return: Nothing.
4671  */
4672 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4673 {
4674         u16 i;
4675         struct mpi3mr_intr_info *intr_info;
4676         struct diag_buffer_desc *diag_buffer;
4677
4678         mpi3mr_free_enclosure_list(mrioc);
4679         mpi3mr_free_ioctl_dma_memory(mrioc);
4680
4681         if (mrioc->sense_buf_pool) {
4682                 if (mrioc->sense_buf)
4683                         dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4684                             mrioc->sense_buf_dma);
4685                 dma_pool_destroy(mrioc->sense_buf_pool);
4686                 mrioc->sense_buf = NULL;
4687                 mrioc->sense_buf_pool = NULL;
4688         }
4689         if (mrioc->sense_buf_q_pool) {
4690                 if (mrioc->sense_buf_q)
4691                         dma_pool_free(mrioc->sense_buf_q_pool,
4692                             mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4693                 dma_pool_destroy(mrioc->sense_buf_q_pool);
4694                 mrioc->sense_buf_q = NULL;
4695                 mrioc->sense_buf_q_pool = NULL;
4696         }
4697
4698         if (mrioc->reply_buf_pool) {
4699                 if (mrioc->reply_buf)
4700                         dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4701                             mrioc->reply_buf_dma);
4702                 dma_pool_destroy(mrioc->reply_buf_pool);
4703                 mrioc->reply_buf = NULL;
4704                 mrioc->reply_buf_pool = NULL;
4705         }
4706         if (mrioc->reply_free_q_pool) {
4707                 if (mrioc->reply_free_q)
4708                         dma_pool_free(mrioc->reply_free_q_pool,
4709                             mrioc->reply_free_q, mrioc->reply_free_q_dma);
4710                 dma_pool_destroy(mrioc->reply_free_q_pool);
4711                 mrioc->reply_free_q = NULL;
4712                 mrioc->reply_free_q_pool = NULL;
4713         }
4714
4715         for (i = 0; i < mrioc->num_op_req_q; i++)
4716                 mpi3mr_free_op_req_q_segments(mrioc, i);
4717
4718         for (i = 0; i < mrioc->num_op_reply_q; i++)
4719                 mpi3mr_free_op_reply_q_segments(mrioc, i);
4720
4721         for (i = 0; i < mrioc->intr_info_count; i++) {
4722                 intr_info = mrioc->intr_info + i;
4723                 intr_info->op_reply_q = NULL;
4724         }
4725
4726         kfree(mrioc->req_qinfo);
4727         mrioc->req_qinfo = NULL;
4728         mrioc->num_op_req_q = 0;
4729
4730         kfree(mrioc->op_reply_qinfo);
4731         mrioc->op_reply_qinfo = NULL;
4732         mrioc->num_op_reply_q = 0;
4733
4734         kfree(mrioc->init_cmds.reply);
4735         mrioc->init_cmds.reply = NULL;
4736
4737         kfree(mrioc->bsg_cmds.reply);
4738         mrioc->bsg_cmds.reply = NULL;
4739
4740         kfree(mrioc->host_tm_cmds.reply);
4741         mrioc->host_tm_cmds.reply = NULL;
4742
4743         kfree(mrioc->pel_cmds.reply);
4744         mrioc->pel_cmds.reply = NULL;
4745
4746         kfree(mrioc->pel_abort_cmd.reply);
4747         mrioc->pel_abort_cmd.reply = NULL;
4748
4749         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4750                 kfree(mrioc->evtack_cmds[i].reply);
4751                 mrioc->evtack_cmds[i].reply = NULL;
4752         }
4753
4754         bitmap_free(mrioc->removepend_bitmap);
4755         mrioc->removepend_bitmap = NULL;
4756
4757         bitmap_free(mrioc->devrem_bitmap);
4758         mrioc->devrem_bitmap = NULL;
4759
4760         bitmap_free(mrioc->evtack_cmds_bitmap);
4761         mrioc->evtack_cmds_bitmap = NULL;
4762
4763         bitmap_free(mrioc->chain_bitmap);
4764         mrioc->chain_bitmap = NULL;
4765
4766         kfree(mrioc->transport_cmds.reply);
4767         mrioc->transport_cmds.reply = NULL;
4768
4769         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4770                 kfree(mrioc->dev_rmhs_cmds[i].reply);
4771                 mrioc->dev_rmhs_cmds[i].reply = NULL;
4772         }
4773
4774         if (mrioc->chain_buf_pool) {
4775                 for (i = 0; i < mrioc->chain_buf_count; i++) {
4776                         if (mrioc->chain_sgl_list[i].addr) {
4777                                 dma_pool_free(mrioc->chain_buf_pool,
4778                                     mrioc->chain_sgl_list[i].addr,
4779                                     mrioc->chain_sgl_list[i].dma_addr);
4780                                 mrioc->chain_sgl_list[i].addr = NULL;
4781                         }
4782                 }
4783                 dma_pool_destroy(mrioc->chain_buf_pool);
4784                 mrioc->chain_buf_pool = NULL;
4785         }
4786
4787         kfree(mrioc->chain_sgl_list);
4788         mrioc->chain_sgl_list = NULL;
4789
4790         if (mrioc->admin_reply_base) {
4791                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4792                     mrioc->admin_reply_base, mrioc->admin_reply_dma);
4793                 mrioc->admin_reply_base = NULL;
4794         }
4795         if (mrioc->admin_req_base) {
4796                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4797                     mrioc->admin_req_base, mrioc->admin_req_dma);
4798                 mrioc->admin_req_base = NULL;
4799         }
4800
4801         if (mrioc->pel_seqnum_virt) {
4802                 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4803                     mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4804                 mrioc->pel_seqnum_virt = NULL;
4805         }
4806
4807         for (i = 0; i < MPI3MR_MAX_NUM_HDB; i++) {
4808                 diag_buffer = &mrioc->diag_buffers[i];
4809                 if (diag_buffer->addr) {
4810                         dma_free_coherent(&mrioc->pdev->dev,
4811                             diag_buffer->size, diag_buffer->addr,
4812                             diag_buffer->dma_addr);
4813                         diag_buffer->addr = NULL;
4814                         diag_buffer->size = 0;
4815                         diag_buffer->type = 0;
4816                         diag_buffer->status = 0;
4817                 }
4818         }
4819
4820         kfree(mrioc->throttle_groups);
4821         mrioc->throttle_groups = NULL;
4822
4823         kfree(mrioc->logdata_buf);
4824         mrioc->logdata_buf = NULL;
4825
4826 }
4827
4828 /**
4829  * mpi3mr_issue_ioc_shutdown - shutdown controller
4830  * @mrioc: Adapter instance reference
4831  *
4832  * Send shutodwn notification to the controller and wait for the
4833  * shutdown_timeout for it to be completed.
4834  *
4835  * Return: Nothing.
4836  */
4837 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4838 {
4839         u32 ioc_config, ioc_status;
4840         u8 retval = 1;
4841         u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4842
4843         ioc_info(mrioc, "Issuing shutdown Notification\n");
4844         if (mrioc->unrecoverable) {
4845                 ioc_warn(mrioc,
4846                     "IOC is unrecoverable shutdown is not issued\n");
4847                 return;
4848         }
4849         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4850         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4851             == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4852                 ioc_info(mrioc, "shutdown already in progress\n");
4853                 return;
4854         }
4855
4856         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4857         ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4858         ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4859
4860         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4861
4862         if (mrioc->facts.shutdown_timeout)
4863                 timeout = mrioc->facts.shutdown_timeout * 10;
4864
4865         do {
4866                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4867                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4868                     == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4869                         retval = 0;
4870                         break;
4871                 }
4872                 msleep(100);
4873         } while (--timeout);
4874
4875         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4876         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4877
4878         if (retval) {
4879                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4880                     == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4881                         ioc_warn(mrioc,
4882                             "shutdown still in progress after timeout\n");
4883         }
4884
4885         ioc_info(mrioc,
4886             "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4887             (!retval) ? "successful" : "failed", ioc_status,
4888             ioc_config);
4889 }
4890
4891 /**
4892  * mpi3mr_cleanup_ioc - Cleanup controller
4893  * @mrioc: Adapter instance reference
4894  *
4895  * controller cleanup handler, Message unit reset or soft reset
4896  * and shutdown notification is issued to the controller.
4897  *
4898  * Return: Nothing.
4899  */
4900 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4901 {
4902         enum mpi3mr_iocstate ioc_state;
4903
4904         dprint_exit(mrioc, "cleaning up the controller\n");
4905         mpi3mr_ioc_disable_intr(mrioc);
4906
4907         ioc_state = mpi3mr_get_iocstate(mrioc);
4908
4909         if (!mrioc->unrecoverable && !mrioc->reset_in_progress &&
4910             !mrioc->pci_err_recovery &&
4911             (ioc_state == MRIOC_STATE_READY)) {
4912                 if (mpi3mr_issue_and_process_mur(mrioc,
4913                     MPI3MR_RESET_FROM_CTLR_CLEANUP))
4914                         mpi3mr_issue_reset(mrioc,
4915                             MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4916                             MPI3MR_RESET_FROM_MUR_FAILURE);
4917                 mpi3mr_issue_ioc_shutdown(mrioc);
4918         }
4919         dprint_exit(mrioc, "controller cleanup completed\n");
4920 }
4921
4922 /**
4923  * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4924  * @mrioc: Adapter instance reference
4925  * @cmdptr: Internal command tracker
4926  *
4927  * Complete an internal driver commands with state indicating it
4928  * is completed due to reset.
4929  *
4930  * Return: Nothing.
4931  */
4932 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4933         struct mpi3mr_drv_cmd *cmdptr)
4934 {
4935         if (cmdptr->state & MPI3MR_CMD_PENDING) {
4936                 cmdptr->state |= MPI3MR_CMD_RESET;
4937                 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4938                 if (cmdptr->is_waiting) {
4939                         complete(&cmdptr->done);
4940                         cmdptr->is_waiting = 0;
4941                 } else if (cmdptr->callback)
4942                         cmdptr->callback(mrioc, cmdptr);
4943         }
4944 }
4945
4946 /**
4947  * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4948  * @mrioc: Adapter instance reference
4949  *
4950  * Flush all internal driver commands post reset
4951  *
4952  * Return: Nothing.
4953  */
4954 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4955 {
4956         struct mpi3mr_drv_cmd *cmdptr;
4957         u8 i;
4958
4959         cmdptr = &mrioc->init_cmds;
4960         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4961
4962         cmdptr = &mrioc->cfg_cmds;
4963         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4964
4965         cmdptr = &mrioc->bsg_cmds;
4966         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4967         cmdptr = &mrioc->host_tm_cmds;
4968         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4969
4970         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4971                 cmdptr = &mrioc->dev_rmhs_cmds[i];
4972                 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4973         }
4974
4975         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4976                 cmdptr = &mrioc->evtack_cmds[i];
4977                 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4978         }
4979
4980         cmdptr = &mrioc->pel_cmds;
4981         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4982
4983         cmdptr = &mrioc->pel_abort_cmd;
4984         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4985
4986         cmdptr = &mrioc->transport_cmds;
4987         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4988 }
4989
4990 /**
4991  * mpi3mr_pel_wait_post - Issue PEL Wait
4992  * @mrioc: Adapter instance reference
4993  * @drv_cmd: Internal command tracker
4994  *
4995  * Issue PEL Wait MPI request through admin queue and return.
4996  *
4997  * Return: Nothing.
4998  */
4999 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
5000         struct mpi3mr_drv_cmd *drv_cmd)
5001 {
5002         struct mpi3_pel_req_action_wait pel_wait;
5003
5004         mrioc->pel_abort_requested = false;
5005
5006         memset(&pel_wait, 0, sizeof(pel_wait));
5007         drv_cmd->state = MPI3MR_CMD_PENDING;
5008         drv_cmd->is_waiting = 0;
5009         drv_cmd->callback = mpi3mr_pel_wait_complete;
5010         drv_cmd->ioc_status = 0;
5011         drv_cmd->ioc_loginfo = 0;
5012         pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
5013         pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
5014         pel_wait.action = MPI3_PEL_ACTION_WAIT;
5015         pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
5016         pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
5017         pel_wait.class = cpu_to_le16(mrioc->pel_class);
5018         pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
5019         dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
5020             mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
5021
5022         if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
5023                 dprint_bsg_err(mrioc,
5024                             "Issuing PELWait: Admin post failed\n");
5025                 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5026                 drv_cmd->callback = NULL;
5027                 drv_cmd->retry_count = 0;
5028                 mrioc->pel_enabled = false;
5029         }
5030 }
5031
5032 /**
5033  * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
5034  * @mrioc: Adapter instance reference
5035  * @drv_cmd: Internal command tracker
5036  *
5037  * Issue PEL get sequence number MPI request through admin queue
5038  * and return.
5039  *
5040  * Return: 0 on success, non-zero on failure.
5041  */
5042 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
5043         struct mpi3mr_drv_cmd *drv_cmd)
5044 {
5045         struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
5046         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5047         int retval = 0;
5048
5049         memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
5050         mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
5051         mrioc->pel_cmds.is_waiting = 0;
5052         mrioc->pel_cmds.ioc_status = 0;
5053         mrioc->pel_cmds.ioc_loginfo = 0;
5054         mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
5055         pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
5056         pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
5057         pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
5058         mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
5059             mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
5060
5061         retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
5062                         sizeof(pel_getseq_req), 0);
5063         if (retval) {
5064                 if (drv_cmd) {
5065                         drv_cmd->state = MPI3MR_CMD_NOTUSED;
5066                         drv_cmd->callback = NULL;
5067                         drv_cmd->retry_count = 0;
5068                 }
5069                 mrioc->pel_enabled = false;
5070         }
5071
5072         return retval;
5073 }
5074
5075 /**
5076  * mpi3mr_pel_wait_complete - PELWait Completion callback
5077  * @mrioc: Adapter instance reference
5078  * @drv_cmd: Internal command tracker
5079  *
5080  * This is a callback handler for the PELWait request and
5081  * firmware completes a PELWait request when it is aborted or a
5082  * new PEL entry is available. This sends AEN to the application
5083  * and if the PELwait completion is not due to PELAbort then
5084  * this will send a request for new PEL Sequence number
5085  *
5086  * Return: Nothing.
5087  */
5088 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
5089         struct mpi3mr_drv_cmd *drv_cmd)
5090 {
5091         struct mpi3_pel_reply *pel_reply = NULL;
5092         u16 ioc_status, pe_log_status;
5093         bool do_retry = false;
5094
5095         if (drv_cmd->state & MPI3MR_CMD_RESET)
5096                 goto cleanup_drv_cmd;
5097
5098         ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5099         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5100                 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
5101                         __func__, ioc_status, drv_cmd->ioc_loginfo);
5102                 dprint_bsg_err(mrioc,
5103                     "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
5104                     ioc_status, drv_cmd->ioc_loginfo);
5105                 do_retry = true;
5106         }
5107
5108         if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
5109                 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
5110
5111         if (!pel_reply) {
5112                 dprint_bsg_err(mrioc,
5113                     "pel_wait: failed due to no reply\n");
5114                 goto out_failed;
5115         }
5116
5117         pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
5118         if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
5119             (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
5120                 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
5121                         __func__, pe_log_status);
5122                 dprint_bsg_err(mrioc,
5123                     "pel_wait: failed due to pel_log_status(0x%04x)\n",
5124                     pe_log_status);
5125                 do_retry = true;
5126         }
5127
5128         if (do_retry) {
5129                 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
5130                         drv_cmd->retry_count++;
5131                         dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
5132                             drv_cmd->retry_count);
5133                         mpi3mr_pel_wait_post(mrioc, drv_cmd);
5134                         return;
5135                 }
5136                 dprint_bsg_err(mrioc,
5137                     "pel_wait: failed after all retries(%d)\n",
5138                     drv_cmd->retry_count);
5139                 goto out_failed;
5140         }
5141         atomic64_inc(&event_counter);
5142         if (!mrioc->pel_abort_requested) {
5143                 mrioc->pel_cmds.retry_count = 0;
5144                 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
5145         }
5146
5147         return;
5148 out_failed:
5149         mrioc->pel_enabled = false;
5150 cleanup_drv_cmd:
5151         drv_cmd->state = MPI3MR_CMD_NOTUSED;
5152         drv_cmd->callback = NULL;
5153         drv_cmd->retry_count = 0;
5154 }
5155
5156 /**
5157  * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
5158  * @mrioc: Adapter instance reference
5159  * @drv_cmd: Internal command tracker
5160  *
5161  * This is a callback handler for the PEL get sequence number
5162  * request and a new PEL wait request will be issued to the
5163  * firmware from this
5164  *
5165  * Return: Nothing.
5166  */
5167 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
5168         struct mpi3mr_drv_cmd *drv_cmd)
5169 {
5170         struct mpi3_pel_reply *pel_reply = NULL;
5171         struct mpi3_pel_seq *pel_seqnum_virt;
5172         u16 ioc_status;
5173         bool do_retry = false;
5174
5175         pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
5176
5177         if (drv_cmd->state & MPI3MR_CMD_RESET)
5178                 goto cleanup_drv_cmd;
5179
5180         ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5181         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5182                 dprint_bsg_err(mrioc,
5183                     "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
5184                     ioc_status, drv_cmd->ioc_loginfo);
5185                 do_retry = true;
5186         }
5187
5188         if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
5189                 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
5190         if (!pel_reply) {
5191                 dprint_bsg_err(mrioc,
5192                     "pel_get_seqnum: failed due to no reply\n");
5193                 goto out_failed;
5194         }
5195
5196         if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
5197                 dprint_bsg_err(mrioc,
5198                     "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
5199                     le16_to_cpu(pel_reply->pe_log_status));
5200                 do_retry = true;
5201         }
5202
5203         if (do_retry) {
5204                 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
5205                         drv_cmd->retry_count++;
5206                         dprint_bsg_err(mrioc,
5207                             "pel_get_seqnum: retrying(%d)\n",
5208                             drv_cmd->retry_count);
5209                         mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
5210                         return;
5211                 }
5212
5213                 dprint_bsg_err(mrioc,
5214                     "pel_get_seqnum: failed after all retries(%d)\n",
5215                     drv_cmd->retry_count);
5216                 goto out_failed;
5217         }
5218         mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
5219         drv_cmd->retry_count = 0;
5220         mpi3mr_pel_wait_post(mrioc, drv_cmd);
5221
5222         return;
5223 out_failed:
5224         mrioc->pel_enabled = false;
5225 cleanup_drv_cmd:
5226         drv_cmd->state = MPI3MR_CMD_NOTUSED;
5227         drv_cmd->callback = NULL;
5228         drv_cmd->retry_count = 0;
5229 }
5230
5231 /**
5232  * mpi3mr_soft_reset_handler - Reset the controller
5233  * @mrioc: Adapter instance reference
5234  * @reset_reason: Reset reason code
5235  * @snapdump: Flag to generate snapdump in firmware or not
5236  *
5237  * This is an handler for recovering controller by issuing soft
5238  * reset are diag fault reset.  This is a blocking function and
5239  * when one reset is executed if any other resets they will be
5240  * blocked. All BSG requests will be blocked during the reset. If
5241  * controller reset is successful then the controller will be
5242  * reinitalized, otherwise the controller will be marked as not
5243  * recoverable
5244  *
5245  * In snapdump bit is set, the controller is issued with diag
5246  * fault reset so that the firmware can create a snap dump and
5247  * post that the firmware will result in F000 fault and the
5248  * driver will issue soft reset to recover from that.
5249  *
5250  * Return: 0 on success, non-zero on failure.
5251  */
5252 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
5253         u16 reset_reason, u8 snapdump)
5254 {
5255         int retval = 0, i;
5256         unsigned long flags;
5257         u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
5258         union mpi3mr_trigger_data trigger_data;
5259
5260         /* Block the reset handler until diag save in progress*/
5261         dprint_reset(mrioc,
5262             "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
5263             mrioc->diagsave_timeout);
5264         while (mrioc->diagsave_timeout)
5265                 ssleep(1);
5266         /*
5267          * Block new resets until the currently executing one is finished and
5268          * return the status of the existing reset for all blocked resets
5269          */
5270         dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
5271         if (!mutex_trylock(&mrioc->reset_mutex)) {
5272                 ioc_info(mrioc,
5273                     "controller reset triggered by %s is blocked due to another reset in progress\n",
5274                     mpi3mr_reset_rc_name(reset_reason));
5275                 do {
5276                         ssleep(1);
5277                 } while (mrioc->reset_in_progress == 1);
5278                 ioc_info(mrioc,
5279                     "returning previous reset result(%d) for the reset triggered by %s\n",
5280                     mrioc->prev_reset_result,
5281                     mpi3mr_reset_rc_name(reset_reason));
5282                 return mrioc->prev_reset_result;
5283         }
5284         ioc_info(mrioc, "controller reset is triggered by %s\n",
5285             mpi3mr_reset_rc_name(reset_reason));
5286
5287         mrioc->device_refresh_on = 0;
5288         mrioc->reset_in_progress = 1;
5289         mrioc->stop_bsgs = 1;
5290         mrioc->prev_reset_result = -1;
5291         memset(&trigger_data, 0, sizeof(trigger_data));
5292
5293         if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
5294             (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
5295             (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
5296                 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5297                     MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0);
5298                 dprint_reset(mrioc,
5299                     "soft_reset_handler: releasing host diagnostic buffers\n");
5300                 mpi3mr_release_diag_bufs(mrioc, 0);
5301                 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5302                         mrioc->event_masks[i] = -1;
5303
5304                 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
5305                 mpi3mr_issue_event_notification(mrioc);
5306         }
5307
5308         mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
5309
5310         mpi3mr_ioc_disable_intr(mrioc);
5311
5312         if (snapdump) {
5313                 mpi3mr_set_diagsave(mrioc);
5314                 retval = mpi3mr_issue_reset(mrioc,
5315                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
5316                 if (!retval) {
5317                         trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
5318                                       MPI3_SYSIF_FAULT_CODE_MASK);
5319                         do {
5320                                 host_diagnostic =
5321                                     readl(&mrioc->sysif_regs->host_diagnostic);
5322                                 if (!(host_diagnostic &
5323                                     MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
5324                                         break;
5325                                 msleep(100);
5326                         } while (--timeout);
5327                         mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5328                             MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
5329                 }
5330         }
5331
5332         retval = mpi3mr_issue_reset(mrioc,
5333             MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
5334         if (retval) {
5335                 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
5336                 goto out;
5337         }
5338         if (mrioc->num_io_throttle_group !=
5339             mrioc->facts.max_io_throttle_group) {
5340                 ioc_err(mrioc,
5341                     "max io throttle group doesn't match old(%d), new(%d)\n",
5342                     mrioc->num_io_throttle_group,
5343                     mrioc->facts.max_io_throttle_group);
5344                 retval = -EPERM;
5345                 goto out;
5346         }
5347
5348         mpi3mr_flush_delayed_cmd_lists(mrioc);
5349         mpi3mr_flush_drv_cmds(mrioc);
5350         bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
5351         bitmap_clear(mrioc->removepend_bitmap, 0,
5352                      mrioc->dev_handle_bitmap_bits);
5353         bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
5354         mpi3mr_flush_host_io(mrioc);
5355         mpi3mr_cleanup_fwevt_list(mrioc);
5356         mpi3mr_invalidate_devhandles(mrioc);
5357         mpi3mr_free_enclosure_list(mrioc);
5358
5359         if (mrioc->prepare_for_reset) {
5360                 mrioc->prepare_for_reset = 0;
5361                 mrioc->prepare_for_reset_timeout_counter = 0;
5362         }
5363         mpi3mr_memset_buffers(mrioc);
5364         mpi3mr_release_diag_bufs(mrioc, 1);
5365         mrioc->fw_release_trigger_active = false;
5366         mrioc->trace_release_trigger_active = false;
5367         mrioc->snapdump_trigger_active = false;
5368         mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5369             MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0);
5370
5371         dprint_reset(mrioc,
5372             "soft_reset_handler: reinitializing the controller\n");
5373         retval = mpi3mr_reinit_ioc(mrioc, 0);
5374         if (retval) {
5375                 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
5376                     mrioc->name, reset_reason);
5377                 goto out;
5378         }
5379         ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
5380
5381 out:
5382         if (!retval) {
5383                 mrioc->diagsave_timeout = 0;
5384                 mrioc->reset_in_progress = 0;
5385                 mrioc->pel_abort_requested = 0;
5386                 if (mrioc->pel_enabled) {
5387                         mrioc->pel_cmds.retry_count = 0;
5388                         mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
5389                 }
5390
5391                 mrioc->device_refresh_on = 0;
5392
5393                 mrioc->ts_update_counter = 0;
5394                 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
5395                 if (mrioc->watchdog_work_q)
5396                         queue_delayed_work(mrioc->watchdog_work_q,
5397                             &mrioc->watchdog_work,
5398                             msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
5399                 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
5400                 mrioc->stop_bsgs = 0;
5401                 if (mrioc->pel_enabled)
5402                         atomic64_inc(&event_counter);
5403         } else {
5404                 mpi3mr_issue_reset(mrioc,
5405                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
5406                 mrioc->device_refresh_on = 0;
5407                 mrioc->unrecoverable = 1;
5408                 mrioc->reset_in_progress = 0;
5409                 mrioc->stop_bsgs = 0;
5410                 retval = -1;
5411                 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
5412         }
5413         mrioc->prev_reset_result = retval;
5414         mutex_unlock(&mrioc->reset_mutex);
5415         ioc_info(mrioc, "controller reset is %s\n",
5416             ((retval == 0) ? "successful" : "failed"));
5417         return retval;
5418 }
5419
5420 /**
5421  * mpi3mr_post_cfg_req - Issue config requests and wait
5422  * @mrioc: Adapter instance reference
5423  * @cfg_req: Configuration request
5424  * @timeout: Timeout in seconds
5425  * @ioc_status: Pointer to return ioc status
5426  *
5427  * A generic function for posting MPI3 configuration request to
5428  * the firmware. This blocks for the completion of request for
5429  * timeout seconds and if the request times out this function
5430  * faults the controller with proper reason code.
5431  *
5432  * On successful completion of the request this function returns
5433  * appropriate ioc status from the firmware back to the caller.
5434  *
5435  * Return: 0 on success, non-zero on failure.
5436  */
5437 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5438         struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5439 {
5440         int retval = 0;
5441
5442         mutex_lock(&mrioc->cfg_cmds.mutex);
5443         if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5444                 retval = -1;
5445                 ioc_err(mrioc, "sending config request failed due to command in use\n");
5446                 mutex_unlock(&mrioc->cfg_cmds.mutex);
5447                 goto out;
5448         }
5449         mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5450         mrioc->cfg_cmds.is_waiting = 1;
5451         mrioc->cfg_cmds.callback = NULL;
5452         mrioc->cfg_cmds.ioc_status = 0;
5453         mrioc->cfg_cmds.ioc_loginfo = 0;
5454
5455         cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5456         cfg_req->function = MPI3_FUNCTION_CONFIG;
5457
5458         init_completion(&mrioc->cfg_cmds.done);
5459         dprint_cfg_info(mrioc, "posting config request\n");
5460         if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5461                 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5462                     "mpi3_cfg_req");
5463         retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5464         if (retval) {
5465                 ioc_err(mrioc, "posting config request failed\n");
5466                 goto out_unlock;
5467         }
5468         wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5469         if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5470                 mpi3mr_check_rh_fault_ioc(mrioc,
5471                     MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5472                 ioc_err(mrioc, "config request timed out\n");
5473                 retval = -1;
5474                 goto out_unlock;
5475         }
5476         *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5477         if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5478                 dprint_cfg_err(mrioc,
5479                     "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5480                     *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5481
5482 out_unlock:
5483         mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5484         mutex_unlock(&mrioc->cfg_cmds.mutex);
5485
5486 out:
5487         return retval;
5488 }
5489
5490 /**
5491  * mpi3mr_process_cfg_req - config page request processor
5492  * @mrioc: Adapter instance reference
5493  * @cfg_req: Configuration request
5494  * @cfg_hdr: Configuration page header
5495  * @timeout: Timeout in seconds
5496  * @ioc_status: Pointer to return ioc status
5497  * @cfg_buf: Memory pointer to copy config page or header
5498  * @cfg_buf_sz: Size of the memory to get config page or header
5499  *
5500  * This is handler for config page read, write and config page
5501  * header read operations.
5502  *
5503  * This function expects the cfg_req to be populated with page
5504  * type, page number, action for the header read and with page
5505  * address for all other operations.
5506  *
5507  * The cfg_hdr can be passed as null for reading required header
5508  * details for read/write pages the cfg_hdr should point valid
5509  * configuration page header.
5510  *
5511  * This allocates dmaable memory based on the size of the config
5512  * buffer and set the SGE of the cfg_req.
5513  *
5514  * For write actions, the config page data has to be passed in
5515  * the cfg_buf and size of the data has to be mentioned in the
5516  * cfg_buf_sz.
5517  *
5518  * For read/header actions, on successful completion of the
5519  * request with successful ioc_status the data will be copied
5520  * into the cfg_buf limited to a minimum of actual page size and
5521  * cfg_buf_sz
5522  *
5523  *
5524  * Return: 0 on success, non-zero on failure.
5525  */
5526 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5527         struct mpi3_config_request *cfg_req,
5528         struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5529         void *cfg_buf, u32 cfg_buf_sz)
5530 {
5531         struct dma_memory_desc mem_desc;
5532         int retval = -1;
5533         u8 invalid_action = 0;
5534         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5535
5536         memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5537
5538         if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5539                 mem_desc.size = sizeof(struct mpi3_config_page_header);
5540         else {
5541                 if (!cfg_hdr) {
5542                         ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5543                             cfg_req->action, cfg_req->page_type,
5544                             cfg_req->page_number);
5545                         goto out;
5546                 }
5547                 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5548                 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5549                         if (cfg_req->action
5550                             != MPI3_CONFIG_ACTION_READ_CURRENT)
5551                                 invalid_action = 1;
5552                         break;
5553                 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5554                         if ((cfg_req->action ==
5555                              MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5556                             (cfg_req->action ==
5557                              MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5558                                 invalid_action = 1;
5559                         break;
5560                 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5561                 default:
5562                         break;
5563                 }
5564                 if (invalid_action) {
5565                         ioc_err(mrioc,
5566                             "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5567                             cfg_req->action, cfg_req->page_type,
5568                             cfg_req->page_number, cfg_hdr->page_attribute);
5569                         goto out;
5570                 }
5571                 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5572                 cfg_req->page_length = cfg_hdr->page_length;
5573                 cfg_req->page_version = cfg_hdr->page_version;
5574         }
5575
5576         mem_desc.addr = dma_alloc_coherent(&mrioc->pdev->dev,
5577                 mem_desc.size, &mem_desc.dma_addr, GFP_KERNEL);
5578
5579         if (!mem_desc.addr)
5580                 return retval;
5581
5582         mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5583             mem_desc.dma_addr);
5584
5585         if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5586             (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5587                 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5588                     cfg_buf_sz));
5589                 dprint_cfg_info(mrioc, "config buffer to be written\n");
5590                 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5591                         dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5592         }
5593
5594         if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5595                 goto out;
5596
5597         retval = 0;
5598         if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5599             (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5600             (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5601                 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5602                     cfg_buf_sz));
5603                 dprint_cfg_info(mrioc, "config buffer read\n");
5604                 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5605                         dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5606         }
5607
5608 out:
5609         if (mem_desc.addr) {
5610                 dma_free_coherent(&mrioc->pdev->dev, mem_desc.size,
5611                         mem_desc.addr, mem_desc.dma_addr);
5612                 mem_desc.addr = NULL;
5613         }
5614
5615         return retval;
5616 }
5617
5618 /**
5619  * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5620  * @mrioc: Adapter instance reference
5621  * @ioc_status: Pointer to return ioc status
5622  * @dev_pg0: Pointer to return device page 0
5623  * @pg_sz: Size of the memory allocated to the page pointer
5624  * @form: The form to be used for addressing the page
5625  * @form_spec: Form specific information like device handle
5626  *
5627  * This is handler for config page read for a specific device
5628  * page0. The ioc_status has the controller returned ioc_status.
5629  * This routine doesn't check ioc_status to decide whether the
5630  * page read is success or not and it is the callers
5631  * responsibility.
5632  *
5633  * Return: 0 on success, non-zero on failure.
5634  */
5635 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5636         struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5637 {
5638         struct mpi3_config_page_header cfg_hdr;
5639         struct mpi3_config_request cfg_req;
5640         u32 page_address;
5641
5642         memset(dev_pg0, 0, pg_sz);
5643         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5644         memset(&cfg_req, 0, sizeof(cfg_req));
5645
5646         cfg_req.function = MPI3_FUNCTION_CONFIG;
5647         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5648         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5649         cfg_req.page_number = 0;
5650         cfg_req.page_address = 0;
5651
5652         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5653             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5654                 ioc_err(mrioc, "device page0 header read failed\n");
5655                 goto out_failed;
5656         }
5657         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5658                 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5659                     *ioc_status);
5660                 goto out_failed;
5661         }
5662         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5663         page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5664             (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5665         cfg_req.page_address = cpu_to_le32(page_address);
5666         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5667             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5668                 ioc_err(mrioc, "device page0 read failed\n");
5669                 goto out_failed;
5670         }
5671         return 0;
5672 out_failed:
5673         return -1;
5674 }
5675
5676
5677 /**
5678  * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5679  * @mrioc: Adapter instance reference
5680  * @ioc_status: Pointer to return ioc status
5681  * @phy_pg0: Pointer to return SAS Phy page 0
5682  * @pg_sz: Size of the memory allocated to the page pointer
5683  * @form: The form to be used for addressing the page
5684  * @form_spec: Form specific information like phy number
5685  *
5686  * This is handler for config page read for a specific SAS Phy
5687  * page0. The ioc_status has the controller returned ioc_status.
5688  * This routine doesn't check ioc_status to decide whether the
5689  * page read is success or not and it is the callers
5690  * responsibility.
5691  *
5692  * Return: 0 on success, non-zero on failure.
5693  */
5694 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5695         struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5696         u32 form_spec)
5697 {
5698         struct mpi3_config_page_header cfg_hdr;
5699         struct mpi3_config_request cfg_req;
5700         u32 page_address;
5701
5702         memset(phy_pg0, 0, pg_sz);
5703         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5704         memset(&cfg_req, 0, sizeof(cfg_req));
5705
5706         cfg_req.function = MPI3_FUNCTION_CONFIG;
5707         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5708         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5709         cfg_req.page_number = 0;
5710         cfg_req.page_address = 0;
5711
5712         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5713             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5714                 ioc_err(mrioc, "sas phy page0 header read failed\n");
5715                 goto out_failed;
5716         }
5717         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5718                 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5719                     *ioc_status);
5720                 goto out_failed;
5721         }
5722         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5723         page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5724             (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5725         cfg_req.page_address = cpu_to_le32(page_address);
5726         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5727             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5728                 ioc_err(mrioc, "sas phy page0 read failed\n");
5729                 goto out_failed;
5730         }
5731         return 0;
5732 out_failed:
5733         return -1;
5734 }
5735
5736 /**
5737  * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5738  * @mrioc: Adapter instance reference
5739  * @ioc_status: Pointer to return ioc status
5740  * @phy_pg1: Pointer to return SAS Phy page 1
5741  * @pg_sz: Size of the memory allocated to the page pointer
5742  * @form: The form to be used for addressing the page
5743  * @form_spec: Form specific information like phy number
5744  *
5745  * This is handler for config page read for a specific SAS Phy
5746  * page1. The ioc_status has the controller returned ioc_status.
5747  * This routine doesn't check ioc_status to decide whether the
5748  * page read is success or not and it is the callers
5749  * responsibility.
5750  *
5751  * Return: 0 on success, non-zero on failure.
5752  */
5753 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5754         struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5755         u32 form_spec)
5756 {
5757         struct mpi3_config_page_header cfg_hdr;
5758         struct mpi3_config_request cfg_req;
5759         u32 page_address;
5760
5761         memset(phy_pg1, 0, pg_sz);
5762         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5763         memset(&cfg_req, 0, sizeof(cfg_req));
5764
5765         cfg_req.function = MPI3_FUNCTION_CONFIG;
5766         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5767         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5768         cfg_req.page_number = 1;
5769         cfg_req.page_address = 0;
5770
5771         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5772             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5773                 ioc_err(mrioc, "sas phy page1 header read failed\n");
5774                 goto out_failed;
5775         }
5776         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5777                 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5778                     *ioc_status);
5779                 goto out_failed;
5780         }
5781         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5782         page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5783             (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5784         cfg_req.page_address = cpu_to_le32(page_address);
5785         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5786             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5787                 ioc_err(mrioc, "sas phy page1 read failed\n");
5788                 goto out_failed;
5789         }
5790         return 0;
5791 out_failed:
5792         return -1;
5793 }
5794
5795
5796 /**
5797  * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5798  * @mrioc: Adapter instance reference
5799  * @ioc_status: Pointer to return ioc status
5800  * @exp_pg0: Pointer to return SAS Expander page 0
5801  * @pg_sz: Size of the memory allocated to the page pointer
5802  * @form: The form to be used for addressing the page
5803  * @form_spec: Form specific information like device handle
5804  *
5805  * This is handler for config page read for a specific SAS
5806  * Expander page0. The ioc_status has the controller returned
5807  * ioc_status. This routine doesn't check ioc_status to decide
5808  * whether the page read is success or not and it is the callers
5809  * responsibility.
5810  *
5811  * Return: 0 on success, non-zero on failure.
5812  */
5813 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5814         struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5815         u32 form_spec)
5816 {
5817         struct mpi3_config_page_header cfg_hdr;
5818         struct mpi3_config_request cfg_req;
5819         u32 page_address;
5820
5821         memset(exp_pg0, 0, pg_sz);
5822         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5823         memset(&cfg_req, 0, sizeof(cfg_req));
5824
5825         cfg_req.function = MPI3_FUNCTION_CONFIG;
5826         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5827         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5828         cfg_req.page_number = 0;
5829         cfg_req.page_address = 0;
5830
5831         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5832             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5833                 ioc_err(mrioc, "expander page0 header read failed\n");
5834                 goto out_failed;
5835         }
5836         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5837                 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5838                     *ioc_status);
5839                 goto out_failed;
5840         }
5841         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5842         page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5843             (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5844             MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5845         cfg_req.page_address = cpu_to_le32(page_address);
5846         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5847             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5848                 ioc_err(mrioc, "expander page0 read failed\n");
5849                 goto out_failed;
5850         }
5851         return 0;
5852 out_failed:
5853         return -1;
5854 }
5855
5856 /**
5857  * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5858  * @mrioc: Adapter instance reference
5859  * @ioc_status: Pointer to return ioc status
5860  * @exp_pg1: Pointer to return SAS Expander page 1
5861  * @pg_sz: Size of the memory allocated to the page pointer
5862  * @form: The form to be used for addressing the page
5863  * @form_spec: Form specific information like phy number
5864  *
5865  * This is handler for config page read for a specific SAS
5866  * Expander page1. The ioc_status has the controller returned
5867  * ioc_status. This routine doesn't check ioc_status to decide
5868  * whether the page read is success or not and it is the callers
5869  * responsibility.
5870  *
5871  * Return: 0 on success, non-zero on failure.
5872  */
5873 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5874         struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5875         u32 form_spec)
5876 {
5877         struct mpi3_config_page_header cfg_hdr;
5878         struct mpi3_config_request cfg_req;
5879         u32 page_address;
5880
5881         memset(exp_pg1, 0, pg_sz);
5882         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5883         memset(&cfg_req, 0, sizeof(cfg_req));
5884
5885         cfg_req.function = MPI3_FUNCTION_CONFIG;
5886         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5887         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5888         cfg_req.page_number = 1;
5889         cfg_req.page_address = 0;
5890
5891         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5892             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5893                 ioc_err(mrioc, "expander page1 header read failed\n");
5894                 goto out_failed;
5895         }
5896         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5897                 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5898                     *ioc_status);
5899                 goto out_failed;
5900         }
5901         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5902         page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5903             (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5904             MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5905         cfg_req.page_address = cpu_to_le32(page_address);
5906         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5907             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5908                 ioc_err(mrioc, "expander page1 read failed\n");
5909                 goto out_failed;
5910         }
5911         return 0;
5912 out_failed:
5913         return -1;
5914 }
5915
5916 /**
5917  * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
5918  * @mrioc: Adapter instance reference
5919  * @ioc_status: Pointer to return ioc status
5920  * @encl_pg0: Pointer to return Enclosure page 0
5921  * @pg_sz: Size of the memory allocated to the page pointer
5922  * @form: The form to be used for addressing the page
5923  * @form_spec: Form specific information like device handle
5924  *
5925  * This is handler for config page read for a specific Enclosure
5926  * page0. The ioc_status has the controller returned ioc_status.
5927  * This routine doesn't check ioc_status to decide whether the
5928  * page read is success or not and it is the callers
5929  * responsibility.
5930  *
5931  * Return: 0 on success, non-zero on failure.
5932  */
5933 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5934         struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
5935         u32 form_spec)
5936 {
5937         struct mpi3_config_page_header cfg_hdr;
5938         struct mpi3_config_request cfg_req;
5939         u32 page_address;
5940
5941         memset(encl_pg0, 0, pg_sz);
5942         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5943         memset(&cfg_req, 0, sizeof(cfg_req));
5944
5945         cfg_req.function = MPI3_FUNCTION_CONFIG;
5946         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5947         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
5948         cfg_req.page_number = 0;
5949         cfg_req.page_address = 0;
5950
5951         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5952             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5953                 ioc_err(mrioc, "enclosure page0 header read failed\n");
5954                 goto out_failed;
5955         }
5956         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5957                 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
5958                     *ioc_status);
5959                 goto out_failed;
5960         }
5961         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5962         page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
5963             (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
5964         cfg_req.page_address = cpu_to_le32(page_address);
5965         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5966             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
5967                 ioc_err(mrioc, "enclosure page0 read failed\n");
5968                 goto out_failed;
5969         }
5970         return 0;
5971 out_failed:
5972         return -1;
5973 }
5974
5975
5976 /**
5977  * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
5978  * @mrioc: Adapter instance reference
5979  * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
5980  * @pg_sz: Size of the memory allocated to the page pointer
5981  *
5982  * This is handler for config page read for the SAS IO Unit
5983  * page0. This routine checks ioc_status to decide whether the
5984  * page read is success or not.
5985  *
5986  * Return: 0 on success, non-zero on failure.
5987  */
5988 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
5989         struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
5990 {
5991         struct mpi3_config_page_header cfg_hdr;
5992         struct mpi3_config_request cfg_req;
5993         u16 ioc_status = 0;
5994
5995         memset(sas_io_unit_pg0, 0, pg_sz);
5996         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5997         memset(&cfg_req, 0, sizeof(cfg_req));
5998
5999         cfg_req.function = MPI3_FUNCTION_CONFIG;
6000         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6001         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6002         cfg_req.page_number = 0;
6003         cfg_req.page_address = 0;
6004
6005         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6006             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6007                 ioc_err(mrioc, "sas io unit page0 header read failed\n");
6008                 goto out_failed;
6009         }
6010         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6011                 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
6012                     ioc_status);
6013                 goto out_failed;
6014         }
6015         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6016
6017         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6018             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
6019                 ioc_err(mrioc, "sas io unit page0 read failed\n");
6020                 goto out_failed;
6021         }
6022         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6023                 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
6024                     ioc_status);
6025                 goto out_failed;
6026         }
6027         return 0;
6028 out_failed:
6029         return -1;
6030 }
6031
6032 /**
6033  * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
6034  * @mrioc: Adapter instance reference
6035  * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
6036  * @pg_sz: Size of the memory allocated to the page pointer
6037  *
6038  * This is handler for config page read for the SAS IO Unit
6039  * page1. This routine checks ioc_status to decide whether the
6040  * page read is success or not.
6041  *
6042  * Return: 0 on success, non-zero on failure.
6043  */
6044 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
6045         struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
6046 {
6047         struct mpi3_config_page_header cfg_hdr;
6048         struct mpi3_config_request cfg_req;
6049         u16 ioc_status = 0;
6050
6051         memset(sas_io_unit_pg1, 0, pg_sz);
6052         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6053         memset(&cfg_req, 0, sizeof(cfg_req));
6054
6055         cfg_req.function = MPI3_FUNCTION_CONFIG;
6056         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6057         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6058         cfg_req.page_number = 1;
6059         cfg_req.page_address = 0;
6060
6061         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6062             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6063                 ioc_err(mrioc, "sas io unit page1 header read failed\n");
6064                 goto out_failed;
6065         }
6066         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6067                 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
6068                     ioc_status);
6069                 goto out_failed;
6070         }
6071         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6072
6073         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6074             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6075                 ioc_err(mrioc, "sas io unit page1 read failed\n");
6076                 goto out_failed;
6077         }
6078         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6079                 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
6080                     ioc_status);
6081                 goto out_failed;
6082         }
6083         return 0;
6084 out_failed:
6085         return -1;
6086 }
6087
6088 /**
6089  * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
6090  * @mrioc: Adapter instance reference
6091  * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
6092  * @pg_sz: Size of the memory allocated to the page pointer
6093  *
6094  * This is handler for config page write for the SAS IO Unit
6095  * page1. This routine checks ioc_status to decide whether the
6096  * page read is success or not. This will modify both current
6097  * and persistent page.
6098  *
6099  * Return: 0 on success, non-zero on failure.
6100  */
6101 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
6102         struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
6103 {
6104         struct mpi3_config_page_header cfg_hdr;
6105         struct mpi3_config_request cfg_req;
6106         u16 ioc_status = 0;
6107
6108         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6109         memset(&cfg_req, 0, sizeof(cfg_req));
6110
6111         cfg_req.function = MPI3_FUNCTION_CONFIG;
6112         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6113         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6114         cfg_req.page_number = 1;
6115         cfg_req.page_address = 0;
6116
6117         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6118             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6119                 ioc_err(mrioc, "sas io unit page1 header read failed\n");
6120                 goto out_failed;
6121         }
6122         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6123                 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
6124                     ioc_status);
6125                 goto out_failed;
6126         }
6127         cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
6128
6129         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6130             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6131                 ioc_err(mrioc, "sas io unit page1 write current failed\n");
6132                 goto out_failed;
6133         }
6134         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6135                 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
6136                     ioc_status);
6137                 goto out_failed;
6138         }
6139
6140         cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
6141
6142         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6143             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6144                 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
6145                 goto out_failed;
6146         }
6147         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6148                 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
6149                     ioc_status);
6150                 goto out_failed;
6151         }
6152         return 0;
6153 out_failed:
6154         return -1;
6155 }
6156
6157 /**
6158  * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
6159  * @mrioc: Adapter instance reference
6160  * @driver_pg1: Pointer to return Driver page 1
6161  * @pg_sz: Size of the memory allocated to the page pointer
6162  *
6163  * This is handler for config page read for the Driver page1.
6164  * This routine checks ioc_status to decide whether the page
6165  * read is success or not.
6166  *
6167  * Return: 0 on success, non-zero on failure.
6168  */
6169 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
6170         struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
6171 {
6172         struct mpi3_config_page_header cfg_hdr;
6173         struct mpi3_config_request cfg_req;
6174         u16 ioc_status = 0;
6175
6176         memset(driver_pg1, 0, pg_sz);
6177         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6178         memset(&cfg_req, 0, sizeof(cfg_req));
6179
6180         cfg_req.function = MPI3_FUNCTION_CONFIG;
6181         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6182         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
6183         cfg_req.page_number = 1;
6184         cfg_req.page_address = 0;
6185
6186         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6187             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6188                 ioc_err(mrioc, "driver page1 header read failed\n");
6189                 goto out_failed;
6190         }
6191         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6192                 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
6193                     ioc_status);
6194                 goto out_failed;
6195         }
6196         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6197
6198         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6199             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
6200                 ioc_err(mrioc, "driver page1 read failed\n");
6201                 goto out_failed;
6202         }
6203         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6204                 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
6205                     ioc_status);
6206                 goto out_failed;
6207         }
6208         return 0;
6209 out_failed:
6210         return -1;
6211 }
6212
6213 /**
6214  * mpi3mr_cfg_get_driver_pg2 - Read current driver page2
6215  * @mrioc: Adapter instance reference
6216  * @driver_pg2: Pointer to return driver page 2
6217  * @pg_sz: Size of the memory allocated to the page pointer
6218  * @page_action: Page action
6219  *
6220  * This is handler for config page read for the driver page2.
6221  * This routine checks ioc_status to decide whether the page
6222  * read is success or not.
6223  *
6224  * Return: 0 on success, non-zero on failure.
6225  */
6226 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc,
6227         struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_action)
6228 {
6229         struct mpi3_config_page_header cfg_hdr;
6230         struct mpi3_config_request cfg_req;
6231         u16 ioc_status = 0;
6232
6233         memset(driver_pg2, 0, pg_sz);
6234         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6235         memset(&cfg_req, 0, sizeof(cfg_req));
6236
6237         cfg_req.function = MPI3_FUNCTION_CONFIG;
6238         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6239         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
6240         cfg_req.page_number = 2;
6241         cfg_req.page_address = 0;
6242         cfg_req.page_version = MPI3_DRIVER2_PAGEVERSION;
6243
6244         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6245             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6246                 ioc_err(mrioc, "driver page2 header read failed\n");
6247                 goto out_failed;
6248         }
6249         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6250                 ioc_err(mrioc, "driver page2 header read failed with\n"
6251                                "ioc_status(0x%04x)\n",
6252                     ioc_status);
6253                 goto out_failed;
6254         }
6255         cfg_req.action = page_action;
6256
6257         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6258             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg2, pg_sz)) {
6259                 ioc_err(mrioc, "driver page2 read failed\n");
6260                 goto out_failed;
6261         }
6262         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6263                 ioc_err(mrioc, "driver page2 read failed with\n"
6264                                "ioc_status(0x%04x)\n",
6265                     ioc_status);
6266                 goto out_failed;
6267         }
6268         return 0;
6269 out_failed:
6270         return -1;
6271 }
6272