1 // SPDX-License-Identifier: GPL-2.0
3 * R8A779A0 processor support - PFC hardware block.
5 * Copyright (C) 2021 Renesas Electronics Corp.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
10 #include <linux/errno.h>
12 #include <linux/kernel.h>
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
18 #define CPU_ALL_GP(fn, sfx) \
19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(1, 23, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(1, 24, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(1, 25, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(1, 26, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(1, 27, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(1, 28, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \
43 PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \
44 PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \
45 PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \
46 PORT_GP_CFG_25(4, fn, sfx, CFG_FLAGS), \
47 PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \
48 PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \
49 PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
50 PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
52 #define CPU_ALL_NOGP(fn) \
53 PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
54 PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
55 PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
56 PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
59 #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
60 #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
61 #define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0)
62 #define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28)
63 #define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)
64 #define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20)
65 #define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16)
66 #define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12)
67 #define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8)
68 #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
69 #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
70 #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
71 #define GPSR0_6 F_(IRQ0_A, IP0SR0_27_24)
72 #define GPSR0_5 F_(IRQ1_A, IP0SR0_23_20)
73 #define GPSR0_4 F_(IRQ2_A, IP0SR0_19_16)
74 #define GPSR0_3 F_(IRQ3_A, IP0SR0_15_12)
75 #define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
76 #define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
77 #define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
80 #define GPSR1_28 F_(HTX3_A, IP3SR1_19_16)
81 #define GPSR1_27 F_(HCTS3_N_A, IP3SR1_15_12)
82 #define GPSR1_26 F_(HRTS3_N_A, IP3SR1_11_8)
83 #define GPSR1_25 F_(HSCK3_A, IP3SR1_7_4)
84 #define GPSR1_24 F_(HRX3_A, IP3SR1_3_0)
85 #define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
86 #define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
87 #define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
88 #define GPSR1_20 F_(SSI_SD, IP2SR1_19_16)
89 #define GPSR1_19 F_(SSI_WS, IP2SR1_15_12)
90 #define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8)
91 #define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4)
92 #define GPSR1_16 F_(HRX0, IP2SR1_3_0)
93 #define GPSR1_15 F_(HSCK0, IP1SR1_31_28)
94 #define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24)
95 #define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20)
96 #define GPSR1_12 F_(HTX0, IP1SR1_19_16)
97 #define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12)
98 #define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8)
99 #define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4)
100 #define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0)
101 #define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28)
102 #define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24)
103 #define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20)
104 #define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16)
105 #define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)
106 #define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8)
107 #define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4)
108 #define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0)
111 #define GPSR2_19 F_(CANFD7_RX, IP2SR2_15_12)
112 #define GPSR2_18 F_(CANFD7_TX, IP2SR2_11_8)
113 #define GPSR2_17 F_(CANFD4_RX, IP2SR2_7_4)
114 #define GPSR2_16 F_(CANFD4_TX, IP2SR2_3_0)
115 #define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28)
116 #define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24)
117 #define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20)
118 #define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16)
119 #define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
120 #define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
121 #define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
122 #define GPSR2_8 F_(TPU0TO0_A, IP1SR2_3_0)
123 #define GPSR2_7 F_(TPU0TO1_A, IP0SR2_31_28)
124 #define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
125 #define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20)
126 #define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
127 #define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
128 #define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
129 #define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4)
130 #define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
133 #define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20)
134 #define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16)
135 #define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12)
136 #define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8)
137 #define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4)
138 #define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0)
139 #define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28)
140 #define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24)
141 #define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20)
142 #define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16)
143 #define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12)
144 #define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8)
145 #define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4)
146 #define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0)
147 #define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28)
148 #define GPSR3_14 F_(IPC_CLKOUT, IP1SR3_27_24)
149 #define GPSR3_13 F_(IPC_CLKIN, IP1SR3_23_20)
150 #define GPSR3_12 F_(SD_WP, IP1SR3_19_16)
151 #define GPSR3_11 F_(SD_CD, IP1SR3_15_12)
152 #define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8)
153 #define GPSR3_9 F_(MMC_D6, IP1SR3_7_4)
154 #define GPSR3_8 F_(MMC_D7, IP1SR3_3_0)
155 #define GPSR3_7 F_(MMC_D4, IP0SR3_31_28)
156 #define GPSR3_6 F_(MMC_D5, IP0SR3_27_24)
157 #define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20)
158 #define GPSR3_4 F_(MMC_DS, IP0SR3_19_16)
159 #define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12)
160 #define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8)
161 #define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4)
162 #define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)
165 #define GPSR4_24 F_(AVS1, IP3SR4_3_0)
166 #define GPSR4_23 F_(AVS0, IP2SR4_31_28)
167 #define GPSR4_22 F_(PCIE1_CLKREQ_N, IP2SR4_27_24)
168 #define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20)
169 #define GPSR4_20 F_(TSN0_TXCREFCLK, IP2SR4_19_16)
170 #define GPSR4_19 F_(TSN0_TD2, IP2SR4_15_12)
171 #define GPSR4_18 F_(TSN0_TD3, IP2SR4_11_8)
172 #define GPSR4_17 F_(TSN0_RD2, IP2SR4_7_4)
173 #define GPSR4_16 F_(TSN0_RD3, IP2SR4_3_0)
174 #define GPSR4_15 F_(TSN0_TD0, IP1SR4_31_28)
175 #define GPSR4_14 F_(TSN0_TD1, IP1SR4_27_24)
176 #define GPSR4_13 F_(TSN0_RD1, IP1SR4_23_20)
177 #define GPSR4_12 F_(TSN0_TXC, IP1SR4_19_16)
178 #define GPSR4_11 F_(TSN0_RXC, IP1SR4_15_12)
179 #define GPSR4_10 F_(TSN0_RD0, IP1SR4_11_8)
180 #define GPSR4_9 F_(TSN0_TX_CTL, IP1SR4_7_4)
181 #define GPSR4_8 F_(TSN0_AVTP_PPS0, IP1SR4_3_0)
182 #define GPSR4_7 F_(TSN0_RX_CTL, IP0SR4_31_28)
183 #define GPSR4_6 F_(TSN0_AVTP_CAPTURE, IP0SR4_27_24)
184 #define GPSR4_5 F_(TSN0_AVTP_MATCH, IP0SR4_23_20)
185 #define GPSR4_4 F_(TSN0_LINK, IP0SR4_19_16)
186 #define GPSR4_3 F_(TSN0_PHY_INT, IP0SR4_15_12)
187 #define GPSR4_2 F_(TSN0_AVTP_PPS1, IP0SR4_11_8)
188 #define GPSR4_1 F_(TSN0_MDC, IP0SR4_7_4)
189 #define GPSR4_0 F_(TSN0_MDIO, IP0SR4_3_0)
192 #define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16)
193 #define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12)
194 #define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8)
195 #define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4)
196 #define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0)
197 #define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28)
198 #define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24)
199 #define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20)
200 #define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16)
201 #define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12)
202 #define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8)
203 #define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4)
204 #define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0)
205 #define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28)
206 #define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24)
207 #define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20)
208 #define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16)
209 #define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12)
210 #define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8)
211 #define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4)
212 #define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0)
215 #define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
216 #define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
217 #define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
218 #define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
219 #define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
220 #define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
221 #define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
222 #define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
223 #define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
224 #define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
225 #define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
226 #define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
227 #define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
228 #define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
229 #define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
230 #define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
231 #define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
232 #define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
233 #define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
234 #define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
235 #define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
238 #define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
239 #define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
240 #define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
241 #define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
242 #define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
243 #define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
244 #define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
245 #define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
246 #define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
247 #define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
248 #define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
249 #define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
250 #define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
251 #define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
252 #define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
253 #define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
254 #define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
255 #define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
256 #define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
257 #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
258 #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
261 #define GPSR8_13 F_(GP8_13, IP1SR8_23_20)
262 #define GPSR8_12 F_(GP8_12, IP1SR8_19_16)
263 #define GPSR8_11 F_(SDA5, IP1SR8_15_12)
264 #define GPSR8_10 F_(SCL5, IP1SR8_11_8)
265 #define GPSR8_9 F_(SDA4, IP1SR8_7_4)
266 #define GPSR8_8 F_(SCL4, IP1SR8_3_0)
267 #define GPSR8_7 F_(SDA3, IP0SR8_31_28)
268 #define GPSR8_6 F_(SCL3, IP0SR8_27_24)
269 #define GPSR8_5 F_(SDA2, IP0SR8_23_20)
270 #define GPSR8_4 F_(SCL2, IP0SR8_19_16)
271 #define GPSR8_3 F_(SDA1, IP0SR8_15_12)
272 #define GPSR8_2 F_(SCL1, IP0SR8_11_8)
273 #define GPSR8_1 F_(SDA0, IP0SR8_7_4)
274 #define GPSR8_0 F_(SCL0, IP0SR8_3_0)
277 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
278 #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP0SR0_15_12 FM(IRQ3_A) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP0SR0_19_16 FM(IRQ2_A) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP0SR0_23_20 FM(IRQ1_A) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP0SR0_27_24 FM(IRQ0_A) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
288 #define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
298 #define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
304 #define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
314 #define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
324 #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
334 #define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
342 #define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP0SR2_7_4 FM(FXR_TXENA_N_A) FM(CANFD1_RX) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX_A) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX_A) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP0SR2_31_28 FM(TPU0TO1_A) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
352 #define IP1SR2_3_0 FM(TPU0TO0_A) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
362 #define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
369 #define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
379 #define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 #define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 /* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
389 #define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 /* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
399 #define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407 /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
408 #define IP0SR4_3_0 FM(TSN0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409 #define IP0SR4_7_4 FM(TSN0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP0SR4_11_8 FM(TSN0_AVTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411 #define IP0SR4_15_12 FM(TSN0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
412 #define IP0SR4_19_16 FM(TSN0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
413 #define IP0SR4_23_20 FM(TSN0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414 #define IP0SR4_27_24 FM(TSN0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
415 #define IP0SR4_31_28 FM(TSN0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
417 /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
418 #define IP1SR4_3_0 FM(TSN0_AVTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
419 #define IP1SR4_7_4 FM(TSN0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
420 #define IP1SR4_11_8 FM(TSN0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
421 #define IP1SR4_15_12 FM(TSN0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
422 #define IP1SR4_19_16 FM(TSN0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
423 #define IP1SR4_23_20 FM(TSN0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
424 #define IP1SR4_27_24 FM(TSN0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425 #define IP1SR4_31_28 FM(TSN0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
427 /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
428 #define IP2SR4_3_0 FM(TSN0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
429 #define IP2SR4_7_4 FM(TSN0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
430 #define IP2SR4_11_8 FM(TSN0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
431 #define IP2SR4_15_12 FM(TSN0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
432 #define IP2SR4_19_16 FM(TSN0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
433 #define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
434 #define IP2SR4_27_24 FM(PCIE1_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
435 #define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
437 /* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
438 #define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
441 /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
442 #define IP0SR5_3_0 FM(AVB2_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
443 #define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
444 #define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
445 #define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
446 #define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447 #define IP0SR5_23_20 FM(AVB2_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
448 #define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
449 #define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
451 /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
452 #define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
454 #define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
455 #define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
456 #define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
457 #define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
458 #define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
459 #define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
461 /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
462 #define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
463 #define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465 #define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
466 #define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
469 /* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
470 #define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
473 #define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
474 #define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
476 #define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
477 #define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
479 /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
480 #define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
481 #define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
482 #define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
483 #define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
484 #define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
485 #define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
486 #define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
487 #define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
489 /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
490 #define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
491 #define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
492 #define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
493 #define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
494 #define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
497 /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
498 #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499 #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500 #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
501 #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
502 #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503 #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
504 #define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
505 #define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
507 /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
508 #define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
509 #define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
510 #define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
511 #define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
512 #define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
513 #define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
514 #define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
515 #define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
517 /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
518 #define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
519 #define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
520 #define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
521 #define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
522 #define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
525 /* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
526 #define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
527 #define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
528 #define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
529 #define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
530 #define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
531 #define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
532 #define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
533 #define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
535 /* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
536 #define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
537 #define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
538 #define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
539 #define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
540 #define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
541 #define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
543 #define PINMUX_GPSR \
549 GPSR1_24 GPSR3_24 GPSR4_24 \
550 GPSR1_23 GPSR3_23 GPSR4_23 \
551 GPSR1_22 GPSR3_22 GPSR4_22 \
552 GPSR1_21 GPSR3_21 GPSR4_21 \
553 GPSR1_20 GPSR3_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 \
554 GPSR1_19 GPSR2_19 GPSR3_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 \
555 GPSR0_18 GPSR1_18 GPSR2_18 GPSR3_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 \
556 GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 \
557 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 \
558 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \
559 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \
560 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 \
561 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 \
562 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 \
563 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 \
564 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 \
565 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 \
566 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 \
567 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 \
568 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 \
569 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 \
570 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 \
571 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 \
572 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 \
573 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0
575 #define PINMUX_IPSR \
577 FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \
578 FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \
579 FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
580 FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \
581 FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \
582 FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \
583 FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
584 FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \
586 FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
587 FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
588 FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
589 FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
590 FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
591 FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 \
592 FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \
593 FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
595 FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
596 FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
597 FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
598 FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
599 FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \
600 FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \
601 FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \
602 FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \
604 FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \
605 FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \
606 FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \
607 FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \
608 FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \
609 FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \
610 FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 \
611 FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 \
613 FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \
614 FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
615 FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
616 FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
617 FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
618 FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
619 FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
620 FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
622 FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
623 FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
624 FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
625 FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
626 FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
627 FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \
628 FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \
629 FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \
631 FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \
632 FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \
633 FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \
634 FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \
635 FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \
636 FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \
637 FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \
638 FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \
640 FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \
641 FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \
642 FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \
643 FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \
644 FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \
645 FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \
646 FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \
647 FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \
649 FM(IP0SR8_3_0) IP0SR8_3_0 FM(IP1SR8_3_0) IP1SR8_3_0 \
650 FM(IP0SR8_7_4) IP0SR8_7_4 FM(IP1SR8_7_4) IP1SR8_7_4 \
651 FM(IP0SR8_11_8) IP0SR8_11_8 FM(IP1SR8_11_8) IP1SR8_11_8 \
652 FM(IP0SR8_15_12) IP0SR8_15_12 FM(IP1SR8_15_12) IP1SR8_15_12 \
653 FM(IP0SR8_19_16) IP0SR8_19_16 FM(IP1SR8_19_16) IP1SR8_19_16 \
654 FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \
655 FM(IP0SR8_27_24) IP0SR8_27_24 \
656 FM(IP0SR8_31_28) IP0SR8_31_28
658 /* MOD_SEL8 */ /* 0 */ /* 1 */
659 #define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1)
660 #define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1)
661 #define MOD_SEL8_9 FM(SEL_SDA4_0) FM(SEL_SDA4_1)
662 #define MOD_SEL8_8 FM(SEL_SCL4_0) FM(SEL_SCL4_1)
663 #define MOD_SEL8_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1)
664 #define MOD_SEL8_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1)
665 #define MOD_SEL8_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1)
666 #define MOD_SEL8_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1)
667 #define MOD_SEL8_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1)
668 #define MOD_SEL8_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1)
669 #define MOD_SEL8_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1)
670 #define MOD_SEL8_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1)
672 #define PINMUX_MOD_SELS \
695 #define FM(x) FN_##x,
696 PINMUX_FUNCTION_BEGIN,
706 #define FM(x) x##_MARK,
716 static const u16 pinmux_data[] = {
717 PINMUX_DATA_GP_ALL(),
720 PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B),
721 PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B),
723 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
725 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
727 PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3_A),
728 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
730 PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2_A),
731 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
733 PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1_A),
734 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
736 PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0_A),
737 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
739 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
742 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1),
744 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC),
746 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD),
748 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK),
750 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),
752 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),
753 PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A),
754 PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B),
756 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
757 PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A),
758 PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A),
760 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),
761 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A),
762 PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A),
765 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),
766 PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A),
767 PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A),
769 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),
770 PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A),
771 PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A),
773 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),
774 PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A),
775 PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A),
778 PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
779 PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B),
780 PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B),
782 PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
783 PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B),
784 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B),
786 PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
787 PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B),
788 PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B),
790 PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
791 PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),
792 PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),
794 PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
795 PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B),
796 PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B),
798 PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
800 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
801 PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B),
802 PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B),
804 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
805 PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B),
806 PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B),
809 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
810 PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B),
811 PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B),
812 PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_TX_B),
814 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
815 PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B),
816 PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B),
817 PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_RX_B),
819 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
820 PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B),
821 PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B),
823 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
825 PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0),
826 PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0),
828 PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
829 PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
830 PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),
832 PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
833 PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
834 PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),
836 PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
837 PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
838 PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
841 PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
842 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),
844 PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK),
845 PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),
847 PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),
848 PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B),
850 PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),
851 PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B),
853 PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),
854 PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B),
856 PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),
857 PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B),
859 PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
860 PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A),
862 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A),
863 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
864 PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
867 PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A),
868 PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
869 PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
871 PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A),
872 PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
873 PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
874 PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B),
876 PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A),
877 PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
878 PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
879 PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B),
881 PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A),
882 PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
883 PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
885 PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A),
886 PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
887 PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
890 PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
891 PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
892 PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B),
894 PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A),
895 PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
896 PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B),
898 PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
899 PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX_A),
900 PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),
902 PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),
903 PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX_A),
904 PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),
906 PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
908 PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A),
910 PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
912 PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A),
913 PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
914 PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C),
917 PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A),
918 PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),
919 PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B),
921 PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
922 PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B),
924 PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
925 PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B),
927 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
928 PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
930 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
931 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A),
932 PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C),
934 PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
935 PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A),
936 PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),
937 PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C),
939 PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
940 PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
942 PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
943 PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
946 PINMUX_IPSR_GPSR(IP2SR2_3_0, CANFD4_TX),
947 PINMUX_IPSR_GPSR(IP2SR2_3_0, PWM4),
949 PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD4_RX),
950 PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM5),
952 PINMUX_IPSR_GPSR(IP2SR2_11_8, CANFD7_TX),
953 PINMUX_IPSR_GPSR(IP2SR2_11_8, PWM6),
955 PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD7_RX),
956 PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM7),
959 PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1),
960 PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0),
961 PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2),
962 PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK),
963 PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS),
964 PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3),
965 PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5),
966 PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4),
969 PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7),
971 PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6),
973 PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD),
975 PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD),
977 PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP),
979 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
980 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
981 PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),
982 PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_A),
984 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
985 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
986 PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A),
987 PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_A),
989 PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
992 PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3),
993 PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2),
994 PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1),
995 PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0),
996 PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK),
997 PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0),
998 PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK),
999 PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1),
1002 PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2),
1003 PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL),
1004 PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3),
1005 PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N),
1006 PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N),
1007 PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N),
1010 PINMUX_IPSR_GPSR(IP0SR4_3_0, TSN0_MDIO),
1011 PINMUX_IPSR_GPSR(IP0SR4_7_4, TSN0_MDC),
1012 PINMUX_IPSR_GPSR(IP0SR4_11_8, TSN0_AVTP_PPS1),
1013 PINMUX_IPSR_GPSR(IP0SR4_15_12, TSN0_PHY_INT),
1014 PINMUX_IPSR_GPSR(IP0SR4_19_16, TSN0_LINK),
1015 PINMUX_IPSR_GPSR(IP0SR4_23_20, TSN0_AVTP_MATCH),
1016 PINMUX_IPSR_GPSR(IP0SR4_27_24, TSN0_AVTP_CAPTURE),
1017 PINMUX_IPSR_GPSR(IP0SR4_31_28, TSN0_RX_CTL),
1020 PINMUX_IPSR_GPSR(IP1SR4_3_0, TSN0_AVTP_PPS0),
1021 PINMUX_IPSR_GPSR(IP1SR4_7_4, TSN0_TX_CTL),
1022 PINMUX_IPSR_GPSR(IP1SR4_11_8, TSN0_RD0),
1023 PINMUX_IPSR_GPSR(IP1SR4_15_12, TSN0_RXC),
1024 PINMUX_IPSR_GPSR(IP1SR4_19_16, TSN0_TXC),
1025 PINMUX_IPSR_GPSR(IP1SR4_23_20, TSN0_RD1),
1026 PINMUX_IPSR_GPSR(IP1SR4_27_24, TSN0_TD1),
1027 PINMUX_IPSR_GPSR(IP1SR4_31_28, TSN0_TD0),
1030 PINMUX_IPSR_GPSR(IP2SR4_3_0, TSN0_RD3),
1031 PINMUX_IPSR_GPSR(IP2SR4_7_4, TSN0_RD2),
1032 PINMUX_IPSR_GPSR(IP2SR4_11_8, TSN0_TD3),
1033 PINMUX_IPSR_GPSR(IP2SR4_15_12, TSN0_TD2),
1034 PINMUX_IPSR_GPSR(IP2SR4_19_16, TSN0_TXCREFCLK),
1035 PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N),
1036 PINMUX_IPSR_GPSR(IP2SR4_27_24, PCIE1_CLKREQ_N),
1037 PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0),
1040 PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1),
1043 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS),
1044 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE),
1045 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH),
1046 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK),
1047 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT),
1048 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC),
1049 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC),
1050 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK),
1053 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3),
1054 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3),
1055 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO),
1056 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2),
1057 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1),
1058 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2),
1059 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1),
1060 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0),
1063 PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC),
1064 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0),
1065 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC),
1066 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL),
1067 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL),
1070 PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
1072 PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
1074 PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
1076 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
1078 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
1079 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
1081 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
1082 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
1084 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
1085 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
1087 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
1088 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
1091 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
1092 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC),
1094 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
1095 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
1097 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
1098 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
1100 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
1101 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
1103 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
1104 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
1106 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
1107 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
1109 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
1110 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
1112 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0),
1113 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
1116 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
1117 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
1119 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
1120 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
1122 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
1123 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
1125 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
1126 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
1128 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
1131 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),
1132 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),
1134 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
1135 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
1137 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),
1138 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),
1139 PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),
1141 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),
1142 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
1144 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
1145 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
1147 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
1149 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),
1150 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),
1152 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),
1153 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),
1156 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
1157 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),
1159 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
1161 PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),
1163 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),
1164 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),
1166 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
1167 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
1169 PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),
1171 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
1173 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),
1174 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),
1177 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),
1178 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),
1180 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
1181 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
1183 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0),
1184 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0),
1186 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC),
1187 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC),
1189 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL),
1190 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),
1193 PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
1194 PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),
1195 PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_0),
1196 PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_0),
1197 PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_0),
1198 PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_0),
1199 PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_0),
1200 PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_0),
1203 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_0),
1204 PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0),
1205 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0),
1207 PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_0),
1208 PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0),
1209 PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0),
1211 PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_0),
1212 PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0),
1213 PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0),
1215 PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_0),
1216 PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0),
1218 PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N),
1219 PINMUX_IPSR_GPSR(IP1SR8_19_16, TX4),
1221 PINMUX_IPSR_GPSR(IP1SR8_23_20, HSCK2),
1222 PINMUX_IPSR_GPSR(IP1SR8_23_20, RX4),
1226 * Pins not associated with a GPIO port.
1233 static const struct sh_pfc_pin pinmux_pins[] = {
1234 PINMUX_GPIO_GP_ALL(),
1238 /* - AUDIO CLOCK ----------------------------------------- */
1239 static const unsigned int audio_clkin_pins[] = {
1243 static const unsigned int audio_clkin_mux[] = {
1246 static const unsigned int audio_clkout_pins[] = {
1250 static const unsigned int audio_clkout_mux[] = {
1254 /* - AVB0 ------------------------------------------------ */
1255 static const unsigned int avb0_link_pins[] = {
1259 static const unsigned int avb0_link_mux[] = {
1262 static const unsigned int avb0_magic_pins[] = {
1266 static const unsigned int avb0_magic_mux[] = {
1269 static const unsigned int avb0_phy_int_pins[] = {
1273 static const unsigned int avb0_phy_int_mux[] = {
1276 static const unsigned int avb0_mdio_pins[] = {
1277 /* AVB0_MDC, AVB0_MDIO */
1278 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1280 static const unsigned int avb0_mdio_mux[] = {
1281 AVB0_MDC_MARK, AVB0_MDIO_MARK,
1283 static const unsigned int avb0_rgmii_pins[] = {
1285 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1286 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1288 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1289 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
1290 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
1291 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1292 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1293 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
1295 static const unsigned int avb0_rgmii_mux[] = {
1296 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
1297 AVB0_TD0_MARK, AVB0_TD1_MARK,
1298 AVB0_TD2_MARK, AVB0_TD3_MARK,
1299 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
1300 AVB0_RD0_MARK, AVB0_RD1_MARK,
1301 AVB0_RD2_MARK, AVB0_RD3_MARK,
1303 static const unsigned int avb0_txcrefclk_pins[] = {
1304 /* AVB0_TXCREFCLK */
1307 static const unsigned int avb0_txcrefclk_mux[] = {
1308 AVB0_TXCREFCLK_MARK,
1310 static const unsigned int avb0_avtp_pps_pins[] = {
1314 static const unsigned int avb0_avtp_pps_mux[] = {
1317 static const unsigned int avb0_avtp_capture_pins[] = {
1318 /* AVB0_AVTP_CAPTURE */
1321 static const unsigned int avb0_avtp_capture_mux[] = {
1322 AVB0_AVTP_CAPTURE_MARK,
1324 static const unsigned int avb0_avtp_match_pins[] = {
1325 /* AVB0_AVTP_MATCH */
1328 static const unsigned int avb0_avtp_match_mux[] = {
1329 AVB0_AVTP_MATCH_MARK,
1332 /* - AVB1 ------------------------------------------------ */
1333 static const unsigned int avb1_link_pins[] = {
1337 static const unsigned int avb1_link_mux[] = {
1340 static const unsigned int avb1_magic_pins[] = {
1344 static const unsigned int avb1_magic_mux[] = {
1347 static const unsigned int avb1_phy_int_pins[] = {
1351 static const unsigned int avb1_phy_int_mux[] = {
1354 static const unsigned int avb1_mdio_pins[] = {
1355 /* AVB1_MDC, AVB1_MDIO */
1356 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1358 static const unsigned int avb1_mdio_mux[] = {
1359 AVB1_MDC_MARK, AVB1_MDIO_MARK,
1361 static const unsigned int avb1_rgmii_pins[] = {
1363 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1364 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1366 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1367 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1368 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1369 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
1370 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1371 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1373 static const unsigned int avb1_rgmii_mux[] = {
1374 AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
1375 AVB1_TD0_MARK, AVB1_TD1_MARK,
1376 AVB1_TD2_MARK, AVB1_TD3_MARK,
1377 AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
1378 AVB1_RD0_MARK, AVB1_RD1_MARK,
1379 AVB1_RD2_MARK, AVB1_RD3_MARK,
1381 static const unsigned int avb1_txcrefclk_pins[] = {
1382 /* AVB1_TXCREFCLK */
1385 static const unsigned int avb1_txcrefclk_mux[] = {
1386 AVB1_TXCREFCLK_MARK,
1388 static const unsigned int avb1_avtp_pps_pins[] = {
1392 static const unsigned int avb1_avtp_pps_mux[] = {
1395 static const unsigned int avb1_avtp_capture_pins[] = {
1396 /* AVB1_AVTP_CAPTURE */
1399 static const unsigned int avb1_avtp_capture_mux[] = {
1400 AVB1_AVTP_CAPTURE_MARK,
1402 static const unsigned int avb1_avtp_match_pins[] = {
1403 /* AVB1_AVTP_MATCH */
1406 static const unsigned int avb1_avtp_match_mux[] = {
1407 AVB1_AVTP_MATCH_MARK,
1410 /* - AVB2 ------------------------------------------------ */
1411 static const unsigned int avb2_link_pins[] = {
1415 static const unsigned int avb2_link_mux[] = {
1418 static const unsigned int avb2_magic_pins[] = {
1422 static const unsigned int avb2_magic_mux[] = {
1425 static const unsigned int avb2_phy_int_pins[] = {
1429 static const unsigned int avb2_phy_int_mux[] = {
1432 static const unsigned int avb2_mdio_pins[] = {
1433 /* AVB2_MDC, AVB2_MDIO */
1434 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1436 static const unsigned int avb2_mdio_mux[] = {
1437 AVB2_MDC_MARK, AVB2_MDIO_MARK,
1439 static const unsigned int avb2_rgmii_pins[] = {
1441 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1442 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1444 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1445 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1446 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
1447 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1448 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1449 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
1451 static const unsigned int avb2_rgmii_mux[] = {
1452 AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
1453 AVB2_TD0_MARK, AVB2_TD1_MARK,
1454 AVB2_TD2_MARK, AVB2_TD3_MARK,
1455 AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
1456 AVB2_RD0_MARK, AVB2_RD1_MARK,
1457 AVB2_RD2_MARK, AVB2_RD3_MARK,
1459 static const unsigned int avb2_txcrefclk_pins[] = {
1460 /* AVB2_TXCREFCLK */
1463 static const unsigned int avb2_txcrefclk_mux[] = {
1464 AVB2_TXCREFCLK_MARK,
1466 static const unsigned int avb2_avtp_pps_pins[] = {
1470 static const unsigned int avb2_avtp_pps_mux[] = {
1473 static const unsigned int avb2_avtp_capture_pins[] = {
1474 /* AVB2_AVTP_CAPTURE */
1477 static const unsigned int avb2_avtp_capture_mux[] = {
1478 AVB2_AVTP_CAPTURE_MARK,
1480 static const unsigned int avb2_avtp_match_pins[] = {
1481 /* AVB2_AVTP_MATCH */
1484 static const unsigned int avb2_avtp_match_mux[] = {
1485 AVB2_AVTP_MATCH_MARK,
1488 /* - CANFD0 ----------------------------------------------------------------- */
1489 static const unsigned int canfd0_data_pins[] = {
1490 /* CANFD0_TX, CANFD0_RX */
1491 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1493 static const unsigned int canfd0_data_mux[] = {
1494 CANFD0_TX_MARK, CANFD0_RX_MARK,
1497 /* - CANFD1 ----------------------------------------------------------------- */
1498 static const unsigned int canfd1_data_pins[] = {
1499 /* CANFD1_TX, CANFD1_RX */
1500 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1502 static const unsigned int canfd1_data_mux[] = {
1503 CANFD1_TX_MARK, CANFD1_RX_MARK,
1506 /* - CANFD2 ----------------------------------------------------------------- */
1507 static const unsigned int canfd2_data_pins[] = {
1508 /* CANFD2_TX, CANFD2_RX */
1509 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1511 static const unsigned int canfd2_data_mux[] = {
1512 CANFD2_TX_MARK, CANFD2_RX_MARK,
1515 /* - CANFD3 ----------------------------------------------------------------- */
1516 static const unsigned int canfd3_data_pins[] = {
1517 /* CANFD3_TX, CANFD3_RX */
1518 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1520 static const unsigned int canfd3_data_mux[] = {
1521 CANFD3_TX_MARK, CANFD3_RX_MARK,
1524 /* - CANFD4 ----------------------------------------------------------------- */
1525 static const unsigned int canfd4_data_pins[] = {
1526 /* CANFD4_TX, CANFD4_RX */
1527 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1529 static const unsigned int canfd4_data_mux[] = {
1530 CANFD4_TX_MARK, CANFD4_RX_MARK,
1533 /* - CANFD5 ----------------------------------------------------------------- */
1534 static const unsigned int canfd5_data_a_pins[] = {
1535 /* CANFD5_TX_A, CANFD5_RX_A */
1536 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1538 static const unsigned int canfd5_data_a_mux[] = {
1539 CANFD5_TX_A_MARK, CANFD5_RX_A_MARK,
1542 static const unsigned int canfd5_data_b_pins[] = {
1543 /* CANFD5_TX_B, CANFD5_RX_B */
1544 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1546 static const unsigned int canfd5_data_b_mux[] = {
1547 CANFD5_TX_B_MARK, CANFD5_RX_B_MARK,
1550 /* - CANFD6 ----------------------------------------------------------------- */
1551 static const unsigned int canfd6_data_pins[] = {
1552 /* CANFD6_TX, CANFD6_RX */
1553 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1555 static const unsigned int canfd6_data_mux[] = {
1556 CANFD6_TX_MARK, CANFD6_RX_MARK,
1559 /* - CANFD7 ----------------------------------------------------------------- */
1560 static const unsigned int canfd7_data_pins[] = {
1561 /* CANFD7_TX, CANFD7_RX */
1562 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1564 static const unsigned int canfd7_data_mux[] = {
1565 CANFD7_TX_MARK, CANFD7_RX_MARK,
1568 /* - CANFD Clock ------------------------------------------------------------ */
1569 static const unsigned int can_clk_pins[] = {
1573 static const unsigned int can_clk_mux[] = {
1577 /* - HSCIF0 ----------------------------------------------------------------- */
1578 static const unsigned int hscif0_data_pins[] = {
1580 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1582 static const unsigned int hscif0_data_mux[] = {
1583 HRX0_MARK, HTX0_MARK,
1585 static const unsigned int hscif0_clk_pins[] = {
1589 static const unsigned int hscif0_clk_mux[] = {
1592 static const unsigned int hscif0_ctrl_pins[] = {
1593 /* HRTS0_N, HCTS0_N */
1594 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1596 static const unsigned int hscif0_ctrl_mux[] = {
1597 HRTS0_N_MARK, HCTS0_N_MARK,
1600 /* - HSCIF1 ----------------------------------------------------------------- */
1601 static const unsigned int hscif1_data_a_pins[] = {
1602 /* HRX1_A, HTX1_A */
1603 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1605 static const unsigned int hscif1_data_a_mux[] = {
1606 HRX1_A_MARK, HTX1_A_MARK,
1608 static const unsigned int hscif1_clk_a_pins[] = {
1612 static const unsigned int hscif1_clk_a_mux[] = {
1615 static const unsigned int hscif1_ctrl_a_pins[] = {
1616 /* HRTS1_N_A, HCTS1_N_A */
1617 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1619 static const unsigned int hscif1_ctrl_a_mux[] = {
1620 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1623 static const unsigned int hscif1_data_b_pins[] = {
1624 /* HRX1_B, HTX1_B */
1625 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1627 static const unsigned int hscif1_data_b_mux[] = {
1628 HRX1_B_MARK, HTX1_B_MARK,
1630 static const unsigned int hscif1_clk_b_pins[] = {
1634 static const unsigned int hscif1_clk_b_mux[] = {
1637 static const unsigned int hscif1_ctrl_b_pins[] = {
1638 /* HRTS1_N_B, HCTS1_N_B */
1639 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1641 static const unsigned int hscif1_ctrl_b_mux[] = {
1642 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1645 /* - HSCIF2 ----------------------------------------------------------------- */
1646 static const unsigned int hscif2_data_pins[] = {
1648 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1650 static const unsigned int hscif2_data_mux[] = {
1651 HRX2_MARK, HTX2_MARK,
1653 static const unsigned int hscif2_clk_pins[] = {
1657 static const unsigned int hscif2_clk_mux[] = {
1660 static const unsigned int hscif2_ctrl_pins[] = {
1661 /* HRTS2_N, HCTS2_N */
1662 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1664 static const unsigned int hscif2_ctrl_mux[] = {
1665 HRTS2_N_MARK, HCTS2_N_MARK,
1668 /* - HSCIF3 ----------------------------------------------------------------- */
1669 static const unsigned int hscif3_data_a_pins[] = {
1670 /* HRX3_A, HTX3_A */
1671 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1673 static const unsigned int hscif3_data_a_mux[] = {
1674 HRX3_A_MARK, HTX3_A_MARK,
1676 static const unsigned int hscif3_clk_a_pins[] = {
1680 static const unsigned int hscif3_clk_a_mux[] = {
1683 static const unsigned int hscif3_ctrl_a_pins[] = {
1684 /* HRTS3_N_A, HCTS3_N_A */
1685 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1687 static const unsigned int hscif3_ctrl_a_mux[] = {
1688 HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1691 static const unsigned int hscif3_data_b_pins[] = {
1692 /* HRX3_B, HTX3_B */
1693 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1695 static const unsigned int hscif3_data_b_mux[] = {
1696 HRX3_B_MARK, HTX3_B_MARK,
1698 static const unsigned int hscif3_clk_b_pins[] = {
1702 static const unsigned int hscif3_clk_b_mux[] = {
1705 static const unsigned int hscif3_ctrl_b_pins[] = {
1706 /* HRTS3_N_B, HCTS3_N_B */
1707 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1709 static const unsigned int hscif3_ctrl_b_mux[] = {
1710 HRTS3_N_B_MARK, HCTS3_N_B_MARK,
1713 /* - I2C0 ------------------------------------------------------------------- */
1714 static const unsigned int i2c0_pins[] = {
1716 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1718 static const unsigned int i2c0_mux[] = {
1719 SDA0_MARK, SCL0_MARK,
1722 /* - I2C1 ------------------------------------------------------------------- */
1723 static const unsigned int i2c1_pins[] = {
1725 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1727 static const unsigned int i2c1_mux[] = {
1728 SDA1_MARK, SCL1_MARK,
1731 /* - I2C2 ------------------------------------------------------------------- */
1732 static const unsigned int i2c2_pins[] = {
1734 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1736 static const unsigned int i2c2_mux[] = {
1737 SDA2_MARK, SCL2_MARK,
1740 /* - I2C3 ------------------------------------------------------------------- */
1741 static const unsigned int i2c3_pins[] = {
1743 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1745 static const unsigned int i2c3_mux[] = {
1746 SDA3_MARK, SCL3_MARK,
1749 /* - I2C4 ------------------------------------------------------------------- */
1750 static const unsigned int i2c4_pins[] = {
1752 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1754 static const unsigned int i2c4_mux[] = {
1755 SDA4_MARK, SCL4_MARK,
1758 /* - I2C5 ------------------------------------------------------------------- */
1759 static const unsigned int i2c5_pins[] = {
1761 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1763 static const unsigned int i2c5_mux[] = {
1764 SDA5_MARK, SCL5_MARK,
1767 /* - INTC-EX ---------------------------------------------------------------- */
1768 static const unsigned int intc_ex_irq0_a_pins[] = {
1772 static const unsigned int intc_ex_irq0_a_mux[] = {
1775 static const unsigned int intc_ex_irq0_b_pins[] = {
1779 static const unsigned int intc_ex_irq0_b_mux[] = {
1783 static const unsigned int intc_ex_irq1_a_pins[] = {
1787 static const unsigned int intc_ex_irq1_a_mux[] = {
1790 static const unsigned int intc_ex_irq1_b_pins[] = {
1794 static const unsigned int intc_ex_irq1_b_mux[] = {
1798 static const unsigned int intc_ex_irq2_a_pins[] = {
1802 static const unsigned int intc_ex_irq2_a_mux[] = {
1805 static const unsigned int intc_ex_irq2_b_pins[] = {
1809 static const unsigned int intc_ex_irq2_b_mux[] = {
1813 static const unsigned int intc_ex_irq3_a_pins[] = {
1817 static const unsigned int intc_ex_irq3_a_mux[] = {
1820 static const unsigned int intc_ex_irq3_b_pins[] = {
1824 static const unsigned int intc_ex_irq3_b_mux[] = {
1828 static const unsigned int intc_ex_irq4_a_pins[] = {
1832 static const unsigned int intc_ex_irq4_a_mux[] = {
1835 static const unsigned int intc_ex_irq4_b_pins[] = {
1839 static const unsigned int intc_ex_irq4_b_mux[] = {
1843 static const unsigned int intc_ex_irq5_pins[] = {
1847 static const unsigned int intc_ex_irq5_mux[] = {
1851 /* - MMC -------------------------------------------------------------------- */
1852 static const unsigned int mmc_data_pins[] = {
1853 /* MMC_SD_D[0:3], MMC_D[4:7] */
1854 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1855 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1856 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1857 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1859 static const unsigned int mmc_data_mux[] = {
1860 MMC_SD_D0_MARK, MMC_SD_D1_MARK,
1861 MMC_SD_D2_MARK, MMC_SD_D3_MARK,
1862 MMC_D4_MARK, MMC_D5_MARK,
1863 MMC_D6_MARK, MMC_D7_MARK,
1865 static const unsigned int mmc_ctrl_pins[] = {
1866 /* MMC_SD_CLK, MMC_SD_CMD */
1867 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1869 static const unsigned int mmc_ctrl_mux[] = {
1870 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
1872 static const unsigned int mmc_cd_pins[] = {
1876 static const unsigned int mmc_cd_mux[] = {
1879 static const unsigned int mmc_wp_pins[] = {
1883 static const unsigned int mmc_wp_mux[] = {
1886 static const unsigned int mmc_ds_pins[] = {
1890 static const unsigned int mmc_ds_mux[] = {
1894 /* - MSIOF0 ----------------------------------------------------------------- */
1895 static const unsigned int msiof0_clk_pins[] = {
1899 static const unsigned int msiof0_clk_mux[] = {
1902 static const unsigned int msiof0_sync_pins[] = {
1906 static const unsigned int msiof0_sync_mux[] = {
1909 static const unsigned int msiof0_ss1_pins[] = {
1913 static const unsigned int msiof0_ss1_mux[] = {
1916 static const unsigned int msiof0_ss2_pins[] = {
1920 static const unsigned int msiof0_ss2_mux[] = {
1923 static const unsigned int msiof0_txd_pins[] = {
1927 static const unsigned int msiof0_txd_mux[] = {
1930 static const unsigned int msiof0_rxd_pins[] = {
1934 static const unsigned int msiof0_rxd_mux[] = {
1938 /* - MSIOF1 ----------------------------------------------------------------- */
1939 static const unsigned int msiof1_clk_pins[] = {
1943 static const unsigned int msiof1_clk_mux[] = {
1946 static const unsigned int msiof1_sync_pins[] = {
1950 static const unsigned int msiof1_sync_mux[] = {
1953 static const unsigned int msiof1_ss1_pins[] = {
1957 static const unsigned int msiof1_ss1_mux[] = {
1960 static const unsigned int msiof1_ss2_pins[] = {
1964 static const unsigned int msiof1_ss2_mux[] = {
1967 static const unsigned int msiof1_txd_pins[] = {
1971 static const unsigned int msiof1_txd_mux[] = {
1974 static const unsigned int msiof1_rxd_pins[] = {
1978 static const unsigned int msiof1_rxd_mux[] = {
1982 /* - MSIOF2 ----------------------------------------------------------------- */
1983 static const unsigned int msiof2_clk_pins[] = {
1987 static const unsigned int msiof2_clk_mux[] = {
1990 static const unsigned int msiof2_sync_pins[] = {
1994 static const unsigned int msiof2_sync_mux[] = {
1997 static const unsigned int msiof2_ss1_pins[] = {
2001 static const unsigned int msiof2_ss1_mux[] = {
2004 static const unsigned int msiof2_ss2_pins[] = {
2008 static const unsigned int msiof2_ss2_mux[] = {
2011 static const unsigned int msiof2_txd_pins[] = {
2015 static const unsigned int msiof2_txd_mux[] = {
2018 static const unsigned int msiof2_rxd_pins[] = {
2022 static const unsigned int msiof2_rxd_mux[] = {
2026 /* - MSIOF3 ----------------------------------------------------------------- */
2027 static const unsigned int msiof3_clk_pins[] = {
2031 static const unsigned int msiof3_clk_mux[] = {
2034 static const unsigned int msiof3_sync_pins[] = {
2038 static const unsigned int msiof3_sync_mux[] = {
2041 static const unsigned int msiof3_ss1_pins[] = {
2045 static const unsigned int msiof3_ss1_mux[] = {
2048 static const unsigned int msiof3_ss2_pins[] = {
2052 static const unsigned int msiof3_ss2_mux[] = {
2055 static const unsigned int msiof3_txd_pins[] = {
2059 static const unsigned int msiof3_txd_mux[] = {
2062 static const unsigned int msiof3_rxd_pins[] = {
2066 static const unsigned int msiof3_rxd_mux[] = {
2070 /* - MSIOF4 ----------------------------------------------------------------- */
2071 static const unsigned int msiof4_clk_pins[] = {
2075 static const unsigned int msiof4_clk_mux[] = {
2078 static const unsigned int msiof4_sync_pins[] = {
2082 static const unsigned int msiof4_sync_mux[] = {
2085 static const unsigned int msiof4_ss1_pins[] = {
2089 static const unsigned int msiof4_ss1_mux[] = {
2092 static const unsigned int msiof4_ss2_pins[] = {
2096 static const unsigned int msiof4_ss2_mux[] = {
2099 static const unsigned int msiof4_txd_pins[] = {
2103 static const unsigned int msiof4_txd_mux[] = {
2106 static const unsigned int msiof4_rxd_pins[] = {
2110 static const unsigned int msiof4_rxd_mux[] = {
2114 /* - MSIOF5 ----------------------------------------------------------------- */
2115 static const unsigned int msiof5_clk_pins[] = {
2119 static const unsigned int msiof5_clk_mux[] = {
2122 static const unsigned int msiof5_sync_pins[] = {
2126 static const unsigned int msiof5_sync_mux[] = {
2129 static const unsigned int msiof5_ss1_pins[] = {
2133 static const unsigned int msiof5_ss1_mux[] = {
2136 static const unsigned int msiof5_ss2_pins[] = {
2140 static const unsigned int msiof5_ss2_mux[] = {
2143 static const unsigned int msiof5_txd_pins[] = {
2147 static const unsigned int msiof5_txd_mux[] = {
2150 static const unsigned int msiof5_rxd_pins[] = {
2154 static const unsigned int msiof5_rxd_mux[] = {
2158 /* - PCIE ------------------------------------------------------------------- */
2159 static const unsigned int pcie0_clkreq_n_pins[] = {
2160 /* PCIE0_CLKREQ_N */
2164 static const unsigned int pcie0_clkreq_n_mux[] = {
2165 PCIE0_CLKREQ_N_MARK,
2168 static const unsigned int pcie1_clkreq_n_pins[] = {
2169 /* PCIE1_CLKREQ_N */
2173 static const unsigned int pcie1_clkreq_n_mux[] = {
2174 PCIE1_CLKREQ_N_MARK,
2177 /* - PWM0 ------------------------------------------------------------------- */
2178 static const unsigned int pwm0_pins[] = {
2182 static const unsigned int pwm0_mux[] = {
2186 /* - PWM1 ------------------------------------------------------------------- */
2187 static const unsigned int pwm1_a_pins[] = {
2191 static const unsigned int pwm1_a_mux[] = {
2195 static const unsigned int pwm1_b_pins[] = {
2199 static const unsigned int pwm1_b_mux[] = {
2203 /* - PWM2 ------------------------------------------------------------------- */
2204 static const unsigned int pwm2_pins[] = {
2208 static const unsigned int pwm2_mux[] = {
2212 /* - PWM3 ------------------------------------------------------------------- */
2213 static const unsigned int pwm3_a_pins[] = {
2217 static const unsigned int pwm3_a_mux[] = {
2221 static const unsigned int pwm3_b_pins[] = {
2225 static const unsigned int pwm3_b_mux[] = {
2229 /* - PWM4 ------------------------------------------------------------------- */
2230 static const unsigned int pwm4_pins[] = {
2234 static const unsigned int pwm4_mux[] = {
2238 /* - PWM5 ------------------------------------------------------------------- */
2239 static const unsigned int pwm5_pins[] = {
2243 static const unsigned int pwm5_mux[] = {
2247 /* - PWM6 ------------------------------------------------------------------- */
2248 static const unsigned int pwm6_pins[] = {
2252 static const unsigned int pwm6_mux[] = {
2256 /* - PWM7 ------------------------------------------------------------------- */
2257 static const unsigned int pwm7_pins[] = {
2261 static const unsigned int pwm7_mux[] = {
2265 /* - PWM8 ------------------------------------------------------------------- */
2266 static const unsigned int pwm8_pins[] = {
2270 static const unsigned int pwm8_mux[] = {
2274 /* - PWM9 ------------------------------------------------------------------- */
2275 static const unsigned int pwm9_pins[] = {
2279 static const unsigned int pwm9_mux[] = {
2283 /* - QSPI0 ------------------------------------------------------------------ */
2284 static const unsigned int qspi0_ctrl_pins[] = {
2286 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2288 static const unsigned int qspi0_ctrl_mux[] = {
2289 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2291 static const unsigned int qspi0_data_pins[] = {
2292 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2293 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2294 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2296 static const unsigned int qspi0_data_mux[] = {
2297 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2298 QSPI0_IO2_MARK, QSPI0_IO3_MARK
2301 /* - QSPI1 ------------------------------------------------------------------ */
2302 static const unsigned int qspi1_ctrl_pins[] = {
2304 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2306 static const unsigned int qspi1_ctrl_mux[] = {
2307 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2309 static const unsigned int qspi1_data_pins[] = {
2310 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2311 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2312 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2314 static const unsigned int qspi1_data_mux[] = {
2315 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2316 QSPI1_IO2_MARK, QSPI1_IO3_MARK
2319 /* - SCIF0 ------------------------------------------------------------------ */
2320 static const unsigned int scif0_data_pins[] = {
2322 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2324 static const unsigned int scif0_data_mux[] = {
2327 static const unsigned int scif0_clk_pins[] = {
2331 static const unsigned int scif0_clk_mux[] = {
2334 static const unsigned int scif0_ctrl_pins[] = {
2335 /* RTS0_N, CTS0_N */
2336 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2338 static const unsigned int scif0_ctrl_mux[] = {
2339 RTS0_N_MARK, CTS0_N_MARK,
2342 /* - SCIF1 ------------------------------------------------------------------ */
2343 static const unsigned int scif1_data_a_pins[] = {
2345 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2347 static const unsigned int scif1_data_a_mux[] = {
2348 RX1_A_MARK, TX1_A_MARK,
2350 static const unsigned int scif1_clk_a_pins[] = {
2354 static const unsigned int scif1_clk_a_mux[] = {
2357 static const unsigned int scif1_ctrl_a_pins[] = {
2358 /* RTS1_N_A, CTS1_N_A */
2359 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2361 static const unsigned int scif1_ctrl_a_mux[] = {
2362 RTS1_N_A_MARK, CTS1_N_A_MARK,
2365 static const unsigned int scif1_data_b_pins[] = {
2367 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2369 static const unsigned int scif1_data_b_mux[] = {
2370 RX1_B_MARK, TX1_B_MARK,
2372 static const unsigned int scif1_clk_b_pins[] = {
2376 static const unsigned int scif1_clk_b_mux[] = {
2379 static const unsigned int scif1_ctrl_b_pins[] = {
2380 /* RTS1_N_B, CTS1_N_B */
2381 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2383 static const unsigned int scif1_ctrl_b_mux[] = {
2384 RTS1_N_B_MARK, CTS1_N_B_MARK,
2387 /* - SCIF3 ------------------------------------------------------------------ */
2388 static const unsigned int scif3_data_a_pins[] = {
2390 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
2392 static const unsigned int scif3_data_a_mux[] = {
2393 RX3_A_MARK, TX3_A_MARK,
2395 static const unsigned int scif3_clk_a_pins[] = {
2399 static const unsigned int scif3_clk_a_mux[] = {
2402 static const unsigned int scif3_ctrl_a_pins[] = {
2403 /* RTS3_N_A, CTS3_N_A */
2404 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2406 static const unsigned int scif3_ctrl_a_mux[] = {
2407 RTS3_N_A_MARK, CTS3_N_A_MARK,
2410 static const unsigned int scif3_data_b_pins[] = {
2412 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2414 static const unsigned int scif3_data_b_mux[] = {
2415 RX3_B_MARK, TX3_B_MARK,
2417 static const unsigned int scif3_clk_b_pins[] = {
2421 static const unsigned int scif3_clk_b_mux[] = {
2424 static const unsigned int scif3_ctrl_b_pins[] = {
2425 /* RTS3_N_B, CTS3_N_B */
2426 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2428 static const unsigned int scif3_ctrl_b_mux[] = {
2429 RTS3_N_B_MARK, CTS3_N_B_MARK,
2432 /* - SCIF4 ------------------------------------------------------------------ */
2433 static const unsigned int scif4_data_pins[] = {
2435 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2437 static const unsigned int scif4_data_mux[] = {
2440 static const unsigned int scif4_clk_pins[] = {
2444 static const unsigned int scif4_clk_mux[] = {
2447 static const unsigned int scif4_ctrl_pins[] = {
2448 /* RTS4_N, CTS4_N */
2449 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2451 static const unsigned int scif4_ctrl_mux[] = {
2452 RTS4_N_MARK, CTS4_N_MARK,
2455 /* - SCIF Clock ------------------------------------------------------------- */
2456 static const unsigned int scif_clk_pins[] = {
2460 static const unsigned int scif_clk_mux[] = {
2464 static const unsigned int scif_clk2_pins[] = {
2468 static const unsigned int scif_clk2_mux[] = {
2472 /* - SSI ------------------------------------------------- */
2473 static const unsigned int ssi_data_pins[] = {
2477 static const unsigned int ssi_data_mux[] = {
2480 static const unsigned int ssi_ctrl_pins[] = {
2481 /* SSI_SCK, SSI_WS */
2482 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2484 static const unsigned int ssi_ctrl_mux[] = {
2485 SSI_SCK_MARK, SSI_WS_MARK,
2488 /* - TPU -------------------------------------------------------------------- */
2489 static const unsigned int tpu_to0_a_pins[] = {
2493 static const unsigned int tpu_to0_a_mux[] = {
2496 static const unsigned int tpu_to1_a_pins[] = {
2500 static const unsigned int tpu_to1_a_mux[] = {
2503 static const unsigned int tpu_to2_a_pins[] = {
2507 static const unsigned int tpu_to2_a_mux[] = {
2510 static const unsigned int tpu_to3_a_pins[] = {
2514 static const unsigned int tpu_to3_a_mux[] = {
2518 static const unsigned int tpu_to0_b_pins[] = {
2522 static const unsigned int tpu_to0_b_mux[] = {
2525 static const unsigned int tpu_to1_b_pins[] = {
2529 static const unsigned int tpu_to1_b_mux[] = {
2532 static const unsigned int tpu_to2_b_pins[] = {
2536 static const unsigned int tpu_to2_b_mux[] = {
2539 static const unsigned int tpu_to3_b_pins[] = {
2543 static const unsigned int tpu_to3_b_mux[] = {
2547 /* - TSN0 ------------------------------------------------ */
2548 static const unsigned int tsn0_link_pins[] = {
2552 static const unsigned int tsn0_link_mux[] = {
2555 static const unsigned int tsn0_phy_int_pins[] = {
2559 static const unsigned int tsn0_phy_int_mux[] = {
2562 static const unsigned int tsn0_mdio_pins[] = {
2563 /* TSN0_MDC, TSN0_MDIO */
2564 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2566 static const unsigned int tsn0_mdio_mux[] = {
2567 TSN0_MDC_MARK, TSN0_MDIO_MARK,
2569 static const unsigned int tsn0_rgmii_pins[] = {
2571 * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
2572 * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
2574 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),
2575 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2576 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2577 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),
2578 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2579 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2581 static const unsigned int tsn0_rgmii_mux[] = {
2582 TSN0_TX_CTL_MARK, TSN0_TXC_MARK,
2583 TSN0_TD0_MARK, TSN0_TD1_MARK,
2584 TSN0_TD2_MARK, TSN0_TD3_MARK,
2585 TSN0_RX_CTL_MARK, TSN0_RXC_MARK,
2586 TSN0_RD0_MARK, TSN0_RD1_MARK,
2587 TSN0_RD2_MARK, TSN0_RD3_MARK,
2589 static const unsigned int tsn0_txcrefclk_pins[] = {
2590 /* TSN0_TXCREFCLK */
2593 static const unsigned int tsn0_txcrefclk_mux[] = {
2594 TSN0_TXCREFCLK_MARK,
2596 static const unsigned int tsn0_avtp_pps_pins[] = {
2597 /* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
2598 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2600 static const unsigned int tsn0_avtp_pps_mux[] = {
2601 TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
2603 static const unsigned int tsn0_avtp_capture_pins[] = {
2604 /* TSN0_AVTP_CAPTURE */
2607 static const unsigned int tsn0_avtp_capture_mux[] = {
2608 TSN0_AVTP_CAPTURE_MARK,
2610 static const unsigned int tsn0_avtp_match_pins[] = {
2611 /* TSN0_AVTP_MATCH */
2614 static const unsigned int tsn0_avtp_match_mux[] = {
2615 TSN0_AVTP_MATCH_MARK,
2618 static const struct sh_pfc_pin_group pinmux_groups[] = {
2619 SH_PFC_PIN_GROUP(audio_clkin),
2620 SH_PFC_PIN_GROUP(audio_clkout),
2622 SH_PFC_PIN_GROUP(avb0_link),
2623 SH_PFC_PIN_GROUP(avb0_magic),
2624 SH_PFC_PIN_GROUP(avb0_phy_int),
2625 SH_PFC_PIN_GROUP(avb0_mdio),
2626 SH_PFC_PIN_GROUP(avb0_rgmii),
2627 SH_PFC_PIN_GROUP(avb0_txcrefclk),
2628 SH_PFC_PIN_GROUP(avb0_avtp_pps),
2629 SH_PFC_PIN_GROUP(avb0_avtp_capture),
2630 SH_PFC_PIN_GROUP(avb0_avtp_match),
2632 SH_PFC_PIN_GROUP(avb1_link),
2633 SH_PFC_PIN_GROUP(avb1_magic),
2634 SH_PFC_PIN_GROUP(avb1_phy_int),
2635 SH_PFC_PIN_GROUP(avb1_mdio),
2636 SH_PFC_PIN_GROUP(avb1_rgmii),
2637 SH_PFC_PIN_GROUP(avb1_txcrefclk),
2638 SH_PFC_PIN_GROUP(avb1_avtp_pps),
2639 SH_PFC_PIN_GROUP(avb1_avtp_capture),
2640 SH_PFC_PIN_GROUP(avb1_avtp_match),
2642 SH_PFC_PIN_GROUP(avb2_link),
2643 SH_PFC_PIN_GROUP(avb2_magic),
2644 SH_PFC_PIN_GROUP(avb2_phy_int),
2645 SH_PFC_PIN_GROUP(avb2_mdio),
2646 SH_PFC_PIN_GROUP(avb2_rgmii),
2647 SH_PFC_PIN_GROUP(avb2_txcrefclk),
2648 SH_PFC_PIN_GROUP(avb2_avtp_pps),
2649 SH_PFC_PIN_GROUP(avb2_avtp_capture),
2650 SH_PFC_PIN_GROUP(avb2_avtp_match),
2652 SH_PFC_PIN_GROUP(canfd0_data),
2653 SH_PFC_PIN_GROUP(canfd1_data),
2654 SH_PFC_PIN_GROUP(canfd2_data),
2655 SH_PFC_PIN_GROUP(canfd3_data),
2656 SH_PFC_PIN_GROUP(canfd4_data),
2657 SH_PFC_PIN_GROUP(canfd5_data_a),
2658 SH_PFC_PIN_GROUP(canfd5_data_b),
2659 SH_PFC_PIN_GROUP(canfd6_data),
2660 SH_PFC_PIN_GROUP(canfd7_data),
2661 SH_PFC_PIN_GROUP(can_clk),
2663 SH_PFC_PIN_GROUP(hscif0_data),
2664 SH_PFC_PIN_GROUP(hscif0_clk),
2665 SH_PFC_PIN_GROUP(hscif0_ctrl),
2666 SH_PFC_PIN_GROUP(hscif1_data_a),
2667 SH_PFC_PIN_GROUP(hscif1_clk_a),
2668 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
2669 SH_PFC_PIN_GROUP(hscif1_data_b),
2670 SH_PFC_PIN_GROUP(hscif1_clk_b),
2671 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2672 SH_PFC_PIN_GROUP(hscif2_data),
2673 SH_PFC_PIN_GROUP(hscif2_clk),
2674 SH_PFC_PIN_GROUP(hscif2_ctrl),
2675 SH_PFC_PIN_GROUP(hscif3_data_a),
2676 SH_PFC_PIN_GROUP(hscif3_clk_a),
2677 SH_PFC_PIN_GROUP(hscif3_ctrl_a),
2678 SH_PFC_PIN_GROUP(hscif3_data_b),
2679 SH_PFC_PIN_GROUP(hscif3_clk_b),
2680 SH_PFC_PIN_GROUP(hscif3_ctrl_b),
2682 SH_PFC_PIN_GROUP(i2c0),
2683 SH_PFC_PIN_GROUP(i2c1),
2684 SH_PFC_PIN_GROUP(i2c2),
2685 SH_PFC_PIN_GROUP(i2c3),
2686 SH_PFC_PIN_GROUP(i2c4),
2687 SH_PFC_PIN_GROUP(i2c5),
2689 SH_PFC_PIN_GROUP(intc_ex_irq0_a),
2690 SH_PFC_PIN_GROUP(intc_ex_irq0_b),
2691 SH_PFC_PIN_GROUP(intc_ex_irq1_a),
2692 SH_PFC_PIN_GROUP(intc_ex_irq1_b),
2693 SH_PFC_PIN_GROUP(intc_ex_irq2_a),
2694 SH_PFC_PIN_GROUP(intc_ex_irq2_b),
2695 SH_PFC_PIN_GROUP(intc_ex_irq3_a),
2696 SH_PFC_PIN_GROUP(intc_ex_irq3_b),
2697 SH_PFC_PIN_GROUP(intc_ex_irq4_a),
2698 SH_PFC_PIN_GROUP(intc_ex_irq4_b),
2699 SH_PFC_PIN_GROUP(intc_ex_irq5),
2701 BUS_DATA_PIN_GROUP(mmc_data, 1),
2702 BUS_DATA_PIN_GROUP(mmc_data, 4),
2703 BUS_DATA_PIN_GROUP(mmc_data, 8),
2704 SH_PFC_PIN_GROUP(mmc_ctrl),
2705 SH_PFC_PIN_GROUP(mmc_cd),
2706 SH_PFC_PIN_GROUP(mmc_wp),
2707 SH_PFC_PIN_GROUP(mmc_ds),
2709 SH_PFC_PIN_GROUP(msiof0_clk),
2710 SH_PFC_PIN_GROUP(msiof0_sync),
2711 SH_PFC_PIN_GROUP(msiof0_ss1),
2712 SH_PFC_PIN_GROUP(msiof0_ss2),
2713 SH_PFC_PIN_GROUP(msiof0_txd),
2714 SH_PFC_PIN_GROUP(msiof0_rxd),
2716 SH_PFC_PIN_GROUP(msiof1_clk),
2717 SH_PFC_PIN_GROUP(msiof1_sync),
2718 SH_PFC_PIN_GROUP(msiof1_ss1),
2719 SH_PFC_PIN_GROUP(msiof1_ss2),
2720 SH_PFC_PIN_GROUP(msiof1_txd),
2721 SH_PFC_PIN_GROUP(msiof1_rxd),
2723 SH_PFC_PIN_GROUP(msiof2_clk),
2724 SH_PFC_PIN_GROUP(msiof2_sync),
2725 SH_PFC_PIN_GROUP(msiof2_ss1),
2726 SH_PFC_PIN_GROUP(msiof2_ss2),
2727 SH_PFC_PIN_GROUP(msiof2_txd),
2728 SH_PFC_PIN_GROUP(msiof2_rxd),
2730 SH_PFC_PIN_GROUP(msiof3_clk),
2731 SH_PFC_PIN_GROUP(msiof3_sync),
2732 SH_PFC_PIN_GROUP(msiof3_ss1),
2733 SH_PFC_PIN_GROUP(msiof3_ss2),
2734 SH_PFC_PIN_GROUP(msiof3_txd),
2735 SH_PFC_PIN_GROUP(msiof3_rxd),
2737 SH_PFC_PIN_GROUP(msiof4_clk),
2738 SH_PFC_PIN_GROUP(msiof4_sync),
2739 SH_PFC_PIN_GROUP(msiof4_ss1),
2740 SH_PFC_PIN_GROUP(msiof4_ss2),
2741 SH_PFC_PIN_GROUP(msiof4_txd),
2742 SH_PFC_PIN_GROUP(msiof4_rxd),
2744 SH_PFC_PIN_GROUP(msiof5_clk),
2745 SH_PFC_PIN_GROUP(msiof5_sync),
2746 SH_PFC_PIN_GROUP(msiof5_ss1),
2747 SH_PFC_PIN_GROUP(msiof5_ss2),
2748 SH_PFC_PIN_GROUP(msiof5_txd),
2749 SH_PFC_PIN_GROUP(msiof5_rxd),
2751 SH_PFC_PIN_GROUP(pcie0_clkreq_n),
2752 SH_PFC_PIN_GROUP(pcie1_clkreq_n),
2754 SH_PFC_PIN_GROUP(pwm0),
2755 SH_PFC_PIN_GROUP(pwm1_a),
2756 SH_PFC_PIN_GROUP(pwm1_b),
2757 SH_PFC_PIN_GROUP(pwm2),
2758 SH_PFC_PIN_GROUP(pwm3_a),
2759 SH_PFC_PIN_GROUP(pwm3_b),
2760 SH_PFC_PIN_GROUP(pwm4),
2761 SH_PFC_PIN_GROUP(pwm5),
2762 SH_PFC_PIN_GROUP(pwm6),
2763 SH_PFC_PIN_GROUP(pwm7),
2764 SH_PFC_PIN_GROUP(pwm8),
2765 SH_PFC_PIN_GROUP(pwm9),
2767 SH_PFC_PIN_GROUP(qspi0_ctrl),
2768 BUS_DATA_PIN_GROUP(qspi0_data, 2),
2769 BUS_DATA_PIN_GROUP(qspi0_data, 4),
2770 SH_PFC_PIN_GROUP(qspi1_ctrl),
2771 BUS_DATA_PIN_GROUP(qspi1_data, 2),
2772 BUS_DATA_PIN_GROUP(qspi1_data, 4),
2774 SH_PFC_PIN_GROUP(scif0_data),
2775 SH_PFC_PIN_GROUP(scif0_clk),
2776 SH_PFC_PIN_GROUP(scif0_ctrl),
2777 SH_PFC_PIN_GROUP(scif1_data_a),
2778 SH_PFC_PIN_GROUP(scif1_clk_a),
2779 SH_PFC_PIN_GROUP(scif1_ctrl_a),
2780 SH_PFC_PIN_GROUP(scif1_data_b),
2781 SH_PFC_PIN_GROUP(scif1_clk_b),
2782 SH_PFC_PIN_GROUP(scif1_ctrl_b),
2783 SH_PFC_PIN_GROUP(scif3_data_a),
2784 SH_PFC_PIN_GROUP(scif3_clk_a),
2785 SH_PFC_PIN_GROUP(scif3_ctrl_a),
2786 SH_PFC_PIN_GROUP(scif3_data_b),
2787 SH_PFC_PIN_GROUP(scif3_clk_b),
2788 SH_PFC_PIN_GROUP(scif3_ctrl_b),
2789 SH_PFC_PIN_GROUP(scif4_data),
2790 SH_PFC_PIN_GROUP(scif4_clk),
2791 SH_PFC_PIN_GROUP(scif4_ctrl),
2792 SH_PFC_PIN_GROUP(scif_clk),
2793 SH_PFC_PIN_GROUP(scif_clk2),
2795 SH_PFC_PIN_GROUP(ssi_data),
2796 SH_PFC_PIN_GROUP(ssi_ctrl),
2798 SH_PFC_PIN_GROUP(tpu_to0_a),
2799 SH_PFC_PIN_GROUP(tpu_to0_b),
2800 SH_PFC_PIN_GROUP(tpu_to1_a),
2801 SH_PFC_PIN_GROUP(tpu_to1_b),
2802 SH_PFC_PIN_GROUP(tpu_to2_a),
2803 SH_PFC_PIN_GROUP(tpu_to2_b),
2804 SH_PFC_PIN_GROUP(tpu_to3_a),
2805 SH_PFC_PIN_GROUP(tpu_to3_b),
2807 SH_PFC_PIN_GROUP(tsn0_link),
2808 SH_PFC_PIN_GROUP(tsn0_phy_int),
2809 SH_PFC_PIN_GROUP(tsn0_mdio),
2810 SH_PFC_PIN_GROUP(tsn0_rgmii),
2811 SH_PFC_PIN_GROUP(tsn0_txcrefclk),
2812 SH_PFC_PIN_GROUP(tsn0_avtp_pps),
2813 SH_PFC_PIN_GROUP(tsn0_avtp_capture),
2814 SH_PFC_PIN_GROUP(tsn0_avtp_match),
2817 static const char * const audio_clk_groups[] = {
2822 static const char * const avb0_groups[] = {
2830 "avb0_avtp_capture",
2834 static const char * const avb1_groups[] = {
2842 "avb1_avtp_capture",
2846 static const char * const avb2_groups[] = {
2854 "avb2_avtp_capture",
2858 static const char * const canfd0_groups[] = {
2862 static const char * const canfd1_groups[] = {
2866 static const char * const canfd2_groups[] = {
2870 static const char * const canfd3_groups[] = {
2874 static const char * const canfd4_groups[] = {
2878 static const char * const canfd5_groups[] = {
2883 static const char * const canfd6_groups[] = {
2887 static const char * const canfd7_groups[] = {
2891 static const char * const can_clk_groups[] = {
2895 static const char * const hscif0_groups[] = {
2901 static const char * const hscif1_groups[] = {
2910 static const char * const hscif2_groups[] = {
2916 static const char * const hscif3_groups[] = {
2925 static const char * const i2c0_groups[] = {
2929 static const char * const i2c1_groups[] = {
2933 static const char * const i2c2_groups[] = {
2937 static const char * const i2c3_groups[] = {
2941 static const char * const i2c4_groups[] = {
2945 static const char * const i2c5_groups[] = {
2949 static const char * const intc_ex_groups[] = {
2963 static const char * const mmc_groups[] = {
2973 static const char * const msiof0_groups[] = {
2982 static const char * const msiof1_groups[] = {
2991 static const char * const msiof2_groups[] = {
3000 static const char * const msiof3_groups[] = {
3009 static const char * const msiof4_groups[] = {
3018 static const char * const msiof5_groups[] = {
3027 static const char * const pcie_groups[] = {
3032 static const char * const pwm0_groups[] = {
3036 static const char * const pwm1_groups[] = {
3041 static const char * const pwm2_groups[] = {
3045 static const char * const pwm3_groups[] = {
3050 static const char * const pwm4_groups[] = {
3054 static const char * const pwm5_groups[] = {
3058 static const char * const pwm6_groups[] = {
3062 static const char * const pwm7_groups[] = {
3066 static const char * const pwm8_groups[] = {
3070 static const char * const pwm9_groups[] = {
3074 static const char * const qspi0_groups[] = {
3080 static const char * const qspi1_groups[] = {
3086 static const char * const scif0_groups[] = {
3092 static const char * const scif1_groups[] = {
3101 static const char * const scif3_groups[] = {
3110 static const char * const scif4_groups[] = {
3116 static const char * const scif_clk_groups[] = {
3120 static const char * const scif_clk2_groups[] = {
3124 static const char * const ssi_groups[] = {
3129 static const char * const tpu_groups[] = {
3140 static const char * const tsn0_groups[] = {
3147 "tsn0_avtp_capture",
3151 static const struct sh_pfc_function pinmux_functions[] = {
3152 SH_PFC_FUNCTION(audio_clk),
3154 SH_PFC_FUNCTION(avb0),
3155 SH_PFC_FUNCTION(avb1),
3156 SH_PFC_FUNCTION(avb2),
3158 SH_PFC_FUNCTION(canfd0),
3159 SH_PFC_FUNCTION(canfd1),
3160 SH_PFC_FUNCTION(canfd2),
3161 SH_PFC_FUNCTION(canfd3),
3162 SH_PFC_FUNCTION(canfd4),
3163 SH_PFC_FUNCTION(canfd5),
3164 SH_PFC_FUNCTION(canfd6),
3165 SH_PFC_FUNCTION(canfd7),
3166 SH_PFC_FUNCTION(can_clk),
3168 SH_PFC_FUNCTION(hscif0),
3169 SH_PFC_FUNCTION(hscif1),
3170 SH_PFC_FUNCTION(hscif2),
3171 SH_PFC_FUNCTION(hscif3),
3173 SH_PFC_FUNCTION(i2c0),
3174 SH_PFC_FUNCTION(i2c1),
3175 SH_PFC_FUNCTION(i2c2),
3176 SH_PFC_FUNCTION(i2c3),
3177 SH_PFC_FUNCTION(i2c4),
3178 SH_PFC_FUNCTION(i2c5),
3180 SH_PFC_FUNCTION(intc_ex),
3182 SH_PFC_FUNCTION(mmc),
3184 SH_PFC_FUNCTION(msiof0),
3185 SH_PFC_FUNCTION(msiof1),
3186 SH_PFC_FUNCTION(msiof2),
3187 SH_PFC_FUNCTION(msiof3),
3188 SH_PFC_FUNCTION(msiof4),
3189 SH_PFC_FUNCTION(msiof5),
3191 SH_PFC_FUNCTION(pcie),
3193 SH_PFC_FUNCTION(pwm0),
3194 SH_PFC_FUNCTION(pwm1),
3195 SH_PFC_FUNCTION(pwm2),
3196 SH_PFC_FUNCTION(pwm3),
3197 SH_PFC_FUNCTION(pwm4),
3198 SH_PFC_FUNCTION(pwm5),
3199 SH_PFC_FUNCTION(pwm6),
3200 SH_PFC_FUNCTION(pwm7),
3201 SH_PFC_FUNCTION(pwm8),
3202 SH_PFC_FUNCTION(pwm9),
3204 SH_PFC_FUNCTION(qspi0),
3205 SH_PFC_FUNCTION(qspi1),
3207 SH_PFC_FUNCTION(scif0),
3208 SH_PFC_FUNCTION(scif1),
3209 SH_PFC_FUNCTION(scif3),
3210 SH_PFC_FUNCTION(scif4),
3211 SH_PFC_FUNCTION(scif_clk),
3212 SH_PFC_FUNCTION(scif_clk2),
3214 SH_PFC_FUNCTION(ssi),
3216 SH_PFC_FUNCTION(tpu),
3218 SH_PFC_FUNCTION(tsn0),
3221 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3222 #define F_(x, y) FN_##y
3223 #define FM(x) FN_##x
3224 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
3225 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3226 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3228 /* GP0_31_19 RESERVED */
3229 GP_0_18_FN, GPSR0_18,
3230 GP_0_17_FN, GPSR0_17,
3231 GP_0_16_FN, GPSR0_16,
3232 GP_0_15_FN, GPSR0_15,
3233 GP_0_14_FN, GPSR0_14,
3234 GP_0_13_FN, GPSR0_13,
3235 GP_0_12_FN, GPSR0_12,
3236 GP_0_11_FN, GPSR0_11,
3237 GP_0_10_FN, GPSR0_10,
3247 GP_0_0_FN, GPSR0_0, ))
3249 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
3253 GP_1_28_FN, GPSR1_28,
3254 GP_1_27_FN, GPSR1_27,
3255 GP_1_26_FN, GPSR1_26,
3256 GP_1_25_FN, GPSR1_25,
3257 GP_1_24_FN, GPSR1_24,
3258 GP_1_23_FN, GPSR1_23,
3259 GP_1_22_FN, GPSR1_22,
3260 GP_1_21_FN, GPSR1_21,
3261 GP_1_20_FN, GPSR1_20,
3262 GP_1_19_FN, GPSR1_19,
3263 GP_1_18_FN, GPSR1_18,
3264 GP_1_17_FN, GPSR1_17,
3265 GP_1_16_FN, GPSR1_16,
3266 GP_1_15_FN, GPSR1_15,
3267 GP_1_14_FN, GPSR1_14,
3268 GP_1_13_FN, GPSR1_13,
3269 GP_1_12_FN, GPSR1_12,
3270 GP_1_11_FN, GPSR1_11,
3271 GP_1_10_FN, GPSR1_10,
3281 GP_1_0_FN, GPSR1_0, ))
3283 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
3284 GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3285 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3287 /* GP2_31_20 RESERVED */
3288 GP_2_19_FN, GPSR2_19,
3289 GP_2_18_FN, GPSR2_18,
3290 GP_2_17_FN, GPSR2_17,
3291 GP_2_16_FN, GPSR2_16,
3292 GP_2_15_FN, GPSR2_15,
3293 GP_2_14_FN, GPSR2_14,
3294 GP_2_13_FN, GPSR2_13,
3295 GP_2_12_FN, GPSR2_12,
3296 GP_2_11_FN, GPSR2_11,
3297 GP_2_10_FN, GPSR2_10,
3307 GP_2_0_FN, GPSR2_0, ))
3309 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
3312 GP_3_29_FN, GPSR3_29,
3313 GP_3_28_FN, GPSR3_28,
3314 GP_3_27_FN, GPSR3_27,
3315 GP_3_26_FN, GPSR3_26,
3316 GP_3_25_FN, GPSR3_25,
3317 GP_3_24_FN, GPSR3_24,
3318 GP_3_23_FN, GPSR3_23,
3319 GP_3_22_FN, GPSR3_22,
3320 GP_3_21_FN, GPSR3_21,
3321 GP_3_20_FN, GPSR3_20,
3322 GP_3_19_FN, GPSR3_19,
3323 GP_3_18_FN, GPSR3_18,
3324 GP_3_17_FN, GPSR3_17,
3325 GP_3_16_FN, GPSR3_16,
3326 GP_3_15_FN, GPSR3_15,
3327 GP_3_14_FN, GPSR3_14,
3328 GP_3_13_FN, GPSR3_13,
3329 GP_3_12_FN, GPSR3_12,
3330 GP_3_11_FN, GPSR3_11,
3331 GP_3_10_FN, GPSR3_10,
3341 GP_3_0_FN, GPSR3_0, ))
3343 { PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(
3351 GP_4_24_FN, GPSR4_24,
3352 GP_4_23_FN, GPSR4_23,
3353 GP_4_22_FN, GPSR4_22,
3354 GP_4_21_FN, GPSR4_21,
3355 GP_4_20_FN, GPSR4_20,
3356 GP_4_19_FN, GPSR4_19,
3357 GP_4_18_FN, GPSR4_18,
3358 GP_4_17_FN, GPSR4_17,
3359 GP_4_16_FN, GPSR4_16,
3360 GP_4_15_FN, GPSR4_15,
3361 GP_4_14_FN, GPSR4_14,
3362 GP_4_13_FN, GPSR4_13,
3363 GP_4_12_FN, GPSR4_12,
3364 GP_4_11_FN, GPSR4_11,
3365 GP_4_10_FN, GPSR4_10,
3375 GP_4_0_FN, GPSR4_0, ))
3377 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
3378 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3379 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3381 /* GP5_31_21 RESERVED */
3382 GP_5_20_FN, GPSR5_20,
3383 GP_5_19_FN, GPSR5_19,
3384 GP_5_18_FN, GPSR5_18,
3385 GP_5_17_FN, GPSR5_17,
3386 GP_5_16_FN, GPSR5_16,
3387 GP_5_15_FN, GPSR5_15,
3388 GP_5_14_FN, GPSR5_14,
3389 GP_5_13_FN, GPSR5_13,
3390 GP_5_12_FN, GPSR5_12,
3391 GP_5_11_FN, GPSR5_11,
3392 GP_5_10_FN, GPSR5_10,
3402 GP_5_0_FN, GPSR5_0, ))
3404 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3405 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3406 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3408 /* GP6_31_21 RESERVED */
3409 GP_6_20_FN, GPSR6_20,
3410 GP_6_19_FN, GPSR6_19,
3411 GP_6_18_FN, GPSR6_18,
3412 GP_6_17_FN, GPSR6_17,
3413 GP_6_16_FN, GPSR6_16,
3414 GP_6_15_FN, GPSR6_15,
3415 GP_6_14_FN, GPSR6_14,
3416 GP_6_13_FN, GPSR6_13,
3417 GP_6_12_FN, GPSR6_12,
3418 GP_6_11_FN, GPSR6_11,
3419 GP_6_10_FN, GPSR6_10,
3429 GP_6_0_FN, GPSR6_0, ))
3431 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3432 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3435 /* GP7_31_21 RESERVED */
3436 GP_7_20_FN, GPSR7_20,
3437 GP_7_19_FN, GPSR7_19,
3438 GP_7_18_FN, GPSR7_18,
3439 GP_7_17_FN, GPSR7_17,
3440 GP_7_16_FN, GPSR7_16,
3441 GP_7_15_FN, GPSR7_15,
3442 GP_7_14_FN, GPSR7_14,
3443 GP_7_13_FN, GPSR7_13,
3444 GP_7_12_FN, GPSR7_12,
3445 GP_7_11_FN, GPSR7_11,
3446 GP_7_10_FN, GPSR7_10,
3456 GP_7_0_FN, GPSR7_0, ))
3458 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
3459 GROUP(-18, 1, 1, 1, 1,
3460 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3462 /* GP8_31_14 RESERVED */
3463 GP_8_13_FN, GPSR8_13,
3464 GP_8_12_FN, GPSR8_12,
3465 GP_8_11_FN, GPSR8_11,
3466 GP_8_10_FN, GPSR8_10,
3476 GP_8_0_FN, GPSR8_0, ))
3482 #define FM(x) FN_##x,
3483 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
3493 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
3503 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3504 GROUP(-20, 4, 4, 4),
3506 /* IP2SR0_31_12 RESERVED */
3511 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
3521 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
3531 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
3541 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3542 GROUP(-12, 4, 4, 4, 4, 4),
3544 /* IP3SR1_31_20 RESERVED */
3551 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
3561 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
3571 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3572 GROUP(-16, 4, 4, 4, 4),
3574 /* IP2SR2_31_16 RESERVED */
3580 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
3590 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
3600 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
3610 { PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
3611 GROUP(-8, 4, 4, 4, 4, 4, 4),
3613 /* IP3SR3_31_24 RESERVED */
3621 { PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32,
3622 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3633 { PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32,
3634 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3645 { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,
3646 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3657 { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,
3660 /* IP3SR4_31_4 RESERVED */
3663 { PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32,
3664 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3675 { PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32,
3676 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3687 { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,
3688 GROUP(-12, 4, 4, 4, 4, 4),
3690 /* IP2SR5_31_20 RESERVED */
3697 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
3707 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
3717 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
3718 GROUP(-12, 4, 4, 4, 4, 4),
3720 /* IP2SR6_31_20 RESERVED */
3727 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
3737 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
3747 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
3748 GROUP(-12, 4, 4, 4, 4, 4),
3750 /* IP2SR7_31_20 RESERVED */
3757 { PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(
3767 { PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,
3768 GROUP(-8, 4, 4, 4, 4, 4, 4),
3770 /* IP1SR8_31_24 RESERVED */
3782 #define FM(x) FN_##x,
3783 { PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
3784 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3786 /* RESERVED 31-12 */
3803 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3804 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
3805 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
3806 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
3807 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
3808 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
3809 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
3810 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
3811 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
3812 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
3814 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
3815 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
3816 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
3817 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
3818 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
3819 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
3820 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
3821 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
3822 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
3824 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
3825 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
3826 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
3827 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
3829 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
3830 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */
3831 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */
3832 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */
3833 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */
3834 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */
3835 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */
3836 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */
3837 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
3839 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
3840 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */
3841 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */
3842 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */
3843 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */
3844 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */
3845 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */
3846 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
3847 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
3849 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
3850 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */
3851 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */
3852 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */
3853 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */
3854 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */
3855 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */
3856 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */
3857 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
3859 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
3860 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */
3861 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */
3862 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */
3863 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */
3864 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
3866 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
3867 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */
3868 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */
3869 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */
3870 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */
3871 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */
3872 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */
3873 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */
3874 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
3876 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
3877 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */
3878 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */
3879 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */
3880 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */
3881 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */
3882 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */
3883 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
3884 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
3886 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
3887 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */
3888 { RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */
3889 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */
3890 { RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */
3892 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
3893 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */
3894 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */
3895 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */
3896 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */
3897 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */
3898 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */
3899 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */
3900 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
3902 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
3903 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */
3904 { RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */
3905 { RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */
3906 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */
3907 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */
3908 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */
3909 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
3910 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
3912 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
3913 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */
3914 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */
3915 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */
3916 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */
3917 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */
3918 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */
3919 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */
3920 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
3922 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
3923 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */
3924 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */
3925 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */
3926 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */
3927 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */
3928 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
3930 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
3931 { RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */
3932 { RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */
3933 { RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */
3934 { RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */
3935 { RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */
3936 { RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */
3937 { RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */
3938 { RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */
3940 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
3941 { RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */
3942 { RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */
3943 { RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */
3944 { RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */
3945 { RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */
3946 { RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */
3947 { RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */
3948 { RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */
3950 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
3951 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */
3952 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3953 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3954 { RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */
3955 { RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */
3956 { RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */
3957 { RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */
3958 { RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */
3960 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
3961 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
3963 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
3964 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */
3965 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */
3966 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */
3967 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */
3968 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */
3969 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */
3970 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */
3971 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
3973 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
3974 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */
3975 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */
3976 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */
3977 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */
3978 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */
3979 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */
3980 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
3981 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
3983 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
3984 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */
3985 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */
3986 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */
3987 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */
3988 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
3990 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
3991 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */
3992 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */
3993 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */
3994 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */
3995 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */
3996 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */
3997 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */
3998 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
4000 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
4001 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */
4002 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */
4003 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */
4004 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */
4005 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */
4006 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */
4007 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
4008 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
4010 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
4011 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */
4012 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */
4013 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */
4014 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */
4015 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
4017 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
4018 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */
4019 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */
4020 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */
4021 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */
4022 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */
4023 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */
4024 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */
4025 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
4027 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
4028 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */
4029 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */
4030 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */
4031 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */
4032 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */
4033 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */
4034 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
4035 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
4037 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
4038 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */
4039 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */
4040 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */
4041 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */
4042 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
4044 { PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {
4045 { RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */
4046 { RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */
4047 { RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */
4048 { RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */
4049 { RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */
4050 { RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */
4051 { RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */
4052 { RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */
4054 { PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {
4055 { RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */
4056 { RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */
4057 { RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */
4058 { RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */
4059 { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
4060 { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
4076 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
4077 [POC0] = { 0xE60500A0, },
4078 [POC1] = { 0xE60508A0, },
4079 [POC3] = { 0xE60588A0, },
4080 [POC4] = { 0xE60600A0, },
4081 [POC5] = { 0xE60608A0, },
4082 [POC6] = { 0xE60610A0, },
4083 [POC7] = { 0xE60618A0, },
4084 [POC8] = { 0xE60680A0, },
4088 static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
4090 int bit = pin & 0x1f;
4093 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
4094 *pocctrl = pinmux_ioctrl_regs[POC0].reg;
4097 case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
4098 *pocctrl = pinmux_ioctrl_regs[POC1].reg;
4101 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
4102 *pocctrl = pinmux_ioctrl_regs[POC3].reg;
4106 *pocctrl = pinmux_ioctrl_regs[POC4].reg;
4110 *pocctrl = pinmux_ioctrl_regs[POC5].reg;
4114 *pocctrl = pinmux_ioctrl_regs[POC6].reg;
4118 *pocctrl = pinmux_ioctrl_regs[POC7].reg;
4121 case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
4122 *pocctrl = pinmux_ioctrl_regs[POC8].reg;
4130 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4131 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
4132 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
4133 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
4134 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
4135 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
4136 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
4137 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
4138 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
4139 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
4140 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
4141 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
4142 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
4143 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
4144 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
4145 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
4146 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
4147 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
4148 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
4149 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
4150 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
4151 [19] = SH_PFC_PIN_NONE,
4152 [20] = SH_PFC_PIN_NONE,
4153 [21] = SH_PFC_PIN_NONE,
4154 [22] = SH_PFC_PIN_NONE,
4155 [23] = SH_PFC_PIN_NONE,
4156 [24] = SH_PFC_PIN_NONE,
4157 [25] = SH_PFC_PIN_NONE,
4158 [26] = SH_PFC_PIN_NONE,
4159 [27] = SH_PFC_PIN_NONE,
4160 [28] = SH_PFC_PIN_NONE,
4161 [29] = SH_PFC_PIN_NONE,
4162 [30] = SH_PFC_PIN_NONE,
4163 [31] = SH_PFC_PIN_NONE,
4165 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
4166 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
4167 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */
4168 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */
4169 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */
4170 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */
4171 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */
4172 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */
4173 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */
4174 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */
4175 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
4176 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */
4177 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */
4178 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */
4179 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */
4180 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */
4181 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */
4182 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */
4183 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */
4184 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */
4185 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */
4186 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */
4187 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */
4188 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */
4189 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */
4190 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */
4191 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */
4192 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */
4193 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */
4194 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */
4195 [29] = SH_PFC_PIN_NONE,
4196 [30] = SH_PFC_PIN_NONE,
4197 [31] = SH_PFC_PIN_NONE,
4199 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
4200 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
4201 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */
4202 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */
4203 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */
4204 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */
4205 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */
4206 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */
4207 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */
4208 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */
4209 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
4210 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */
4211 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */
4212 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */
4213 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */
4214 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */
4215 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */
4216 [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */
4217 [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */
4218 [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */
4219 [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */
4220 [20] = SH_PFC_PIN_NONE,
4221 [21] = SH_PFC_PIN_NONE,
4222 [22] = SH_PFC_PIN_NONE,
4223 [23] = SH_PFC_PIN_NONE,
4224 [24] = SH_PFC_PIN_NONE,
4225 [25] = SH_PFC_PIN_NONE,
4226 [26] = SH_PFC_PIN_NONE,
4227 [27] = SH_PFC_PIN_NONE,
4228 [28] = SH_PFC_PIN_NONE,
4229 [29] = SH_PFC_PIN_NONE,
4230 [30] = SH_PFC_PIN_NONE,
4231 [31] = SH_PFC_PIN_NONE,
4233 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
4234 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
4235 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */
4236 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */
4237 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */
4238 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */
4239 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */
4240 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */
4241 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */
4242 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */
4243 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
4244 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */
4245 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */
4246 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */
4247 [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */
4248 [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */
4249 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */
4250 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */
4251 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */
4252 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */
4253 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */
4254 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */
4255 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */
4256 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */
4257 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */
4258 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */
4259 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */
4260 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */
4261 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */
4262 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */
4263 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */
4264 [30] = SH_PFC_PIN_NONE,
4265 [31] = SH_PFC_PIN_NONE,
4267 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
4268 [ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */
4269 [ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */
4270 [ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */
4271 [ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */
4272 [ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */
4273 [ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */
4274 [ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */
4275 [ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */
4276 [ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */
4277 [ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */
4278 [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */
4279 [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */
4280 [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */
4281 [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */
4282 [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */
4283 [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */
4284 [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */
4285 [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */
4286 [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */
4287 [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */
4288 [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */
4289 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
4290 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
4291 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */
4292 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */
4293 [25] = SH_PFC_PIN_NONE,
4294 [26] = SH_PFC_PIN_NONE,
4295 [27] = SH_PFC_PIN_NONE,
4296 [28] = SH_PFC_PIN_NONE,
4297 [29] = SH_PFC_PIN_NONE,
4298 [30] = SH_PFC_PIN_NONE,
4299 [31] = SH_PFC_PIN_NONE,
4301 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
4302 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
4303 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */
4304 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */
4305 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */
4306 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */
4307 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */
4308 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */
4309 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */
4310 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */
4311 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
4312 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */
4313 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */
4314 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */
4315 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */
4316 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */
4317 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */
4318 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */
4319 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */
4320 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */
4321 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */
4322 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */
4323 [21] = SH_PFC_PIN_NONE,
4324 [22] = SH_PFC_PIN_NONE,
4325 [23] = SH_PFC_PIN_NONE,
4326 [24] = SH_PFC_PIN_NONE,
4327 [25] = SH_PFC_PIN_NONE,
4328 [26] = SH_PFC_PIN_NONE,
4329 [27] = SH_PFC_PIN_NONE,
4330 [28] = SH_PFC_PIN_NONE,
4331 [29] = SH_PFC_PIN_NONE,
4332 [30] = SH_PFC_PIN_NONE,
4333 [31] = SH_PFC_PIN_NONE,
4335 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
4336 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
4337 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */
4338 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */
4339 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */
4340 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */
4341 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */
4342 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */
4343 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */
4344 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */
4345 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
4346 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */
4347 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */
4348 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */
4349 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */
4350 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/
4351 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */
4352 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */
4353 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */
4354 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */
4355 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */
4356 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */
4357 [21] = SH_PFC_PIN_NONE,
4358 [22] = SH_PFC_PIN_NONE,
4359 [23] = SH_PFC_PIN_NONE,
4360 [24] = SH_PFC_PIN_NONE,
4361 [25] = SH_PFC_PIN_NONE,
4362 [26] = SH_PFC_PIN_NONE,
4363 [27] = SH_PFC_PIN_NONE,
4364 [28] = SH_PFC_PIN_NONE,
4365 [29] = SH_PFC_PIN_NONE,
4366 [30] = SH_PFC_PIN_NONE,
4367 [31] = SH_PFC_PIN_NONE,
4369 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
4370 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
4371 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */
4372 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */
4373 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */
4374 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */
4375 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */
4376 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */
4377 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */
4378 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */
4379 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
4380 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */
4381 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */
4382 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */
4383 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */
4384 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */
4385 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */
4386 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */
4387 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */
4388 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */
4389 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */
4390 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */
4391 [21] = SH_PFC_PIN_NONE,
4392 [22] = SH_PFC_PIN_NONE,
4393 [23] = SH_PFC_PIN_NONE,
4394 [24] = SH_PFC_PIN_NONE,
4395 [25] = SH_PFC_PIN_NONE,
4396 [26] = SH_PFC_PIN_NONE,
4397 [27] = SH_PFC_PIN_NONE,
4398 [28] = SH_PFC_PIN_NONE,
4399 [29] = SH_PFC_PIN_NONE,
4400 [30] = SH_PFC_PIN_NONE,
4401 [31] = SH_PFC_PIN_NONE,
4403 { PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {
4404 [ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */
4405 [ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */
4406 [ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */
4407 [ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */
4408 [ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */
4409 [ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */
4410 [ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */
4411 [ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */
4412 [ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */
4413 [ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */
4414 [10] = RCAR_GP_PIN(8, 10), /* SCL5 */
4415 [11] = RCAR_GP_PIN(8, 11), /* SDA5 */
4416 [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */
4417 [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */
4418 [14] = SH_PFC_PIN_NONE,
4419 [15] = SH_PFC_PIN_NONE,
4420 [16] = SH_PFC_PIN_NONE,
4421 [17] = SH_PFC_PIN_NONE,
4422 [18] = SH_PFC_PIN_NONE,
4423 [19] = SH_PFC_PIN_NONE,
4424 [20] = SH_PFC_PIN_NONE,
4425 [21] = SH_PFC_PIN_NONE,
4426 [22] = SH_PFC_PIN_NONE,
4427 [23] = SH_PFC_PIN_NONE,
4428 [24] = SH_PFC_PIN_NONE,
4429 [25] = SH_PFC_PIN_NONE,
4430 [26] = SH_PFC_PIN_NONE,
4431 [27] = SH_PFC_PIN_NONE,
4432 [28] = SH_PFC_PIN_NONE,
4433 [29] = SH_PFC_PIN_NONE,
4434 [30] = SH_PFC_PIN_NONE,
4435 [31] = SH_PFC_PIN_NONE,
4440 static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
4441 .pin_to_pocctrl = r8a779g0_pin_to_pocctrl,
4442 .get_bias = rcar_pinmux_get_bias,
4443 .set_bias = rcar_pinmux_set_bias,
4446 const struct sh_pfc_soc_info r8a779g0_pinmux_info = {
4447 .name = "r8a779g0_pfc",
4448 .ops = &r8a779g0_pin_ops,
4449 .unlock_reg = 0x1ff, /* PMMRn mask */
4451 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4453 .pins = pinmux_pins,
4454 .nr_pins = ARRAY_SIZE(pinmux_pins),
4455 .groups = pinmux_groups,
4456 .nr_groups = ARRAY_SIZE(pinmux_groups),
4457 .functions = pinmux_functions,
4458 .nr_functions = ARRAY_SIZE(pinmux_functions),
4460 .cfg_regs = pinmux_config_regs,
4461 .drive_regs = pinmux_drive_regs,
4462 .bias_regs = pinmux_bias_regs,
4463 .ioctrl_regs = pinmux_ioctrl_regs,
4465 .pinmux_data = pinmux_data,
4466 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / linux.git / blob