1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 MediaTek Inc.
7 #include "phy-mtk-hdmi.h"
9 static int mtk_hdmi_phy_power_on(struct phy *phy);
10 static int mtk_hdmi_phy_power_off(struct phy *phy);
11 static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opts *opts);
13 static const struct phy_ops mtk_hdmi_phy_dev_ops = {
14 .power_on = mtk_hdmi_phy_power_on,
15 .power_off = mtk_hdmi_phy_power_off,
16 .configure = mtk_hdmi_phy_configure,
20 inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
22 return container_of(hw, struct mtk_hdmi_phy, pll_hw);
25 static int mtk_hdmi_phy_power_on(struct phy *phy)
27 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
30 ret = clk_prepare_enable(hdmi_phy->pll);
34 hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
38 static int mtk_hdmi_phy_power_off(struct phy *phy)
40 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
42 hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
43 clk_disable_unprepare(hdmi_phy->pll);
48 static int mtk_hdmi_phy_configure(struct phy *phy, union phy_configure_opts *opts)
50 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
52 if (hdmi_phy->conf->hdmi_phy_configure)
53 return hdmi_phy->conf->hdmi_phy_configure(phy, opts);
58 static const struct phy_ops *
59 mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
61 if (hdmi_phy && hdmi_phy->conf &&
62 hdmi_phy->conf->hdmi_phy_enable_tmds &&
63 hdmi_phy->conf->hdmi_phy_disable_tmds)
64 return &mtk_hdmi_phy_dev_ops;
67 dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
71 static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy,
72 struct clk_init_data *clk_init)
74 clk_init->flags = hdmi_phy->conf->flags;
75 clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops;
78 static int mtk_hdmi_phy_register_regulators(struct mtk_hdmi_phy *hdmi_phy)
80 const struct regulator_desc *vreg_desc = hdmi_phy->conf->hdmi_phy_regulator_desc;
81 const struct regulator_init_data vreg_init_data = {
83 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
86 struct regulator_config vreg_config = {
88 .driver_data = hdmi_phy,
89 .init_data = &vreg_init_data,
90 .of_node = hdmi_phy->dev->of_node
93 hdmi_phy->rdev = devm_regulator_register(hdmi_phy->dev, vreg_desc, &vreg_config);
94 if (IS_ERR(hdmi_phy->rdev))
95 return PTR_ERR(hdmi_phy->rdev);
100 static int mtk_hdmi_phy_probe(struct platform_device *pdev)
102 struct device *dev = &pdev->dev;
103 struct mtk_hdmi_phy *hdmi_phy;
105 const char *ref_clk_name;
106 struct clk_init_data clk_init = {
108 .parent_names = (const char * const *)&ref_clk_name,
112 struct phy_provider *phy_provider;
115 hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
119 hdmi_phy->regs = devm_platform_ioremap_resource(pdev, 0);
120 if (IS_ERR(hdmi_phy->regs))
121 return PTR_ERR(hdmi_phy->regs);
123 ref_clk = devm_clk_get(dev, "pll_ref");
125 return dev_err_probe(dev, PTR_ERR(ref_clk),
126 "Failed to get PLL reference clock\n");
128 ref_clk_name = __clk_get_name(ref_clk);
130 ret = of_property_read_string(dev->of_node, "clock-output-names",
133 return dev_err_probe(dev, ret, "Failed to read clock-output-names\n");
137 (struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
138 mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init);
139 hdmi_phy->pll_hw.init = &clk_init;
140 hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
141 if (IS_ERR(hdmi_phy->pll))
142 return dev_err_probe(dev, PTR_ERR(hdmi_phy->pll),
143 "Failed to register PLL\n");
145 ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
148 return dev_err_probe(dev, ret, "Failed to get ibias\n");
150 ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
151 &hdmi_phy->ibias_up);
153 return dev_err_probe(dev, ret, "Failed to get ibias_up\n");
155 dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
156 hdmi_phy->drv_imp_clk = 0x30;
157 hdmi_phy->drv_imp_d2 = 0x30;
158 hdmi_phy->drv_imp_d1 = 0x30;
159 hdmi_phy->drv_imp_d0 = 0x30;
161 phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
163 return dev_err_probe(dev, PTR_ERR(phy), "Cannot create HDMI PHY\n");
165 phy_set_drvdata(phy, hdmi_phy);
167 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
168 if (IS_ERR(phy_provider))
169 return dev_err_probe(dev, PTR_ERR(phy_provider),
170 "Failed to register HDMI PHY\n");
172 if (hdmi_phy->conf->pll_default_off)
173 hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
175 if (hdmi_phy->conf->hdmi_phy_regulator_desc) {
176 ret = mtk_hdmi_phy_register_regulators(hdmi_phy);
181 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
185 static const struct of_device_id mtk_hdmi_phy_match[] = {
186 { .compatible = "mediatek,mt2701-hdmi-phy",
187 .data = &mtk_hdmi_phy_2701_conf,
189 { .compatible = "mediatek,mt8173-hdmi-phy",
190 .data = &mtk_hdmi_phy_8173_conf,
192 { .compatible = "mediatek,mt8195-hdmi-phy",
193 .data = &mtk_hdmi_phy_8195_conf,
197 MODULE_DEVICE_TABLE(of, mtk_hdmi_phy_match);
199 static struct platform_driver mtk_hdmi_phy_driver = {
200 .probe = mtk_hdmi_phy_probe,
202 .name = "mediatek-hdmi-phy",
203 .of_match_table = mtk_hdmi_phy_match,
206 module_platform_driver(mtk_hdmi_phy_driver);
208 MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
209 MODULE_LICENSE("GPL v2");