drivers/phy/broadcom/phy-brcm-usb-init.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
   4  *
   5  * Copyright (C) 2014-2017 Broadcom
   6  */
   7
   8 /*
   9  * This module contains USB PHY initialization for power up and S3 resume
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/io.h>
  14
  15 #include <linux/soc/brcmstb/brcmstb.h>
  16 #include "phy-brcm-usb-init.h"
  17
  18 #define PHY_PORTS 2
  19 #define PHY_PORT_SELECT_0 0
  20 #define PHY_PORT_SELECT_1 0x1000
  21
  22 /* Register definitions for the USB CTRL block */
  23 #define USB_CTRL_SETUP                  0x00
  24 #define   USB_CTRL_SETUP_BABO_MASK                      BIT(0)
  25 #define   USB_CTRL_SETUP_FNHW_MASK                      BIT(1)
  26 #define   USB_CTRL_SETUP_FNBO_MASK                      BIT(2)
  27 #define   USB_CTRL_SETUP_WABO_MASK                      BIT(3)
  28 #define   USB_CTRL_SETUP_IOC_MASK                       BIT(4)
  29 #define   USB_CTRL_SETUP_IPP_MASK                       BIT(5)
  30 #define   USB_CTRL_SETUP_SCB_CLIENT_SWAP_MASK           BIT(13) /* option */
  31 #define   USB_CTRL_SETUP_SCB1_EN_MASK                   BIT(14) /* option */
  32 #define   USB_CTRL_SETUP_SCB2_EN_MASK                   BIT(15) /* option */
  33 #define   USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK           BIT(17) /* option */
  34 #define   USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK       BIT(16) /* option */
  35 #define   USB_CTRL_SETUP_STRAP_IPP_SEL_MASK             BIT(25) /* option */
  36 #define   USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK        BIT(26) /* option */
  37 #define   USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK BIT(27) /* opt */
  38 #define   USB_CTRL_SETUP_OC_DISABLE_PORT0_MASK          BIT(28)
  39 #define   USB_CTRL_SETUP_OC_DISABLE_PORT1_MASK          BIT(29)
  40 #define   USB_CTRL_SETUP_OC_DISABLE_MASK                GENMASK(29, 28) /* option */
  41 #define   USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK         BIT(30)
  42 #define   USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK         BIT(31)
  43 #define   USB_CTRL_SETUP_OC3_DISABLE_MASK               GENMASK(31, 30) /* option */
  44 #define USB_CTRL_PLL_CTL                0x04
  45 #define   USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK          BIT(27)
  46 #define   USB_CTRL_PLL_CTL_PLL_RESETB_MASK              BIT(30)
  47 #define   USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK          BIT(31) /* option */
  48 #define USB_CTRL_EBRIDGE                0x0c
  49 #define   USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK            GENMASK(11, 7) /* option */
  50 #define   USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK           BIT(17) /* option */
  51 #define USB_CTRL_OBRIDGE                0x10
  52 #define   USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK           BIT(27)
  53 #define USB_CTRL_MDIO                   0x14
  54 #define USB_CTRL_MDIO2                  0x18
  55 #define USB_CTRL_UTMI_CTL_1             0x2c
  56 #define   USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK      BIT(11)
  57 #define   USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK   BIT(27)
  58 #define USB_CTRL_USB_PM                 0x34
  59 #define   USB_CTRL_USB_PM_RMTWKUP_EN_MASK               BIT(0)
  60 #define   USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK      GENMASK(21, 20) /* option */
  61 #define   USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK          BIT(22) /* option */
  62 #define   USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK          BIT(23) /* option */
  63 #define   USB_CTRL_USB_PM_USB20_HC_RESETB_MASK          GENMASK(29, 28) /* option */
  64 #define   USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK      BIT(30) /* option */
  65 #define   USB_CTRL_USB_PM_SOFT_RESET_MASK               BIT(30) /* option */
  66 #define   USB_CTRL_USB_PM_USB_PWRDN_MASK                BIT(31) /* option */
  67 #define USB_CTRL_USB_PM_STATUS          0x38
  68 #define USB_CTRL_USB30_CTL1             0x60
  69 #define   USB_CTRL_USB30_CTL1_PHY3_PLL_SEQ_START_MASK   BIT(4)
  70 #define   USB_CTRL_USB30_CTL1_PHY3_RESETB_MASK          BIT(16)
  71 #define   USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK      BIT(17) /* option */
  72 #define   USB_CTRL_USB30_CTL1_USB3_IOC_MASK             BIT(28) /* option */
  73 #define   USB_CTRL_USB30_CTL1_USB3_IPP_MASK             BIT(29) /* option */
  74 #define USB_CTRL_USB30_PCTL             0x70
  75 #define   USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK     BIT(1)
  76 #define   USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK   BIT(15)
  77 #define   USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK  BIT(17)
  78 #define USB_CTRL_USB_DEVICE_CTL1        0x90
  79 #define   USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK       GENMASK(1, 0) /* option */
  80
  81 /* Register definitions for the XHCI EC block */
  82 #define USB_XHCI_EC_IRAADR 0x658
  83 #define USB_XHCI_EC_IRADAT 0x65c
  84
  85 enum brcm_family_type {
  86         BRCM_FAMILY_3390A0,
  87         BRCM_FAMILY_4908,
  88         BRCM_FAMILY_7250B0,
  89         BRCM_FAMILY_7271A0,
  90         BRCM_FAMILY_7364A0,
  91         BRCM_FAMILY_7366C0,
  92         BRCM_FAMILY_74371A0,
  93         BRCM_FAMILY_7439B0,
  94         BRCM_FAMILY_7445D0,
  95         BRCM_FAMILY_7260A0,
  96         BRCM_FAMILY_7278A0,
  97         BRCM_FAMILY_COUNT,
  98 };
  99
 100 #define USB_BRCM_FAMILY(chip) \
 101         [BRCM_FAMILY_##chip] = __stringify(chip)
 102
 103 static const char *family_names[BRCM_FAMILY_COUNT] = {
 104         USB_BRCM_FAMILY(3390A0),
 105         USB_BRCM_FAMILY(4908),
 106         USB_BRCM_FAMILY(7250B0),
 107         USB_BRCM_FAMILY(7271A0),
 108         USB_BRCM_FAMILY(7364A0),
 109         USB_BRCM_FAMILY(7366C0),
 110         USB_BRCM_FAMILY(74371A0),
 111         USB_BRCM_FAMILY(7439B0),
 112         USB_BRCM_FAMILY(7445D0),
 113         USB_BRCM_FAMILY(7260A0),
 114         USB_BRCM_FAMILY(7278A0),
 115 };
 116
 117 enum {
 118         USB_CTRL_SETUP_SCB1_EN_SELECTOR,
 119         USB_CTRL_SETUP_SCB2_EN_SELECTOR,
 120         USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR,
 121         USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR,
 122         USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR,
 123         USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR,
 124         USB_CTRL_SETUP_OC3_DISABLE_SELECTOR,
 125         USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR,
 126         USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR,
 127         USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR,
 128         USB_CTRL_USB_PM_USB_PWRDN_SELECTOR,
 129         USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR,
 130         USB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR,
 131         USB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR,
 132         USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR,
 133         USB_CTRL_USB_PM_SOFT_RESET_SELECTOR,
 134         USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR,
 135         USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR,
 136         USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR,
 137         USB_CTRL_SETUP_ENDIAN_SELECTOR,
 138         USB_CTRL_SELECTOR_COUNT,
 139 };
 140
 141 #define USB_CTRL_MASK_FAMILY(params, reg, field)                        \
 142         (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
 143
 144 #define USB_CTRL_SET_FAMILY(params, reg, field) \
 145         usb_ctrl_set_family(params, USB_CTRL_##reg,     \
 146                         USB_CTRL_##reg##_##field##_SELECTOR)
 147 #define USB_CTRL_UNSET_FAMILY(params, reg, field)       \
 148         usb_ctrl_unset_family(params, USB_CTRL_##reg,   \
 149                 USB_CTRL_##reg##_##field##_SELECTOR)
 150
 151 #define MDIO_USB2       0
 152 #define MDIO_USB3       BIT(31)
 153
 154 #define USB_CTRL_SETUP_ENDIAN_BITS (    \
 155                 USB_CTRL_MASK(SETUP, BABO) |    \
 156                 USB_CTRL_MASK(SETUP, FNHW) |    \
 157                 USB_CTRL_MASK(SETUP, FNBO) |    \
 158                 USB_CTRL_MASK(SETUP, WABO))
 159
 160 #ifdef __LITTLE_ENDIAN
 161 #define ENDIAN_SETTINGS (                       \
 162                 USB_CTRL_MASK(SETUP, BABO) |    \
 163                 USB_CTRL_MASK(SETUP, FNHW))
 164 #else
 165 #define ENDIAN_SETTINGS (                       \
 166                 USB_CTRL_MASK(SETUP, FNHW) |    \
 167                 USB_CTRL_MASK(SETUP, FNBO) |    \
 168                 USB_CTRL_MASK(SETUP, WABO))
 169 #endif
 170
 171 struct id_to_type {
 172         u32 id;
 173         int type;
 174 };
 175
 176 static const struct id_to_type id_to_type_table[] = {
 177         { 0x33900000, BRCM_FAMILY_3390A0 },
 178         { 0x72500010, BRCM_FAMILY_7250B0 },
 179         { 0x72600000, BRCM_FAMILY_7260A0 },
 180         { 0x72550000, BRCM_FAMILY_7260A0 },
 181         { 0x72680000, BRCM_FAMILY_7271A0 },
 182         { 0x72710000, BRCM_FAMILY_7271A0 },
 183         { 0x73640000, BRCM_FAMILY_7364A0 },
 184         { 0x73660020, BRCM_FAMILY_7366C0 },
 185         { 0x07437100, BRCM_FAMILY_74371A0 },
 186         { 0x74390010, BRCM_FAMILY_7439B0 },
 187         { 0x74450030, BRCM_FAMILY_7445D0 },
 188         { 0x72780000, BRCM_FAMILY_7278A0 },
 189         { 0, BRCM_FAMILY_7271A0 }, /* default */
 190 };
 191
 192 static const u32
 193 usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
 194         /* 3390B0 */
 195         [BRCM_FAMILY_3390A0] = {
 196                 [USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
 197                         USB_CTRL_SETUP_SCB1_EN_MASK,
 198                 [USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
 199                         USB_CTRL_SETUP_SCB2_EN_MASK,
 200                 [USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
 201                         USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 202                 [USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR] =
 203                         USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 204                 [USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
 205                         USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
 206                 [USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
 207                         USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
 208                 [USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
 209                         USB_CTRL_SETUP_OC3_DISABLE_MASK,
 210                 [USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
 211                         USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 212                 [USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
 213                         USB_CTRL_USB_PM_USB_PWRDN_MASK,
 214                 [USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR] =
 215                         USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 216                 [USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
 217                         USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 218                 [USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
 219         },
 220         /* 4908 */
 221         [BRCM_FAMILY_4908] = {
 222                 [USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
 223                         USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 224                 [USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
 225                         USB_CTRL_USB_PM_USB_PWRDN_MASK,
 226         },
 227         /* 7250b0 */
 228         [BRCM_FAMILY_7250B0] = {
 229                 [USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
 230                         USB_CTRL_SETUP_SCB1_EN_MASK,
 231                 [USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
 232                         USB_CTRL_SETUP_SCB2_EN_MASK,
 233                 [USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
 234                         USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 235                 [USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
 236                         USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
 237                 [USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
 238                         USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
 239                 [USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
 240                         USB_CTRL_SETUP_OC3_DISABLE_MASK,
 241                 [USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR] =
 242                         USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 243                 [USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
 244                         USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
 245                 [USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
 246                         USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
 247                 [USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
 248         },
 249         /* 7271a0 */
 250         [BRCM_FAMILY_7271A0] = {
 251                 [USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
 252                         USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 253                 [USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR] =
 254                         USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 255                 [USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
 256                         USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
 257                 [USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
 258                         USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
 259                 [USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
 260                         USB_CTRL_SETUP_OC3_DISABLE_MASK,
 261                 [USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR] =
 262                         USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 263                 [USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
 264                         USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 265                 [USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
 266                         USB_CTRL_USB_PM_USB_PWRDN_MASK,
 267                 [USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR] =
 268                         USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 269                 [USB_CTRL_USB_PM_SOFT_RESET_SELECTOR] =
 270                         USB_CTRL_USB_PM_SOFT_RESET_MASK,
 271                 [USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR] =
 272                         USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
 273                 [USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR] =
 274                         USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
 275                 [USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
 276                         USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 277                 [USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
 278         },
 279         /* 7364a0 */
 280         [BRCM_FAMILY_7364A0] = {
 281                 [USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
 282                         USB_CTRL_SETUP_SCB1_EN_MASK,
 283                 [USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
 284                         USB_CTRL_SETUP_SCB2_EN_MASK,
 285                 [USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
 286                         USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 287                 [USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
 288                         USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
 289                 [USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
 290                         USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
 291                 [USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
 292                         USB_CTRL_SETUP_OC3_DISABLE_MASK,
 293                 [USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR] =
 294                         USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 295                 [USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
 296                         USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
 297                 [USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
 298                         USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
 299                 [USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
 300         },
 301         /* 7366c0 */
 302         [BRCM_FAMILY_7366C0] = {
 303                 [USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
 304                         USB_CTRL_SETUP_SCB1_EN_MASK,
 305                 [USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
 306                         USB_CTRL_SETUP_SCB2_EN_MASK,
 307                 [USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
 308                         USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 309                 [USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
 310                         USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
 311                 [USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
 312                         USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
 313                 [USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
 314                         USB_CTRL_SETUP_OC3_DISABLE_MASK,
 315                 [USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
 316                         USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
 317                 [USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
 318                         USB_CTRL_USB_PM_USB_PWRDN_MASK,
 319                 [USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
 320                         USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
 321                 [USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
 322         },
 323         /* 74371A0 */
 324         [BRCM_FAMILY_74371A0] = {
 325                 [USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
 326                         USB_CTRL_SETUP_SCB1_EN_MASK,
 327                 [USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
 328                         USB_CTRL_SETUP_SCB2_EN_MASK,
 329                 [USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
 330                         USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
 331                 [USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR] =
 332                         USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 333                 [USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR] =
 334                         USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
 335                 [USB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR] =
 336                         USB_CTRL_USB30_CTL1_USB3_IOC_MASK,
 337                 [USB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR] =
 338                         USB_CTRL_USB30_CTL1_USB3_IPP_MASK,
 339                 [USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
 340         },
 341         /* 7439B0 */
 342         [BRCM_FAMILY_7439B0] = {
 343                 [USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
 344                         USB_CTRL_SETUP_SCB1_EN_MASK,
 345                 [USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
 346                         USB_CTRL_SETUP_SCB2_EN_MASK,
 347                 [USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
 348                         USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 349                 [USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR] =
 350                         USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 351                 [USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
 352                         USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
 353                 [USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
 354                         USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
 355                 [USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
 356                         USB_CTRL_SETUP_OC3_DISABLE_MASK,
 357                 [USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR] =
 358                         USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 359                 [USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
 360                         USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 361                 [USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
 362                         USB_CTRL_USB_PM_USB_PWRDN_MASK,
 363                 [USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR] =
 364                         USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 365                 [USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
 366                         USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 367                 [USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
 368         },
 369         /* 7445d0 */
 370         [BRCM_FAMILY_7445D0] = {
 371                 [USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
 372                         USB_CTRL_SETUP_SCB1_EN_MASK,
 373                 [USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
 374                         USB_CTRL_SETUP_SCB2_EN_MASK,
 375                 [USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
 376                         USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
 377                 [USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
 378                         USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
 379                 [USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
 380                         USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
 381                 [USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
 382                         USB_CTRL_SETUP_OC3_DISABLE_MASK,
 383                 [USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR] =
 384                         USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 385                 [USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR] =
 386                         USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
 387                 [USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
 388                         USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 389                 [USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
 390         },
 391         /* 7260a0 */
 392         [BRCM_FAMILY_7260A0] = {
 393                 [USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
 394                         USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 395                 [USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR] =
 396                         USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 397                 [USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
 398                         USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
 399                 [USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
 400                         USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
 401                 [USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
 402                         USB_CTRL_SETUP_OC3_DISABLE_MASK,
 403                 [USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR] =
 404                         USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 405                 [USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
 406                         USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 407                 [USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
 408                         USB_CTRL_USB_PM_USB_PWRDN_MASK,
 409                 [USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR] =
 410                         USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 411                 [USB_CTRL_USB_PM_SOFT_RESET_SELECTOR] =
 412                         USB_CTRL_USB_PM_SOFT_RESET_MASK,
 413                 [USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR] =
 414                         USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
 415                 [USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR] =
 416                         USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
 417                 [USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
 418                         USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 419                 [USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
 420         },
 421         /* 7278a0 */
 422         [BRCM_FAMILY_7278A0] = {
 423                 [USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR] =
 424                         USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 425                 [USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
 426                         USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
 427                 [USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
 428                         USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
 429                 [USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
 430                         USB_CTRL_SETUP_OC3_DISABLE_MASK,
 431                 [USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR] =
 432                         USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 433                 [USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
 434                         USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 435                 [USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
 436                         USB_CTRL_USB_PM_USB_PWRDN_MASK,
 437                 [USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR] =
 438                         USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 439                 [USB_CTRL_USB_PM_SOFT_RESET_SELECTOR] =
 440                         USB_CTRL_USB_PM_SOFT_RESET_MASK,
 441         },
 442 };
 443
 444 static inline
 445 void usb_ctrl_unset_family(struct brcm_usb_init_params *params,
 446                            u32 reg_offset, u32 field)
 447 {
 448         u32 mask;
 449
 450         mask = params->usb_reg_bits_map[field];
 451         brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask);
 452 };
 453
 454 static inline
 455 void usb_ctrl_set_family(struct brcm_usb_init_params *params,
 456                          u32 reg_offset, u32 field)
 457 {
 458         u32 mask;
 459
 460         mask = params->usb_reg_bits_map[field];
 461         brcm_usb_ctrl_set(params->regs[BRCM_REGS_CTRL] + reg_offset, mask);
 462 };
 463
 464 static u32 brcmusb_usb_mdio_read(void __iomem *ctrl_base, u32 reg, int mode)
 465 {
 466         u32 data;
 467
 468         data = (reg << 16) | mode;
 469         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 470         data |= (1 << 24);
 471         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 472         data &= ~(1 << 24);
 473         /* wait for the 60MHz parallel to serial shifter */
 474         usleep_range(10, 20);
 475         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 476         /* wait for the 60MHz parallel to serial shifter */
 477         usleep_range(10, 20);
 478
 479         return brcm_usb_readl(USB_CTRL_REG(ctrl_base, MDIO2)) & 0xffff;
 480 }
 481
 482 static void brcmusb_usb_mdio_write(void __iomem *ctrl_base, u32 reg,
 483                                    u32 val, int mode)
 484 {
 485         u32 data;
 486
 487         data = (reg << 16) | val | mode;
 488         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 489         data |= (1 << 25);
 490         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 491         data &= ~(1 << 25);
 492
 493         /* wait for the 60MHz parallel to serial shifter */
 494         usleep_range(10, 20);
 495         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 496         /* wait for the 60MHz parallel to serial shifter */
 497         usleep_range(10, 20);
 498 }
 499
 500 static void brcmusb_usb_phy_ldo_fix(void __iomem *ctrl_base)
 501 {
 502         /* first disable FSM but also leave it that way */
 503         /* to allow normal suspend/resume */
 504         USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN);
 505         USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN_P1);
 506
 507         /* reset USB 2.0 PLL */
 508         USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB);
 509         /* PLL reset period */
 510         udelay(1);
 511         USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB);
 512         /* Give PLL enough time to lock */
 513         usleep_range(1000, 2000);
 514 }
 515
 516 static void brcmusb_usb2_eye_fix(void __iomem *ctrl_base)
 517 {
 518         /* Increase USB 2.0 TX level to meet spec requirement */
 519         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x80a0, MDIO_USB2);
 520         brcmusb_usb_mdio_write(ctrl_base, 0x0a, 0xc6a0, MDIO_USB2);
 521 }
 522
 523 static void brcmusb_usb3_pll_fix(void __iomem *ctrl_base)
 524 {
 525         /* Set correct window for PLL lock detect */
 526         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
 527         brcmusb_usb_mdio_write(ctrl_base, 0x07, 0x1503, MDIO_USB3);
 528 }
 529
 530 static void brcmusb_usb3_enable_pipe_reset(void __iomem *ctrl_base)
 531 {
 532         u32 val;
 533
 534         /* Re-enable USB 3.0 pipe reset */
 535         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
 536         val = brcmusb_usb_mdio_read(ctrl_base, 0x0f, MDIO_USB3) | 0x200;
 537         brcmusb_usb_mdio_write(ctrl_base, 0x0f, val, MDIO_USB3);
 538 }
 539
 540 static void brcmusb_usb3_enable_sigdet(void __iomem *ctrl_base)
 541 {
 542         u32 val, ofs;
 543         int ii;
 544
 545         ofs = 0;
 546         for (ii = 0; ii < PHY_PORTS; ++ii) {
 547                 /* Set correct default for sigdet */
 548                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8080 + ofs),
 549                                        MDIO_USB3);
 550                 val = brcmusb_usb_mdio_read(ctrl_base, 0x05, MDIO_USB3);
 551                 val = (val & ~0x800f) | 0x800d;
 552                 brcmusb_usb_mdio_write(ctrl_base, 0x05, val, MDIO_USB3);
 553                 ofs = PHY_PORT_SELECT_1;
 554         }
 555 }
 556
 557 static void brcmusb_usb3_enable_skip_align(void __iomem *ctrl_base)
 558 {
 559         u32 val, ofs;
 560         int ii;
 561
 562         ofs = 0;
 563         for (ii = 0; ii < PHY_PORTS; ++ii) {
 564                 /* Set correct default for SKIP align */
 565                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8060 + ofs),
 566                                        MDIO_USB3);
 567                 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0x200;
 568                 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 569                 ofs = PHY_PORT_SELECT_1;
 570         }
 571 }
 572
 573 static void brcmusb_usb3_unfreeze_aeq(void __iomem *ctrl_base)
 574 {
 575         u32 val, ofs;
 576         int ii;
 577
 578         ofs = 0;
 579         for (ii = 0; ii < PHY_PORTS; ++ii) {
 580                 /* Let EQ freeze after TSEQ */
 581                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x80e0 + ofs),
 582                                        MDIO_USB3);
 583                 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3);
 584                 val &= ~0x0008;
 585                 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 586                 ofs = PHY_PORT_SELECT_1;
 587         }
 588 }
 589
 590 static void brcmusb_usb3_pll_54mhz(struct brcm_usb_init_params *params)
 591 {
 592         u32 ofs;
 593         int ii;
 594         void __iomem *ctrl_base = params->regs[BRCM_REGS_CTRL];
 595
 596         /*
 597          * On newer B53 based SoC's, the reference clock for the
 598          * 3.0 PLL has been changed from 50MHz to 54MHz so the
 599          * PLL needs to be reprogrammed.
 600          * See SWLINUX-4006.
 601          *
 602          * On the 7364C0, the reference clock for the
 603          * 3.0 PLL has been changed from 50MHz to 54MHz to
 604          * work around a MOCA issue.
 605          * See SWLINUX-4169.
 606          */
 607         switch (params->selected_family) {
 608         case BRCM_FAMILY_3390A0:
 609         case BRCM_FAMILY_4908:
 610         case BRCM_FAMILY_7250B0:
 611         case BRCM_FAMILY_7366C0:
 612         case BRCM_FAMILY_74371A0:
 613         case BRCM_FAMILY_7439B0:
 614         case BRCM_FAMILY_7445D0:
 615         case BRCM_FAMILY_7260A0:
 616                 return;
 617         case BRCM_FAMILY_7364A0:
 618                 if (BRCM_REV(params->family_id) < 0x20)
 619                         return;
 620                 break;
 621         }
 622
 623         /* set USB 3.0 PLL to accept 54Mhz reference clock */
 624         USB_CTRL_UNSET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START);
 625
 626         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
 627         brcmusb_usb_mdio_write(ctrl_base, 0x10, 0x5784, MDIO_USB3);
 628         brcmusb_usb_mdio_write(ctrl_base, 0x11, 0x01d0, MDIO_USB3);
 629         brcmusb_usb_mdio_write(ctrl_base, 0x12, 0x1DE8, MDIO_USB3);
 630         brcmusb_usb_mdio_write(ctrl_base, 0x13, 0xAA80, MDIO_USB3);
 631         brcmusb_usb_mdio_write(ctrl_base, 0x14, 0x8826, MDIO_USB3);
 632         brcmusb_usb_mdio_write(ctrl_base, 0x15, 0x0044, MDIO_USB3);
 633         brcmusb_usb_mdio_write(ctrl_base, 0x16, 0x8000, MDIO_USB3);
 634         brcmusb_usb_mdio_write(ctrl_base, 0x17, 0x0851, MDIO_USB3);
 635         brcmusb_usb_mdio_write(ctrl_base, 0x18, 0x0000, MDIO_USB3);
 636
 637         /* both ports */
 638         ofs = 0;
 639         for (ii = 0; ii < PHY_PORTS; ++ii) {
 640                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8040 + ofs),
 641                                        MDIO_USB3);
 642                 brcmusb_usb_mdio_write(ctrl_base, 0x03, 0x0090, MDIO_USB3);
 643                 brcmusb_usb_mdio_write(ctrl_base, 0x04, 0x0134, MDIO_USB3);
 644                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8020 + ofs),
 645                                        MDIO_USB3);
 646                 brcmusb_usb_mdio_write(ctrl_base, 0x01, 0x00e2, MDIO_USB3);
 647                 ofs = PHY_PORT_SELECT_1;
 648         }
 649
 650         /* restart PLL sequence */
 651         USB_CTRL_SET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START);
 652         /* Give PLL enough time to lock */
 653         usleep_range(1000, 2000);
 654 }
 655
 656 static void brcmusb_usb3_ssc_enable(void __iomem *ctrl_base)
 657 {
 658         u32 val;
 659
 660         /* Enable USB 3.0 TX spread spectrum */
 661         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8040, MDIO_USB3);
 662         val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
 663         brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 664
 665         /* Currently, USB 3.0 SSC is enabled via port 0 MDIO registers,
 666          * which should have been adequate. However, due to a bug in the
 667          * USB 3.0 PHY, it must be enabled via both ports (HWUSB3DVT-26).
 668          */
 669         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x9040, MDIO_USB3);
 670         val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
 671         brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 672 }
 673
 674 static void brcmusb_usb3_phy_workarounds(struct brcm_usb_init_params *params)
 675 {
 676         void __iomem *ctrl_base = params->regs[BRCM_REGS_CTRL];
 677
 678         brcmusb_usb3_pll_fix(ctrl_base);
 679         brcmusb_usb3_pll_54mhz(params);
 680         brcmusb_usb3_ssc_enable(ctrl_base);
 681         brcmusb_usb3_enable_pipe_reset(ctrl_base);
 682         brcmusb_usb3_enable_sigdet(ctrl_base);
 683         brcmusb_usb3_enable_skip_align(ctrl_base);
 684         brcmusb_usb3_unfreeze_aeq(ctrl_base);
 685 }
 686
 687 static void brcmusb_memc_fix(struct brcm_usb_init_params *params)
 688 {
 689         u32 prid;
 690
 691         if (params->selected_family != BRCM_FAMILY_7445D0)
 692                 return;
 693         /*
 694          * This is a workaround for HW7445-1869 where a DMA write ends up
 695          * doing a read pre-fetch after the end of the DMA buffer. This
 696          * causes a problem when the DMA buffer is at the end of physical
 697          * memory, causing the pre-fetch read to access non-existent memory,
 698          * and the chip bondout has MEMC2 disabled. When the pre-fetch read
 699          * tries to use the disabled MEMC2, it hangs the bus. The workaround
 700          * is to disable MEMC2 access in the usb controller which avoids
 701          * the hang.
 702          */
 703
 704         prid = params->product_id & 0xfffff000;
 705         switch (prid) {
 706         case 0x72520000:
 707         case 0x74480000:
 708         case 0x74490000:
 709         case 0x07252000:
 710         case 0x07448000:
 711         case 0x07449000:
 712                 USB_CTRL_UNSET_FAMILY(params, SETUP, SCB2_EN);
 713         }
 714 }
 715
 716 static void brcmusb_usb3_otp_fix(struct brcm_usb_init_params *params)
 717 {
 718         void __iomem *xhci_ec_base = params->regs[BRCM_REGS_XHCI_EC];
 719         u32 val;
 720
 721         if (params->family_id != 0x74371000 || !xhci_ec_base)
 722                 return;
 723         brcm_usb_writel(0xa20c, USB_XHCI_EC_REG(xhci_ec_base, IRAADR));
 724         val = brcm_usb_readl(USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
 725
 726         /* set cfg_pick_ss_lock */
 727         val |= (1 << 27);
 728         brcm_usb_writel(val, USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
 729
 730         /* Reset USB 3.0 PHY for workaround to take effect */
 731         USB_CTRL_UNSET(params->regs[BRCM_REGS_CTRL], USB30_CTL1, PHY3_RESETB);
 732         USB_CTRL_SET(params->regs[BRCM_REGS_CTRL], USB30_CTL1, PHY3_RESETB);
 733 }
 734
 735 static void brcmusb_xhci_soft_reset(struct brcm_usb_init_params *params,
 736                                     int on_off)
 737 {
 738         /* Assert reset */
 739         if (on_off) {
 740                 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB))
 741                         USB_CTRL_UNSET_FAMILY(params, USB_PM, XHC_SOFT_RESETB);
 742                 else
 743                         USB_CTRL_UNSET_FAMILY(params,
 744                                               USB30_CTL1, XHC_SOFT_RESETB);
 745         } else { /* De-assert reset */
 746                 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB))
 747                         USB_CTRL_SET_FAMILY(params, USB_PM, XHC_SOFT_RESETB);
 748                 else
 749                         USB_CTRL_SET_FAMILY(params, USB30_CTL1,
 750                                             XHC_SOFT_RESETB);
 751         }
 752 }
 753
 754 /*
 755  * Return the best map table family. The order is:
 756  *   - exact match of chip and major rev
 757  *   - exact match of chip and closest older major rev
 758  *   - default chip/rev.
 759  * NOTE: The minor rev is always ignored.
 760  */
 761 static enum brcm_family_type get_family_type(
 762         struct brcm_usb_init_params *params)
 763 {
 764         int last_type = -1;
 765         u32 last_family = 0;
 766         u32 family_no_major;
 767         unsigned int x;
 768         u32 family;
 769
 770         family = params->family_id & 0xfffffff0;
 771         family_no_major = params->family_id & 0xffffff00;
 772         for (x = 0; id_to_type_table[x].id; x++) {
 773                 if (family == id_to_type_table[x].id)
 774                         return id_to_type_table[x].type;
 775                 if (family_no_major == (id_to_type_table[x].id & 0xffffff00))
 776                         if (family > id_to_type_table[x].id &&
 777                             last_family < id_to_type_table[x].id) {
 778                                 last_family = id_to_type_table[x].id;
 779                                 last_type = id_to_type_table[x].type;
 780                         }
 781         }
 782
 783         /* If no match, return the default family */
 784         if (last_type == -1)
 785                 return id_to_type_table[x].type;
 786         return last_type;
 787 }
 788
 789 static void usb_init_ipp(struct brcm_usb_init_params *params)
 790 {
 791         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 792         u32 reg;
 793         u32 orig_reg;
 794
 795         /* Starting with the 7445d0, there are no longer separate 3.0
 796          * versions of IOC and IPP.
 797          */
 798         if (USB_CTRL_MASK_FAMILY(params, USB30_CTL1, USB3_IOC)) {
 799                 if (params->ioc)
 800                         USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IOC);
 801                 if (params->ipp == 1)
 802                         USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IPP);
 803         }
 804
 805         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
 806         orig_reg = reg;
 807         if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_CC_DRD_MODE_ENABLE_SEL))
 808                 /* Never use the strap, it's going away. */
 809                 reg &= ~(USB_CTRL_MASK_FAMILY(params,
 810                                               SETUP,
 811                                               STRAP_CC_DRD_MODE_ENABLE_SEL));
 812         if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_IPP_SEL))
 813                 /* override ipp strap pin (if it exits) */
 814                 if (params->ipp != 2)
 815                         reg &= ~(USB_CTRL_MASK_FAMILY(params, SETUP,
 816                                                       STRAP_IPP_SEL));
 817
 818         /* Override the default OC and PP polarity */
 819         reg &= ~(USB_CTRL_MASK(SETUP, IPP) | USB_CTRL_MASK(SETUP, IOC));
 820         if (params->ioc)
 821                 reg |= USB_CTRL_MASK(SETUP, IOC);
 822         if (params->ipp == 1)
 823                 reg |= USB_CTRL_MASK(SETUP, IPP);
 824         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
 825
 826         /*
 827          * If we're changing IPP, make sure power is off long enough
 828          * to turn off any connected devices.
 829          */
 830         if ((reg ^ orig_reg) & USB_CTRL_MASK(SETUP, IPP))
 831                 msleep(50);
 832 }
 833
 834 static void usb_wake_enable(struct brcm_usb_init_params *params,
 835                           bool enable)
 836 {
 837         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 838
 839         if (enable)
 840                 USB_CTRL_SET(ctrl, USB_PM, RMTWKUP_EN);
 841         else
 842                 USB_CTRL_UNSET(ctrl, USB_PM, RMTWKUP_EN);
 843 }
 844
 845 static void usb_init_common(struct brcm_usb_init_params *params)
 846 {
 847         u32 reg;
 848         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 849
 850         /* Clear any pending wake conditions */
 851         usb_wake_enable(params, false);
 852         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_PM_STATUS));
 853         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_PM_STATUS));
 854
 855         /* Take USB out of power down */
 856         if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN)) {
 857                 USB_CTRL_UNSET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN);
 858                 /* 1 millisecond - for USB clocks to settle down */
 859                 usleep_range(1000, 2000);
 860         }
 861
 862         if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN)) {
 863                 USB_CTRL_UNSET_FAMILY(params, USB_PM, USB_PWRDN);
 864                 /* 1 millisecond - for USB clocks to settle down */
 865                 usleep_range(1000, 2000);
 866         }
 867
 868         if (params->selected_family != BRCM_FAMILY_74371A0 &&
 869             (BRCM_ID(params->family_id) != 0x7364))
 870                 /*
 871                  * HW7439-637: 7439a0 and its derivatives do not have large
 872                  * enough descriptor storage for this.
 873                  */
 874                 USB_CTRL_SET_FAMILY(params, SETUP, SS_EHCI64BIT_EN);
 875
 876         /* Block auto PLL suspend by USB2 PHY (Sasi) */
 877         USB_CTRL_SET(ctrl, PLL_CTL, PLL_SUSPEND_EN);
 878
 879         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
 880         if (params->selected_family == BRCM_FAMILY_7364A0)
 881                 /* Suppress overcurrent indication from USB30 ports for A0 */
 882                 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, OC3_DISABLE);
 883
 884         brcmusb_usb_phy_ldo_fix(ctrl);
 885         brcmusb_usb2_eye_fix(ctrl);
 886
 887         /*
 888          * Make sure the second and third memory controller
 889          * interfaces are enabled if they exist.
 890          */
 891         if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN))
 892                 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN);
 893         if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN))
 894                 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN);
 895         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
 896
 897         brcmusb_memc_fix(params);
 898
 899         /* Workaround for false positive OC for 7439b2 in DRD/Device mode */
 900         if ((params->family_id == 0x74390012) &&
 901             (params->supported_port_modes != USB_CTLR_MODE_HOST)) {
 902                 USB_CTRL_SET(ctrl, SETUP, OC_DISABLE_PORT1);
 903                 USB_CTRL_SET_FAMILY(params, SETUP, OC3_DISABLE_PORT1);
 904         }
 905
 906         if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
 907                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
 908                 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
 909                                         PORT_MODE);
 910                 reg |= params->port_mode;
 911                 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
 912         }
 913         if (USB_CTRL_MASK_FAMILY(params, USB_PM, BDC_SOFT_RESETB)) {
 914                 switch (params->supported_port_modes) {
 915                 case USB_CTLR_MODE_HOST:
 916                         USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
 917                         break;
 918                 default:
 919                         USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
 920                         USB_CTRL_SET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
 921                 break;
 922                 }
 923         }
 924         if (USB_CTRL_MASK_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE)) {
 925                 if (params->supported_port_modes == USB_CTLR_MODE_TYPEC_PD)
 926                         USB_CTRL_SET_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE);
 927                 else
 928                         USB_CTRL_UNSET_FAMILY(params, SETUP,
 929                                               CC_DRD_MODE_ENABLE);
 930         }
 931 }
 932
 933 static void usb_init_eohci(struct brcm_usb_init_params *params)
 934 {
 935         u32 reg;
 936         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 937
 938         if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB20_HC_RESETB))
 939                 USB_CTRL_SET_FAMILY(params, USB_PM, USB20_HC_RESETB);
 940
 941         if (params->selected_family == BRCM_FAMILY_7366C0)
 942                 /*
 943                  * Don't enable this so the memory controller doesn't read
 944                  * into memory holes. NOTE: This bit is low true on 7366C0.
 945                  */
 946                 USB_CTRL_SET(ctrl, EBRIDGE, ESTOP_SCB_REQ);
 947
 948         /* Setup the endian bits */
 949         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
 950         reg &= ~USB_CTRL_SETUP_ENDIAN_BITS;
 951         reg |= USB_CTRL_MASK_FAMILY(params, SETUP, ENDIAN);
 952         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
 953
 954         if (params->selected_family == BRCM_FAMILY_7271A0)
 955                 /* Enable LS keep alive fix for certain keyboards */
 956                 USB_CTRL_SET(ctrl, OBRIDGE, LS_KEEP_ALIVE);
 957
 958         if (params->family_id == 0x72550000) {
 959                 /*
 960                  * Make the burst size 512 bytes to fix a hardware bug
 961                  * on the 7255a0. See HW7255-24.
 962                  */
 963                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, EBRIDGE));
 964                 reg &= ~USB_CTRL_MASK(EBRIDGE, EBR_SCB_SIZE);
 965                 reg |= 0x800;
 966                 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, EBRIDGE));
 967         }
 968 }
 969
 970 static void usb_init_xhci(struct brcm_usb_init_params *params)
 971 {
 972         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 973
 974         USB_CTRL_UNSET(ctrl, USB30_PCTL, PHY3_IDDQ_OVERRIDE);
 975         /* 1 millisecond - for USB clocks to settle down */
 976         usleep_range(1000, 2000);
 977
 978         if (BRCM_ID(params->family_id) == 0x7366) {
 979                 /*
 980                  * The PHY3_SOFT_RESETB bits default to the wrong state.
 981                  */
 982                 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB);
 983                 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB_P1);
 984         }
 985
 986         /*
 987          * Kick start USB3 PHY
 988          * Make sure it's low to insure a rising edge.
 989          */
 990         USB_CTRL_UNSET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START);
 991         USB_CTRL_SET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START);
 992
 993         brcmusb_usb3_phy_workarounds(params);
 994         brcmusb_xhci_soft_reset(params, 0);
 995         brcmusb_usb3_otp_fix(params);
 996 }
 997
 998 static void usb_uninit_common(struct brcm_usb_init_params *params)
 999 {
1000         if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN))
1001                 USB_CTRL_SET_FAMILY(params, USB_PM, USB_PWRDN);
1002
1003         if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN))
1004                 USB_CTRL_SET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN);
1005         if (params->wake_enabled)
1006                 usb_wake_enable(params, true);
1007 }
1008
1009 static void usb_uninit_eohci(struct brcm_usb_init_params *params)
1010 {
1011 }
1012
1013 static void usb_uninit_xhci(struct brcm_usb_init_params *params)
1014 {
1015         brcmusb_xhci_soft_reset(params, 1);
1016         USB_CTRL_SET(params->regs[BRCM_REGS_CTRL], USB30_PCTL,
1017                      PHY3_IDDQ_OVERRIDE);
1018 }
1019
1020 static int usb_get_dual_select(struct brcm_usb_init_params *params)
1021 {
1022         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
1023         u32 reg = 0;
1024
1025         pr_debug("%s\n", __func__);
1026         if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
1027                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
1028                 reg &= USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
1029                                         PORT_MODE);
1030         }
1031         return reg;
1032 }
1033
1034 static void usb_set_dual_select(struct brcm_usb_init_params *params)
1035 {
1036         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
1037         u32 reg;
1038
1039         pr_debug("%s\n", __func__);
1040
1041         if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
1042                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
1043                 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
1044                                         PORT_MODE);
1045                 reg |= params->port_mode;
1046                 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
1047         }
1048 }
1049
1050 static const struct brcm_usb_init_ops bcm7445_ops = {
1051         .init_ipp = usb_init_ipp,
1052         .init_common = usb_init_common,
1053         .init_eohci = usb_init_eohci,
1054         .init_xhci = usb_init_xhci,
1055         .uninit_common = usb_uninit_common,
1056         .uninit_eohci = usb_uninit_eohci,
1057         .uninit_xhci = usb_uninit_xhci,
1058         .get_dual_select = usb_get_dual_select,
1059         .set_dual_select = usb_set_dual_select,
1060 };
1061
1062 void brcm_usb_dvr_init_4908(struct brcm_usb_init_params *params)
1063 {
1064         int fam;
1065
1066         fam = BRCM_FAMILY_4908;
1067         params->selected_family = fam;
1068         params->usb_reg_bits_map =
1069                 &usb_reg_bits_map_table[fam][0];
1070         params->family_name = family_names[fam];
1071         params->ops = &bcm7445_ops;
1072 }
1073
1074 void brcm_usb_dvr_init_7445(struct brcm_usb_init_params *params)
1075 {
1076         int fam;
1077
1078         pr_debug("%s\n", __func__);
1079
1080         fam = get_family_type(params);
1081         params->selected_family = fam;
1082         params->usb_reg_bits_map =
1083                 &usb_reg_bits_map_table[fam][0];
1084         params->family_name = family_names[fam];
1085         params->ops = &bcm7445_ops;
1086 }