1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2003-2015, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
7 #ifndef __iwl_trans_int_pcie_h__
8 #define __iwl_trans_int_pcie_h__
10 #include <linux/spinlock.h>
11 #include <linux/interrupt.h>
12 #include <linux/skbuff.h>
13 #include <linux/wait.h>
14 #include <linux/pci.h>
15 #include <linux/timer.h>
16 #include <linux/cpu.h>
20 #include "iwl-trans.h"
21 #include "iwl-debug.h"
23 #include "iwl-op-mode.h"
25 #include "iwl-context-info.h"
28 * RX related structures and functions
30 #define RX_NUM_QUEUES 1
31 #define RX_POST_REQ_ALLOC 2
32 #define RX_CLAIM_REQ_ALLOC 8
33 #define RX_PENDING_WATERMARK 16
34 #define FIRST_RX_QUEUE 512
38 /*This file includes the declaration that are internal to the
42 * struct iwl_rx_mem_buffer
43 * @page_dma: bus address of rxb page
44 * @page: driver's pointer to the rxb page
45 * @list: list entry for the membuffer
46 * @invalid: rxb is in driver ownership - not owned by HW
47 * @vid: index of this rxb in the global table
48 * @offset: indicates which offset of the page (in bytes)
49 * this buffer uses (if multiple RBs fit into one page)
51 struct iwl_rx_mem_buffer {
54 struct list_head list;
60 /* interrupt statistics */
61 struct isr_statistics {
76 * struct iwl_rx_transfer_desc - transfer descriptor
77 * @addr: ptr to free buffer start address
78 * @rbid: unique tag of the buffer
81 struct iwl_rx_transfer_desc {
87 #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0)
90 * struct iwl_rx_completion_desc - completion descriptor
91 * @reserved1: reserved
92 * @rbid: unique tag of the received buffer
93 * @flags: flags (0: fragmented, all others: reserved)
94 * @reserved2: reserved
96 struct iwl_rx_completion_desc {
104 * struct iwl_rx_completion_desc_bz - Bz completion descriptor
105 * @rbid: unique tag of the received buffer
106 * @flags: flags (0: fragmented, all others: reserved)
107 * @reserved: reserved
109 struct iwl_rx_completion_desc_bz {
116 * struct iwl_rxq - Rx queue
118 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
119 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
120 * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's
121 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
122 * @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd)
123 * @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd)
124 * @read: Shared index to newest available Rx buffer
125 * @write: Shared index to oldest written Rx packet
126 * @write_actual: actual write pointer written to device, since we update in
128 * @free_count: Number of pre-allocated buffers in rx_free
129 * @used_count: Number of RBDs handled to allocator to use for allocation
131 * @rx_free: list of RBDs with allocated RB ready for use
132 * @rx_used: list of RBDs with no RB attached
133 * @need_update: flag to indicate we need to update read/write index
134 * @rb_stts: driver's pointer to receive buffer status
135 * @rb_stts_dma: bus address of receive buffer status
136 * @lock: per-queue lock
137 * @queue: actual rx queue. Not used for multi-rx queue.
138 * @next_rb_is_fragment: indicates that the previous RB that we handled set
139 * the fragmented flag, so the next one is still another fragment
140 * @napi: NAPI struct for this queue
141 * @queue_size: size of this queue
143 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
150 dma_addr_t used_bd_dma;
157 struct list_head rx_free;
158 struct list_head rx_used;
159 bool need_update, next_rb_is_fragment;
161 dma_addr_t rb_stts_dma;
163 struct napi_struct napi;
164 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
168 * struct iwl_rb_allocator - Rx allocator
169 * @req_pending: number of requests the allcator had not processed yet
170 * @req_ready: number of requests honored and ready for claiming
171 * @rbd_allocated: RBDs with pages allocated and ready to be handled to
172 * the queue. This is a list of &struct iwl_rx_mem_buffer
173 * @rbd_empty: RBDs with no page attached for allocator use. This is a list
174 * of &struct iwl_rx_mem_buffer
175 * @lock: protects the rbd_allocated and rbd_empty lists
176 * @alloc_wq: work queue for background calls
177 * @rx_alloc: work struct for background calls
179 struct iwl_rb_allocator {
180 atomic_t req_pending;
182 struct list_head rbd_allocated;
183 struct list_head rbd_empty;
185 struct workqueue_struct *alloc_wq;
186 struct work_struct rx_alloc;
190 * iwl_get_closed_rb_stts - get closed rb stts from different structs
191 * @trans: transport pointer (for configuration)
192 * @rxq: the rxq to get the rb stts from
194 static inline u16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
197 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
198 __le16 *rb_stts = rxq->rb_stts;
200 return le16_to_cpu(READ_ONCE(*rb_stts));
202 struct iwl_rb_status *rb_stts = rxq->rb_stts;
204 return le16_to_cpu(READ_ONCE(rb_stts->closed_rb_num)) & 0xFFF;
208 #ifdef CONFIG_IWLWIFI_DEBUGFS
210 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
213 * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed.
214 * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open.
215 * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is
216 * set the file can no longer be used.
218 enum iwl_fw_mon_dbgfs_state {
219 IWL_FW_MON_DBGFS_STATE_CLOSED,
220 IWL_FW_MON_DBGFS_STATE_OPEN,
221 IWL_FW_MON_DBGFS_STATE_DISABLED,
226 * enum iwl_shared_irq_flags - level of sharing for irq
227 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
228 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
230 enum iwl_shared_irq_flags {
231 IWL_SHARED_IRQ_NON_RX = BIT(0),
232 IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
236 * enum iwl_image_response_code - image response values
237 * @IWL_IMAGE_RESP_DEF: the default value of the register
238 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully
239 * @IWL_IMAGE_RESP_FAIL: iml reading failed
241 enum iwl_image_response_code {
242 IWL_IMAGE_RESP_DEF = 0,
243 IWL_IMAGE_RESP_SUCCESS = 1,
244 IWL_IMAGE_RESP_FAIL = 2,
247 #ifdef CONFIG_IWLWIFI_DEBUGFS
249 * struct cont_rec: continuous recording data structure
250 * @prev_wr_ptr: the last address that was read in monitor_data
252 * @prev_wrap_cnt: the wrap count that was used during the last read in
253 * monitor_data debugfs file
254 * @state: the state of monitor_data debugfs file as described
255 * in &iwl_fw_mon_dbgfs_state enum
256 * @mutex: locked while reading from monitor_data debugfs file
262 /* Used to sync monitor_data debugfs file with driver unload flow */
267 enum iwl_pcie_fw_reset_state {
275 * enum iwl_pcie_imr_status - imr dma transfer state
276 * @IMR_D2S_IDLE: default value of the dma transfer
277 * @IMR_D2S_REQUESTED: dma transfer requested
278 * @IMR_D2S_COMPLETED: dma transfer completed
279 * @IMR_D2S_ERROR: dma transfer error
281 enum iwl_pcie_imr_status {
289 * struct iwl_pcie_txqs - TX queues data
291 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes)
292 * @page_offs: offset from skb->cb to mac header page pointer
293 * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer
294 * @queue_used: bit mask of used queues
295 * @queue_stopped: bit mask of stopped queues
296 * @txq: array of TXQ data structures representing the TXQs
297 * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler
298 * @queue_alloc_cmd_ver: queue allocation command version
299 * @bc_pool: bytecount DMA allocations pool
300 * @bc_tbl_size: bytecount table size
301 * @tso_hdr_page: page allocated (per CPU) for A-MSDU headers when doing TSO
302 * (and similar usage)
303 * @cmd: command queue data
304 * @cmd.fifo: FIFO number
305 * @cmd.q_id: queue ID
306 * @cmd.wdg_timeout: watchdog timeout
308 * @tfd.max_tbs: max number of buffers per TFD
309 * @tfd.size: TFD size
310 * @tfd.addr_size: TFD/TB address size
312 struct iwl_pcie_txqs {
313 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
314 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
315 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES];
316 struct dma_pool *bc_pool;
321 struct iwl_tso_hdr_page __percpu *tso_hdr_page;
326 unsigned int wdg_timeout;
335 struct iwl_dma_ptr scd_bc_tbls;
337 u8 queue_alloc_cmd_ver;
341 * struct iwl_trans_pcie - PCIe transport specific data
342 * @rxq: all the RX queue data
343 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
344 * @global_table: table mapping received VID from hw to rxb
345 * @rba: allocator for RX replenishing
346 * @ctxt_info: context information for FW self init
347 * @ctxt_info_gen3: context information for gen3 devices
348 * @prph_info: prph info for self init
349 * @prph_scratch: prph scratch for self init
350 * @ctxt_info_dma_addr: dma addr of context information
351 * @prph_info_dma_addr: dma addr of prph info
352 * @prph_scratch_dma_addr: dma addr of prph scratch
353 * @ctxt_info_dma_addr: dma addr of context information
354 * @iml: image loader image virtual address
355 * @iml_dma_addr: image loader image DMA address
356 * @trans: pointer to the generic transport area
357 * @scd_base_addr: scheduler sram base address in SRAM
358 * @kw: keep warm address
359 * @pnvm_data: holds info about pnvm payloads allocated in DRAM
360 * @reduced_tables_data: holds info about power reduced tablse
361 * payloads allocated in DRAM
362 * @pci_dev: basic pci-network driver stuff
363 * @hw_base: pci hardware address support
364 * @ucode_write_complete: indicates that the ucode has been copied.
365 * @ucode_write_waitq: wait queue for uCode load
366 * @cmd_queue - command queue number
367 * @rx_buf_size: Rx buffer size
368 * @scd_set_active: should the transport configure the SCD for HCMD queue
369 * @rx_page_order: page order for receive buffer size
370 * @rx_buf_bytes: RX buffer (RB) size in bytes
371 * @reg_lock: protect hw register access
372 * @mutex: to protect stop_device / start_fw / start_hw
373 * @fw_mon_data: fw continuous recording data
374 * @cmd_hold_nic_awake: indicates NIC is held awake for APMG workaround
375 * during commands in flight
376 * @msix_entries: array of MSI-X entries
377 * @msix_enabled: true if managed to enable MSI-X
378 * @shared_vec_mask: the type of causes the shared vector handles
379 * (see iwl_shared_irq_flags).
380 * @alloc_vecs: the number of interrupt vectors allocated by the OS
381 * @def_irq: default irq for non rx causes
382 * @fh_init_mask: initial unmasked fh causes
383 * @hw_init_mask: initial unmasked hw causes
384 * @fh_mask: current unmasked fh causes
385 * @hw_mask: current unmasked hw causes
386 * @in_rescan: true if we have triggered a device rescan
387 * @base_rb_stts: base virtual address of receive buffer status for all queues
388 * @base_rb_stts_dma: base physical address of receive buffer status
389 * @supported_dma_mask: DMA mask to validate the actual address against,
390 * will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device
391 * @alloc_page_lock: spinlock for the page allocator
392 * @alloc_page: allocated page to still use parts of
393 * @alloc_page_used: how much of the allocated page was already used (bytes)
394 * @imr_status: imr dma state machine
395 * @imr_waitq: imr wait queue for dma completion
396 * @rf_name: name/version of the CRF, if any
397 * @use_ict: whether or not ICT (interrupt table) is used
398 * @ict_index: current ICT read index
399 * @ict_tbl: ICT table pointer
400 * @ict_tbl_dma: ICT table DMA address
401 * @inta_mask: interrupt (INT-A) mask
402 * @irq_lock: lock to synchronize IRQ handling
403 * @txq_memory: TXQ allocation array
404 * @sx_waitq: waitqueue for Sx transitions
405 * @sx_complete: completion for Sx transitions
406 * @pcie_dbg_dumped_once: indicates PCIe regs were dumped already
407 * @opmode_down: indicates opmode went away
408 * @num_rx_bufs: number of RX buffers to allocate/use
409 * @no_reclaim_cmds: special commands not using reclaim flow
410 * (firmware workaround)
411 * @n_no_reclaim_cmds: number of special commands not using reclaim flow
412 * @affinity_mask: IRQ affinity mask for each RX queue
413 * @debug_rfkill: RF-kill debugging state, -1 for unset, 0/1 for radio
415 * @fw_reset_handshake: indicates FW reset handshake is needed
416 * @fw_reset_state: state of FW reset handshake
417 * @fw_reset_waitq: waitqueue for FW reset handshake
418 * @is_down: indicates the NIC is down
419 * @isr_stats: interrupt statistics
420 * @napi_dev: (fake) netdev for NAPI registration
421 * @txqs: transport tx queues data.
423 struct iwl_trans_pcie {
425 struct iwl_rx_mem_buffer *rx_pool;
426 struct iwl_rx_mem_buffer **global_table;
427 struct iwl_rb_allocator rba;
429 struct iwl_context_info *ctxt_info;
430 struct iwl_context_info_gen3 *ctxt_info_gen3;
432 struct iwl_prph_info *prph_info;
433 struct iwl_prph_scratch *prph_scratch;
435 dma_addr_t ctxt_info_dma_addr;
436 dma_addr_t prph_info_dma_addr;
437 dma_addr_t prph_scratch_dma_addr;
438 dma_addr_t iml_dma_addr;
439 struct iwl_trans *trans;
441 struct net_device *napi_dev;
445 dma_addr_t ict_tbl_dma;
448 bool is_down, opmode_down;
450 struct isr_statistics isr_stats;
456 struct iwl_dma_ptr kw;
459 struct iwl_dram_regions pnvm_data;
460 struct iwl_dram_regions reduced_tables_data;
462 struct iwl_txq *txq_memory;
464 /* PCI bus related data */
465 struct pci_dev *pci_dev;
468 bool ucode_write_complete;
470 wait_queue_head_t ucode_write_waitq;
471 wait_queue_head_t sx_waitq;
473 u8 n_no_reclaim_cmds;
474 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
477 enum iwl_amsdu_size rx_buf_size;
479 bool pcie_dbg_dumped_once;
482 u32 supported_dma_mask;
484 /* allocator lock for the two values below */
485 spinlock_t alloc_page_lock;
486 struct page *alloc_page;
489 /*protect hw register */
491 bool cmd_hold_nic_awake;
493 #ifdef CONFIG_IWLWIFI_DEBUGFS
494 struct cont_rec fw_mon_data;
497 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
506 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
507 u16 tx_cmd_queue_size;
511 dma_addr_t base_rb_stts_dma;
513 bool fw_reset_handshake;
514 enum iwl_pcie_fw_reset_state fw_reset_state;
515 wait_queue_head_t fw_reset_waitq;
516 enum iwl_pcie_imr_status imr_status;
517 wait_queue_head_t imr_waitq;
520 struct iwl_pcie_txqs txqs;
523 static inline struct iwl_trans_pcie *
524 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
526 return (void *)trans->trans_specific;
529 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue)
532 * Before sending the interrupt the HW disables it to prevent
533 * a nested interrupt. This is done by writing 1 to the corresponding
534 * bit in the mask register. After handling the interrupt, it should be
535 * re-enabled by clearing this bit. This register is defined as
536 * write 1 clear (W1C) register, meaning that it's being clear
537 * by writing 1 to the bit.
539 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
542 static inline struct iwl_trans *
543 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
545 return container_of((void *)trans_pcie, struct iwl_trans,
550 * Convention: trans API functions: iwl_trans_pcie_XXX
551 * Other functions: iwl_pcie_XXX
554 *iwl_trans_pcie_alloc(struct pci_dev *pdev,
555 const struct pci_device_id *ent,
556 const struct iwl_cfg_trans_params *cfg_trans);
557 void iwl_trans_pcie_free(struct iwl_trans *trans);
558 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
561 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
562 #define _iwl_trans_pcie_grab_nic_access(trans) \
563 __cond_lock(nic_access_nobh, \
564 likely(__iwl_trans_pcie_grab_nic_access(trans)))
566 void iwl_trans_pcie_check_product_reset_status(struct pci_dev *pdev);
567 void iwl_trans_pcie_check_product_reset_mode(struct pci_dev *pdev);
569 /*****************************************************
571 ******************************************************/
572 int iwl_pcie_rx_init(struct iwl_trans *trans);
573 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
574 irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
575 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
576 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
577 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
578 int iwl_pcie_rx_stop(struct iwl_trans *trans);
579 void iwl_pcie_rx_free(struct iwl_trans *trans);
580 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
581 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
582 void iwl_pcie_rx_napi_sync(struct iwl_trans *trans);
583 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
584 struct iwl_rxq *rxq);
586 /*****************************************************
587 * ICT - interrupt handling
588 ******************************************************/
589 irqreturn_t iwl_pcie_isr(int irq, void *data);
590 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
591 void iwl_pcie_free_ict(struct iwl_trans *trans);
592 void iwl_pcie_reset_ict(struct iwl_trans *trans);
593 void iwl_pcie_disable_ict(struct iwl_trans *trans);
595 /*****************************************************
597 ******************************************************/
598 /* We need 2 entries for the TX command and header, and another one might
599 * be needed for potential data in the SKB's head. The remaining ones can
602 #define IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie) ((trans_pcie)->txqs.tfd.max_tbs - 3)
604 struct iwl_tso_hdr_page {
610 * Note that we put this struct *last* in the page. By doing that, we ensure
611 * that no TB referencing this page can trigger the 32-bit boundary hardware
614 struct iwl_tso_page_info {
617 refcount_t use_count;
620 #define IWL_TSO_PAGE_DATA_SIZE (PAGE_SIZE - sizeof(struct iwl_tso_page_info))
621 #define IWL_TSO_PAGE_INFO(addr) \
622 ((struct iwl_tso_page_info *)(((unsigned long)addr & PAGE_MASK) + \
623 IWL_TSO_PAGE_DATA_SIZE))
625 int iwl_pcie_tx_init(struct iwl_trans *trans);
626 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
627 int iwl_pcie_tx_stop(struct iwl_trans *trans);
628 void iwl_pcie_tx_free(struct iwl_trans *trans);
629 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
630 const struct iwl_trans_txq_scd_cfg *cfg,
631 unsigned int wdg_timeout);
632 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
634 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
636 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
637 struct iwl_device_tx_cmd *dev_cmd, int txq_id);
638 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
639 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
640 struct iwl_rx_cmd_buffer *rxb);
641 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
642 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
643 int slots_num, bool cmd_queue);
645 dma_addr_t iwl_pcie_get_sgt_tb_phys(struct sg_table *sgt, unsigned int offset,
647 struct sg_table *iwl_pcie_prep_tso(struct iwl_trans *trans, struct sk_buff *skb,
648 struct iwl_cmd_meta *cmd_meta,
649 u8 **hdr, unsigned int hdr_room);
651 void iwl_pcie_free_tso_pages(struct iwl_trans *trans, struct sk_buff *skb,
652 struct iwl_cmd_meta *cmd_meta);
654 static inline dma_addr_t iwl_pcie_get_tso_page_phys(void *addr)
658 res = IWL_TSO_PAGE_INFO(addr)->dma_addr;
659 res += (unsigned long)addr & ~PAGE_MASK;
664 static inline dma_addr_t
665 iwl_txq_get_first_tb_dma(struct iwl_txq *txq, int idx)
667 return txq->first_tb_dma +
668 sizeof(struct iwl_pcie_first_tb_buf) * idx;
671 static inline u16 iwl_txq_get_cmd_index(const struct iwl_txq *q, u32 index)
673 return index & (q->n_window - 1);
676 static inline void *iwl_txq_get_tfd(struct iwl_trans *trans,
677 struct iwl_txq *txq, int idx)
679 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
681 if (trans->trans_cfg->gen2)
682 idx = iwl_txq_get_cmd_index(txq, idx);
684 return (u8 *)txq->tfds + trans_pcie->txqs.tfd.size * idx;
688 * We need this inline in case dma_addr_t is only 32-bits - since the
689 * hardware is always 64-bit, the issue can still occur in that case,
690 * so use u64 for 'phys' here to force the addition in 64-bit.
692 static inline bool iwl_txq_crosses_4g_boundary(u64 phys, u16 len)
694 return upper_32_bits(phys) != upper_32_bits(phys + len);
697 int iwl_txq_space(struct iwl_trans *trans, const struct iwl_txq *q);
699 static inline void iwl_txq_stop(struct iwl_trans *trans, struct iwl_txq *txq)
701 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
703 if (!test_and_set_bit(txq->id, trans_pcie->txqs.queue_stopped)) {
704 iwl_op_mode_queue_full(trans->op_mode, txq->id);
705 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id);
707 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
713 * iwl_txq_inc_wrap - increment queue index, wrap back to beginning
714 * @trans: the transport (for configuration data)
715 * @index: current index
717 static inline int iwl_txq_inc_wrap(struct iwl_trans *trans, int index)
720 (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
724 * iwl_txq_dec_wrap - decrement queue index, wrap back to end
725 * @trans: the transport (for configuration data)
726 * @index: current index
728 static inline int iwl_txq_dec_wrap(struct iwl_trans *trans, int index)
731 (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
734 void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq);
737 iwl_trans_pcie_wake_queue(struct iwl_trans *trans, struct iwl_txq *txq)
739 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
741 if (test_and_clear_bit(txq->id, trans_pcie->txqs.queue_stopped)) {
742 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id);
743 iwl_op_mode_queue_not_full(trans->op_mode, txq->id);
747 int iwl_txq_gen2_set_tb(struct iwl_trans *trans,
748 struct iwl_tfh_tfd *tfd, dma_addr_t addr,
751 static inline void iwl_txq_set_tfd_invalid_gen2(struct iwl_trans *trans,
752 struct iwl_tfh_tfd *tfd)
756 iwl_txq_gen2_set_tb(trans, tfd, trans->invalid_tx_cmd.dma,
757 trans->invalid_tx_cmd.size);
760 void iwl_txq_gen2_tfd_unmap(struct iwl_trans *trans,
761 struct iwl_cmd_meta *meta,
762 struct iwl_tfh_tfd *tfd);
764 int iwl_txq_dyn_alloc(struct iwl_trans *trans, u32 flags,
765 u32 sta_mask, u8 tid,
766 int size, unsigned int timeout);
768 int iwl_txq_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
769 struct iwl_device_tx_cmd *dev_cmd, int txq_id);
771 void iwl_txq_dyn_free(struct iwl_trans *trans, int queue);
772 void iwl_txq_gen2_tx_free(struct iwl_trans *trans);
773 int iwl_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
774 int slots_num, bool cmd_queue);
775 int iwl_txq_gen2_init(struct iwl_trans *trans, int txq_id,
778 static inline u16 iwl_txq_gen1_tfd_tb_get_len(struct iwl_trans *trans,
782 struct iwl_tfd_tb *tb;
784 if (trans->trans_cfg->gen2) {
785 struct iwl_tfh_tfd *tfh_tfd = _tfd;
786 struct iwl_tfh_tb *tfh_tb = &tfh_tfd->tbs[idx];
788 return le16_to_cpu(tfh_tb->tb_len);
791 tfd = (struct iwl_tfd *)_tfd;
794 return le16_to_cpu(tb->hi_n_len) >> 4;
797 void iwl_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
798 struct sk_buff_head *skbs, bool is_flush);
799 void iwl_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr);
800 void iwl_pcie_freeze_txq_timer(struct iwl_trans *trans,
801 unsigned long txqs, bool freeze);
802 int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx);
803 int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm);
805 /*****************************************************
807 ******************************************************/
808 void iwl_pcie_dump_csr(struct iwl_trans *trans);
810 /*****************************************************
812 ******************************************************/
813 static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
815 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
817 clear_bit(STATUS_INT_ENABLED, &trans->status);
818 if (!trans_pcie->msix_enabled) {
819 /* disable interrupts from uCode/NIC to host */
820 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
822 /* acknowledge/clear/reset any interrupts still pending
823 * from uCode or flow handler (Rx/Tx DMA) */
824 iwl_write32(trans, CSR_INT, 0xffffffff);
825 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
827 /* disable all the interrupt we might use */
828 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
829 trans_pcie->fh_init_mask);
830 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
831 trans_pcie->hw_init_mask);
833 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
836 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
841 while (start < fw->num_sec &&
842 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
843 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
851 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
853 struct iwl_self_init_dram *dram = &trans->init_dram;
857 WARN_ON(dram->fw_cnt);
861 for (i = 0; i < dram->fw_cnt; i++)
862 dma_free_coherent(trans->dev, dram->fw[i].size,
863 dram->fw[i].block, dram->fw[i].physical);
870 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
872 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
874 spin_lock_bh(&trans_pcie->irq_lock);
875 _iwl_disable_interrupts(trans);
876 spin_unlock_bh(&trans_pcie->irq_lock);
879 static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
881 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
883 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
884 set_bit(STATUS_INT_ENABLED, &trans->status);
885 if (!trans_pcie->msix_enabled) {
886 trans_pcie->inta_mask = CSR_INI_SET_MASK;
887 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
890 * fh/hw_mask keeps all the unmasked causes.
891 * Unlike msi, in msix cause is enabled when it is unset.
893 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
894 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
895 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
896 ~trans_pcie->fh_mask);
897 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
898 ~trans_pcie->hw_mask);
902 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
904 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
906 spin_lock_bh(&trans_pcie->irq_lock);
907 _iwl_enable_interrupts(trans);
908 spin_unlock_bh(&trans_pcie->irq_lock);
910 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
912 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
914 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
915 trans_pcie->hw_mask = msk;
918 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
920 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
922 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
923 trans_pcie->fh_mask = msk;
926 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
928 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
930 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
931 if (!trans_pcie->msix_enabled) {
932 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
933 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
935 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
936 trans_pcie->hw_init_mask);
937 iwl_enable_fh_int_msk_msix(trans,
938 MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
942 static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans)
944 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
946 IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n");
948 if (!trans_pcie->msix_enabled) {
950 * When we'll receive the ALIVE interrupt, the ISR will call
951 * iwl_enable_fw_load_int_ctx_info again to set the ALIVE
952 * interrupt (which is not really needed anymore) but also the
953 * RX interrupt which will allow us to receive the ALIVE
954 * notification (which is Rx) and continue the flow.
956 trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX;
957 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
959 iwl_enable_hw_int_msk_msix(trans,
960 MSIX_HW_INT_CAUSES_REG_ALIVE);
962 * Leave all the FH causes enabled to get the ALIVE
965 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask);
969 static inline const char *queue_name(struct device *dev,
970 struct iwl_trans_pcie *trans_p, int i)
972 if (trans_p->shared_vec_mask) {
973 int vec = trans_p->shared_vec_mask &
974 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
977 return DRV_NAME ":shared_IRQ";
979 return devm_kasprintf(dev, GFP_KERNEL,
980 DRV_NAME ":queue_%d", i + vec);
983 return DRV_NAME ":default_queue";
985 if (i == trans_p->alloc_vecs - 1)
986 return DRV_NAME ":exception";
988 return devm_kasprintf(dev, GFP_KERNEL,
989 DRV_NAME ":queue_%d", i);
992 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
994 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
996 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
997 if (!trans_pcie->msix_enabled) {
998 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
999 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
1001 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
1002 trans_pcie->fh_init_mask);
1003 iwl_enable_hw_int_msk_msix(trans,
1004 MSIX_HW_INT_CAUSES_REG_RF_KILL);
1007 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) {
1009 * On 9000-series devices this bit isn't enabled by default, so
1010 * when we power down the device we need set the bit to allow it
1011 * to wake up the PCI-E bus for RF-kill interrupts.
1013 iwl_set_bit(trans, CSR_GP_CNTRL,
1014 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
1018 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans, bool from_irq);
1020 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
1022 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1024 lockdep_assert_held(&trans_pcie->mutex);
1026 if (trans_pcie->debug_rfkill == 1)
1029 return !(iwl_read32(trans, CSR_GP_CNTRL) &
1030 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1033 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
1034 u32 reg, u32 mask, u32 value)
1038 #ifdef CONFIG_IWLWIFI_DEBUG
1039 WARN_ON_ONCE(value & ~mask);
1042 v = iwl_read32(trans, reg);
1045 iwl_write32(trans, reg, v);
1048 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
1051 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
1054 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
1057 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
1060 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
1062 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans));
1065 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq);
1066 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
1068 #ifdef CONFIG_IWLWIFI_DEBUGFS
1069 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
1070 void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans);
1072 static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { }
1075 void iwl_pcie_rx_allocator_work(struct work_struct *data);
1077 /* common trans ops for all generations transports */
1078 void iwl_trans_pcie_configure(struct iwl_trans *trans,
1079 const struct iwl_trans_config *trans_cfg);
1080 int iwl_trans_pcie_start_hw(struct iwl_trans *trans);
1081 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans);
1082 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val);
1083 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val);
1084 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs);
1085 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg);
1086 void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val);
1087 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1088 void *buf, int dwords);
1089 int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1090 const void *buf, int dwords);
1091 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership);
1092 struct iwl_trans_dump_data *
1093 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask,
1094 const struct iwl_dump_sanitize_ops *sanitize_ops,
1095 void *sanitize_ctx);
1096 int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1097 enum iwl_d3_status *status,
1098 bool test, bool reset);
1099 int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset);
1100 void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable);
1101 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans);
1102 void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1103 u32 mask, u32 value);
1104 int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
1106 bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
1107 void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans);
1109 /* transport gen 1 exported functions */
1110 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr);
1111 int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1112 const struct fw_img *fw, bool run_in_rfkill);
1113 void iwl_trans_pcie_stop_device(struct iwl_trans *trans);
1115 /* common functions that are used by gen2 transport */
1116 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans);
1117 void iwl_pcie_apm_config(struct iwl_trans *trans);
1118 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
1119 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
1120 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
1121 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1122 bool was_in_rfkill);
1123 void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
1124 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
1125 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
1126 struct iwl_dma_ptr *ptr, size_t size);
1127 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
1128 void iwl_pcie_apply_destination(struct iwl_trans *trans);
1130 /* common functions that are used by gen3 transport */
1131 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
1133 /* transport gen 2 exported functions */
1134 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
1135 const struct fw_img *fw, bool run_in_rfkill);
1136 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans);
1137 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
1138 struct iwl_host_cmd *cmd);
1139 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
1140 int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
1141 struct iwl_host_cmd *cmd);
1142 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1143 struct iwl_host_cmd *cmd);
1144 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
1145 u32 dst_addr, u64 src_addr, u32 byte_cnt);
1146 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
1147 u32 dst_addr, u64 src_addr, u32 byte_cnt);
1148 int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
1149 struct iwl_trans_rxq_dma_data *data);
1151 #endif /* __iwl_trans_int_pcie_h__ */