drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright Altera Corporation (C) 2014. All rights reserved.
   3  *
   4  * Adopted from dwmac-sti.c
   5  */
   6
   7 #include <linux/mfd/altera-sysmgr.h>
   8 #include <linux/of.h>
   9 #include <linux/of_address.h>
  10 #include <linux/of_net.h>
  11 #include <linux/phy.h>
  12 #include <linux/regmap.h>
  13 #include <linux/mdio/mdio-regmap.h>
  14 #include <linux/pcs-lynx.h>
  15 #include <linux/reset.h>
  16 #include <linux/stmmac.h>
  17
  18 #include "stmmac.h"
  19 #include "stmmac_platform.h"
  20
  21 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
  22 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
  23 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
  24 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
  25 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
  26 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
  27 #define SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000100
  28
  29 #define SYSMGR_FPGAGRP_MODULE_REG  0x00000028
  30 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
  31 #define SYSMGR_FPGAINTF_EMAC_REG        0x00000070
  32 #define SYSMGR_FPGAINTF_EMAC_BIT        0x1
  33
  34 #define EMAC_SPLITTER_CTRL_REG                  0x0
  35 #define EMAC_SPLITTER_CTRL_SPEED_MASK           0x3
  36 #define EMAC_SPLITTER_CTRL_SPEED_10             0x2
  37 #define EMAC_SPLITTER_CTRL_SPEED_100            0x3
  38 #define EMAC_SPLITTER_CTRL_SPEED_1000           0x0
  39
  40 #define SGMII_ADAPTER_CTRL_REG          0x00
  41 #define SGMII_ADAPTER_ENABLE            0x0000
  42 #define SGMII_ADAPTER_DISABLE           0x0001
  43
  44 struct socfpga_dwmac;
  45 struct socfpga_dwmac_ops {
  46         int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
  47 };
  48
  49 struct socfpga_dwmac {
  50         u32     reg_offset;
  51         u32     reg_shift;
  52         struct  device *dev;
  53         struct regmap *sys_mgr_base_addr;
  54         struct reset_control *stmmac_rst;
  55         struct reset_control *stmmac_ocp_rst;
  56         void __iomem *splitter_base;
  57         void __iomem *tse_pcs_base;
  58         void __iomem *sgmii_adapter_base;
  59         bool f2h_ptp_ref_clk;
  60         const struct socfpga_dwmac_ops *ops;
  61         struct mdio_device *pcs_mdiodev;
  62 };
  63
  64 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode)
  65 {
  66         struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv;
  67         void __iomem *splitter_base = dwmac->splitter_base;
  68         void __iomem *sgmii_adapter_base = dwmac->sgmii_adapter_base;
  69         struct device *dev = dwmac->dev;
  70         struct net_device *ndev = dev_get_drvdata(dev);
  71         struct phy_device *phy_dev = ndev->phydev;
  72         u32 val;
  73
  74         if (sgmii_adapter_base)
  75                 writew(SGMII_ADAPTER_DISABLE,
  76                        sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
  77
  78         if (splitter_base) {
  79                 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
  80                 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
  81
  82                 switch (speed) {
  83                 case 1000:
  84                         val |= EMAC_SPLITTER_CTRL_SPEED_1000;
  85                         break;
  86                 case 100:
  87                         val |= EMAC_SPLITTER_CTRL_SPEED_100;
  88                         break;
  89                 case 10:
  90                         val |= EMAC_SPLITTER_CTRL_SPEED_10;
  91                         break;
  92                 default:
  93                         return;
  94                 }
  95                 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
  96         }
  97
  98         if (phy_dev && sgmii_adapter_base)
  99                 writew(SGMII_ADAPTER_ENABLE,
 100                        sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
 101 }
 102
 103 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
 104 {
 105         struct device_node *np = dev->of_node;
 106         struct regmap *sys_mgr_base_addr;
 107         u32 reg_offset, reg_shift;
 108         int ret, index;
 109         struct device_node *np_splitter = NULL;
 110         struct device_node *np_sgmii_adapter = NULL;
 111         struct resource res_splitter;
 112         struct resource res_tse_pcs;
 113         struct resource res_sgmii_adapter;
 114
 115         sys_mgr_base_addr =
 116                 altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
 117         if (IS_ERR(sys_mgr_base_addr)) {
 118                 dev_info(dev, "No sysmgr-syscon node found\n");
 119                 return PTR_ERR(sys_mgr_base_addr);
 120         }
 121
 122         ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
 123         if (ret) {
 124                 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
 125                 return -EINVAL;
 126         }
 127
 128         ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
 129         if (ret) {
 130                 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
 131                 return -EINVAL;
 132         }
 133
 134         dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
 135
 136         np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
 137         if (np_splitter) {
 138                 ret = of_address_to_resource(np_splitter, 0, &res_splitter);
 139                 of_node_put(np_splitter);
 140                 if (ret) {
 141                         dev_info(dev, "Missing emac splitter address\n");
 142                         return -EINVAL;
 143                 }
 144
 145                 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
 146                 if (IS_ERR(dwmac->splitter_base)) {
 147                         dev_info(dev, "Failed to mapping emac splitter\n");
 148                         return PTR_ERR(dwmac->splitter_base);
 149                 }
 150         }
 151
 152         np_sgmii_adapter = of_parse_phandle(np,
 153                                             "altr,gmii-to-sgmii-converter", 0);
 154         if (np_sgmii_adapter) {
 155                 index = of_property_match_string(np_sgmii_adapter, "reg-names",
 156                                                  "hps_emac_interface_splitter_avalon_slave");
 157
 158                 if (index >= 0) {
 159                         if (of_address_to_resource(np_sgmii_adapter, index,
 160                                                    &res_splitter)) {
 161                                 dev_err(dev,
 162                                         "%s: ERROR: missing emac splitter address\n",
 163                                         __func__);
 164                                 ret = -EINVAL;
 165                                 goto err_node_put;
 166                         }
 167
 168                         dwmac->splitter_base =
 169                             devm_ioremap_resource(dev, &res_splitter);
 170
 171                         if (IS_ERR(dwmac->splitter_base)) {
 172                                 ret = PTR_ERR(dwmac->splitter_base);
 173                                 goto err_node_put;
 174                         }
 175                 }
 176
 177                 index = of_property_match_string(np_sgmii_adapter, "reg-names",
 178                                                  "gmii_to_sgmii_adapter_avalon_slave");
 179
 180                 if (index >= 0) {
 181                         if (of_address_to_resource(np_sgmii_adapter, index,
 182                                                    &res_sgmii_adapter)) {
 183                                 dev_err(dev,
 184                                         "%s: ERROR: failed mapping adapter\n",
 185                                         __func__);
 186                                 ret = -EINVAL;
 187                                 goto err_node_put;
 188                         }
 189
 190                         dwmac->sgmii_adapter_base =
 191                             devm_ioremap_resource(dev, &res_sgmii_adapter);
 192
 193                         if (IS_ERR(dwmac->sgmii_adapter_base)) {
 194                                 ret = PTR_ERR(dwmac->sgmii_adapter_base);
 195                                 goto err_node_put;
 196                         }
 197                 }
 198
 199                 index = of_property_match_string(np_sgmii_adapter, "reg-names",
 200                                                  "eth_tse_control_port");
 201
 202                 if (index >= 0) {
 203                         if (of_address_to_resource(np_sgmii_adapter, index,
 204                                                    &res_tse_pcs)) {
 205                                 dev_err(dev,
 206                                         "%s: ERROR: failed mapping tse control port\n",
 207                                         __func__);
 208                                 ret = -EINVAL;
 209                                 goto err_node_put;
 210                         }
 211
 212                         dwmac->tse_pcs_base =
 213                             devm_ioremap_resource(dev, &res_tse_pcs);
 214
 215                         if (IS_ERR(dwmac->tse_pcs_base)) {
 216                                 ret = PTR_ERR(dwmac->tse_pcs_base);
 217                                 goto err_node_put;
 218                         }
 219                 }
 220         }
 221         dwmac->reg_offset = reg_offset;
 222         dwmac->reg_shift = reg_shift;
 223         dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
 224         dwmac->dev = dev;
 225         of_node_put(np_sgmii_adapter);
 226
 227         return 0;
 228
 229 err_node_put:
 230         of_node_put(np_sgmii_adapter);
 231         return ret;
 232 }
 233
 234 static int socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)
 235 {
 236         struct net_device *ndev = dev_get_drvdata(dwmac->dev);
 237         struct stmmac_priv *priv = netdev_priv(ndev);
 238
 239         return priv->plat->mac_interface;
 240 }
 241
 242 static void socfpga_sgmii_config(struct socfpga_dwmac *dwmac, bool enable)
 243 {
 244         u16 val = enable ? SGMII_ADAPTER_ENABLE : SGMII_ADAPTER_DISABLE;
 245
 246         writew(val, dwmac->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
 247 }
 248
 249 static int socfpga_set_phy_mode_common(int phymode, u32 *val)
 250 {
 251         switch (phymode) {
 252         case PHY_INTERFACE_MODE_RGMII:
 253         case PHY_INTERFACE_MODE_RGMII_ID:
 254         case PHY_INTERFACE_MODE_RGMII_RXID:
 255         case PHY_INTERFACE_MODE_RGMII_TXID:
 256                 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
 257                 break;
 258         case PHY_INTERFACE_MODE_MII:
 259         case PHY_INTERFACE_MODE_GMII:
 260         case PHY_INTERFACE_MODE_SGMII:
 261                 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
 262                 break;
 263         case PHY_INTERFACE_MODE_RMII:
 264                 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
 265                 break;
 266         default:
 267                 return -EINVAL;
 268         }
 269         return 0;
 270 }
 271
 272 static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac)
 273 {
 274         struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
 275         int phymode = socfpga_get_plat_phymode(dwmac);
 276         u32 reg_offset = dwmac->reg_offset;
 277         u32 reg_shift = dwmac->reg_shift;
 278         u32 ctrl, val, module;
 279
 280         if (socfpga_set_phy_mode_common(phymode, &val)) {
 281                 dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
 282                 return -EINVAL;
 283         }
 284
 285         /* Overwrite val to GMII if splitter core is enabled. The phymode here
 286          * is the actual phy mode on phy hardware, but phy interface from
 287          * EMAC core is GMII.
 288          */
 289         if (dwmac->splitter_base)
 290                 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
 291
 292         /* Assert reset to the enet controller before changing the phy mode */
 293         reset_control_assert(dwmac->stmmac_ocp_rst);
 294         reset_control_assert(dwmac->stmmac_rst);
 295
 296         regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
 297         ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
 298         ctrl |= val << reg_shift;
 299
 300         if (dwmac->f2h_ptp_ref_clk ||
 301             phymode == PHY_INTERFACE_MODE_MII ||
 302             phymode == PHY_INTERFACE_MODE_GMII ||
 303             phymode == PHY_INTERFACE_MODE_SGMII) {
 304                 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
 305                             &module);
 306                 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
 307                 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
 308                              module);
 309         }
 310
 311         if (dwmac->f2h_ptp_ref_clk)
 312                 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
 313         else
 314                 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK <<
 315                           (reg_shift / 2));
 316
 317         regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
 318
 319         /* Deassert reset for the phy configuration to be sampled by
 320          * the enet controller, and operation to start in requested mode
 321          */
 322         reset_control_deassert(dwmac->stmmac_ocp_rst);
 323         reset_control_deassert(dwmac->stmmac_rst);
 324         if (phymode == PHY_INTERFACE_MODE_SGMII)
 325                 socfpga_sgmii_config(dwmac, true);
 326
 327         return 0;
 328 }
 329
 330 static int socfpga_gen10_set_phy_mode(struct socfpga_dwmac *dwmac)
 331 {
 332         struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
 333         int phymode = socfpga_get_plat_phymode(dwmac);
 334         u32 reg_offset = dwmac->reg_offset;
 335         u32 reg_shift = dwmac->reg_shift;
 336         u32 ctrl, val, module;
 337
 338         if (socfpga_set_phy_mode_common(phymode, &val))
 339                 return -EINVAL;
 340
 341         /* Overwrite val to GMII if splitter core is enabled. The phymode here
 342          * is the actual phy mode on phy hardware, but phy interface from
 343          * EMAC core is GMII.
 344          */
 345         if (dwmac->splitter_base)
 346                 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
 347
 348         /* Assert reset to the enet controller before changing the phy mode */
 349         reset_control_assert(dwmac->stmmac_ocp_rst);
 350         reset_control_assert(dwmac->stmmac_rst);
 351
 352         regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
 353         ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK);
 354         ctrl |= val;
 355
 356         if (dwmac->f2h_ptp_ref_clk ||
 357             phymode == PHY_INTERFACE_MODE_MII ||
 358             phymode == PHY_INTERFACE_MODE_GMII ||
 359             phymode == PHY_INTERFACE_MODE_SGMII) {
 360                 ctrl |= SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK;
 361                 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAINTF_EMAC_REG,
 362                             &module);
 363                 module |= (SYSMGR_FPGAINTF_EMAC_BIT << reg_shift);
 364                 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAINTF_EMAC_REG,
 365                              module);
 366         } else {
 367                 ctrl &= ~SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK;
 368         }
 369
 370         regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
 371
 372         /* Deassert reset for the phy configuration to be sampled by
 373          * the enet controller, and operation to start in requested mode
 374          */
 375         reset_control_deassert(dwmac->stmmac_ocp_rst);
 376         reset_control_deassert(dwmac->stmmac_rst);
 377         if (phymode == PHY_INTERFACE_MODE_SGMII)
 378                 socfpga_sgmii_config(dwmac, true);
 379         return 0;
 380 }
 381
 382 static int socfpga_dwmac_pcs_init(struct stmmac_priv *priv)
 383 {
 384         struct socfpga_dwmac *dwmac = priv->plat->bsp_priv;
 385         struct regmap_config pcs_regmap_cfg = {
 386                 .reg_bits = 16,
 387                 .val_bits = 16,
 388                 .reg_shift = REGMAP_UPSHIFT(1),
 389         };
 390         struct mdio_regmap_config mrc;
 391         struct regmap *pcs_regmap;
 392         struct phylink_pcs *pcs;
 393         struct mii_bus *pcs_bus;
 394
 395         if (!dwmac->tse_pcs_base)
 396                 return 0;
 397
 398         pcs_regmap = devm_regmap_init_mmio(priv->device, dwmac->tse_pcs_base,
 399                                            &pcs_regmap_cfg);
 400         if (IS_ERR(pcs_regmap))
 401                 return PTR_ERR(pcs_regmap);
 402
 403         memset(&mrc, 0, sizeof(mrc));
 404         mrc.regmap = pcs_regmap;
 405         mrc.parent = priv->device;
 406         mrc.valid_addr = 0x0;
 407         mrc.autoscan = false;
 408
 409         /* Can't use ndev->name here because it will not have been initialised,
 410          * and in any case, the user can rename network interfaces at runtime.
 411          */
 412         snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-pcs-mii",
 413                  dev_name(priv->device));
 414         pcs_bus = devm_mdio_regmap_register(priv->device, &mrc);
 415         if (IS_ERR(pcs_bus))
 416                 return PTR_ERR(pcs_bus);
 417
 418         pcs = lynx_pcs_create_mdiodev(pcs_bus, 0);
 419         if (IS_ERR(pcs))
 420                 return PTR_ERR(pcs);
 421
 422         priv->hw->phylink_pcs = pcs;
 423         return 0;
 424 }
 425
 426 static void socfpga_dwmac_pcs_exit(struct stmmac_priv *priv)
 427 {
 428         if (priv->hw->phylink_pcs)
 429                 lynx_pcs_destroy(priv->hw->phylink_pcs);
 430 }
 431
 432 static struct phylink_pcs *socfpga_dwmac_select_pcs(struct stmmac_priv *priv,
 433                                                     phy_interface_t interface)
 434 {
 435         return priv->hw->phylink_pcs;
 436 }
 437
 438 static int socfpga_dwmac_probe(struct platform_device *pdev)
 439 {
 440         struct plat_stmmacenet_data *plat_dat;
 441         struct stmmac_resources stmmac_res;
 442         struct device           *dev = &pdev->dev;
 443         int                     ret;
 444         struct socfpga_dwmac    *dwmac;
 445         struct net_device       *ndev;
 446         struct stmmac_priv      *stpriv;
 447         const struct socfpga_dwmac_ops *ops;
 448
 449         ops = device_get_match_data(&pdev->dev);
 450         if (!ops) {
 451                 dev_err(&pdev->dev, "no of match data provided\n");
 452                 return -EINVAL;
 453         }
 454
 455         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
 456         if (ret)
 457                 return ret;
 458
 459         plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
 460         if (IS_ERR(plat_dat))
 461                 return PTR_ERR(plat_dat);
 462
 463         dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
 464         if (!dwmac)
 465                 return -ENOMEM;
 466
 467         dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp");
 468         if (IS_ERR(dwmac->stmmac_ocp_rst)) {
 469                 ret = PTR_ERR(dwmac->stmmac_ocp_rst);
 470                 dev_err(dev, "error getting reset control of ocp %d\n", ret);
 471                 return ret;
 472         }
 473
 474         reset_control_deassert(dwmac->stmmac_ocp_rst);
 475
 476         ret = socfpga_dwmac_parse_data(dwmac, dev);
 477         if (ret) {
 478                 dev_err(dev, "Unable to parse OF data\n");
 479                 return ret;
 480         }
 481
 482         dwmac->ops = ops;
 483         plat_dat->bsp_priv = dwmac;
 484         plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
 485         plat_dat->pcs_init = socfpga_dwmac_pcs_init;
 486         plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
 487         plat_dat->select_pcs = socfpga_dwmac_select_pcs;
 488         plat_dat->has_gmac = true;
 489
 490         plat_dat->riwt_off = 1;
 491
 492         ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
 493         if (ret)
 494                 return ret;
 495
 496         ndev = platform_get_drvdata(pdev);
 497         stpriv = netdev_priv(ndev);
 498
 499         /* The socfpga driver needs to control the stmmac reset to set the phy
 500          * mode. Create a copy of the core reset handle so it can be used by
 501          * the driver later.
 502          */
 503         dwmac->stmmac_rst = stpriv->plat->stmmac_rst;
 504
 505         ret = ops->set_phy_mode(dwmac);
 506         if (ret)
 507                 goto err_dvr_remove;
 508
 509         return 0;
 510
 511 err_dvr_remove:
 512         stmmac_dvr_remove(&pdev->dev);
 513
 514         return ret;
 515 }
 516
 517 #ifdef CONFIG_PM_SLEEP
 518 static int socfpga_dwmac_resume(struct device *dev)
 519 {
 520         struct net_device *ndev = dev_get_drvdata(dev);
 521         struct stmmac_priv *priv = netdev_priv(ndev);
 522         struct socfpga_dwmac *dwmac_priv = get_stmmac_bsp_priv(dev);
 523
 524         dwmac_priv->ops->set_phy_mode(priv->plat->bsp_priv);
 525
 526         /* Before the enet controller is suspended, the phy is suspended.
 527          * This causes the phy clock to be gated. The enet controller is
 528          * resumed before the phy, so the clock is still gated "off" when
 529          * the enet controller is resumed. This code makes sure the phy
 530          * is "resumed" before reinitializing the enet controller since
 531          * the enet controller depends on an active phy clock to complete
 532          * a DMA reset. A DMA reset will "time out" if executed
 533          * with no phy clock input on the Synopsys enet controller.
 534          * Verified through Synopsys Case #8000711656.
 535          *
 536          * Note that the phy clock is also gated when the phy is isolated.
 537          * Phy "suspend" and "isolate" controls are located in phy basic
 538          * control register 0, and can be modified by the phy driver
 539          * framework.
 540          */
 541         if (ndev->phydev)
 542                 phy_resume(ndev->phydev);
 543
 544         return stmmac_resume(dev);
 545 }
 546 #endif /* CONFIG_PM_SLEEP */
 547
 548 static int __maybe_unused socfpga_dwmac_runtime_suspend(struct device *dev)
 549 {
 550         struct net_device *ndev = dev_get_drvdata(dev);
 551         struct stmmac_priv *priv = netdev_priv(ndev);
 552
 553         stmmac_bus_clks_config(priv, false);
 554
 555         return 0;
 556 }
 557
 558 static int __maybe_unused socfpga_dwmac_runtime_resume(struct device *dev)
 559 {
 560         struct net_device *ndev = dev_get_drvdata(dev);
 561         struct stmmac_priv *priv = netdev_priv(ndev);
 562
 563         return stmmac_bus_clks_config(priv, true);
 564 }
 565
 566 static const struct dev_pm_ops socfpga_dwmac_pm_ops = {
 567         SET_SYSTEM_SLEEP_PM_OPS(stmmac_suspend, socfpga_dwmac_resume)
 568         SET_RUNTIME_PM_OPS(socfpga_dwmac_runtime_suspend, socfpga_dwmac_runtime_resume, NULL)
 569 };
 570
 571 static const struct socfpga_dwmac_ops socfpga_gen5_ops = {
 572         .set_phy_mode = socfpga_gen5_set_phy_mode,
 573 };
 574
 575 static const struct socfpga_dwmac_ops socfpga_gen10_ops = {
 576         .set_phy_mode = socfpga_gen10_set_phy_mode,
 577 };
 578
 579 static const struct of_device_id socfpga_dwmac_match[] = {
 580         { .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops },
 581         { .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops },
 582         { }
 583 };
 584 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
 585
 586 static struct platform_driver socfpga_dwmac_driver = {
 587         .probe  = socfpga_dwmac_probe,
 588         .remove = stmmac_pltfr_remove,
 589         .driver = {
 590                 .name           = "socfpga-dwmac",
 591                 .pm             = &socfpga_dwmac_pm_ops,
 592                 .of_match_table = socfpga_dwmac_match,
 593         },
 594 };
 595 module_platform_driver(socfpga_dwmac_driver);
 596
 597 MODULE_DESCRIPTION("Altera SOC DWMAC Specific Glue layer");
 598 MODULE_LICENSE("GPL v2");