1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
7 #include <linux/dsa/ocelot.h>
8 #include <linux/if_bridge.h>
9 #include <linux/iopoll.h>
10 #include <linux/phy/phy.h>
11 #include <net/pkt_sched.h>
12 #include <soc/mscc/ocelot_hsio.h>
13 #include <soc/mscc/ocelot_vcap.h>
15 #include "ocelot_vcap.h"
17 #define TABLE_UPDATE_SLEEP_US 10
18 #define TABLE_UPDATE_TIMEOUT_US 100000
19 #define MEM_INIT_SLEEP_US 1000
20 #define MEM_INIT_TIMEOUT_US 100000
22 #define OCELOT_RSV_VLAN_RANGE_START 4000
24 struct ocelot_mact_entry {
27 enum macaccess_entry_type type;
30 /* Caller must hold &ocelot->mact_lock */
31 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
33 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
36 /* Caller must hold &ocelot->mact_lock */
37 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
41 return readx_poll_timeout(ocelot_mact_read_macaccess,
43 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
45 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
48 /* Caller must hold &ocelot->mact_lock */
49 static void ocelot_mact_select(struct ocelot *ocelot,
50 const unsigned char mac[ETH_ALEN],
53 u32 macl = 0, mach = 0;
55 /* Set the MAC address to handle and the vlan associated in a format
56 * understood by the hardware.
66 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
67 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
71 static int __ocelot_mact_learn(struct ocelot *ocelot, int port,
72 const unsigned char mac[ETH_ALEN],
73 unsigned int vid, enum macaccess_entry_type type)
75 u32 cmd = ANA_TABLES_MACACCESS_VALID |
76 ANA_TABLES_MACACCESS_DEST_IDX(port) |
77 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
78 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
79 unsigned int mc_ports;
82 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
83 if (type == ENTRYTYPE_MACv4)
84 mc_ports = (mac[1] << 8) | mac[2];
85 else if (type == ENTRYTYPE_MACv6)
86 mc_ports = (mac[0] << 8) | mac[1];
90 if (mc_ports & BIT(ocelot->num_phys_ports))
91 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
93 ocelot_mact_select(ocelot, mac, vid);
95 /* Issue a write command */
96 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
98 err = ocelot_mact_wait_for_completion(ocelot);
103 int ocelot_mact_learn(struct ocelot *ocelot, int port,
104 const unsigned char mac[ETH_ALEN],
105 unsigned int vid, enum macaccess_entry_type type)
109 mutex_lock(&ocelot->mact_lock);
110 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type);
111 mutex_unlock(&ocelot->mact_lock);
115 EXPORT_SYMBOL(ocelot_mact_learn);
117 int ocelot_mact_forget(struct ocelot *ocelot,
118 const unsigned char mac[ETH_ALEN], unsigned int vid)
122 mutex_lock(&ocelot->mact_lock);
124 ocelot_mact_select(ocelot, mac, vid);
126 /* Issue a forget command */
128 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
129 ANA_TABLES_MACACCESS);
131 err = ocelot_mact_wait_for_completion(ocelot);
133 mutex_unlock(&ocelot->mact_lock);
137 EXPORT_SYMBOL(ocelot_mact_forget);
139 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
140 const unsigned char mac[ETH_ALEN],
141 unsigned int vid, enum macaccess_entry_type *type)
145 mutex_lock(&ocelot->mact_lock);
147 ocelot_mact_select(ocelot, mac, vid);
149 /* Issue a read command with MACACCESS_VALID=1. */
150 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID |
151 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
152 ANA_TABLES_MACACCESS);
154 if (ocelot_mact_wait_for_completion(ocelot)) {
155 mutex_unlock(&ocelot->mact_lock);
159 /* Read back the entry flags */
160 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
162 mutex_unlock(&ocelot->mact_lock);
164 if (!(val & ANA_TABLES_MACACCESS_VALID))
167 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val);
168 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val);
172 EXPORT_SYMBOL(ocelot_mact_lookup);
174 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
175 const unsigned char mac[ETH_ALEN],
177 enum macaccess_entry_type type,
182 mutex_lock(&ocelot->mact_lock);
185 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) |
186 ANA_TABLES_STREAMDATA_SFID(sfid) |
187 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) |
188 ANA_TABLES_STREAMDATA_SSID(ssid),
189 ANA_TABLES_STREAMDATA);
191 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type);
193 mutex_unlock(&ocelot->mact_lock);
197 EXPORT_SYMBOL(ocelot_mact_learn_streamdata);
199 static void ocelot_mact_init(struct ocelot *ocelot)
201 /* Configure the learning mode entries attributes:
202 * - Do not copy the frame to the CPU extraction queues.
203 * - Use the vlan and mac_cpoy for dmac lookup.
205 ocelot_rmw(ocelot, 0,
206 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
207 | ANA_AGENCTRL_LEARN_FWD_KILL
208 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
211 /* Clear the MAC table. We are not concurrent with anyone, so
212 * holding &ocelot->mact_lock is pointless.
214 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
217 void ocelot_pll5_init(struct ocelot *ocelot)
219 /* Configure PLL5. This will need a proper CCF driver
220 * The values are coming from the VTSS API for Ocelot
222 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4,
223 HSIO_PLL5G_CFG4_IB_CTRL(0x7600) |
224 HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8));
225 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0,
226 HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) |
227 HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) |
228 HSIO_PLL5G_CFG0_ENA_BIAS |
229 HSIO_PLL5G_CFG0_ENA_VCO_BUF |
230 HSIO_PLL5G_CFG0_ENA_CP1 |
231 HSIO_PLL5G_CFG0_SELCPI(2) |
232 HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) |
233 HSIO_PLL5G_CFG0_SELBGV820(4) |
234 HSIO_PLL5G_CFG0_DIV4 |
235 HSIO_PLL5G_CFG0_ENA_CLKTREE |
236 HSIO_PLL5G_CFG0_ENA_LANE);
237 regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2,
238 HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET |
239 HSIO_PLL5G_CFG2_EN_RESET_OVERRUN |
240 HSIO_PLL5G_CFG2_GAIN_TEST(0x8) |
241 HSIO_PLL5G_CFG2_ENA_AMPCTRL |
242 HSIO_PLL5G_CFG2_PWD_AMPCTRL_N |
243 HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
245 EXPORT_SYMBOL(ocelot_pll5_init);
247 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
249 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
250 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
251 ANA_PORT_VCAP_S2_CFG, port);
253 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
254 ANA_PORT_VCAP_CFG, port);
256 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
261 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot,
262 struct netlink_ext_ack *extack)
264 struct net_device *bridge = NULL;
267 for (port = 0; port < ocelot->num_phys_ports; port++) {
268 struct ocelot_port *ocelot_port = ocelot->ports[port];
270 if (!ocelot_port || !ocelot_port->bridge ||
271 !br_vlan_enabled(ocelot_port->bridge))
275 bridge = ocelot_port->bridge;
279 if (bridge == ocelot_port->bridge)
282 NL_SET_ERR_MSG_MOD(extack,
283 "Only one VLAN-aware bridge is supported");
290 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
292 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
295 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
299 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
302 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
303 ANA_TABLES_VLANACCESS_CMD_IDLE,
304 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
307 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
309 /* Select the VID to configure */
310 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
311 ANA_TABLES_VLANTIDX);
312 /* Set the vlan port members mask and issue a write command */
313 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
314 ANA_TABLES_VLANACCESS_CMD_WRITE,
315 ANA_TABLES_VLANACCESS);
317 return ocelot_vlant_wait_for_completion(ocelot);
320 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port)
322 struct ocelot_bridge_vlan *vlan;
323 int num_untagged = 0;
325 list_for_each_entry(vlan, &ocelot->vlans, list) {
326 if (!(vlan->portmask & BIT(port)))
329 /* Ignore the VLAN added by ocelot_add_vlan_unaware_pvid(),
330 * because this is never active in hardware at the same time as
331 * the bridge VLANs, which only matter in VLAN-aware mode.
333 if (vlan->vid >= OCELOT_RSV_VLAN_RANGE_START)
336 if (vlan->untagged & BIT(port))
343 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port)
345 struct ocelot_bridge_vlan *vlan;
348 list_for_each_entry(vlan, &ocelot->vlans, list) {
349 if (!(vlan->portmask & BIT(port)))
352 if (!(vlan->untagged & BIT(port)))
359 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly
360 * _one_ egress-untagged VLAN (_the_ native VLAN)
362 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port)
364 return ocelot_port_num_tagged_vlans(ocelot, port) &&
365 ocelot_port_num_untagged_vlans(ocelot, port) == 1;
368 static struct ocelot_bridge_vlan *
369 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port)
371 struct ocelot_bridge_vlan *vlan;
373 list_for_each_entry(vlan, &ocelot->vlans, list)
374 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port))
380 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable,
381 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness
384 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port)
386 struct ocelot_port *ocelot_port = ocelot->ports[port];
387 enum ocelot_port_tag_config tag_cfg;
388 bool uses_native_vlan = false;
390 if (ocelot_port->vlan_aware) {
391 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port);
393 if (uses_native_vlan)
394 tag_cfg = OCELOT_PORT_TAG_NATIVE;
395 else if (ocelot_port_num_untagged_vlans(ocelot, port))
396 tag_cfg = OCELOT_PORT_TAG_DISABLED;
398 tag_cfg = OCELOT_PORT_TAG_TRUNK;
400 tag_cfg = OCELOT_PORT_TAG_DISABLED;
403 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg),
404 REW_TAG_CFG_TAG_CFG_M,
407 if (uses_native_vlan) {
408 struct ocelot_bridge_vlan *native_vlan;
410 /* Not having a native VLAN is impossible, because
411 * ocelot_port_num_untagged_vlans has returned 1.
412 * So there is no use in checking for NULL here.
414 native_vlan = ocelot_port_find_native_vlan(ocelot, port);
416 ocelot_rmw_gix(ocelot,
417 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid),
418 REW_PORT_VLAN_CFG_PORT_VID_M,
419 REW_PORT_VLAN_CFG, port);
423 int ocelot_bridge_num_find(struct ocelot *ocelot,
424 const struct net_device *bridge)
428 for (port = 0; port < ocelot->num_phys_ports; port++) {
429 struct ocelot_port *ocelot_port = ocelot->ports[port];
431 if (ocelot_port && ocelot_port->bridge == bridge)
432 return ocelot_port->bridge_num;
437 EXPORT_SYMBOL_GPL(ocelot_bridge_num_find);
439 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot,
440 const struct net_device *bridge)
444 /* Standalone ports use VID 0 */
448 bridge_num = ocelot_bridge_num_find(ocelot, bridge);
449 if (WARN_ON(bridge_num < 0))
452 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */
453 return VLAN_N_VID - bridge_num - 1;
457 * ocelot_update_vlan_reclassify_rule() - Make switch aware only to bridge VLAN TPID
459 * @ocelot: Switch private data structure
460 * @port: Index of ingress port
462 * IEEE 802.1Q-2018 clauses "5.5 C-VLAN component conformance" and "5.6 S-VLAN
463 * component conformance" suggest that a C-VLAN component should only recognize
464 * and filter on C-Tags, and an S-VLAN component should only recognize and
465 * process based on C-Tags.
467 * In Linux, as per commit 1a0b20b25732 ("Merge branch 'bridge-next'"), C-VLAN
468 * components are largely represented by a bridge with vlan_protocol 802.1Q,
469 * and S-VLAN components by a bridge with vlan_protocol 802.1ad.
471 * Currently the driver only offloads vlan_protocol 802.1Q, but the hardware
472 * design is non-conformant, because the switch assigns each frame to a VLAN
473 * based on an entirely different question, as detailed in figure "Basic VLAN
474 * Classification Flow" from its manual and reproduced below.
476 * Set TAG_TYPE, PCP, DEI, VID to port-default values in VLAN_CFG register
477 * if VLAN_AWARE_ENA[port] and frame has outer tag then:
478 * if VLAN_INNER_TAG_ENA[port] and frame has inner tag then:
479 * TAG_TYPE = (Frame.InnerTPID <> 0x8100)
480 * Set PCP, DEI, VID to values from inner VLAN header
482 * TAG_TYPE = (Frame.OuterTPID <> 0x8100)
483 * Set PCP, DEI, VID to values from outer VLAN header
485 * VID = VLAN_CFG.VLAN_VID
487 * Summarized, the switch will recognize both 802.1Q and 802.1ad TPIDs as VLAN
488 * "with equal rights", and just set the TAG_TYPE bit to 0 (if 802.1Q) or to 1
489 * (if 802.1ad). It will classify based on whichever of the tags is "outer", no
490 * matter what TPID that may have (or "inner", if VLAN_INNER_TAG_ENA[port]).
492 * In the VLAN Table, the TAG_TYPE information is not accessible - just the
493 * classified VID is - so it is as if each VLAN Table entry is for 2 VLANs:
494 * C-VLAN X, and S-VLAN X.
496 * Whereas the Linux bridge behavior is to only filter on frames with a TPID
497 * equal to the vlan_protocol, and treat everything else as VLAN-untagged.
499 * Consider an ingress packet tagged with 802.1ad VID=3 and 802.1Q VID=5,
500 * received on a bridge vlan_filtering=1 vlan_protocol=802.1Q port. This frame
501 * should be treated as 802.1Q-untagged, and classified to the PVID of that
502 * bridge port. Not to VID=3, and not to VID=5.
504 * The VCAP IS1 TCAM has everything we need to overwrite the choices made in
505 * the basic VLAN classification pipeline: it can match on TAG_TYPE in the key,
506 * and it can modify the classified VID in the action. Thus, for each port
507 * under a vlan_filtering bridge, we can insert a rule in VCAP IS1 lookup 0 to
508 * match on 802.1ad tagged frames and modify their classified VID to the 802.1Q
509 * PVID of the port. This effectively makes it appear to the outside world as
510 * if those packets were processed as VLAN-untagged.
512 * The rule needs to be updated each time the bridge PVID changes, and needs
513 * to be deleted if the bridge PVID is deleted, or if the port becomes
516 static int ocelot_update_vlan_reclassify_rule(struct ocelot *ocelot, int port)
518 unsigned long cookie = OCELOT_VCAP_IS1_VLAN_RECLASSIFY(ocelot, port);
519 struct ocelot_vcap_block *block_vcap_is1 = &ocelot->block[VCAP_IS1];
520 struct ocelot_port *ocelot_port = ocelot->ports[port];
521 const struct ocelot_bridge_vlan *pvid_vlan;
522 struct ocelot_vcap_filter *filter;
523 int err, val, pcp, dei;
524 bool vid_replace_ena;
527 pvid_vlan = ocelot_port->pvid_vlan;
528 vid_replace_ena = ocelot_port->vlan_aware && pvid_vlan;
530 filter = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, cookie,
532 if (!vid_replace_ena) {
533 /* If the reclassification filter doesn't need to exist, delete
534 * it if it was previously installed, and exit doing nothing
538 return ocelot_vcap_filter_del(ocelot, filter);
543 /* The reclassification rule must apply. See if it already exists
544 * or if it must be created.
547 /* Treating as VLAN-untagged means using as classified VID equal to
548 * the bridge PVID, and PCP/DEI set to the port default QoS values.
550 vid = pvid_vlan->vid;
551 val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
552 pcp = ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val);
553 dei = !!(val & ANA_PORT_QOS_CFG_DP_DEFAULT_VAL);
556 bool changed = false;
558 /* Filter exists, just update it */
559 if (filter->action.vid != vid) {
560 filter->action.vid = vid;
563 if (filter->action.pcp != pcp) {
564 filter->action.pcp = pcp;
567 if (filter->action.dei != dei) {
568 filter->action.dei = dei;
575 return ocelot_vcap_filter_replace(ocelot, filter);
578 /* Filter doesn't exist, create it */
579 filter = kzalloc(sizeof(*filter), GFP_KERNEL);
583 filter->key_type = OCELOT_VCAP_KEY_ANY;
584 filter->ingress_port_mask = BIT(port);
585 filter->vlan.tpid = OCELOT_VCAP_BIT_1;
587 filter->id.cookie = cookie;
588 filter->id.tc_offload = false;
589 filter->block_id = VCAP_IS1;
590 filter->type = OCELOT_VCAP_FILTER_OFFLOAD;
592 filter->action.vid_replace_ena = true;
593 filter->action.pcp_dei_ena = true;
594 filter->action.vid = vid;
595 filter->action.pcp = pcp;
596 filter->action.dei = dei;
598 err = ocelot_vcap_filter_add(ocelot, filter, NULL);
605 /* Default vlan to clasify for untagged frames (may be zero) */
606 static int ocelot_port_set_pvid(struct ocelot *ocelot, int port,
607 const struct ocelot_bridge_vlan *pvid_vlan)
609 struct ocelot_port *ocelot_port = ocelot->ports[port];
610 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge);
613 ocelot_port->pvid_vlan = pvid_vlan;
615 if (ocelot_port->vlan_aware && pvid_vlan)
616 pvid = pvid_vlan->vid;
618 ocelot_rmw_gix(ocelot,
619 ANA_PORT_VLAN_CFG_VLAN_VID(pvid),
620 ANA_PORT_VLAN_CFG_VLAN_VID_M,
621 ANA_PORT_VLAN_CFG, port);
623 /* If there's no pvid, we should drop not only untagged traffic (which
624 * happens automatically), but also 802.1p traffic which gets
625 * classified to VLAN 0, but that is always in our RX filter, so it
626 * would get accepted were it not for this setting.
628 * Also, we only support the bridge 802.1Q VLAN protocol, so
629 * 802.1ad-tagged frames (carrying S-Tags) should be considered
630 * 802.1Q-untagged, and also dropped.
632 if (!pvid_vlan && ocelot_port->vlan_aware)
633 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
634 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA |
635 ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA;
637 ocelot_rmw_gix(ocelot, val,
638 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
639 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA |
640 ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA,
641 ANA_PORT_DROP_CFG, port);
643 return ocelot_update_vlan_reclassify_rule(ocelot, port);
646 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot,
649 struct ocelot_bridge_vlan *vlan;
651 list_for_each_entry(vlan, &ocelot->vlans, list)
652 if (vlan->vid == vid)
658 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid,
661 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
662 unsigned long portmask;
666 portmask = vlan->portmask | BIT(port);
668 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
672 vlan->portmask = portmask;
673 /* Bridge VLANs can be overwritten with a different
674 * egress-tagging setting, so make sure to override an untagged
675 * with a tagged VID if that's going on.
678 vlan->untagged |= BIT(port);
680 vlan->untagged &= ~BIT(port);
685 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
689 portmask = BIT(port);
691 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
698 vlan->portmask = portmask;
700 vlan->untagged = BIT(port);
701 INIT_LIST_HEAD(&vlan->list);
702 list_add_tail(&vlan->list, &ocelot->vlans);
707 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
709 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid);
710 unsigned long portmask;
716 portmask = vlan->portmask & ~BIT(port);
718 err = ocelot_vlant_set_mask(ocelot, vid, portmask);
722 vlan->portmask = portmask;
726 list_del(&vlan->list);
732 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port,
733 const struct net_device *bridge)
735 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
737 return ocelot_vlan_member_add(ocelot, port, vid, true);
740 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port,
741 const struct net_device *bridge)
743 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
745 return ocelot_vlan_member_del(ocelot, port, vid);
748 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
749 bool vlan_aware, struct netlink_ext_ack *extack)
751 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
752 struct ocelot_port *ocelot_port = ocelot->ports[port];
753 struct ocelot_vcap_filter *filter;
757 list_for_each_entry(filter, &block->rules, list) {
758 if (filter->ingress_port_mask & BIT(port) &&
759 filter->action.vid_replace_ena) {
760 NL_SET_ERR_MSG_MOD(extack,
761 "Cannot change VLAN state with vlan modify rules active");
766 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
771 err = ocelot_del_vlan_unaware_pvid(ocelot, port,
772 ocelot_port->bridge);
773 else if (ocelot_port->bridge)
774 err = ocelot_add_vlan_unaware_pvid(ocelot, port,
775 ocelot_port->bridge);
779 ocelot_port->vlan_aware = vlan_aware;
782 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
783 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
786 ocelot_rmw_gix(ocelot, val,
787 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
788 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
789 ANA_PORT_VLAN_CFG, port);
791 err = ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
795 ocelot_port_manage_port_tag(ocelot, port);
799 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
801 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
802 bool untagged, struct netlink_ext_ack *extack)
805 /* We are adding an egress-tagged VLAN */
806 if (ocelot_port_uses_native_vlan(ocelot, port)) {
807 NL_SET_ERR_MSG_MOD(extack,
808 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN");
812 /* We are adding an egress-tagged VLAN */
813 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) {
814 NL_SET_ERR_MSG_MOD(extack,
815 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs");
820 if (vid > OCELOT_RSV_VLAN_RANGE_START) {
821 NL_SET_ERR_MSG_MOD(extack,
822 "VLAN range 4000-4095 reserved for VLAN-unaware bridging");
828 EXPORT_SYMBOL(ocelot_vlan_prepare);
830 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
835 /* Ignore VID 0 added to our RX filter by the 8021q module, since
836 * that collides with OCELOT_STANDALONE_PVID and changes it from
837 * egress-untagged to egress-tagged.
842 err = ocelot_vlan_member_add(ocelot, port, vid, untagged);
846 /* Default ingress vlan classification */
848 err = ocelot_port_set_pvid(ocelot, port,
849 ocelot_bridge_vlan_find(ocelot, vid));
854 /* Untagged egress vlan clasification */
855 ocelot_port_manage_port_tag(ocelot, port);
859 EXPORT_SYMBOL(ocelot_vlan_add);
861 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
863 struct ocelot_port *ocelot_port = ocelot->ports[port];
864 bool del_pvid = false;
870 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid)
873 err = ocelot_vlan_member_del(ocelot, port, vid);
879 err = ocelot_port_set_pvid(ocelot, port, NULL);
885 ocelot_port_manage_port_tag(ocelot, port);
889 EXPORT_SYMBOL(ocelot_vlan_del);
891 static void ocelot_vlan_init(struct ocelot *ocelot)
893 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
896 /* Clear VLAN table, by default all ports are members of all VLANs */
897 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
898 ANA_TABLES_VLANACCESS);
899 ocelot_vlant_wait_for_completion(ocelot);
901 /* Configure the port VLAN memberships */
902 for (vid = 1; vid < VLAN_N_VID; vid++)
903 ocelot_vlant_set_mask(ocelot, vid, 0);
905 /* We need VID 0 to get traffic on standalone ports.
906 * It is added automatically if the 8021q module is loaded, but we
907 * can't rely on that since it might not be.
909 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports);
911 /* Set vlan ingress filter mask to all ports but the CPU port by
914 ocelot_write(ocelot, all_ports, ANA_VLANMASK);
916 for (port = 0; port < ocelot->num_phys_ports; port++) {
917 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
918 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
922 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
924 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
927 static int ocelot_port_flush(struct ocelot *ocelot, int port)
929 unsigned int pause_ena;
932 /* Disable dequeuing from the egress queues */
933 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
934 QSYS_PORT_MODE_DEQUEUE_DIS,
935 QSYS_PORT_MODE, port);
937 /* Disable flow control */
938 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
939 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
941 /* Disable priority flow control */
942 ocelot_fields_write(ocelot, port,
943 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
945 /* Wait at least the time it takes to receive a frame of maximum length
947 * Worst-case delays for 10 kilobyte jumbo frames are:
949 * 800 μs on a 100M port
950 * 80 μs on a 1G port
951 * 32 μs on a 2.5G port
953 usleep_range(8000, 10000);
955 /* Disable half duplex backpressure. */
956 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
957 SYS_FRONT_PORT_MODE, port);
959 /* Flush the queues associated with the port. */
960 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
963 /* Enable dequeuing from the egress queues. */
964 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
967 /* Wait until flushing is complete. */
968 err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
969 100, 2000000, false, ocelot, port);
971 /* Clear flushing again. */
972 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
974 /* Re-enable flow control */
975 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
980 int ocelot_port_configure_serdes(struct ocelot *ocelot, int port,
981 struct device_node *portnp)
983 struct ocelot_port *ocelot_port = ocelot->ports[port];
984 struct device *dev = ocelot->dev;
987 /* Ensure clock signals and speed are set on all QSGMII links */
988 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_QSGMII)
989 ocelot_port_rmwl(ocelot_port, 0,
990 DEV_CLOCK_CFG_MAC_TX_RST |
991 DEV_CLOCK_CFG_MAC_RX_RST,
994 if (ocelot_port->phy_mode != PHY_INTERFACE_MODE_INTERNAL) {
995 struct phy *serdes = of_phy_get(portnp, NULL);
997 if (IS_ERR(serdes)) {
998 err = PTR_ERR(serdes);
999 dev_err_probe(dev, err,
1000 "missing SerDes phys for port %d\n",
1005 err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET,
1006 ocelot_port->phy_mode);
1009 dev_err(dev, "Could not SerDes mode on port %d: %pe\n",
1010 port, ERR_PTR(err));
1017 EXPORT_SYMBOL_GPL(ocelot_port_configure_serdes);
1019 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port,
1020 unsigned int link_an_mode,
1021 const struct phylink_link_state *state)
1023 struct ocelot_port *ocelot_port = ocelot->ports[port];
1025 /* Disable HDX fast control */
1026 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS,
1029 /* SGMII only for now */
1030 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
1032 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
1035 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
1037 /* No aneg on SGMII */
1038 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG);
1041 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
1043 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_config);
1045 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
1046 unsigned int link_an_mode,
1047 phy_interface_t interface,
1048 unsigned long quirks)
1050 struct ocelot_port *ocelot_port = ocelot->ports[port];
1053 ocelot_port->speed = SPEED_UNKNOWN;
1055 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
1058 if (ocelot->ops->cut_through_fwd) {
1059 mutex_lock(&ocelot->fwd_domain_lock);
1060 ocelot->ops->cut_through_fwd(ocelot);
1061 mutex_unlock(&ocelot->fwd_domain_lock);
1064 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
1066 err = ocelot_port_flush(ocelot, port);
1068 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
1071 /* Put the port in reset. */
1072 if (interface != PHY_INTERFACE_MODE_QSGMII ||
1073 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))
1074 ocelot_port_rmwl(ocelot_port,
1075 DEV_CLOCK_CFG_MAC_TX_RST |
1076 DEV_CLOCK_CFG_MAC_RX_RST,
1077 DEV_CLOCK_CFG_MAC_TX_RST |
1078 DEV_CLOCK_CFG_MAC_RX_RST,
1081 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);
1083 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
1084 struct phy_device *phydev,
1085 unsigned int link_an_mode,
1086 phy_interface_t interface,
1087 int speed, int duplex,
1088 bool tx_pause, bool rx_pause,
1089 unsigned long quirks)
1091 struct ocelot_port *ocelot_port = ocelot->ports[port];
1092 int mac_speed, mode = 0;
1095 ocelot_port->speed = speed;
1097 /* The MAC might be integrated in systems where the MAC speed is fixed
1098 * and it's the PCS who is performing the rate adaptation, so we have
1099 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
1100 * (which is also its default value).
1102 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||
1103 speed == SPEED_1000) {
1104 mac_speed = OCELOT_SPEED_1000;
1105 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
1106 } else if (speed == SPEED_2500) {
1107 mac_speed = OCELOT_SPEED_2500;
1108 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
1109 } else if (speed == SPEED_100) {
1110 mac_speed = OCELOT_SPEED_100;
1112 mac_speed = OCELOT_SPEED_10;
1115 if (duplex == DUPLEX_FULL)
1116 mode |= DEV_MAC_MODE_CFG_FDX_ENA;
1118 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);
1120 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
1121 * PORT_RST bits in DEV_CLOCK_CFG.
1123 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
1128 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);
1131 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);
1135 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);
1138 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
1144 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
1147 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
1148 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
1149 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
1150 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
1152 /* Flow control. Link speed is only used here to evaluate the time
1153 * specification in incoming pause frames.
1155 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
1157 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
1159 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */
1160 if (port != ocelot->npi)
1161 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA,
1164 /* Undo the effects of ocelot_phylink_mac_link_down:
1167 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
1168 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
1170 /* If the port supports cut-through forwarding, update the masks before
1171 * enabling forwarding on the port.
1173 if (ocelot->ops->cut_through_fwd) {
1174 mutex_lock(&ocelot->fwd_domain_lock);
1175 /* Workaround for hardware bug - FP doesn't work
1176 * at all link speeds for all PHY modes. The function
1177 * below also calls ocelot->ops->cut_through_fwd(),
1178 * so we don't need to do it twice.
1180 ocelot_port_update_active_preemptible_tcs(ocelot, port);
1181 mutex_unlock(&ocelot->fwd_domain_lock);
1184 /* Core: Enable port for frame transfer */
1185 ocelot_fields_write(ocelot, port,
1186 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
1188 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);
1190 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
1193 u32 bytes_valid, val;
1195 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1196 if (val == XTR_NOT_READY) {
1201 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1202 } while (val == XTR_NOT_READY);
1213 bytes_valid = XTR_VALID_BYTES(val);
1214 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1215 if (val == XTR_ESCAPE)
1216 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1222 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1232 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
1236 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
1237 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
1239 return (err < 0) ? err : -EIO;
1245 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
1248 struct skb_shared_hwtstamps *shhwtstamps;
1249 u64 tod_in_ns, full_ts_in_ns;
1250 struct timespec64 ts;
1252 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1254 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
1255 if ((tod_in_ns & 0xffffffff) < timestamp)
1256 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
1259 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
1262 shhwtstamps = skb_hwtstamps(skb);
1263 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
1264 shhwtstamps->hwtstamp = full_ts_in_ns;
1266 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp);
1268 void ocelot_lock_inj_grp(struct ocelot *ocelot, int grp)
1269 __acquires(&ocelot->inj_lock)
1271 spin_lock(&ocelot->inj_lock);
1273 EXPORT_SYMBOL_GPL(ocelot_lock_inj_grp);
1275 void ocelot_unlock_inj_grp(struct ocelot *ocelot, int grp)
1276 __releases(&ocelot->inj_lock)
1278 spin_unlock(&ocelot->inj_lock);
1280 EXPORT_SYMBOL_GPL(ocelot_unlock_inj_grp);
1282 void ocelot_lock_xtr_grp(struct ocelot *ocelot, int grp)
1283 __acquires(&ocelot->inj_lock)
1285 spin_lock(&ocelot->inj_lock);
1287 EXPORT_SYMBOL_GPL(ocelot_lock_xtr_grp);
1289 void ocelot_unlock_xtr_grp(struct ocelot *ocelot, int grp)
1290 __releases(&ocelot->inj_lock)
1292 spin_unlock(&ocelot->inj_lock);
1294 EXPORT_SYMBOL_GPL(ocelot_unlock_xtr_grp);
1296 void ocelot_lock_xtr_grp_bh(struct ocelot *ocelot, int grp)
1297 __acquires(&ocelot->xtr_lock)
1299 spin_lock_bh(&ocelot->xtr_lock);
1301 EXPORT_SYMBOL_GPL(ocelot_lock_xtr_grp_bh);
1303 void ocelot_unlock_xtr_grp_bh(struct ocelot *ocelot, int grp)
1304 __releases(&ocelot->xtr_lock)
1306 spin_unlock_bh(&ocelot->xtr_lock);
1308 EXPORT_SYMBOL_GPL(ocelot_unlock_xtr_grp_bh);
1310 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
1312 u64 timestamp, src_port, len;
1313 u32 xfh[OCELOT_TAG_LEN / 4];
1314 struct net_device *dev;
1315 struct sk_buff *skb;
1320 lockdep_assert_held(&ocelot->xtr_lock);
1322 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
1326 ocelot_xfh_get_src_port(xfh, &src_port);
1327 ocelot_xfh_get_len(xfh, &len);
1328 ocelot_xfh_get_rew_val(xfh, ×tamp);
1330 if (WARN_ON(src_port >= ocelot->num_phys_ports))
1333 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
1337 skb = netdev_alloc_skb(dev, len);
1338 if (unlikely(!skb)) {
1339 netdev_err(dev, "Unable to allocate sk_buff\n");
1343 buf_len = len - ETH_FCS_LEN;
1344 buf = (u32 *)skb_put(skb, buf_len);
1348 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1355 } while (len < buf_len);
1358 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
1364 /* Update the statistics if part of the FCS was read before */
1365 len -= ETH_FCS_LEN - sz;
1367 if (unlikely(dev->features & NETIF_F_RXFCS)) {
1368 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
1373 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp);
1375 /* Everything we see on an interface that is in the HW bridge
1376 * has already been forwarded.
1378 if (ocelot->ports[src_port]->bridge)
1379 skb->offload_fwd_mark = 1;
1381 skb->protocol = eth_type_trans(skb, dev);
1391 EXPORT_SYMBOL(ocelot_xtr_poll_frame);
1393 bool ocelot_can_inject(struct ocelot *ocelot, int grp)
1395 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
1397 lockdep_assert_held(&ocelot->inj_lock);
1399 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
1401 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
1406 EXPORT_SYMBOL(ocelot_can_inject);
1409 * ocelot_ifh_set_basic - Set basic information in Injection Frame Header
1410 * @ifh: Pointer to Injection Frame Header memory
1411 * @ocelot: Switch private data structure
1412 * @port: Egress port number
1413 * @rew_op: Egress rewriter operation for PTP
1414 * @skb: Pointer to socket buffer (packet)
1416 * Populate the Injection Frame Header with basic information for this skb: the
1417 * analyzer bypass bit, destination port, VLAN info, egress rewriter info.
1419 void ocelot_ifh_set_basic(void *ifh, struct ocelot *ocelot, int port,
1420 u32 rew_op, struct sk_buff *skb)
1422 struct ocelot_port *ocelot_port = ocelot->ports[port];
1423 struct net_device *dev = skb->dev;
1424 u64 vlan_tci, tag_type;
1427 ocelot_xmit_get_vlan_info(skb, ocelot_port->bridge, &vlan_tci,
1430 qos_class = netdev_get_num_tc(dev) ?
1431 netdev_get_prio_tc_map(dev, skb->priority) : skb->priority;
1433 memset(ifh, 0, OCELOT_TAG_LEN);
1434 ocelot_ifh_set_bypass(ifh, 1);
1435 ocelot_ifh_set_src(ifh, ocelot->num_phys_ports);
1436 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
1437 ocelot_ifh_set_qos_class(ifh, qos_class);
1438 ocelot_ifh_set_tag_type(ifh, tag_type);
1439 ocelot_ifh_set_vlan_tci(ifh, vlan_tci);
1441 ocelot_ifh_set_rew_op(ifh, rew_op);
1443 EXPORT_SYMBOL(ocelot_ifh_set_basic);
1445 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
1446 u32 rew_op, struct sk_buff *skb)
1448 u32 ifh[OCELOT_TAG_LEN / 4];
1449 unsigned int i, count, last;
1451 lockdep_assert_held(&ocelot->inj_lock);
1453 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1454 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
1456 ocelot_ifh_set_basic(ifh, ocelot, port, rew_op, skb);
1458 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
1459 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
1461 count = DIV_ROUND_UP(skb->len, 4);
1462 last = skb->len % 4;
1463 for (i = 0; i < count; i++)
1464 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
1467 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
1468 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1472 /* Indicate EOF and valid bytes in last word */
1473 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
1474 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
1479 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
1480 skb_tx_timestamp(skb);
1482 skb->dev->stats.tx_packets++;
1483 skb->dev->stats.tx_bytes += skb->len;
1485 EXPORT_SYMBOL(ocelot_port_inject_frame);
1487 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
1489 lockdep_assert_held(&ocelot->xtr_lock);
1491 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
1492 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
1494 EXPORT_SYMBOL(ocelot_drain_cpu_queue);
1496 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1497 u16 vid, const struct net_device *bridge)
1500 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1502 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
1504 EXPORT_SYMBOL(ocelot_fdb_add);
1506 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1507 u16 vid, const struct net_device *bridge)
1510 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
1512 return ocelot_mact_forget(ocelot, addr, vid);
1514 EXPORT_SYMBOL(ocelot_fdb_del);
1516 /* Caller must hold &ocelot->mact_lock */
1517 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1518 struct ocelot_mact_entry *entry)
1520 u32 val, dst, macl, mach;
1523 /* Set row and column to read from */
1524 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1525 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1527 /* Issue a read command */
1528 ocelot_write(ocelot,
1529 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1530 ANA_TABLES_MACACCESS);
1532 if (ocelot_mact_wait_for_completion(ocelot))
1535 /* Read the entry flags */
1536 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1537 if (!(val & ANA_TABLES_MACACCESS_VALID))
1540 /* If the entry read has another port configured as its destination,
1543 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1547 /* Get the entry's MAC address and VLAN id */
1548 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1549 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1551 mac[0] = (mach >> 8) & 0xff;
1552 mac[1] = (mach >> 0) & 0xff;
1553 mac[2] = (macl >> 24) & 0xff;
1554 mac[3] = (macl >> 16) & 0xff;
1555 mac[4] = (macl >> 8) & 0xff;
1556 mac[5] = (macl >> 0) & 0xff;
1558 entry->vid = (mach >> 16) & 0xfff;
1559 ether_addr_copy(entry->mac, mac);
1564 int ocelot_mact_flush(struct ocelot *ocelot, int port)
1568 mutex_lock(&ocelot->mact_lock);
1570 /* Program ageing filter for a single port */
1571 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port),
1574 /* Flushing dynamic FDB entries requires two successive age scans */
1575 ocelot_write(ocelot,
1576 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1577 ANA_TABLES_MACACCESS);
1579 err = ocelot_mact_wait_for_completion(ocelot);
1581 mutex_unlock(&ocelot->mact_lock);
1586 ocelot_write(ocelot,
1587 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE),
1588 ANA_TABLES_MACACCESS);
1590 err = ocelot_mact_wait_for_completion(ocelot);
1592 /* Restore ageing filter */
1593 ocelot_write(ocelot, 0, ANA_ANAGEFIL);
1595 mutex_unlock(&ocelot->mact_lock);
1599 EXPORT_SYMBOL_GPL(ocelot_mact_flush);
1601 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1602 dsa_fdb_dump_cb_t *cb, void *data)
1607 /* We could take the lock just around ocelot_mact_read, but doing so
1608 * thousands of times in a row seems rather pointless and inefficient.
1610 mutex_lock(&ocelot->mact_lock);
1612 /* Loop through all the mac tables entries. */
1613 for (i = 0; i < ocelot->num_mact_rows; i++) {
1614 for (j = 0; j < 4; j++) {
1615 struct ocelot_mact_entry entry;
1618 err = ocelot_mact_read(ocelot, port, i, j, &entry);
1619 /* If the entry is invalid (wrong port, invalid...),
1627 is_static = (entry.type == ENTRYTYPE_LOCKED);
1629 /* Hide the reserved VLANs used for
1630 * VLAN-unaware bridging.
1632 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START)
1635 err = cb(entry.mac, entry.vid, is_static, data);
1641 mutex_unlock(&ocelot->mact_lock);
1645 EXPORT_SYMBOL(ocelot_fdb_dump);
1647 int ocelot_trap_add(struct ocelot *ocelot, int port,
1648 unsigned long cookie, bool take_ts,
1649 void (*populate)(struct ocelot_vcap_filter *f))
1651 struct ocelot_vcap_block *block_vcap_is2;
1652 struct ocelot_vcap_filter *trap;
1656 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1658 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1661 trap = kzalloc(sizeof(*trap), GFP_KERNEL);
1667 trap->id.cookie = cookie;
1668 trap->id.tc_offload = false;
1669 trap->block_id = VCAP_IS2;
1670 trap->type = OCELOT_VCAP_FILTER_OFFLOAD;
1672 trap->action.cpu_copy_ena = true;
1673 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY;
1674 trap->action.port_mask = 0;
1675 trap->take_ts = take_ts;
1676 trap->is_trap = true;
1680 trap->ingress_port_mask |= BIT(port);
1683 err = ocelot_vcap_filter_add(ocelot, trap, NULL);
1685 err = ocelot_vcap_filter_replace(ocelot, trap);
1687 trap->ingress_port_mask &= ~BIT(port);
1688 if (!trap->ingress_port_mask)
1696 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie)
1698 struct ocelot_vcap_block *block_vcap_is2;
1699 struct ocelot_vcap_filter *trap;
1701 block_vcap_is2 = &ocelot->block[VCAP_IS2];
1703 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie,
1708 trap->ingress_port_mask &= ~BIT(port);
1709 if (!trap->ingress_port_mask)
1710 return ocelot_vcap_filter_del(ocelot, trap);
1712 return ocelot_vcap_filter_replace(ocelot, trap);
1715 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond)
1720 lockdep_assert_held(&ocelot->fwd_domain_lock);
1722 for (port = 0; port < ocelot->num_phys_ports; port++) {
1723 struct ocelot_port *ocelot_port = ocelot->ports[port];
1728 if (ocelot_port->bond == bond)
1735 /* The logical port number of a LAG is equal to the lowest numbered physical
1736 * port ID present in that LAG. It may change if that port ever leaves the LAG.
1738 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)
1740 int bond_mask = ocelot_get_bond_mask(ocelot, bond);
1745 return __ffs(bond_mask);
1747 EXPORT_SYMBOL_GPL(ocelot_bond_get_id);
1749 /* Returns the mask of user ports assigned to this DSA tag_8021q CPU port.
1750 * Note that when CPU ports are in a LAG, the user ports are assigned to the
1751 * 'primary' CPU port, the one whose physical port number gives the logical
1752 * port number of the LAG.
1754 * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG
1755 * (to which no user port is assigned), but it appears that forwarding from
1756 * this secondary CPU port looks at the PGID_SRC associated with the logical
1757 * port ID that it's assigned to, which *is* configured properly.
1759 static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot,
1760 struct ocelot_port *cpu)
1765 for (port = 0; port < ocelot->num_phys_ports; port++) {
1766 struct ocelot_port *ocelot_port = ocelot->ports[port];
1771 if (ocelot_port->dsa_8021q_cpu == cpu)
1776 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond);
1781 /* Returns the DSA tag_8021q CPU port that the given port is assigned to,
1782 * or the bit mask of CPU ports if said CPU port is in a LAG.
1784 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port)
1786 struct ocelot_port *ocelot_port = ocelot->ports[port];
1787 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu;
1793 return ocelot_get_bond_mask(ocelot, cpu_port->bond);
1795 return BIT(cpu_port->index);
1797 EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask);
1799 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
1801 struct ocelot_port *ocelot_port = ocelot->ports[src_port];
1802 const struct net_device *bridge;
1806 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING)
1809 bridge = ocelot_port->bridge;
1813 for (port = 0; port < ocelot->num_phys_ports; port++) {
1814 ocelot_port = ocelot->ports[port];
1819 if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
1820 ocelot_port->bridge == bridge)
1826 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
1828 static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
1832 lockdep_assert_held(&ocelot->fwd_domain_lock);
1834 /* If cut-through forwarding is supported, update the masks before a
1835 * port joins the forwarding domain, to avoid potential underruns if it
1836 * has the highest speed from the new domain.
1838 if (joining && ocelot->ops->cut_through_fwd)
1839 ocelot->ops->cut_through_fwd(ocelot);
1841 /* Apply FWD mask. The loop is needed to add/remove the current port as
1842 * a source for the other ports.
1844 for (port = 0; port < ocelot->num_phys_ports; port++) {
1845 struct ocelot_port *ocelot_port = ocelot->ports[port];
1849 /* Unused ports can't send anywhere */
1851 } else if (ocelot_port->is_dsa_8021q_cpu) {
1852 /* The DSA tag_8021q CPU ports need to be able to
1853 * forward packets to all ports assigned to them.
1855 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot,
1857 } else if (ocelot_port->bridge) {
1858 struct net_device *bond = ocelot_port->bond;
1860 mask = ocelot_get_bridge_fwd_mask(ocelot, port);
1863 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1867 mask &= ~ocelot_get_bond_mask(ocelot, bond);
1869 /* Standalone ports forward only to DSA tag_8021q CPU
1870 * ports (if those exist), or to the hardware CPU port
1873 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
1877 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1880 /* If cut-through forwarding is supported and a port is leaving, there
1881 * is a chance that cut-through was disabled on the other ports due to
1882 * the port which is leaving (it has a higher link speed). We need to
1883 * update the cut-through masks of the remaining ports no earlier than
1884 * after the port has left, to prevent underruns from happening between
1885 * the cut-through update and the forwarding domain update.
1887 if (!joining && ocelot->ops->cut_through_fwd)
1888 ocelot->ops->cut_through_fwd(ocelot);
1891 /* Update PGID_CPU which is the destination port mask used for whitelisting
1892 * unicast addresses filtered towards the host. In the normal and NPI modes,
1893 * this points to the analyzer entry for the CPU port module, while in DSA
1894 * tag_8021q mode, it is a bit mask of all active CPU ports.
1895 * PGID_SRC will take care of forwarding a packet from one user port to
1896 * no more than a single CPU port.
1898 static void ocelot_update_pgid_cpu(struct ocelot *ocelot)
1903 for (port = 0; port < ocelot->num_phys_ports; port++) {
1904 struct ocelot_port *ocelot_port = ocelot->ports[port];
1906 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu)
1909 pgid_cpu |= BIT(port);
1913 pgid_cpu = BIT(ocelot->num_phys_ports);
1915 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU);
1918 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1920 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1923 mutex_lock(&ocelot->fwd_domain_lock);
1925 cpu_port->is_dsa_8021q_cpu = true;
1927 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1928 ocelot_vlan_member_add(ocelot, cpu, vid, true);
1930 ocelot_update_pgid_cpu(ocelot);
1932 mutex_unlock(&ocelot->fwd_domain_lock);
1934 EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu);
1936 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu)
1938 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1941 mutex_lock(&ocelot->fwd_domain_lock);
1943 cpu_port->is_dsa_8021q_cpu = false;
1945 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
1946 ocelot_vlan_member_del(ocelot, cpu_port->index, vid);
1948 ocelot_update_pgid_cpu(ocelot);
1950 mutex_unlock(&ocelot->fwd_domain_lock);
1952 EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu);
1954 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port,
1957 struct ocelot_port *cpu_port = ocelot->ports[cpu];
1959 mutex_lock(&ocelot->fwd_domain_lock);
1961 ocelot->ports[port]->dsa_8021q_cpu = cpu_port;
1962 ocelot_apply_bridge_fwd_mask(ocelot, true);
1964 mutex_unlock(&ocelot->fwd_domain_lock);
1966 EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu);
1968 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port)
1970 mutex_lock(&ocelot->fwd_domain_lock);
1972 ocelot->ports[port]->dsa_8021q_cpu = NULL;
1973 ocelot_apply_bridge_fwd_mask(ocelot, true);
1975 mutex_unlock(&ocelot->fwd_domain_lock);
1977 EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu);
1979 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1981 struct ocelot_port *ocelot_port = ocelot->ports[port];
1984 mutex_lock(&ocelot->fwd_domain_lock);
1986 ocelot_port->stp_state = state;
1988 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
1989 ocelot_port->learn_ena)
1990 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
1992 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
1993 ANA_PORT_PORT_CFG, port);
1995 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING);
1997 mutex_unlock(&ocelot->fwd_domain_lock);
1999 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
2001 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
2003 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
2005 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
2006 * which is clearly not what our intention is. So avoid that.
2011 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
2013 EXPORT_SYMBOL(ocelot_set_ageing_time);
2015 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
2016 const unsigned char *addr,
2019 struct ocelot_multicast *mc;
2021 list_for_each_entry(mc, &ocelot->multicast, list) {
2022 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
2029 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
2031 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
2032 return ENTRYTYPE_MACv4;
2033 if (addr[0] == 0x33 && addr[1] == 0x33)
2034 return ENTRYTYPE_MACv6;
2035 return ENTRYTYPE_LOCKED;
2038 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
2039 unsigned long ports)
2041 struct ocelot_pgid *pgid;
2043 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
2045 return ERR_PTR(-ENOMEM);
2047 pgid->ports = ports;
2048 pgid->index = index;
2049 refcount_set(&pgid->refcount, 1);
2050 list_add_tail(&pgid->list, &ocelot->pgids);
2055 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
2057 if (!refcount_dec_and_test(&pgid->refcount))
2060 list_del(&pgid->list);
2064 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
2065 const struct ocelot_multicast *mc)
2067 struct ocelot_pgid *pgid;
2070 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
2071 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
2072 * destination mask table (PGID), the destination set is programmed as
2073 * part of the entry MAC address.", and the DEST_IDX is set to 0.
2075 if (mc->entry_type == ENTRYTYPE_MACv4 ||
2076 mc->entry_type == ENTRYTYPE_MACv6)
2077 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
2079 list_for_each_entry(pgid, &ocelot->pgids, list) {
2080 /* When searching for a nonreserved multicast PGID, ignore the
2081 * dummy PGID of zero that we have for MACv4/MACv6 entries
2083 if (pgid->index && pgid->ports == mc->ports) {
2084 refcount_inc(&pgid->refcount);
2089 /* Search for a free index in the nonreserved multicast PGID area */
2090 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
2093 list_for_each_entry(pgid, &ocelot->pgids, list) {
2094 if (pgid->index == index) {
2101 return ocelot_pgid_alloc(ocelot, index, mc->ports);
2104 return ERR_PTR(-ENOSPC);
2107 static void ocelot_encode_ports_to_mdb(unsigned char *addr,
2108 struct ocelot_multicast *mc)
2110 ether_addr_copy(addr, mc->addr);
2112 if (mc->entry_type == ENTRYTYPE_MACv4) {
2114 addr[1] = mc->ports >> 8;
2115 addr[2] = mc->ports & 0xff;
2116 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
2117 addr[0] = mc->ports >> 8;
2118 addr[1] = mc->ports & 0xff;
2122 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
2123 const struct switchdev_obj_port_mdb *mdb,
2124 const struct net_device *bridge)
2126 unsigned char addr[ETH_ALEN];
2127 struct ocelot_multicast *mc;
2128 struct ocelot_pgid *pgid;
2132 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2134 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2137 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
2141 mc->entry_type = ocelot_classify_mdb(mdb->addr);
2142 ether_addr_copy(mc->addr, mdb->addr);
2145 list_add_tail(&mc->list, &ocelot->multicast);
2147 /* Existing entry. Clean up the current port mask from
2148 * hardware now, because we'll be modifying it.
2150 ocelot_pgid_free(ocelot, mc->pgid);
2151 ocelot_encode_ports_to_mdb(addr, mc);
2152 ocelot_mact_forget(ocelot, addr, vid);
2155 mc->ports |= BIT(port);
2157 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2159 dev_err(ocelot->dev,
2160 "Cannot allocate PGID for mdb %pM vid %d\n",
2162 devm_kfree(ocelot->dev, mc);
2163 return PTR_ERR(pgid);
2167 ocelot_encode_ports_to_mdb(addr, mc);
2169 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2170 mc->entry_type != ENTRYTYPE_MACv6)
2171 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2174 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2177 EXPORT_SYMBOL(ocelot_port_mdb_add);
2179 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
2180 const struct switchdev_obj_port_mdb *mdb,
2181 const struct net_device *bridge)
2183 unsigned char addr[ETH_ALEN];
2184 struct ocelot_multicast *mc;
2185 struct ocelot_pgid *pgid;
2189 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2191 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
2195 ocelot_encode_ports_to_mdb(addr, mc);
2196 ocelot_mact_forget(ocelot, addr, vid);
2198 ocelot_pgid_free(ocelot, mc->pgid);
2199 mc->ports &= ~BIT(port);
2201 list_del(&mc->list);
2202 devm_kfree(ocelot->dev, mc);
2206 /* We have a PGID with fewer ports now */
2207 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2209 return PTR_ERR(pgid);
2212 ocelot_encode_ports_to_mdb(addr, mc);
2214 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2215 mc->entry_type != ENTRYTYPE_MACv6)
2216 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2219 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2222 EXPORT_SYMBOL(ocelot_port_mdb_del);
2224 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
2225 struct net_device *bridge, int bridge_num,
2226 struct netlink_ext_ack *extack)
2228 struct ocelot_port *ocelot_port = ocelot->ports[port];
2231 err = ocelot_single_vlan_aware_bridge(ocelot, extack);
2235 mutex_lock(&ocelot->fwd_domain_lock);
2237 ocelot_port->bridge = bridge;
2238 ocelot_port->bridge_num = bridge_num;
2240 ocelot_apply_bridge_fwd_mask(ocelot, true);
2242 mutex_unlock(&ocelot->fwd_domain_lock);
2244 if (br_vlan_enabled(bridge))
2247 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge);
2249 EXPORT_SYMBOL(ocelot_port_bridge_join);
2251 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
2252 struct net_device *bridge)
2254 struct ocelot_port *ocelot_port = ocelot->ports[port];
2256 mutex_lock(&ocelot->fwd_domain_lock);
2258 if (!br_vlan_enabled(bridge))
2259 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge);
2261 ocelot_port->bridge = NULL;
2262 ocelot_port->bridge_num = -1;
2264 ocelot_port_set_pvid(ocelot, port, NULL);
2265 ocelot_port_manage_port_tag(ocelot, port);
2266 ocelot_apply_bridge_fwd_mask(ocelot, false);
2268 mutex_unlock(&ocelot->fwd_domain_lock);
2270 EXPORT_SYMBOL(ocelot_port_bridge_leave);
2272 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
2274 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
2277 /* Reset destination and aggregation PGIDS */
2278 for_each_unicast_dest_pgid(ocelot, port)
2279 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2281 for_each_aggr_pgid(ocelot, i)
2282 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
2285 /* The visited ports bitmask holds the list of ports offloading any
2286 * bonding interface. Initially we mark all these ports as unvisited,
2287 * then every time we visit a port in this bitmask, we know that it is
2288 * the lowest numbered port, i.e. the one whose logical ID == physical
2289 * port ID == LAG ID. So we mark as visited all further ports in the
2290 * bitmask that are offloading the same bonding interface. This way,
2291 * we set up the aggregation PGIDs only once per bonding interface.
2293 for (port = 0; port < ocelot->num_phys_ports; port++) {
2294 struct ocelot_port *ocelot_port = ocelot->ports[port];
2296 if (!ocelot_port || !ocelot_port->bond)
2299 visited &= ~BIT(port);
2302 /* Now, set PGIDs for each active LAG */
2303 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
2304 struct net_device *bond = ocelot->ports[lag]->bond;
2305 int num_active_ports = 0;
2306 unsigned long bond_mask;
2309 if (!bond || (visited & BIT(lag)))
2312 bond_mask = ocelot_get_bond_mask(ocelot, bond);
2314 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
2315 struct ocelot_port *ocelot_port = ocelot->ports[port];
2318 ocelot_write_rix(ocelot, bond_mask,
2319 ANA_PGID_PGID, port);
2321 if (ocelot_port->lag_tx_active)
2322 aggr_idx[num_active_ports++] = port;
2325 for_each_aggr_pgid(ocelot, i) {
2328 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
2330 /* Don't do division by zero if there was no active
2331 * port. Just make all aggregation codes zero.
2333 if (num_active_ports)
2334 ac |= BIT(aggr_idx[i % num_active_ports]);
2335 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
2338 /* Mark all ports in the same LAG as visited to avoid applying
2339 * the same config again.
2341 for (port = lag; port < ocelot->num_phys_ports; port++) {
2342 struct ocelot_port *ocelot_port = ocelot->ports[port];
2347 if (ocelot_port->bond == bond)
2348 visited |= BIT(port);
2353 /* When offloading a bonding interface, the switch ports configured under the
2354 * same bond must have the same logical port ID, equal to the physical port ID
2355 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
2356 * bridged mode, each port has a logical port ID equal to its physical port ID.
2358 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
2362 for (port = 0; port < ocelot->num_phys_ports; port++) {
2363 struct ocelot_port *ocelot_port = ocelot->ports[port];
2364 struct net_device *bond;
2369 bond = ocelot_port->bond;
2371 int lag = ocelot_bond_get_id(ocelot, bond);
2373 ocelot_rmw_gix(ocelot,
2374 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
2375 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2376 ANA_PORT_PORT_CFG, port);
2378 ocelot_rmw_gix(ocelot,
2379 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2380 ANA_PORT_PORT_CFG_PORTID_VAL_M,
2381 ANA_PORT_PORT_CFG, port);
2386 static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc,
2387 unsigned long from_mask, unsigned long to_mask)
2389 unsigned char addr[ETH_ALEN];
2390 struct ocelot_pgid *pgid;
2393 dev_dbg(ocelot->dev,
2394 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n",
2395 mc->addr, mc->vid, from_mask, to_mask);
2397 /* First clean up the current port mask from hardware, because
2398 * we'll be modifying it.
2400 ocelot_pgid_free(ocelot, mc->pgid);
2401 ocelot_encode_ports_to_mdb(addr, mc);
2402 ocelot_mact_forget(ocelot, addr, vid);
2404 mc->ports &= ~from_mask;
2405 mc->ports |= to_mask;
2407 pgid = ocelot_mdb_get_pgid(ocelot, mc);
2409 dev_err(ocelot->dev,
2410 "Cannot allocate PGID for mdb %pM vid %d\n",
2412 devm_kfree(ocelot->dev, mc);
2413 return PTR_ERR(pgid);
2417 ocelot_encode_ports_to_mdb(addr, mc);
2419 if (mc->entry_type != ENTRYTYPE_MACv4 &&
2420 mc->entry_type != ENTRYTYPE_MACv6)
2421 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
2424 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
2428 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
2429 unsigned long to_mask)
2431 struct ocelot_multicast *mc;
2434 list_for_each_entry(mc, &ocelot->multicast, list) {
2435 if (!(mc->ports & from_mask))
2438 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask);
2445 EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs);
2447 /* Documentation for PORTID_VAL says:
2448 * Logical port number for front port. If port is not a member of a LLAG,
2449 * then PORTID must be set to the physical port number.
2450 * If port is a member of a LLAG, then PORTID must be set to the common
2451 * PORTID_VAL used for all member ports of the LLAG.
2452 * The value must not exceed the number of physical ports on the device.
2454 * This means we have little choice but to migrate FDB entries pointing towards
2455 * a logical port when that changes.
2457 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot,
2458 struct net_device *bond,
2461 struct ocelot_lag_fdb *fdb;
2464 lockdep_assert_held(&ocelot->fwd_domain_lock);
2466 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) {
2467 if (fdb->bond != bond)
2470 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid);
2472 dev_err(ocelot->dev,
2473 "failed to delete LAG %s FDB %pM vid %d: %pe\n",
2474 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2477 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid,
2480 dev_err(ocelot->dev,
2481 "failed to migrate LAG %s FDB %pM vid %d: %pe\n",
2482 bond->name, fdb->addr, fdb->vid, ERR_PTR(err));
2487 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
2488 struct net_device *bond,
2489 struct netdev_lag_upper_info *info,
2490 struct netlink_ext_ack *extack)
2492 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
2493 NL_SET_ERR_MSG_MOD(extack,
2494 "Can only offload LAG using hash TX type");
2498 mutex_lock(&ocelot->fwd_domain_lock);
2500 ocelot->ports[port]->bond = bond;
2502 ocelot_setup_logical_port_ids(ocelot);
2503 ocelot_apply_bridge_fwd_mask(ocelot, true);
2504 ocelot_set_aggr_pgids(ocelot);
2506 mutex_unlock(&ocelot->fwd_domain_lock);
2510 EXPORT_SYMBOL(ocelot_port_lag_join);
2512 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
2513 struct net_device *bond)
2515 int old_lag_id, new_lag_id;
2517 mutex_lock(&ocelot->fwd_domain_lock);
2519 old_lag_id = ocelot_bond_get_id(ocelot, bond);
2521 ocelot->ports[port]->bond = NULL;
2523 ocelot_setup_logical_port_ids(ocelot);
2524 ocelot_apply_bridge_fwd_mask(ocelot, false);
2525 ocelot_set_aggr_pgids(ocelot);
2527 new_lag_id = ocelot_bond_get_id(ocelot, bond);
2529 if (new_lag_id >= 0 && old_lag_id != new_lag_id)
2530 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id);
2532 mutex_unlock(&ocelot->fwd_domain_lock);
2534 EXPORT_SYMBOL(ocelot_port_lag_leave);
2536 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
2538 struct ocelot_port *ocelot_port = ocelot->ports[port];
2540 mutex_lock(&ocelot->fwd_domain_lock);
2542 ocelot_port->lag_tx_active = lag_tx_active;
2544 /* Rebalance the LAGs */
2545 ocelot_set_aggr_pgids(ocelot);
2547 mutex_unlock(&ocelot->fwd_domain_lock);
2549 EXPORT_SYMBOL(ocelot_port_lag_change);
2551 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
2552 const unsigned char *addr, u16 vid,
2553 const struct net_device *bridge)
2555 struct ocelot_lag_fdb *fdb;
2558 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL);
2562 mutex_lock(&ocelot->fwd_domain_lock);
2565 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2567 ether_addr_copy(fdb->addr, addr);
2571 lag = ocelot_bond_get_id(ocelot, bond);
2573 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED);
2575 mutex_unlock(&ocelot->fwd_domain_lock);
2580 list_add_tail(&fdb->list, &ocelot->lag_fdbs);
2581 mutex_unlock(&ocelot->fwd_domain_lock);
2585 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add);
2587 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
2588 const unsigned char *addr, u16 vid,
2589 const struct net_device *bridge)
2591 struct ocelot_lag_fdb *fdb, *tmp;
2593 mutex_lock(&ocelot->fwd_domain_lock);
2596 vid = ocelot_vlan_unaware_pvid(ocelot, bridge);
2598 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) {
2599 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid ||
2603 ocelot_mact_forget(ocelot, addr, vid);
2604 list_del(&fdb->list);
2605 mutex_unlock(&ocelot->fwd_domain_lock);
2611 mutex_unlock(&ocelot->fwd_domain_lock);
2615 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del);
2617 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
2618 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
2619 * In the special case that it's the NPI port that we're configuring, the
2620 * length of the tag and optional prefix needs to be accounted for privately,
2621 * in order to be able to sustain communication at the requested @sdu.
2623 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
2625 struct ocelot_port *ocelot_port = ocelot->ports[port];
2626 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
2627 int pause_start, pause_stop;
2630 if (port == ocelot->npi) {
2631 maxlen += OCELOT_TAG_LEN;
2633 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2634 maxlen += OCELOT_SHORT_PREFIX_LEN;
2635 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2636 maxlen += OCELOT_LONG_PREFIX_LEN;
2639 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
2641 /* Set Pause watermark hysteresis */
2642 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
2643 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
2644 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
2646 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
2649 /* Tail dropping watermarks */
2650 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
2651 OCELOT_BUFFER_CELL_SZ;
2652 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
2653 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
2654 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
2656 EXPORT_SYMBOL(ocelot_port_set_maxlen);
2658 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
2660 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
2662 if (port == ocelot->npi) {
2663 max_mtu -= OCELOT_TAG_LEN;
2665 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
2666 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
2667 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
2668 max_mtu -= OCELOT_LONG_PREFIX_LEN;
2673 EXPORT_SYMBOL(ocelot_get_max_mtu);
2675 static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
2678 struct ocelot_port *ocelot_port = ocelot->ports[port];
2682 val = ANA_PORT_PORT_CFG_LEARN_ENA;
2684 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
2685 ANA_PORT_PORT_CFG, port);
2687 ocelot_port->learn_ena = enabled;
2690 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
2698 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
2701 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
2709 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
2710 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4);
2711 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6);
2714 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
2722 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
2725 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
2726 struct switchdev_brport_flags flags)
2728 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2734 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
2736 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
2737 struct switchdev_brport_flags flags)
2739 if (flags.mask & BR_LEARNING)
2740 ocelot_port_set_learning(ocelot, port,
2741 !!(flags.val & BR_LEARNING));
2743 if (flags.mask & BR_FLOOD)
2744 ocelot_port_set_ucast_flood(ocelot, port,
2745 !!(flags.val & BR_FLOOD));
2747 if (flags.mask & BR_MCAST_FLOOD)
2748 ocelot_port_set_mcast_flood(ocelot, port,
2749 !!(flags.val & BR_MCAST_FLOOD));
2751 if (flags.mask & BR_BCAST_FLOOD)
2752 ocelot_port_set_bcast_flood(ocelot, port,
2753 !!(flags.val & BR_BCAST_FLOOD));
2755 EXPORT_SYMBOL(ocelot_port_bridge_flags);
2757 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port)
2759 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2761 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val);
2763 EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio);
2765 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio)
2767 if (prio >= OCELOT_NUM_TC)
2770 ocelot_rmw_gix(ocelot,
2771 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio),
2772 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M,
2776 return ocelot_update_vlan_reclassify_rule(ocelot, port);
2778 EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio);
2780 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp)
2782 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port);
2783 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2785 /* Return error if DSCP prioritization isn't enabled */
2786 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA))
2789 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) {
2790 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg);
2791 /* Re-read ANA_DSCP_CFG for the translated DSCP */
2792 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2795 /* If the DSCP value is not trusted, the QoS classification falls back
2796 * to VLAN PCP or port-based default.
2798 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA))
2801 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg);
2803 EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio);
2805 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2809 if (prio >= OCELOT_NUM_TC)
2812 /* There is at least one app table priority (this one), so we need to
2813 * make sure DSCP prioritization is enabled on the port.
2814 * Also make sure DSCP translation is disabled
2815 * (dcbnl doesn't support it).
2817 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2818 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2820 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask,
2821 ANA_PORT_QOS_CFG, port);
2823 /* Trust this DSCP value and map it to the given QoS class */
2824 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio);
2826 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp);
2830 EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio);
2832 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio)
2834 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp);
2837 /* During a "dcb app replace" command, the new app table entry will be
2838 * added first, then the old one will be deleted. But the hardware only
2839 * supports one QoS class per DSCP value (duh), so if we blindly delete
2840 * the app table entry for this DSCP value, we end up deleting the
2841 * entry with the new priority. Avoid that by checking whether user
2842 * space wants to delete the priority which is currently configured, or
2843 * something else which is no longer current.
2845 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio)
2848 /* Untrust this DSCP value */
2849 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp);
2851 for (i = 0; i < 64; i++) {
2852 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i);
2854 /* There are still app table entries on the port, so we need to
2855 * keep DSCP enabled, nothing to do.
2857 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)
2861 /* Disable DSCP QoS classification if there isn't any trusted
2864 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA |
2865 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA;
2867 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port);
2871 EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio);
2873 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to,
2874 struct netlink_ext_ack *extack)
2876 struct ocelot_mirror *m = ocelot->mirror;
2880 NL_SET_ERR_MSG_MOD(extack,
2881 "Mirroring already configured towards different egress port");
2882 return ERR_PTR(-EBUSY);
2885 refcount_inc(&m->refcount);
2889 m = kzalloc(sizeof(*m), GFP_KERNEL);
2891 return ERR_PTR(-ENOMEM);
2894 refcount_set(&m->refcount, 1);
2897 /* Program the mirror port to hardware */
2898 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS);
2903 void ocelot_mirror_put(struct ocelot *ocelot)
2905 struct ocelot_mirror *m = ocelot->mirror;
2907 if (!refcount_dec_and_test(&m->refcount))
2910 ocelot_write(ocelot, 0, ANA_MIRRORPORTS);
2911 ocelot->mirror = NULL;
2915 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
2916 bool ingress, struct netlink_ext_ack *extack)
2918 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack);
2924 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2925 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2926 ANA_PORT_PORT_CFG, from);
2928 ocelot_rmw(ocelot, BIT(from), BIT(from),
2934 EXPORT_SYMBOL_GPL(ocelot_port_mirror_add);
2936 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress)
2939 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA,
2940 ANA_PORT_PORT_CFG, from);
2942 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS);
2945 ocelot_mirror_put(ocelot);
2947 EXPORT_SYMBOL_GPL(ocelot_port_mirror_del);
2949 static void ocelot_port_reset_mqprio(struct ocelot *ocelot, int port)
2951 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port);
2953 netdev_reset_tc(dev);
2954 ocelot_port_change_fp(ocelot, port, 0);
2957 int ocelot_port_mqprio(struct ocelot *ocelot, int port,
2958 struct tc_mqprio_qopt_offload *mqprio)
2960 struct net_device *dev = ocelot->ops->port_to_netdev(ocelot, port);
2961 struct netlink_ext_ack *extack = mqprio->extack;
2962 struct tc_mqprio_qopt *qopt = &mqprio->qopt;
2963 int num_tc = qopt->num_tc;
2967 ocelot_port_reset_mqprio(ocelot, port);
2971 err = netdev_set_num_tc(dev, num_tc);
2975 for (tc = 0; tc < num_tc; tc++) {
2976 if (qopt->count[tc] != 1) {
2977 NL_SET_ERR_MSG_MOD(extack,
2978 "Only one TXQ per TC supported");
2982 err = netdev_set_tc_queue(dev, tc, 1, qopt->offset[tc]);
2987 err = netif_set_real_num_tx_queues(dev, num_tc);
2991 ocelot_port_change_fp(ocelot, port, mqprio->preemptible_tcs);
2996 ocelot_port_reset_mqprio(ocelot, port);
2999 EXPORT_SYMBOL_GPL(ocelot_port_mqprio);
3001 void ocelot_init_port(struct ocelot *ocelot, int port)
3003 struct ocelot_port *ocelot_port = ocelot->ports[port];
3005 skb_queue_head_init(&ocelot_port->tx_skbs);
3007 /* Basic L2 initialization */
3010 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
3011 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
3013 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
3016 /* Load seed (0) and set MAC HDX late collision */
3017 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
3018 DEV_MAC_HDX_CFG_SEED_LOAD,
3021 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
3024 /* Set Max Length and maximum tags allowed */
3025 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
3026 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
3027 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
3028 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
3029 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
3032 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
3033 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
3034 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
3036 /* Enable transmission of pause frames */
3037 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
3039 /* Drop frames with multicast source address */
3040 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
3041 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
3042 ANA_PORT_DROP_CFG, port);
3044 /* Set default VLAN and tag type to 8021Q. */
3045 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
3046 REW_PORT_VLAN_CFG_PORT_TPID_M,
3047 REW_PORT_VLAN_CFG, port);
3049 /* Disable source address learning for standalone mode */
3050 ocelot_port_set_learning(ocelot, port, false);
3052 /* Set the port's initial logical port ID value, enable receiving
3053 * frames on it, and configure the MAC address learning type to
3056 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
3057 ANA_PORT_PORT_CFG_RECV_ENA |
3058 ANA_PORT_PORT_CFG_PORTID_VAL(port),
3059 ANA_PORT_PORT_CFG, port);
3061 /* Enable vcap lookups */
3062 ocelot_vcap_enable(ocelot, port);
3064 EXPORT_SYMBOL(ocelot_init_port);
3066 /* Configure and enable the CPU port module, which is a set of queues
3067 * accessible through register MMIO, frame DMA or Ethernet (in case
3068 * NPI mode is used).
3070 static void ocelot_cpu_port_init(struct ocelot *ocelot)
3072 int cpu = ocelot->num_phys_ports;
3074 /* The unicast destination PGID for the CPU port module is unused */
3075 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
3076 /* Instead set up a multicast destination PGID for traffic copied to
3077 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
3078 * addresses will be copied to the CPU via this PGID.
3080 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
3081 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
3082 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
3083 ANA_PORT_PORT_CFG, cpu);
3085 /* Enable CPU port module */
3086 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
3087 /* CPU port Injection/Extraction configuration */
3088 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
3089 OCELOT_TAG_PREFIX_NONE);
3090 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
3091 OCELOT_TAG_PREFIX_NONE);
3093 /* Configure the CPU port to be VLAN aware */
3094 ocelot_write_gix(ocelot,
3095 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) |
3096 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
3097 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
3098 ANA_PORT_VLAN_CFG, cpu);
3101 static void ocelot_detect_features(struct ocelot *ocelot)
3105 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
3106 * the number of 240-byte free memory words (aka 4-cell chunks) and not
3107 * 192 bytes as the documentation incorrectly says.
3109 mmgt = ocelot_read(ocelot, SYS_MMGT);
3110 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
3112 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
3113 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
3116 static int ocelot_mem_init_status(struct ocelot *ocelot)
3121 err = regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT],
3127 int ocelot_reset(struct ocelot *ocelot)
3132 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1);
3136 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
3140 /* MEM_INIT is a self-clearing bit. Wait for it to be cleared (should be
3141 * 100us) before enabling the switch core.
3143 err = readx_poll_timeout(ocelot_mem_init_status, ocelot, val, !val,
3144 MEM_INIT_SLEEP_US, MEM_INIT_TIMEOUT_US);
3148 err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1);
3152 return regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1);
3154 EXPORT_SYMBOL(ocelot_reset);
3156 int ocelot_init(struct ocelot *ocelot)
3161 if (ocelot->ops->reset) {
3162 ret = ocelot->ops->reset(ocelot);
3164 dev_err(ocelot->dev, "Switch reset failed\n");
3169 mutex_init(&ocelot->mact_lock);
3170 mutex_init(&ocelot->fwd_domain_lock);
3171 spin_lock_init(&ocelot->ptp_clock_lock);
3172 spin_lock_init(&ocelot->ts_id_lock);
3173 spin_lock_init(&ocelot->inj_lock);
3174 spin_lock_init(&ocelot->xtr_lock);
3176 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
3180 ret = ocelot_stats_init(ocelot);
3182 goto err_stats_init;
3184 INIT_LIST_HEAD(&ocelot->multicast);
3185 INIT_LIST_HEAD(&ocelot->pgids);
3186 INIT_LIST_HEAD(&ocelot->vlans);
3187 INIT_LIST_HEAD(&ocelot->lag_fdbs);
3188 ocelot_detect_features(ocelot);
3189 ocelot_mact_init(ocelot);
3190 ocelot_vlan_init(ocelot);
3191 ocelot_vcap_init(ocelot);
3192 ocelot_cpu_port_init(ocelot);
3194 if (ocelot->ops->psfp_init)
3195 ocelot->ops->psfp_init(ocelot);
3197 if (ocelot->mm_supported) {
3198 ret = ocelot_mm_init(ocelot);
3203 for (port = 0; port < ocelot->num_phys_ports; port++) {
3204 /* Clear all counters (5 groups) */
3205 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
3206 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
3210 /* Only use S-Tag */
3211 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
3213 /* Aggregation mode */
3214 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
3215 ANA_AGGR_CFG_AC_DMAC_ENA |
3216 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
3217 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
3218 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
3219 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
3222 /* Set MAC age time to default value. The entry is aged after
3225 ocelot_write(ocelot,
3226 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
3229 /* Disable learning for frames discarded by VLAN ingress filtering */
3230 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
3232 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
3233 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
3234 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
3236 /* Setup flooding PGIDs */
3237 for (i = 0; i < ocelot->num_flooding_pgids; i++)
3238 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
3239 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
3240 ANA_FLOODING_FLD_UNICAST(PGID_UC),
3242 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
3243 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
3244 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
3245 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
3248 for (port = 0; port < ocelot->num_phys_ports; port++) {
3249 /* Transmit the frame to the local port. */
3250 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
3251 /* Do not forward BPDU frames to the front ports. */
3252 ocelot_write_gix(ocelot,
3253 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
3254 ANA_PORT_CPU_FWD_BPDU_CFG,
3256 /* Ensure bridging is disabled */
3257 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
3260 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
3261 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
3263 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
3266 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
3268 /* Allow broadcast and unknown L2 multicast to the CPU. */
3269 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3270 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3271 ANA_PGID_PGID, PGID_MC);
3272 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3273 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
3274 ANA_PGID_PGID, PGID_BC);
3275 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
3276 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
3278 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
3279 * registers endianness.
3281 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
3282 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
3283 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
3284 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
3285 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
3286 ANA_CPUQ_CFG_CPUQ_LRN(2) |
3287 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
3288 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
3289 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
3290 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
3291 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
3292 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
3293 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
3294 for (i = 0; i < 16; i++)
3295 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
3296 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
3297 ANA_CPUQ_8021_CFG, i);
3302 ocelot_stats_deinit(ocelot);
3304 destroy_workqueue(ocelot->owq);
3307 EXPORT_SYMBOL(ocelot_init);
3309 void ocelot_deinit(struct ocelot *ocelot)
3311 ocelot_stats_deinit(ocelot);
3312 destroy_workqueue(ocelot->owq);
3314 EXPORT_SYMBOL(ocelot_deinit);
3316 void ocelot_deinit_port(struct ocelot *ocelot, int port)
3318 struct ocelot_port *ocelot_port = ocelot->ports[port];
3320 skb_queue_purge(&ocelot_port->tx_skbs);
3322 EXPORT_SYMBOL(ocelot_deinit_port);
3324 MODULE_DESCRIPTION("Microsemi Ocelot switch family library");
3325 MODULE_LICENSE("Dual MIT/GPL");