drivers/net/dsa/realtek/rtl8366rb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
   3  *
   4  * This is a sparsely documented chip, the only viable documentation seems
   5  * to be a patched up code drop from the vendor that appear in various
   6  * GPL source trees.
   7  *
   8  * Copyright (C) 2017 Linus Walleij <[email protected]>
   9  * Copyright (C) 2009-2010 Gabor Juhos <[email protected]>
  10  * Copyright (C) 2010 Antti Seppälä <[email protected]>
  11  * Copyright (C) 2010 Roman Yeryomin <[email protected]>
  12  * Copyright (C) 2011 Colin Leitner <[email protected]>
  13  */
  14
  15 #include <linux/bitops.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/irqchip/chained_irq.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/regmap.h>
  24 #include <linux/string_choices.h>
  25
  26 #include "realtek.h"
  27 #include "realtek-smi.h"
  28 #include "realtek-mdio.h"
  29 #include "rtl83xx.h"
  30
  31 #define RTL8366RB_PORT_NUM_CPU          5
  32 #define RTL8366RB_NUM_PORTS             6
  33 #define RTL8366RB_PHY_NO_MAX            4
  34 #define RTL8366RB_PHY_ADDR_MAX          31
  35
  36 /* Switch Global Configuration register */
  37 #define RTL8366RB_SGCR                          0x0000
  38 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL         BIT(0)
  39 #define RTL8366RB_SGCR_MAX_LENGTH(a)            ((a) << 4)
  40 #define RTL8366RB_SGCR_MAX_LENGTH_MASK          RTL8366RB_SGCR_MAX_LENGTH(0x3)
  41 #define RTL8366RB_SGCR_MAX_LENGTH_1522          RTL8366RB_SGCR_MAX_LENGTH(0x0)
  42 #define RTL8366RB_SGCR_MAX_LENGTH_1536          RTL8366RB_SGCR_MAX_LENGTH(0x1)
  43 #define RTL8366RB_SGCR_MAX_LENGTH_1552          RTL8366RB_SGCR_MAX_LENGTH(0x2)
  44 #define RTL8366RB_SGCR_MAX_LENGTH_16000         RTL8366RB_SGCR_MAX_LENGTH(0x3)
  45 #define RTL8366RB_SGCR_EN_VLAN                  BIT(13)
  46 #define RTL8366RB_SGCR_EN_VLAN_4KTB             BIT(14)
  47
  48 /* Port Enable Control register */
  49 #define RTL8366RB_PECR                          0x0001
  50
  51 /* Switch per-port learning disablement register */
  52 #define RTL8366RB_PORT_LEARNDIS_CTRL            0x0002
  53
  54 /* Security control, actually aging register */
  55 #define RTL8366RB_SECURITY_CTRL                 0x0003
  56
  57 #define RTL8366RB_SSCR2                         0x0004
  58 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA         BIT(0)
  59
  60 /* Port Mode Control registers */
  61 #define RTL8366RB_PMC0                          0x0005
  62 #define RTL8366RB_PMC0_SPI                      BIT(0)
  63 #define RTL8366RB_PMC0_EN_AUTOLOAD              BIT(1)
  64 #define RTL8366RB_PMC0_PROBE                    BIT(2)
  65 #define RTL8366RB_PMC0_DIS_BISR                 BIT(3)
  66 #define RTL8366RB_PMC0_ADCTEST                  BIT(4)
  67 #define RTL8366RB_PMC0_SRAM_DIAG                BIT(5)
  68 #define RTL8366RB_PMC0_EN_SCAN                  BIT(6)
  69 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT          7
  70 #define RTL8366RB_PMC0_P4_IOMODE_MASK           GENMASK(9, 7)
  71 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT          10
  72 #define RTL8366RB_PMC0_P5_IOMODE_MASK           GENMASK(12, 10)
  73 #define RTL8366RB_PMC0_SDSMODE_SHIFT            13
  74 #define RTL8366RB_PMC0_SDSMODE_MASK             GENMASK(15, 13)
  75 #define RTL8366RB_PMC1                          0x0006
  76
  77 /* Port Mirror Control Register */
  78 #define RTL8366RB_PMCR                          0x0007
  79 #define RTL8366RB_PMCR_SOURCE_PORT(a)           (a)
  80 #define RTL8366RB_PMCR_SOURCE_PORT_MASK         0x000f
  81 #define RTL8366RB_PMCR_MONITOR_PORT(a)          ((a) << 4)
  82 #define RTL8366RB_PMCR_MONITOR_PORT_MASK        0x00f0
  83 #define RTL8366RB_PMCR_MIRROR_RX                BIT(8)
  84 #define RTL8366RB_PMCR_MIRROR_TX                BIT(9)
  85 #define RTL8366RB_PMCR_MIRROR_SPC               BIT(10)
  86 #define RTL8366RB_PMCR_MIRROR_ISO               BIT(11)
  87
  88 /* bits 0..7 = port 0, bits 8..15 = port 1 */
  89 #define RTL8366RB_PAACR0                0x0010
  90 /* bits 0..7 = port 2, bits 8..15 = port 3 */
  91 #define RTL8366RB_PAACR1                0x0011
  92 /* bits 0..7 = port 4, bits 8..15 = port 5 */
  93 #define RTL8366RB_PAACR2                0x0012
  94 #define RTL8366RB_PAACR_SPEED_10M       0
  95 #define RTL8366RB_PAACR_SPEED_100M      1
  96 #define RTL8366RB_PAACR_SPEED_1000M     2
  97 #define RTL8366RB_PAACR_FULL_DUPLEX     BIT(2)
  98 #define RTL8366RB_PAACR_LINK_UP         BIT(4)
  99 #define RTL8366RB_PAACR_TX_PAUSE        BIT(5)
 100 #define RTL8366RB_PAACR_RX_PAUSE        BIT(6)
 101 #define RTL8366RB_PAACR_AN              BIT(7)
 102
 103 /* bits 0..7 = port 0, bits 8..15 = port 1 */
 104 #define RTL8366RB_PSTAT0                0x0014
 105 /* bits 0..7 = port 2, bits 8..15 = port 3 */
 106 #define RTL8366RB_PSTAT1                0x0015
 107 /* bits 0..7 = port 4, bits 8..15 = port 5 */
 108 #define RTL8366RB_PSTAT2                0x0016
 109
 110 #define RTL8366RB_POWER_SAVING_REG      0x0021
 111
 112 /* Spanning tree status (STP) control, two bits per port per FID */
 113 #define RTL8366RB_STP_STATE_BASE        0x0050 /* 0x0050..0x0057 */
 114 #define RTL8366RB_STP_STATE_DISABLED    0x0
 115 #define RTL8366RB_STP_STATE_BLOCKING    0x1
 116 #define RTL8366RB_STP_STATE_LEARNING    0x2
 117 #define RTL8366RB_STP_STATE_FORWARDING  0x3
 118 #define RTL8366RB_STP_MASK              GENMASK(1, 0)
 119 #define RTL8366RB_STP_STATE(port, state) \
 120         ((state) << ((port) * 2))
 121 #define RTL8366RB_STP_STATE_MASK(port) \
 122         RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
 123
 124 /* CPU port control reg */
 125 #define RTL8366RB_CPU_CTRL_REG          0x0061
 126 #define RTL8366RB_CPU_PORTS_MSK         0x00FF
 127 /* Disables inserting custom tag length/type 0x8899 */
 128 #define RTL8366RB_CPU_NO_TAG            BIT(15)
 129 #define RTL8366RB_CPU_TAG_SIZE          4
 130
 131 #define RTL8366RB_SMAR0                 0x0070 /* bits 0..15 */
 132 #define RTL8366RB_SMAR1                 0x0071 /* bits 16..31 */
 133 #define RTL8366RB_SMAR2                 0x0072 /* bits 32..47 */
 134
 135 #define RTL8366RB_RESET_CTRL_REG                0x0100
 136 #define RTL8366RB_CHIP_CTRL_RESET_HW            BIT(0)
 137 #define RTL8366RB_CHIP_CTRL_RESET_SW            BIT(1)
 138
 139 #define RTL8366RB_CHIP_ID_REG                   0x0509
 140 #define RTL8366RB_CHIP_ID_8366                  0x5937
 141 #define RTL8366RB_CHIP_VERSION_CTRL_REG         0x050A
 142 #define RTL8366RB_CHIP_VERSION_MASK             0xf
 143
 144 /* PHY registers control */
 145 #define RTL8366RB_PHY_ACCESS_CTRL_REG           0x8000
 146 #define RTL8366RB_PHY_CTRL_READ                 BIT(0)
 147 #define RTL8366RB_PHY_CTRL_WRITE                0
 148 #define RTL8366RB_PHY_ACCESS_BUSY_REG           0x8001
 149 #define RTL8366RB_PHY_INT_BUSY                  BIT(0)
 150 #define RTL8366RB_PHY_EXT_BUSY                  BIT(4)
 151 #define RTL8366RB_PHY_ACCESS_DATA_REG           0x8002
 152 #define RTL8366RB_PHY_EXT_CTRL_REG              0x8010
 153 #define RTL8366RB_PHY_EXT_WRDATA_REG            0x8011
 154 #define RTL8366RB_PHY_EXT_RDDATA_REG            0x8012
 155
 156 #define RTL8366RB_PHY_REG_MASK                  0x1f
 157 #define RTL8366RB_PHY_PAGE_OFFSET               5
 158 #define RTL8366RB_PHY_PAGE_MASK                 (0xf << 5)
 159 #define RTL8366RB_PHY_NO_OFFSET                 9
 160 #define RTL8366RB_PHY_NO_MASK                   (0x1f << 9)
 161
 162 /* VLAN Ingress Control Register 1, one bit per port.
 163  * bit 0 .. 5 will make the switch drop ingress frames without
 164  * VID such as untagged or priority-tagged frames for respective
 165  * port.
 166  * bit 6 .. 11 will make the switch drop ingress frames carrying
 167  * a C-tag with VID != 0 for respective port.
 168  */
 169 #define RTL8366RB_VLAN_INGRESS_CTRL1_REG        0x037E
 170 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6))
 171
 172 /* VLAN Ingress Control Register 2, one bit per port.
 173  * bit0 .. bit5 will make the switch drop all ingress frames with
 174  * a VLAN classification that does not include the port is in its
 175  * member set.
 176  */
 177 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG        0x037f
 178
 179 /* LED control registers */
 180 /* The LED blink rate is global; it is used by all triggers in all groups. */
 181 #define RTL8366RB_LED_BLINKRATE_REG             0x0430
 182 #define RTL8366RB_LED_BLINKRATE_MASK            0x0007
 183 #define RTL8366RB_LED_BLINKRATE_28MS            0x0000
 184 #define RTL8366RB_LED_BLINKRATE_56MS            0x0001
 185 #define RTL8366RB_LED_BLINKRATE_84MS            0x0002
 186 #define RTL8366RB_LED_BLINKRATE_111MS           0x0003
 187 #define RTL8366RB_LED_BLINKRATE_222MS           0x0004
 188 #define RTL8366RB_LED_BLINKRATE_446MS           0x0005
 189
 190 /* LED trigger event for each group */
 191 #define RTL8366RB_LED_CTRL_REG                  0x0431
 192 #define RTL8366RB_LED_CTRL_OFFSET(led_group)    \
 193         (4 * (led_group))
 194 #define RTL8366RB_LED_CTRL_MASK(led_group)      \
 195         (0xf << RTL8366RB_LED_CTRL_OFFSET(led_group))
 196
 197 /* The RTL8366RB_LED_X_X registers are used to manually set the LED state only
 198  * when the corresponding LED group in RTL8366RB_LED_CTRL_REG is
 199  * RTL8366RB_LEDGROUP_FORCE. Otherwise, it is ignored.
 200  */
 201 #define RTL8366RB_LED_0_1_CTRL_REG              0x0432
 202 #define RTL8366RB_LED_2_3_CTRL_REG              0x0433
 203 #define RTL8366RB_LED_X_X_CTRL_REG(led_group)   \
 204         ((led_group) <= 1 ? \
 205                 RTL8366RB_LED_0_1_CTRL_REG : \
 206                 RTL8366RB_LED_2_3_CTRL_REG)
 207 #define RTL8366RB_LED_0_X_CTRL_MASK             GENMASK(5, 0)
 208 #define RTL8366RB_LED_X_1_CTRL_MASK             GENMASK(11, 6)
 209 #define RTL8366RB_LED_2_X_CTRL_MASK             GENMASK(5, 0)
 210 #define RTL8366RB_LED_X_3_CTRL_MASK             GENMASK(11, 6)
 211
 212 #define RTL8366RB_MIB_COUNT                     33
 213 #define RTL8366RB_GLOBAL_MIB_COUNT              1
 214 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET       0x0050
 215 #define RTL8366RB_MIB_COUNTER_BASE              0x1000
 216 #define RTL8366RB_MIB_CTRL_REG                  0x13F0
 217 #define RTL8366RB_MIB_CTRL_USER_MASK            0x0FFC
 218 #define RTL8366RB_MIB_CTRL_BUSY_MASK            BIT(0)
 219 #define RTL8366RB_MIB_CTRL_RESET_MASK           BIT(1)
 220 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)       BIT(2 + (_p))
 221 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET         BIT(11)
 222
 223 #define RTL8366RB_PORT_VLAN_CTRL_BASE           0x0063
 224 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
 225                 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
 226 #define RTL8366RB_PORT_VLAN_CTRL_MASK           0xf
 227 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)      (4 * ((_p) % 4))
 228
 229 #define RTL8366RB_VLAN_TABLE_READ_BASE          0x018C
 230 #define RTL8366RB_VLAN_TABLE_WRITE_BASE         0x0185
 231
 232 #define RTL8366RB_TABLE_ACCESS_CTRL_REG         0x0180
 233 #define RTL8366RB_TABLE_VLAN_READ_CTRL          0x0E01
 234 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL         0x0F01
 235
 236 #define RTL8366RB_VLAN_MC_BASE(_x)              (0x0020 + (_x) * 3)
 237
 238 #define RTL8366RB_PORT_LINK_STATUS_BASE         0x0014
 239 #define RTL8366RB_PORT_STATUS_SPEED_MASK        0x0003
 240 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK       0x0004
 241 #define RTL8366RB_PORT_STATUS_LINK_MASK         0x0010
 242 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK      0x0020
 243 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK      0x0040
 244 #define RTL8366RB_PORT_STATUS_AN_MASK           0x0080
 245
 246 #define RTL8366RB_NUM_VLANS             16
 247 #define RTL8366RB_NUM_LEDGROUPS         4
 248 #define RTL8366RB_NUM_VIDS              4096
 249 #define RTL8366RB_PRIORITYMAX           7
 250 #define RTL8366RB_NUM_FIDS              8
 251 #define RTL8366RB_FIDMAX                7
 252
 253 #define RTL8366RB_PORT_1                BIT(0) /* In userspace port 0 */
 254 #define RTL8366RB_PORT_2                BIT(1) /* In userspace port 1 */
 255 #define RTL8366RB_PORT_3                BIT(2) /* In userspace port 2 */
 256 #define RTL8366RB_PORT_4                BIT(3) /* In userspace port 3 */
 257 #define RTL8366RB_PORT_5                BIT(4) /* In userspace port 4 */
 258
 259 #define RTL8366RB_PORT_CPU              BIT(5) /* CPU port */
 260
 261 #define RTL8366RB_PORT_ALL              (RTL8366RB_PORT_1 |     \
 262                                          RTL8366RB_PORT_2 |     \
 263                                          RTL8366RB_PORT_3 |     \
 264                                          RTL8366RB_PORT_4 |     \
 265                                          RTL8366RB_PORT_5 |     \
 266                                          RTL8366RB_PORT_CPU)
 267
 268 #define RTL8366RB_PORT_ALL_BUT_CPU      (RTL8366RB_PORT_1 |     \
 269                                          RTL8366RB_PORT_2 |     \
 270                                          RTL8366RB_PORT_3 |     \
 271                                          RTL8366RB_PORT_4 |     \
 272                                          RTL8366RB_PORT_5)
 273
 274 #define RTL8366RB_PORT_ALL_EXTERNAL     (RTL8366RB_PORT_1 |     \
 275                                          RTL8366RB_PORT_2 |     \
 276                                          RTL8366RB_PORT_3 |     \
 277                                          RTL8366RB_PORT_4)
 278
 279 #define RTL8366RB_PORT_ALL_INTERNAL      RTL8366RB_PORT_CPU
 280
 281 /* First configuration word per member config, VID and prio */
 282 #define RTL8366RB_VLAN_VID_MASK         0xfff
 283 #define RTL8366RB_VLAN_PRIORITY_SHIFT   12
 284 #define RTL8366RB_VLAN_PRIORITY_MASK    0x7
 285 /* Second configuration word per member config, member and untagged */
 286 #define RTL8366RB_VLAN_UNTAG_SHIFT      8
 287 #define RTL8366RB_VLAN_UNTAG_MASK       0xff
 288 #define RTL8366RB_VLAN_MEMBER_MASK      0xff
 289 /* Third config word per member config, STAG currently unused */
 290 #define RTL8366RB_VLAN_STAG_MBR_MASK    0xff
 291 #define RTL8366RB_VLAN_STAG_MBR_SHIFT   8
 292 #define RTL8366RB_VLAN_STAG_IDX_MASK    0x7
 293 #define RTL8366RB_VLAN_STAG_IDX_SHIFT   5
 294 #define RTL8366RB_VLAN_FID_MASK         0x7
 295
 296 /* Port ingress bandwidth control */
 297 #define RTL8366RB_IB_BASE               0x0200
 298 #define RTL8366RB_IB_REG(pnum)          (RTL8366RB_IB_BASE + (pnum))
 299 #define RTL8366RB_IB_BDTH_MASK          0x3fff
 300 #define RTL8366RB_IB_PREIFG             BIT(14)
 301
 302 /* Port egress bandwidth control */
 303 #define RTL8366RB_EB_BASE               0x02d1
 304 #define RTL8366RB_EB_REG(pnum)          (RTL8366RB_EB_BASE + (pnum))
 305 #define RTL8366RB_EB_BDTH_MASK          0x3fff
 306 #define RTL8366RB_EB_PREIFG_REG         0x02f8
 307 #define RTL8366RB_EB_PREIFG             BIT(9)
 308
 309 #define RTL8366RB_BDTH_SW_MAX           1048512 /* 1048576? */
 310 #define RTL8366RB_BDTH_UNIT             64
 311 #define RTL8366RB_BDTH_REG_DEFAULT      16383
 312
 313 /* QOS */
 314 #define RTL8366RB_QOS                   BIT(15)
 315 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
 316 #define RTL8366RB_QOS_DEFAULT_PREIFG    1
 317
 318 /* Interrupt handling */
 319 #define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440
 320 #define RTL8366RB_INTERRUPT_POLARITY    BIT(0)
 321 #define RTL8366RB_P4_RGMII_LED          BIT(2)
 322 #define RTL8366RB_INTERRUPT_MASK_REG    0x0441
 323 #define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)
 324 #define RTL8366RB_INTERRUPT_ACLEXCEED   BIT(8)
 325 #define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)
 326 #define RTL8366RB_INTERRUPT_P4_FIBER    BIT(12)
 327 #define RTL8366RB_INTERRUPT_P4_UTP      BIT(13)
 328 #define RTL8366RB_INTERRUPT_VALID       (RTL8366RB_INTERRUPT_LINK_CHGALL | \
 329                                          RTL8366RB_INTERRUPT_ACLEXCEED | \
 330                                          RTL8366RB_INTERRUPT_STORMEXCEED | \
 331                                          RTL8366RB_INTERRUPT_P4_FIBER | \
 332                                          RTL8366RB_INTERRUPT_P4_UTP)
 333 #define RTL8366RB_INTERRUPT_STATUS_REG  0x0442
 334 #define RTL8366RB_NUM_INTERRUPT         14 /* 0..13 */
 335
 336 /* Port isolation registers */
 337 #define RTL8366RB_PORT_ISO_BASE         0x0F08
 338 #define RTL8366RB_PORT_ISO(pnum)        (RTL8366RB_PORT_ISO_BASE + (pnum))
 339 #define RTL8366RB_PORT_ISO_EN           BIT(0)
 340 #define RTL8366RB_PORT_ISO_PORTS_MASK   GENMASK(7, 1)
 341 #define RTL8366RB_PORT_ISO_PORTS(pmask) ((pmask) << 1)
 342
 343 /* bits 0..5 enable force when cleared */
 344 #define RTL8366RB_MAC_FORCE_CTRL_REG    0x0F11
 345
 346 #define RTL8366RB_OAM_PARSER_REG        0x0F14
 347 #define RTL8366RB_OAM_MULTIPLEXER_REG   0x0F15
 348
 349 #define RTL8366RB_GREEN_FEATURE_REG     0x0F51
 350 #define RTL8366RB_GREEN_FEATURE_MSK     0x0007
 351 #define RTL8366RB_GREEN_FEATURE_TX      BIT(0)
 352 #define RTL8366RB_GREEN_FEATURE_RX      BIT(2)
 353
 354 enum rtl8366_ledgroup_mode {
 355         RTL8366RB_LEDGROUP_OFF                  = 0x0,
 356         RTL8366RB_LEDGROUP_DUP_COL              = 0x1,
 357         RTL8366RB_LEDGROUP_LINK_ACT             = 0x2,
 358         RTL8366RB_LEDGROUP_SPD1000              = 0x3,
 359         RTL8366RB_LEDGROUP_SPD100               = 0x4,
 360         RTL8366RB_LEDGROUP_SPD10                = 0x5,
 361         RTL8366RB_LEDGROUP_SPD1000_ACT          = 0x6,
 362         RTL8366RB_LEDGROUP_SPD100_ACT           = 0x7,
 363         RTL8366RB_LEDGROUP_SPD10_ACT            = 0x8,
 364         RTL8366RB_LEDGROUP_SPD100_10_ACT        = 0x9,
 365         RTL8366RB_LEDGROUP_FIBER                = 0xa,
 366         RTL8366RB_LEDGROUP_AN_FAULT             = 0xb,
 367         RTL8366RB_LEDGROUP_LINK_RX              = 0xc,
 368         RTL8366RB_LEDGROUP_LINK_TX              = 0xd,
 369         RTL8366RB_LEDGROUP_MASTER               = 0xe,
 370         RTL8366RB_LEDGROUP_FORCE                = 0xf,
 371
 372         __RTL8366RB_LEDGROUP_MODE_MAX
 373 };
 374
 375 struct rtl8366rb_led {
 376         u8 port_num;
 377         u8 led_group;
 378         struct realtek_priv *priv;
 379         struct led_classdev cdev;
 380 };
 381
 382 /**
 383  * struct rtl8366rb - RTL8366RB-specific data
 384  * @max_mtu: per-port max MTU setting
 385  * @pvid_enabled: if PVID is set for respective port
 386  * @leds: per-port and per-ledgroup led info
 387  */
 388 struct rtl8366rb {
 389         unsigned int max_mtu[RTL8366RB_NUM_PORTS];
 390         bool pvid_enabled[RTL8366RB_NUM_PORTS];
 391         struct rtl8366rb_led leds[RTL8366RB_NUM_PORTS][RTL8366RB_NUM_LEDGROUPS];
 392 };
 393
 394 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
 395         { 0,  0, 4, "IfInOctets"                                },
 396         { 0,  4, 4, "EtherStatsOctets"                          },
 397         { 0,  8, 2, "EtherStatsUnderSizePkts"                   },
 398         { 0, 10, 2, "EtherFragments"                            },
 399         { 0, 12, 2, "EtherStatsPkts64Octets"                    },
 400         { 0, 14, 2, "EtherStatsPkts65to127Octets"               },
 401         { 0, 16, 2, "EtherStatsPkts128to255Octets"              },
 402         { 0, 18, 2, "EtherStatsPkts256to511Octets"              },
 403         { 0, 20, 2, "EtherStatsPkts512to1023Octets"             },
 404         { 0, 22, 2, "EtherStatsPkts1024to1518Octets"            },
 405         { 0, 24, 2, "EtherOversizeStats"                        },
 406         { 0, 26, 2, "EtherStatsJabbers"                         },
 407         { 0, 28, 2, "IfInUcastPkts"                             },
 408         { 0, 30, 2, "EtherStatsMulticastPkts"                   },
 409         { 0, 32, 2, "EtherStatsBroadcastPkts"                   },
 410         { 0, 34, 2, "EtherStatsDropEvents"                      },
 411         { 0, 36, 2, "Dot3StatsFCSErrors"                        },
 412         { 0, 38, 2, "Dot3StatsSymbolErrors"                     },
 413         { 0, 40, 2, "Dot3InPauseFrames"                         },
 414         { 0, 42, 2, "Dot3ControlInUnknownOpcodes"               },
 415         { 0, 44, 4, "IfOutOctets"                               },
 416         { 0, 48, 2, "Dot3StatsSingleCollisionFrames"            },
 417         { 0, 50, 2, "Dot3StatMultipleCollisionFrames"           },
 418         { 0, 52, 2, "Dot3sDeferredTransmissions"                },
 419         { 0, 54, 2, "Dot3StatsLateCollisions"                   },
 420         { 0, 56, 2, "EtherStatsCollisions"                      },
 421         { 0, 58, 2, "Dot3StatsExcessiveCollisions"              },
 422         { 0, 60, 2, "Dot3OutPauseFrames"                        },
 423         { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"        },
 424         { 0, 64, 2, "Dot1dTpPortInDiscards"                     },
 425         { 0, 66, 2, "IfOutUcastPkts"                            },
 426         { 0, 68, 2, "IfOutMulticastPkts"                        },
 427         { 0, 70, 2, "IfOutBroadcastPkts"                        },
 428 };
 429
 430 static int rtl8366rb_get_mib_counter(struct realtek_priv *priv,
 431                                      int port,
 432                                      struct rtl8366_mib_counter *mib,
 433                                      u64 *mibvalue)
 434 {
 435         u32 addr, val;
 436         int ret;
 437         int i;
 438
 439         addr = RTL8366RB_MIB_COUNTER_BASE +
 440                 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
 441                 mib->offset;
 442
 443         /* Writing access counter address first
 444          * then ASIC will prepare 64bits counter wait for being retrived
 445          */
 446         ret = regmap_write(priv->map, addr, 0); /* Write whatever */
 447         if (ret)
 448                 return ret;
 449
 450         /* Read MIB control register */
 451         ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);
 452         if (ret)
 453                 return -EIO;
 454
 455         if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
 456                 return -EBUSY;
 457
 458         if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
 459                 return -EIO;
 460
 461         /* Read each individual MIB 16 bits at the time */
 462         *mibvalue = 0;
 463         for (i = mib->length; i > 0; i--) {
 464                 ret = regmap_read(priv->map, addr + (i - 1), &val);
 465                 if (ret)
 466                         return ret;
 467                 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
 468         }
 469         return 0;
 470 }
 471
 472 static u32 rtl8366rb_get_irqmask(struct irq_data *d)
 473 {
 474         int line = irqd_to_hwirq(d);
 475         u32 val;
 476
 477         /* For line interrupts we combine link down in bits
 478          * 6..11 with link up in bits 0..5 into one interrupt.
 479          */
 480         if (line < 12)
 481                 val = BIT(line) | BIT(line + 6);
 482         else
 483                 val = BIT(line);
 484         return val;
 485 }
 486
 487 static void rtl8366rb_mask_irq(struct irq_data *d)
 488 {
 489         struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
 490         int ret;
 491
 492         ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
 493                                  rtl8366rb_get_irqmask(d), 0);
 494         if (ret)
 495                 dev_err(priv->dev, "could not mask IRQ\n");
 496 }
 497
 498 static void rtl8366rb_unmask_irq(struct irq_data *d)
 499 {
 500         struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
 501         int ret;
 502
 503         ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
 504                                  rtl8366rb_get_irqmask(d),
 505                                  rtl8366rb_get_irqmask(d));
 506         if (ret)
 507                 dev_err(priv->dev, "could not unmask IRQ\n");
 508 }
 509
 510 static irqreturn_t rtl8366rb_irq(int irq, void *data)
 511 {
 512         struct realtek_priv *priv = data;
 513         u32 stat;
 514         int ret;
 515
 516         /* This clears the IRQ status register */
 517         ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
 518                           &stat);
 519         if (ret) {
 520                 dev_err(priv->dev, "can't read interrupt status\n");
 521                 return IRQ_NONE;
 522         }
 523         stat &= RTL8366RB_INTERRUPT_VALID;
 524         if (!stat)
 525                 return IRQ_NONE;
 526         while (stat) {
 527                 int line = __ffs(stat);
 528                 int child_irq;
 529
 530                 stat &= ~BIT(line);
 531                 /* For line interrupts we combine link down in bits
 532                  * 6..11 with link up in bits 0..5 into one interrupt.
 533                  */
 534                 if (line < 12 && line > 5)
 535                         line -= 5;
 536                 child_irq = irq_find_mapping(priv->irqdomain, line);
 537                 handle_nested_irq(child_irq);
 538         }
 539         return IRQ_HANDLED;
 540 }
 541
 542 static struct irq_chip rtl8366rb_irq_chip = {
 543         .name = "RTL8366RB",
 544         .irq_mask = rtl8366rb_mask_irq,
 545         .irq_unmask = rtl8366rb_unmask_irq,
 546 };
 547
 548 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
 549                              irq_hw_number_t hwirq)
 550 {
 551         irq_set_chip_data(irq, domain->host_data);
 552         irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
 553         irq_set_nested_thread(irq, 1);
 554         irq_set_noprobe(irq);
 555
 556         return 0;
 557 }
 558
 559 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
 560 {
 561         irq_set_nested_thread(irq, 0);
 562         irq_set_chip_and_handler(irq, NULL, NULL);
 563         irq_set_chip_data(irq, NULL);
 564 }
 565
 566 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
 567         .map = rtl8366rb_irq_map,
 568         .unmap = rtl8366rb_irq_unmap,
 569         .xlate  = irq_domain_xlate_onecell,
 570 };
 571
 572 static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv)
 573 {
 574         struct device_node *intc;
 575         unsigned long irq_trig;
 576         int irq;
 577         int ret;
 578         u32 val;
 579         int i;
 580
 581         intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
 582         if (!intc) {
 583                 dev_err(priv->dev, "missing child interrupt-controller node\n");
 584                 return -EINVAL;
 585         }
 586         /* RB8366RB IRQs cascade off this one */
 587         irq = of_irq_get(intc, 0);
 588         if (irq <= 0) {
 589                 dev_err(priv->dev, "failed to get parent IRQ\n");
 590                 ret = irq ? irq : -EINVAL;
 591                 goto out_put_node;
 592         }
 593
 594         /* This clears the IRQ status register */
 595         ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
 596                           &val);
 597         if (ret) {
 598                 dev_err(priv->dev, "can't read interrupt status\n");
 599                 goto out_put_node;
 600         }
 601
 602         /* Fetch IRQ edge information from the descriptor */
 603         irq_trig = irq_get_trigger_type(irq);
 604         switch (irq_trig) {
 605         case IRQF_TRIGGER_RISING:
 606         case IRQF_TRIGGER_HIGH:
 607                 dev_info(priv->dev, "active high/rising IRQ\n");
 608                 val = 0;
 609                 break;
 610         case IRQF_TRIGGER_FALLING:
 611         case IRQF_TRIGGER_LOW:
 612                 dev_info(priv->dev, "active low/falling IRQ\n");
 613                 val = RTL8366RB_INTERRUPT_POLARITY;
 614                 break;
 615         }
 616         ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,
 617                                  RTL8366RB_INTERRUPT_POLARITY,
 618                                  val);
 619         if (ret) {
 620                 dev_err(priv->dev, "could not configure IRQ polarity\n");
 621                 goto out_put_node;
 622         }
 623
 624         ret = devm_request_threaded_irq(priv->dev, irq, NULL,
 625                                         rtl8366rb_irq, IRQF_ONESHOT,
 626                                         "RTL8366RB", priv);
 627         if (ret) {
 628                 dev_err(priv->dev, "unable to request irq: %d\n", ret);
 629                 goto out_put_node;
 630         }
 631         priv->irqdomain = irq_domain_add_linear(intc,
 632                                                 RTL8366RB_NUM_INTERRUPT,
 633                                                 &rtl8366rb_irqdomain_ops,
 634                                                 priv);
 635         if (!priv->irqdomain) {
 636                 dev_err(priv->dev, "failed to create IRQ domain\n");
 637                 ret = -EINVAL;
 638                 goto out_put_node;
 639         }
 640         for (i = 0; i < priv->num_ports; i++)
 641                 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq);
 642
 643 out_put_node:
 644         of_node_put(intc);
 645         return ret;
 646 }
 647
 648 static int rtl8366rb_set_addr(struct realtek_priv *priv)
 649 {
 650         u8 addr[ETH_ALEN];
 651         u16 val;
 652         int ret;
 653
 654         eth_random_addr(addr);
 655
 656         dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
 657                  addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
 658         val = addr[0] << 8 | addr[1];
 659         ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);
 660         if (ret)
 661                 return ret;
 662         val = addr[2] << 8 | addr[3];
 663         ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);
 664         if (ret)
 665                 return ret;
 666         val = addr[4] << 8 | addr[5];
 667         ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);
 668         if (ret)
 669                 return ret;
 670
 671         return 0;
 672 }
 673
 674 /* Found in a vendor driver */
 675
 676 /* Struct for handling the jam tables' entries */
 677 struct rtl8366rb_jam_tbl_entry {
 678         u16 reg;
 679         u16 val;
 680 };
 681
 682 /* For the "version 0" early silicon, appear in most source releases */
 683 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {
 684         {0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},
 685         {0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},
 686         {0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},
 687         {0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},
 688         {0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},
 689         {0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},
 690         {0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},
 691         {0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},
 692         {0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},
 693         {0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},
 694         {0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},
 695         {0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},
 696         {0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},
 697         {0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},
 698         {0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},
 699         {0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},
 700         {0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},
 701         {0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},
 702         {0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},
 703         {0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},
 704         {0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},
 705         {0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},
 706         {0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},
 707         {0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},
 708         {0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},
 709         {0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},
 710         {0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},
 711         {0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},
 712         {0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},
 713 };
 714
 715 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
 716 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {
 717         {0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},
 718         {0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
 719         {0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},
 720         {0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},
 721         {0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},
 722         {0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},
 723         {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},
 724         {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},
 725         {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},
 726         {0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},
 727         {0xBE79, 0x3C3C}, {0xBE00, 0x1340},
 728 };
 729
 730 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
 731 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {
 732         {0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
 733         {0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},
 734         {0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},
 735         {0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},
 736         {0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},
 737         {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
 738         {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},
 739         {0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
 740         {0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},
 741         {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},
 742         {0xBE00, 0x1340}, {0x0F51, 0x0010},
 743 };
 744
 745 /* Appears in a DDWRT code dump */
 746 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {
 747         {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
 748         {0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
 749         {0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},
 750         {0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},
 751         {0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},
 752         {0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},
 753         {0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},
 754         {0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},
 755         {0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},
 756         {0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},
 757         {0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},
 758         {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
 759         {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},
 760         {0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
 761         {0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},
 762         {0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},
 763         {0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},
 764 };
 765
 766 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
 767 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {
 768         {0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},
 769         {0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},
 770         {0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},
 771         {0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},
 772         {0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},
 773         {0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},
 774         {0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},
 775         {0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},
 776         {0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},
 777 };
 778
 779 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
 780 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {
 781         {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},
 782         {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},
 783         {0x0401, 0x0000}, {0x0431, 0x0960},
 784 };
 785
 786 /* This jam table activates "green ethernet", which means low power mode
 787  * and is claimed to detect the cable length and not use more power than
 788  * necessary, and the ports should enter power saving mode 10 seconds after
 789  * a cable is disconnected. Seems to always be the same.
 790  */
 791 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {
 792         {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
 793         {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
 794         {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
 795 };
 796
 797 /* Function that jams the tables in the proper registers */
 798 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,
 799                                int jam_size, struct realtek_priv *priv,
 800                                bool write_dbg)
 801 {
 802         u32 val;
 803         int ret;
 804         int i;
 805
 806         for (i = 0; i < jam_size; i++) {
 807                 if ((jam_table[i].reg & 0xBE00) == 0xBE00) {
 808                         ret = regmap_read(priv->map,
 809                                           RTL8366RB_PHY_ACCESS_BUSY_REG,
 810                                           &val);
 811                         if (ret)
 812                                 return ret;
 813                         if (!(val & RTL8366RB_PHY_INT_BUSY)) {
 814                                 ret = regmap_write(priv->map,
 815                                                    RTL8366RB_PHY_ACCESS_CTRL_REG,
 816                                                    RTL8366RB_PHY_CTRL_WRITE);
 817                                 if (ret)
 818                                         return ret;
 819                         }
 820                 }
 821                 if (write_dbg)
 822                         dev_dbg(priv->dev, "jam %04x into register %04x\n",
 823                                 jam_table[i].val,
 824                                 jam_table[i].reg);
 825                 ret = regmap_write(priv->map,
 826                                    jam_table[i].reg,
 827                                    jam_table[i].val);
 828                 if (ret)
 829                         return ret;
 830         }
 831         return 0;
 832 }
 833
 834 static int rb8366rb_set_ledgroup_mode(struct realtek_priv *priv,
 835                                       u8 led_group,
 836                                       enum rtl8366_ledgroup_mode mode)
 837 {
 838         int ret;
 839         u32 val;
 840
 841         val = mode << RTL8366RB_LED_CTRL_OFFSET(led_group);
 842
 843         ret = regmap_update_bits(priv->map,
 844                                  RTL8366RB_LED_CTRL_REG,
 845                                  RTL8366RB_LED_CTRL_MASK(led_group),
 846                                  val);
 847         if (ret)
 848                 return ret;
 849
 850         return 0;
 851 }
 852
 853 static inline u32 rtl8366rb_led_group_port_mask(u8 led_group, u8 port)
 854 {
 855         switch (led_group) {
 856         case 0:
 857                 return FIELD_PREP(RTL8366RB_LED_0_X_CTRL_MASK, BIT(port));
 858         case 1:
 859                 return FIELD_PREP(RTL8366RB_LED_0_X_CTRL_MASK, BIT(port));
 860         case 2:
 861                 return FIELD_PREP(RTL8366RB_LED_0_X_CTRL_MASK, BIT(port));
 862         case 3:
 863                 return FIELD_PREP(RTL8366RB_LED_0_X_CTRL_MASK, BIT(port));
 864         default:
 865                 return 0;
 866         }
 867 }
 868
 869 static int rb8366rb_get_port_led(struct rtl8366rb_led *led)
 870 {
 871         struct realtek_priv *priv = led->priv;
 872         u8 led_group = led->led_group;
 873         u8 port_num = led->port_num;
 874         int ret;
 875         u32 val;
 876
 877         ret = regmap_read(priv->map, RTL8366RB_LED_X_X_CTRL_REG(led_group),
 878                           &val);
 879         if (ret) {
 880                 dev_err(priv->dev, "error reading LED on port %d group %d\n",
 881                         led_group, port_num);
 882                 return ret;
 883         }
 884
 885         return !!(val & rtl8366rb_led_group_port_mask(led_group, port_num));
 886 }
 887
 888 static int rb8366rb_set_port_led(struct rtl8366rb_led *led, bool enable)
 889 {
 890         struct realtek_priv *priv = led->priv;
 891         u8 led_group = led->led_group;
 892         u8 port_num = led->port_num;
 893         int ret;
 894
 895         ret = regmap_update_bits(priv->map,
 896                                  RTL8366RB_LED_X_X_CTRL_REG(led_group),
 897                                  rtl8366rb_led_group_port_mask(led_group,
 898                                                                port_num),
 899                                  enable ? 0xffff : 0);
 900         if (ret) {
 901                 dev_err(priv->dev, "error updating LED on port %d group %d\n",
 902                         led_group, port_num);
 903                 return ret;
 904         }
 905
 906         /* Change the LED group to manual controlled LEDs if required */
 907         ret = rb8366rb_set_ledgroup_mode(priv, led_group,
 908                                          RTL8366RB_LEDGROUP_FORCE);
 909
 910         if (ret) {
 911                 dev_err(priv->dev, "error updating LED GROUP group %d\n",
 912                         led_group);
 913                 return ret;
 914         }
 915
 916         return 0;
 917 }
 918
 919 static int
 920 rtl8366rb_cled_brightness_set_blocking(struct led_classdev *ldev,
 921                                        enum led_brightness brightness)
 922 {
 923         struct rtl8366rb_led *led = container_of(ldev, struct rtl8366rb_led,
 924                                                  cdev);
 925
 926         return rb8366rb_set_port_led(led, brightness == LED_ON);
 927 }
 928
 929 static int rtl8366rb_setup_led(struct realtek_priv *priv, struct dsa_port *dp,
 930                                struct fwnode_handle *led_fwnode)
 931 {
 932         struct rtl8366rb *rb = priv->chip_data;
 933         struct led_init_data init_data = { };
 934         enum led_default_state state;
 935         struct rtl8366rb_led *led;
 936         u32 led_group;
 937         int ret;
 938
 939         ret = fwnode_property_read_u32(led_fwnode, "reg", &led_group);
 940         if (ret)
 941                 return ret;
 942
 943         if (led_group >= RTL8366RB_NUM_LEDGROUPS) {
 944                 dev_warn(priv->dev, "Invalid LED reg %d defined for port %d",
 945                          led_group, dp->index);
 946                 return -EINVAL;
 947         }
 948
 949         led = &rb->leds[dp->index][led_group];
 950         led->port_num = dp->index;
 951         led->led_group = led_group;
 952         led->priv = priv;
 953
 954         state = led_init_default_state_get(led_fwnode);
 955         switch (state) {
 956         case LEDS_DEFSTATE_ON:
 957                 led->cdev.brightness = 1;
 958                 rb8366rb_set_port_led(led, 1);
 959                 break;
 960         case LEDS_DEFSTATE_KEEP:
 961                 led->cdev.brightness =
 962                         rb8366rb_get_port_led(led);
 963                 break;
 964         case LEDS_DEFSTATE_OFF:
 965         default:
 966                 led->cdev.brightness = 0;
 967                 rb8366rb_set_port_led(led, 0);
 968         }
 969
 970         led->cdev.max_brightness = 1;
 971         led->cdev.brightness_set_blocking =
 972                 rtl8366rb_cled_brightness_set_blocking;
 973         init_data.fwnode = led_fwnode;
 974         init_data.devname_mandatory = true;
 975
 976         init_data.devicename = kasprintf(GFP_KERNEL, "Realtek-%d:0%d:%d",
 977                                          dp->ds->index, dp->index, led_group);
 978         if (!init_data.devicename)
 979                 return -ENOMEM;
 980
 981         ret = devm_led_classdev_register_ext(priv->dev, &led->cdev, &init_data);
 982         if (ret) {
 983                 dev_warn(priv->dev, "Failed to init LED %d for port %d",
 984                          led_group, dp->index);
 985                 return ret;
 986         }
 987
 988         return 0;
 989 }
 990
 991 static int rtl8366rb_setup_all_leds_off(struct realtek_priv *priv)
 992 {
 993         int ret = 0;
 994         int i;
 995
 996         regmap_update_bits(priv->map,
 997                            RTL8366RB_INTERRUPT_CONTROL_REG,
 998                            RTL8366RB_P4_RGMII_LED,
 999                            0);
1000
1001         for (i = 0; i < RTL8366RB_NUM_LEDGROUPS; i++) {
1002                 ret = rb8366rb_set_ledgroup_mode(priv, i,
1003                                                  RTL8366RB_LEDGROUP_OFF);
1004                 if (ret)
1005                         return ret;
1006         }
1007
1008         return ret;
1009 }
1010
1011 static int rtl8366rb_setup_leds(struct realtek_priv *priv)
1012 {
1013         struct dsa_switch *ds = &priv->ds;
1014         struct device_node *leds_np;
1015         struct dsa_port *dp;
1016         int ret = 0;
1017
1018         dsa_switch_for_each_port(dp, ds) {
1019                 if (!dp->dn)
1020                         continue;
1021
1022                 leds_np = of_get_child_by_name(dp->dn, "leds");
1023                 if (!leds_np) {
1024                         dev_dbg(priv->dev, "No leds defined for port %d",
1025                                 dp->index);
1026                         continue;
1027                 }
1028
1029                 for_each_child_of_node_scoped(leds_np, led_np) {
1030                         ret = rtl8366rb_setup_led(priv, dp,
1031                                                   of_fwnode_handle(led_np));
1032                         if (ret)
1033                                 break;
1034                 }
1035
1036                 of_node_put(leds_np);
1037                 if (ret)
1038                         return ret;
1039         }
1040         return 0;
1041 }
1042
1043 static int rtl8366rb_setup(struct dsa_switch *ds)
1044 {
1045         struct realtek_priv *priv = ds->priv;
1046         const struct rtl8366rb_jam_tbl_entry *jam_table;
1047         struct rtl8366rb *rb;
1048         u32 chip_ver = 0;
1049         u32 chip_id = 0;
1050         int jam_size;
1051         int ret;
1052         int i;
1053
1054         rb = priv->chip_data;
1055
1056         ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id);
1057         if (ret) {
1058                 dev_err(priv->dev, "unable to read chip id\n");
1059                 return ret;
1060         }
1061
1062         switch (chip_id) {
1063         case RTL8366RB_CHIP_ID_8366:
1064                 break;
1065         default:
1066                 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);
1067                 return -ENODEV;
1068         }
1069
1070         ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
1071                           &chip_ver);
1072         if (ret) {
1073                 dev_err(priv->dev, "unable to read chip version\n");
1074                 return ret;
1075         }
1076
1077         dev_info(priv->dev, "RTL%04x ver %u chip found\n",
1078                  chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1079
1080         /* Do the init dance using the right jam table */
1081         switch (chip_ver) {
1082         case 0:
1083                 jam_table = rtl8366rb_init_jam_ver_0;
1084                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
1085                 break;
1086         case 1:
1087                 jam_table = rtl8366rb_init_jam_ver_1;
1088                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
1089                 break;
1090         case 2:
1091                 jam_table = rtl8366rb_init_jam_ver_2;
1092                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
1093                 break;
1094         default:
1095                 jam_table = rtl8366rb_init_jam_ver_3;
1096                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
1097                 break;
1098         }
1099
1100         /* Special jam tables for special routers
1101          * TODO: are these necessary? Maintainers, please test
1102          * without them, using just the off-the-shelf tables.
1103          */
1104         if (of_machine_is_compatible("belkin,f5d8235-v1")) {
1105                 jam_table = rtl8366rb_init_jam_f5d8235;
1106                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
1107         }
1108         if (of_machine_is_compatible("netgear,dgn3500") ||
1109             of_machine_is_compatible("netgear,dgn3500b")) {
1110                 jam_table = rtl8366rb_init_jam_dgn3500;
1111                 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
1112         }
1113
1114         ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true);
1115         if (ret)
1116                 return ret;
1117
1118         /* Isolate all user ports so they can only send packets to itself and the CPU port */
1119         for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1120                 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i),
1121                                    RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) |
1122                                    RTL8366RB_PORT_ISO_EN);
1123                 if (ret)
1124                         return ret;
1125         }
1126         /* CPU port can send packets to all ports */
1127         ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),
1128                            RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) |
1129                            RTL8366RB_PORT_ISO_EN);
1130         if (ret)
1131                 return ret;
1132
1133         /* Set up the "green ethernet" feature */
1134         ret = rtl8366rb_jam_table(rtl8366rb_green_jam,
1135                                   ARRAY_SIZE(rtl8366rb_green_jam), priv, false);
1136         if (ret)
1137                 return ret;
1138
1139         ret = regmap_write(priv->map,
1140                            RTL8366RB_GREEN_FEATURE_REG,
1141                            (chip_ver == 1) ? 0x0007 : 0x0003);
1142         if (ret)
1143                 return ret;
1144
1145         /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
1146         ret = regmap_write(priv->map, 0x0c, 0x240);
1147         if (ret)
1148                 return ret;
1149         ret = regmap_write(priv->map, 0x0d, 0x240);
1150         if (ret)
1151                 return ret;
1152
1153         /* Set some random MAC address */
1154         ret = rtl8366rb_set_addr(priv);
1155         if (ret)
1156                 return ret;
1157
1158         /* Enable CPU port with custom DSA tag 8899.
1159          *
1160          * If you set RTL8366RB_CPU_NO_TAG (bit 15) in this register
1161          * the custom tag is turned off.
1162          */
1163         ret = regmap_update_bits(priv->map, RTL8366RB_CPU_CTRL_REG,
1164                                  0xFFFF,
1165                                  BIT(priv->cpu_port));
1166         if (ret)
1167                 return ret;
1168
1169         /* Make sure we default-enable the fixed CPU port */
1170         ret = regmap_update_bits(priv->map, RTL8366RB_PECR,
1171                                  BIT(priv->cpu_port),
1172                                  0);
1173         if (ret)
1174                 return ret;
1175
1176         /* Set default maximum packet length to 1536 bytes */
1177         ret = regmap_update_bits(priv->map, RTL8366RB_SGCR,
1178                                  RTL8366RB_SGCR_MAX_LENGTH_MASK,
1179                                  RTL8366RB_SGCR_MAX_LENGTH_1536);
1180         if (ret)
1181                 return ret;
1182         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1183                 if (i == priv->cpu_port)
1184                         /* CPU port need to also accept the tag */
1185                         rb->max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE;
1186                 else
1187                         rb->max_mtu[i] = ETH_DATA_LEN;
1188         }
1189
1190         /* Disable learning for all ports */
1191         ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
1192                            RTL8366RB_PORT_ALL);
1193         if (ret)
1194                 return ret;
1195
1196         /* Enable auto ageing for all ports */
1197         ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0);
1198         if (ret)
1199                 return ret;
1200
1201         /* Port 4 setup: this enables Port 4, usually the WAN port,
1202          * common PHY IO mode is apparently mode 0, and this is not what
1203          * the port is initialized to. There is no explanation of the
1204          * IO modes in the Realtek source code, if your WAN port is
1205          * connected to something exotic such as fiber, then this might
1206          * be worth experimenting with.
1207          */
1208         ret = regmap_update_bits(priv->map, RTL8366RB_PMC0,
1209                                  RTL8366RB_PMC0_P4_IOMODE_MASK,
1210                                  0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
1211         if (ret)
1212                 return ret;
1213
1214         /* Accept all packets by default, we enable filtering on-demand */
1215         ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1216                            0);
1217         if (ret)
1218                 return ret;
1219         ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1220                            0);
1221         if (ret)
1222                 return ret;
1223
1224         /* Don't drop packets whose DA has not been learned */
1225         ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2,
1226                                  RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
1227         if (ret)
1228                 return ret;
1229
1230         /* Set blinking, used by all LED groups using HW triggers.
1231          * TODO: make this configurable
1232          */
1233         ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG,
1234                                  RTL8366RB_LED_BLINKRATE_MASK,
1235                                  RTL8366RB_LED_BLINKRATE_56MS);
1236         if (ret)
1237                 return ret;
1238
1239         /* Set up LED activity:
1240          * Each port has 4 LEDs on fixed groups. Each group shares the same
1241          * hardware trigger across all ports. LEDs can only be indiviually
1242          * controlled setting the LED group to fixed mode and using the driver
1243          * to toggle them LEDs on/off.
1244          */
1245         if (priv->leds_disabled) {
1246                 ret = rtl8366rb_setup_all_leds_off(priv);
1247                 if (ret)
1248                         return ret;
1249         } else {
1250                 ret = rtl8366rb_setup_leds(priv);
1251                 if (ret)
1252                         return ret;
1253         }
1254
1255         ret = rtl8366_reset_vlan(priv);
1256         if (ret)
1257                 return ret;
1258
1259         ret = rtl8366rb_setup_cascaded_irq(priv);
1260         if (ret)
1261                 dev_info(priv->dev, "no interrupt support\n");
1262
1263         ret = rtl83xx_setup_user_mdio(ds);
1264         if (ret) {
1265                 dev_err(priv->dev, "could not set up MDIO bus\n");
1266                 return -ENODEV;
1267         }
1268
1269         return 0;
1270 }
1271
1272 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
1273                                                       int port,
1274                                                       enum dsa_tag_protocol mp)
1275 {
1276         /* This switch uses the 4 byte protocol A Realtek DSA tag */
1277         return DSA_TAG_PROTO_RTL4_A;
1278 }
1279
1280 static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,
1281                                        struct phylink_config *config)
1282 {
1283         unsigned long *interfaces = config->supported_interfaces;
1284         struct realtek_priv *priv = ds->priv;
1285
1286         if (port == priv->cpu_port) {
1287                 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
1288                 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1289                 /* REVMII only supports 100M FD */
1290                 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
1291                 /* RGMII only supports 1G FD */
1292                 phy_interface_set_rgmii(interfaces);
1293
1294                 config->mac_capabilities = MAC_1000 | MAC_100 |
1295                                            MAC_SYM_PAUSE;
1296         } else {
1297                 /* RSGMII port, but we don't have that, and we don't
1298                  * specify in DT, so phylib uses the default of GMII
1299                  */
1300                 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1301                 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |
1302                                            MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
1303         }
1304 }
1305
1306 static void
1307 rtl8366rb_mac_config(struct phylink_config *config, unsigned int mode,
1308                      const struct phylink_link_state *state)
1309 {
1310 }
1311
1312 static void
1313 rtl8366rb_mac_link_up(struct phylink_config *config, struct phy_device *phydev,
1314                       unsigned int mode, phy_interface_t interface,
1315                       int speed, int duplex, bool tx_pause, bool rx_pause)
1316 {
1317         struct dsa_port *dp = dsa_phylink_to_port(config);
1318         struct realtek_priv *priv = dp->ds->priv;
1319         int port = dp->index;
1320         unsigned int val;
1321         int ret;
1322
1323         /* Allow forcing the mode on the fixed CPU port, no autonegotiation.
1324          * We assume autonegotiation works on the PHY-facing ports.
1325          */
1326         if (port != priv->cpu_port)
1327                 return;
1328
1329         dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1330
1331         ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1332                                  BIT(port), BIT(port));
1333         if (ret) {
1334                 dev_err(priv->dev, "failed to force CPU port\n");
1335                 return;
1336         }
1337
1338         /* Conjure port config */
1339         switch (speed) {
1340         case SPEED_10:
1341                 val = RTL8366RB_PAACR_SPEED_10M;
1342                 break;
1343         case SPEED_100:
1344                 val = RTL8366RB_PAACR_SPEED_100M;
1345                 break;
1346         case SPEED_1000:
1347                 val = RTL8366RB_PAACR_SPEED_1000M;
1348                 break;
1349         default:
1350                 val = RTL8366RB_PAACR_SPEED_1000M;
1351                 break;
1352         }
1353
1354         if (duplex == DUPLEX_FULL)
1355                 val |= RTL8366RB_PAACR_FULL_DUPLEX;
1356
1357         if (tx_pause)
1358                 val |=  RTL8366RB_PAACR_TX_PAUSE;
1359
1360         if (rx_pause)
1361                 val |= RTL8366RB_PAACR_RX_PAUSE;
1362
1363         val |= RTL8366RB_PAACR_LINK_UP;
1364
1365         ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,
1366                                  0xFF00U,
1367                                  val << 8);
1368         if (ret) {
1369                 dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1370                 return;
1371         }
1372
1373         dev_dbg(priv->dev, "set PAACR to %04x\n", val);
1374
1375         /* Enable the CPU port */
1376         ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1377                                  0);
1378         if (ret) {
1379                 dev_err(priv->dev, "failed to enable the CPU port\n");
1380                 return;
1381         }
1382 }
1383
1384 static void
1385 rtl8366rb_mac_link_down(struct phylink_config *config, unsigned int mode,
1386                         phy_interface_t interface)
1387 {
1388         struct dsa_port *dp = dsa_phylink_to_port(config);
1389         struct realtek_priv *priv = dp->ds->priv;
1390         int port = dp->index;
1391         int ret;
1392
1393         if (port != priv->cpu_port)
1394                 return;
1395
1396         dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1397
1398         /* Disable the CPU port */
1399         ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1400                                  BIT(port));
1401         if (ret) {
1402                 dev_err(priv->dev, "failed to disable the CPU port\n");
1403                 return;
1404         }
1405 }
1406
1407 static int
1408 rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1409                       struct phy_device *phy)
1410 {
1411         struct realtek_priv *priv = ds->priv;
1412         int ret;
1413
1414         dev_dbg(priv->dev, "enable port %d\n", port);
1415         ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1416                                  0);
1417         if (ret)
1418                 return ret;
1419
1420         return 0;
1421 }
1422
1423 static void
1424 rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1425 {
1426         struct realtek_priv *priv = ds->priv;
1427         int ret;
1428
1429         dev_dbg(priv->dev, "disable port %d\n", port);
1430         ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1431                                  BIT(port));
1432         if (ret)
1433                 return;
1434 }
1435
1436 static int
1437 rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,
1438                            struct dsa_bridge bridge,
1439                            bool *tx_fwd_offload,
1440                            struct netlink_ext_ack *extack)
1441 {
1442         struct realtek_priv *priv = ds->priv;
1443         unsigned int port_bitmap = 0;
1444         int ret, i;
1445
1446         /* Loop over all other ports than the current one */
1447         for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1448                 /* Current port handled last */
1449                 if (i == port)
1450                         continue;
1451                 /* Not on this bridge */
1452                 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1453                         continue;
1454                 /* Join this port to each other port on the bridge */
1455                 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1456                                          RTL8366RB_PORT_ISO_PORTS(BIT(port)),
1457                                          RTL8366RB_PORT_ISO_PORTS(BIT(port)));
1458                 if (ret)
1459                         dev_err(priv->dev, "failed to join port %d\n", port);
1460
1461                 port_bitmap |= BIT(i);
1462         }
1463
1464         /* Set the bits for the ports we can access */
1465         return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1466                                   RTL8366RB_PORT_ISO_PORTS(port_bitmap),
1467                                   RTL8366RB_PORT_ISO_PORTS(port_bitmap));
1468 }
1469
1470 static void
1471 rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,
1472                             struct dsa_bridge bridge)
1473 {
1474         struct realtek_priv *priv = ds->priv;
1475         unsigned int port_bitmap = 0;
1476         int ret, i;
1477
1478         /* Loop over all other ports than this one */
1479         for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1480                 /* Current port handled last */
1481                 if (i == port)
1482                         continue;
1483                 /* Not on this bridge */
1484                 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1485                         continue;
1486                 /* Remove this port from any other port on the bridge */
1487                 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1488                                          RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0);
1489                 if (ret)
1490                         dev_err(priv->dev, "failed to leave port %d\n", port);
1491
1492                 port_bitmap |= BIT(i);
1493         }
1494
1495         /* Clear the bits for the ports we can not access, leave ourselves */
1496         regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1497                            RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0);
1498 }
1499
1500 /**
1501  * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1502  * @priv: SMI state container
1503  * @port: the port to drop untagged and C-tagged frames on
1504  * @drop: whether to drop or pass untagged and C-tagged frames
1505  *
1506  * Return: zero for success, a negative number on error.
1507  */
1508 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)
1509 {
1510         return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1511                                   RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),
1512                                   drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);
1513 }
1514
1515 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,
1516                                     bool vlan_filtering,
1517                                     struct netlink_ext_ack *extack)
1518 {
1519         struct realtek_priv *priv = ds->priv;
1520         struct rtl8366rb *rb;
1521         int ret;
1522
1523         rb = priv->chip_data;
1524
1525         dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1526                 str_enable_disable(vlan_filtering));
1527
1528         /* If the port is not in the member set, the frame will be dropped */
1529         ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1530                                  BIT(port), vlan_filtering ? BIT(port) : 0);
1531         if (ret)
1532                 return ret;
1533
1534         /* If VLAN filtering is enabled and PVID is also enabled, we must
1535          * not drop any untagged or C-tagged frames. If we turn off VLAN
1536          * filtering on a port, we need to accept any frames.
1537          */
1538         if (vlan_filtering)
1539                 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);
1540         else
1541                 ret = rtl8366rb_drop_untagged(priv, port, false);
1542
1543         return ret;
1544 }
1545
1546 static int
1547 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1548                                 struct switchdev_brport_flags flags,
1549                                 struct netlink_ext_ack *extack)
1550 {
1551         /* We support enabling/disabling learning */
1552         if (flags.mask & ~(BR_LEARNING))
1553                 return -EINVAL;
1554
1555         return 0;
1556 }
1557
1558 static int
1559 rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,
1560                             struct switchdev_brport_flags flags,
1561                             struct netlink_ext_ack *extack)
1562 {
1563         struct realtek_priv *priv = ds->priv;
1564         int ret;
1565
1566         if (flags.mask & BR_LEARNING) {
1567                 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
1568                                          BIT(port),
1569                                          (flags.val & BR_LEARNING) ? 0 : BIT(port));
1570                 if (ret)
1571                         return ret;
1572         }
1573
1574         return 0;
1575 }
1576
1577 static void
1578 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1579 {
1580         struct realtek_priv *priv = ds->priv;
1581         u32 val;
1582         int i;
1583
1584         switch (state) {
1585         case BR_STATE_DISABLED:
1586                 val = RTL8366RB_STP_STATE_DISABLED;
1587                 break;
1588         case BR_STATE_BLOCKING:
1589         case BR_STATE_LISTENING:
1590                 val = RTL8366RB_STP_STATE_BLOCKING;
1591                 break;
1592         case BR_STATE_LEARNING:
1593                 val = RTL8366RB_STP_STATE_LEARNING;
1594                 break;
1595         case BR_STATE_FORWARDING:
1596                 val = RTL8366RB_STP_STATE_FORWARDING;
1597                 break;
1598         default:
1599                 dev_err(priv->dev, "unknown bridge state requested\n");
1600                 return;
1601         }
1602
1603         /* Set the same status for the port on all the FIDs */
1604         for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {
1605                 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i,
1606                                    RTL8366RB_STP_STATE_MASK(port),
1607                                    RTL8366RB_STP_STATE(port, val));
1608         }
1609 }
1610
1611 static void
1612 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
1613 {
1614         struct realtek_priv *priv = ds->priv;
1615
1616         /* This will age out any learned L2 entries */
1617         regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1618                            BIT(port), BIT(port));
1619         /* Restore the normal state of things */
1620         regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1621                            BIT(port), 0);
1622 }
1623
1624 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1625 {
1626         struct realtek_priv *priv = ds->priv;
1627         struct rtl8366rb *rb;
1628         unsigned int max_mtu;
1629         u32 len;
1630         int i;
1631
1632         /* Cache the per-port MTU setting */
1633         rb = priv->chip_data;
1634         rb->max_mtu[port] = new_mtu;
1635
1636         /* Roof out the MTU for the entire switch to the greatest
1637          * common denominator: the biggest set for any one port will
1638          * be the biggest MTU for the switch.
1639          */
1640         max_mtu = ETH_DATA_LEN;
1641         for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1642                 if (rb->max_mtu[i] > max_mtu)
1643                         max_mtu = rb->max_mtu[i];
1644         }
1645
1646         /* Translate to layer 2 size.
1647          * Add ethernet and (possible) VLAN headers, and checksum to the size.
1648          * For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.
1649          */
1650         max_mtu += VLAN_ETH_HLEN;
1651         max_mtu += ETH_FCS_LEN;
1652
1653         if (max_mtu <= 1522)
1654                 len = RTL8366RB_SGCR_MAX_LENGTH_1522;
1655         else if (max_mtu > 1522 && max_mtu <= 1536)
1656                 /* This will be the most common default if using VLAN and
1657                  * CPU tagging on a port as both VLAN and CPU tag will
1658                  * result in 1518 + 4 + 4 = 1526 bytes.
1659                  */
1660                 len = RTL8366RB_SGCR_MAX_LENGTH_1536;
1661         else if (max_mtu > 1536 && max_mtu <= 1552)
1662                 len = RTL8366RB_SGCR_MAX_LENGTH_1552;
1663         else
1664                 len = RTL8366RB_SGCR_MAX_LENGTH_16000;
1665
1666         return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1667                                   RTL8366RB_SGCR_MAX_LENGTH_MASK,
1668                                   len);
1669 }
1670
1671 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1672 {
1673         /* The max MTU is 16000 bytes, so we subtract the ethernet
1674          * headers with VLAN and checksum and arrive at
1675          * 16000 - 18 - 4 = 15978. This does not include the CPU tag
1676          * since that is added to the requested MTU by the DSA framework.
1677          */
1678         return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN;
1679 }
1680
1681 static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,
1682                                  struct rtl8366_vlan_4k *vlan4k)
1683 {
1684         u32 data[3];
1685         int ret;
1686         int i;
1687
1688         memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1689
1690         if (vid >= RTL8366RB_NUM_VIDS)
1691                 return -EINVAL;
1692
1693         /* write VID */
1694         ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1695                            vid & RTL8366RB_VLAN_VID_MASK);
1696         if (ret)
1697                 return ret;
1698
1699         /* write table access control word */
1700         ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1701                            RTL8366RB_TABLE_VLAN_READ_CTRL);
1702         if (ret)
1703                 return ret;
1704
1705         for (i = 0; i < 3; i++) {
1706                 ret = regmap_read(priv->map,
1707                                   RTL8366RB_VLAN_TABLE_READ_BASE + i,
1708                                   &data[i]);
1709                 if (ret)
1710                         return ret;
1711         }
1712
1713         vlan4k->vid = vid;
1714         vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1715                         RTL8366RB_VLAN_UNTAG_MASK;
1716         vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1717         vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1718
1719         return 0;
1720 }
1721
1722 static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv,
1723                                  const struct rtl8366_vlan_4k *vlan4k)
1724 {
1725         u32 data[3];
1726         int ret;
1727         int i;
1728
1729         if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1730             vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1731             vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1732             vlan4k->fid > RTL8366RB_FIDMAX)
1733                 return -EINVAL;
1734
1735         data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1736         data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1737                   ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1738                         RTL8366RB_VLAN_UNTAG_SHIFT);
1739         data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1740
1741         for (i = 0; i < 3; i++) {
1742                 ret = regmap_write(priv->map,
1743                                    RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1744                                    data[i]);
1745                 if (ret)
1746                         return ret;
1747         }
1748
1749         /* write table access control word */
1750         ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1751                            RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1752
1753         return ret;
1754 }
1755
1756 static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index,
1757                                  struct rtl8366_vlan_mc *vlanmc)
1758 {
1759         u32 data[3];
1760         int ret;
1761         int i;
1762
1763         memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1764
1765         if (index >= RTL8366RB_NUM_VLANS)
1766                 return -EINVAL;
1767
1768         for (i = 0; i < 3; i++) {
1769                 ret = regmap_read(priv->map,
1770                                   RTL8366RB_VLAN_MC_BASE(index) + i,
1771                                   &data[i]);
1772                 if (ret)
1773                         return ret;
1774         }
1775
1776         vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1777         vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1778                 RTL8366RB_VLAN_PRIORITY_MASK;
1779         vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1780                 RTL8366RB_VLAN_UNTAG_MASK;
1781         vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1782         vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1783
1784         return 0;
1785 }
1786
1787 static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index,
1788                                  const struct rtl8366_vlan_mc *vlanmc)
1789 {
1790         u32 data[3];
1791         int ret;
1792         int i;
1793
1794         if (index >= RTL8366RB_NUM_VLANS ||
1795             vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1796             vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1797             vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1798             vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1799             vlanmc->fid > RTL8366RB_FIDMAX)
1800                 return -EINVAL;
1801
1802         data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1803                   ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1804                         RTL8366RB_VLAN_PRIORITY_SHIFT);
1805         data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1806                   ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1807                         RTL8366RB_VLAN_UNTAG_SHIFT);
1808         data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1809
1810         for (i = 0; i < 3; i++) {
1811                 ret = regmap_write(priv->map,
1812                                    RTL8366RB_VLAN_MC_BASE(index) + i,
1813                                    data[i]);
1814                 if (ret)
1815                         return ret;
1816         }
1817
1818         return 0;
1819 }
1820
1821 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1822 {
1823         u32 data;
1824         int ret;
1825
1826         if (port >= priv->num_ports)
1827                 return -EINVAL;
1828
1829         ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1830                           &data);
1831         if (ret)
1832                 return ret;
1833
1834         *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1835                 RTL8366RB_PORT_VLAN_CTRL_MASK;
1836
1837         return 0;
1838 }
1839
1840 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)
1841 {
1842         struct dsa_switch *ds = &priv->ds;
1843         struct rtl8366rb *rb;
1844         bool pvid_enabled;
1845         int ret;
1846
1847         rb = priv->chip_data;
1848         pvid_enabled = !!index;
1849
1850         if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1851                 return -EINVAL;
1852
1853         ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1854                                  RTL8366RB_PORT_VLAN_CTRL_MASK <<
1855                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1856                                  (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1857                                         RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1858         if (ret)
1859                 return ret;
1860
1861         rb->pvid_enabled[port] = pvid_enabled;
1862
1863         /* If VLAN filtering is enabled and PVID is also enabled, we must
1864          * not drop any untagged or C-tagged frames. Make sure to update the
1865          * filtering setting.
1866          */
1867         if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1868                 ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled);
1869
1870         return ret;
1871 }
1872
1873 static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan)
1874 {
1875         unsigned int max = RTL8366RB_NUM_VLANS - 1;
1876
1877         if (priv->vlan4k_enabled)
1878                 max = RTL8366RB_NUM_VIDS - 1;
1879
1880         if (vlan > max)
1881                 return false;
1882
1883         return true;
1884 }
1885
1886 static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable)
1887 {
1888         dev_dbg(priv->dev, "%s VLAN\n", str_enable_disable(enable));
1889         return regmap_update_bits(priv->map,
1890                                   RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1891                                   enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1892 }
1893
1894 static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable)
1895 {
1896         dev_dbg(priv->dev, "%s VLAN 4k\n", str_enable_disable(enable));
1897         return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1898                                   RTL8366RB_SGCR_EN_VLAN_4KTB,
1899                                   enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1900 }
1901
1902 static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum)
1903 {
1904         u32 val;
1905         u32 reg;
1906         int ret;
1907
1908         if (phy > RTL8366RB_PHY_NO_MAX)
1909                 return -EINVAL;
1910
1911         rtl83xx_lock(priv);
1912
1913         ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1914                            RTL8366RB_PHY_CTRL_READ);
1915         if (ret)
1916                 goto out;
1917
1918         reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1919
1920         ret = regmap_write(priv->map_nolock, reg, 0);
1921         if (ret) {
1922                 dev_err(priv->dev,
1923                         "failed to write PHY%d reg %04x @ %04x, ret %d\n",
1924                         phy, regnum, reg, ret);
1925                 goto out;
1926         }
1927
1928         ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG,
1929                           &val);
1930         if (ret)
1931                 goto out;
1932
1933         ret = val;
1934
1935         dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1936                 phy, regnum, reg, val);
1937
1938 out:
1939         rtl83xx_unlock(priv);
1940
1941         return ret;
1942 }
1943
1944 static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum,
1945                                u16 val)
1946 {
1947         u32 reg;
1948         int ret;
1949
1950         if (phy > RTL8366RB_PHY_NO_MAX)
1951                 return -EINVAL;
1952
1953         rtl83xx_lock(priv);
1954
1955         ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1956                            RTL8366RB_PHY_CTRL_WRITE);
1957         if (ret)
1958                 goto out;
1959
1960         reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1961
1962         dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1963                 phy, regnum, reg, val);
1964
1965         ret = regmap_write(priv->map_nolock, reg, val);
1966         if (ret)
1967                 goto out;
1968
1969 out:
1970         rtl83xx_unlock(priv);
1971
1972         return ret;
1973 }
1974
1975 static int rtl8366rb_reset_chip(struct realtek_priv *priv)
1976 {
1977         int timeout = 10;
1978         u32 val;
1979         int ret;
1980
1981         priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,
1982                               RTL8366RB_CHIP_CTRL_RESET_HW);
1983         do {
1984                 usleep_range(20000, 25000);
1985                 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);
1986                 if (ret)
1987                         return ret;
1988
1989                 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1990                         break;
1991         } while (--timeout);
1992
1993         if (!timeout) {
1994                 dev_err(priv->dev, "timeout waiting for the switch to reset\n");
1995                 return -EIO;
1996         }
1997
1998         return 0;
1999 }
2000
2001 static int rtl8366rb_detect(struct realtek_priv *priv)
2002 {
2003         struct device *dev = priv->dev;
2004         int ret;
2005         u32 val;
2006
2007         /* Detect device */
2008         ret = regmap_read(priv->map, 0x5c, &val);
2009         if (ret) {
2010                 dev_err(dev, "can't get chip ID (%d)\n", ret);
2011                 return ret;
2012         }
2013
2014         switch (val) {
2015         case 0x6027:
2016                 dev_info(dev, "found an RTL8366S switch\n");
2017                 dev_err(dev, "this switch is not yet supported, submit patches!\n");
2018                 return -ENODEV;
2019         case 0x5937:
2020                 dev_info(dev, "found an RTL8366RB switch\n");
2021                 priv->cpu_port = RTL8366RB_PORT_NUM_CPU;
2022                 priv->num_ports = RTL8366RB_NUM_PORTS;
2023                 priv->num_vlan_mc = RTL8366RB_NUM_VLANS;
2024                 priv->mib_counters = rtl8366rb_mib_counters;
2025                 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
2026                 break;
2027         default:
2028                 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
2029                          val);
2030                 break;
2031         }
2032
2033         ret = rtl8366rb_reset_chip(priv);
2034         if (ret)
2035                 return ret;
2036
2037         return 0;
2038 }
2039
2040 static const struct phylink_mac_ops rtl8366rb_phylink_mac_ops = {
2041         .mac_config = rtl8366rb_mac_config,
2042         .mac_link_down = rtl8366rb_mac_link_down,
2043         .mac_link_up = rtl8366rb_mac_link_up,
2044 };
2045
2046 static const struct dsa_switch_ops rtl8366rb_switch_ops = {
2047         .get_tag_protocol = rtl8366_get_tag_protocol,
2048         .setup = rtl8366rb_setup,
2049         .phylink_get_caps = rtl8366rb_phylink_get_caps,
2050         .get_strings = rtl8366_get_strings,
2051         .get_ethtool_stats = rtl8366_get_ethtool_stats,
2052         .get_sset_count = rtl8366_get_sset_count,
2053         .port_bridge_join = rtl8366rb_port_bridge_join,
2054         .port_bridge_leave = rtl8366rb_port_bridge_leave,
2055         .port_vlan_filtering = rtl8366rb_vlan_filtering,
2056         .port_vlan_add = rtl8366_vlan_add,
2057         .port_vlan_del = rtl8366_vlan_del,
2058         .port_enable = rtl8366rb_port_enable,
2059         .port_disable = rtl8366rb_port_disable,
2060         .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
2061         .port_bridge_flags = rtl8366rb_port_bridge_flags,
2062         .port_stp_state_set = rtl8366rb_port_stp_state_set,
2063         .port_fast_age = rtl8366rb_port_fast_age,
2064         .port_change_mtu = rtl8366rb_change_mtu,
2065         .port_max_mtu = rtl8366rb_max_mtu,
2066 };
2067
2068 static const struct realtek_ops rtl8366rb_ops = {
2069         .detect         = rtl8366rb_detect,
2070         .get_vlan_mc    = rtl8366rb_get_vlan_mc,
2071         .set_vlan_mc    = rtl8366rb_set_vlan_mc,
2072         .get_vlan_4k    = rtl8366rb_get_vlan_4k,
2073         .set_vlan_4k    = rtl8366rb_set_vlan_4k,
2074         .get_mc_index   = rtl8366rb_get_mc_index,
2075         .set_mc_index   = rtl8366rb_set_mc_index,
2076         .get_mib_counter = rtl8366rb_get_mib_counter,
2077         .is_vlan_valid  = rtl8366rb_is_vlan_valid,
2078         .enable_vlan    = rtl8366rb_enable_vlan,
2079         .enable_vlan4k  = rtl8366rb_enable_vlan4k,
2080         .phy_read       = rtl8366rb_phy_read,
2081         .phy_write      = rtl8366rb_phy_write,
2082 };
2083
2084 const struct realtek_variant rtl8366rb_variant = {
2085         .ds_ops = &rtl8366rb_switch_ops,
2086         .ops = &rtl8366rb_ops,
2087         .phylink_mac_ops = &rtl8366rb_phylink_mac_ops,
2088         .clk_delay = 10,
2089         .cmd_read = 0xa9,
2090         .cmd_write = 0xa8,
2091         .chip_data_sz = sizeof(struct rtl8366rb),
2092 };
2093
2094 static const struct of_device_id rtl8366rb_of_match[] = {
2095         { .compatible = "realtek,rtl8366rb", .data = &rtl8366rb_variant, },
2096         { /* sentinel */ },
2097 };
2098 MODULE_DEVICE_TABLE(of, rtl8366rb_of_match);
2099
2100 static struct platform_driver rtl8366rb_smi_driver = {
2101         .driver = {
2102                 .name = "rtl8366rb-smi",
2103                 .of_match_table = rtl8366rb_of_match,
2104         },
2105         .probe  = realtek_smi_probe,
2106         .remove = realtek_smi_remove,
2107         .shutdown = realtek_smi_shutdown,
2108 };
2109
2110 static struct mdio_driver rtl8366rb_mdio_driver = {
2111         .mdiodrv.driver = {
2112                 .name = "rtl8366rb-mdio",
2113                 .of_match_table = rtl8366rb_of_match,
2114         },
2115         .probe  = realtek_mdio_probe,
2116         .remove = realtek_mdio_remove,
2117         .shutdown = realtek_mdio_shutdown,
2118 };
2119
2120 static int rtl8366rb_init(void)
2121 {
2122         int ret;
2123
2124         ret = realtek_mdio_driver_register(&rtl8366rb_mdio_driver);
2125         if (ret)
2126                 return ret;
2127
2128         ret = realtek_smi_driver_register(&rtl8366rb_smi_driver);
2129         if (ret) {
2130                 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);
2131                 return ret;
2132         }
2133
2134         return 0;
2135 }
2136 module_init(rtl8366rb_init);
2137
2138 static void __exit rtl8366rb_exit(void)
2139 {
2140         realtek_smi_driver_unregister(&rtl8366rb_smi_driver);
2141         realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);
2142 }
2143 module_exit(rtl8366rb_exit);
2144
2145 MODULE_AUTHOR("Linus Walleij <[email protected]>");
2146 MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch");
2147 MODULE_LICENSE("GPL");
2148 MODULE_IMPORT_NS("REALTEK_DSA");