drivers/mtd/nand/raw/mxc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   4  * Copyright 2008 Sascha Hauer, [email protected]
   5  */
   6
   7 #include <linux/delay.h>
   8 #include <linux/slab.h>
   9 #include <linux/init.h>
  10 #include <linux/module.h>
  11 #include <linux/mtd/mtd.h>
  12 #include <linux/mtd/rawnand.h>
  13 #include <linux/mtd/partitions.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/irq.h>
  21 #include <linux/completion.h>
  22 #include <linux/of.h>
  23 #include <linux/bitfield.h>
  24
  25 #define DRIVER_NAME "mxc_nand"
  26
  27 /* Addresses for NFC registers */
  28 #define NFC_V1_V2_BUF_SIZE              (host->regs + 0x00)
  29 #define NFC_V1_V2_BUF_ADDR              (host->regs + 0x04)
  30 #define NFC_V1_V2_FLASH_ADDR            (host->regs + 0x06)
  31 #define NFC_V1_V2_FLASH_CMD             (host->regs + 0x08)
  32 #define NFC_V1_V2_CONFIG                (host->regs + 0x0a)
  33 #define NFC_V1_V2_ECC_STATUS_RESULT     (host->regs + 0x0c)
  34 #define NFC_V1_V2_RSLTMAIN_AREA         (host->regs + 0x0e)
  35 #define NFC_V21_RSLTSPARE_AREA          (host->regs + 0x10)
  36 #define NFC_V1_V2_WRPROT                (host->regs + 0x12)
  37 #define NFC_V1_UNLOCKSTART_BLKADDR      (host->regs + 0x14)
  38 #define NFC_V1_UNLOCKEND_BLKADDR        (host->regs + 0x16)
  39 #define NFC_V21_UNLOCKSTART_BLKADDR0    (host->regs + 0x20)
  40 #define NFC_V21_UNLOCKSTART_BLKADDR1    (host->regs + 0x24)
  41 #define NFC_V21_UNLOCKSTART_BLKADDR2    (host->regs + 0x28)
  42 #define NFC_V21_UNLOCKSTART_BLKADDR3    (host->regs + 0x2c)
  43 #define NFC_V21_UNLOCKEND_BLKADDR0      (host->regs + 0x22)
  44 #define NFC_V21_UNLOCKEND_BLKADDR1      (host->regs + 0x26)
  45 #define NFC_V21_UNLOCKEND_BLKADDR2      (host->regs + 0x2a)
  46 #define NFC_V21_UNLOCKEND_BLKADDR3      (host->regs + 0x2e)
  47 #define NFC_V1_V2_NF_WRPRST             (host->regs + 0x18)
  48 #define NFC_V1_V2_CONFIG1               (host->regs + 0x1a)
  49 #define NFC_V1_V2_CONFIG2               (host->regs + 0x1c)
  50
  51 #define NFC_V1_V2_ECC_STATUS_RESULT_ERM GENMASK(3, 2)
  52
  53 #define NFC_V2_CONFIG1_ECC_MODE_4       (1 << 0)
  54 #define NFC_V1_V2_CONFIG1_SP_EN         (1 << 2)
  55 #define NFC_V1_V2_CONFIG1_ECC_EN        (1 << 3)
  56 #define NFC_V1_V2_CONFIG1_INT_MSK       (1 << 4)
  57 #define NFC_V1_V2_CONFIG1_BIG           (1 << 5)
  58 #define NFC_V1_V2_CONFIG1_RST           (1 << 6)
  59 #define NFC_V1_V2_CONFIG1_CE            (1 << 7)
  60 #define NFC_V2_CONFIG1_ONE_CYCLE        (1 << 8)
  61 #define NFC_V2_CONFIG1_PPB(x)           (((x) & 0x3) << 9)
  62 #define NFC_V2_CONFIG1_FP_INT           (1 << 11)
  63
  64 #define NFC_V1_V2_CONFIG2_INT           (1 << 15)
  65
  66 /*
  67  * Operation modes for the NFC. Valid for v1, v2 and v3
  68  * type controllers.
  69  */
  70 #define NFC_CMD                         (1 << 0)
  71 #define NFC_ADDR                        (1 << 1)
  72 #define NFC_INPUT                       (1 << 2)
  73 #define NFC_OUTPUT                      (1 << 3)
  74 #define NFC_ID                          (1 << 4)
  75 #define NFC_STATUS                      (1 << 5)
  76
  77 #define NFC_V3_FLASH_CMD                (host->regs_axi + 0x00)
  78 #define NFC_V3_FLASH_ADDR0              (host->regs_axi + 0x04)
  79
  80 #define NFC_V3_CONFIG1                  (host->regs_axi + 0x34)
  81 #define NFC_V3_CONFIG1_SP_EN            (1 << 0)
  82 #define NFC_V3_CONFIG1_RBA(x)           (((x) & 0x7 ) << 4)
  83
  84 #define NFC_V3_ECC_STATUS_RESULT        (host->regs_axi + 0x38)
  85
  86 #define NFC_V3_LAUNCH                   (host->regs_axi + 0x40)
  87
  88 #define NFC_V3_WRPROT                   (host->regs_ip + 0x0)
  89 #define NFC_V3_WRPROT_LOCK_TIGHT        (1 << 0)
  90 #define NFC_V3_WRPROT_LOCK              (1 << 1)
  91 #define NFC_V3_WRPROT_UNLOCK            (1 << 2)
  92 #define NFC_V3_WRPROT_BLS_UNLOCK        (2 << 6)
  93
  94 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0   (host->regs_ip + 0x04)
  95
  96 #define NFC_V3_CONFIG2                  (host->regs_ip + 0x24)
  97 #define NFC_V3_CONFIG2_PS_512                   (0 << 0)
  98 #define NFC_V3_CONFIG2_PS_2048                  (1 << 0)
  99 #define NFC_V3_CONFIG2_PS_4096                  (2 << 0)
 100 #define NFC_V3_CONFIG2_ONE_CYCLE                (1 << 2)
 101 #define NFC_V3_CONFIG2_ECC_EN                   (1 << 3)
 102 #define NFC_V3_CONFIG2_2CMD_PHASES              (1 << 4)
 103 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0          (1 << 5)
 104 #define NFC_V3_CONFIG2_ECC_MODE_8               (1 << 6)
 105 #define NFC_V3_CONFIG2_PPB(x, shift)            (((x) & 0x3) << shift)
 106 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)       (((x) & 0x3) << 12)
 107 #define NFC_V3_CONFIG2_INT_MSK                  (1 << 15)
 108 #define NFC_V3_CONFIG2_ST_CMD(x)                (((x) & 0xff) << 24)
 109 #define NFC_V3_CONFIG2_SPAS(x)                  (((x) & 0xff) << 16)
 110
 111 #define NFC_V3_CONFIG3                          (host->regs_ip + 0x28)
 112 #define NFC_V3_CONFIG3_ADD_OP(x)                (((x) & 0x3) << 0)
 113 #define NFC_V3_CONFIG3_FW8                      (1 << 3)
 114 #define NFC_V3_CONFIG3_SBB(x)                   (((x) & 0x7) << 8)
 115 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x)        (((x) & 0x7) << 12)
 116 #define NFC_V3_CONFIG3_RBB_MODE                 (1 << 15)
 117 #define NFC_V3_CONFIG3_NO_SDMA                  (1 << 20)
 118
 119 #define NFC_V3_IPC                      (host->regs_ip + 0x2C)
 120 #define NFC_V3_IPC_CREQ                 (1 << 0)
 121 #define NFC_V3_IPC_INT                  (1 << 31)
 122
 123 #define NFC_V3_DELAY_LINE               (host->regs_ip + 0x34)
 124
 125 struct mxc_nand_host;
 126
 127 struct mxc_nand_devtype_data {
 128         void (*preset)(struct mtd_info *);
 129         int (*read_page)(struct nand_chip *chip);
 130         void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
 131         void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
 132         void (*send_page)(struct mtd_info *, unsigned int);
 133         void (*send_read_id)(struct mxc_nand_host *);
 134         uint16_t (*get_dev_status)(struct mxc_nand_host *);
 135         int (*check_int)(struct mxc_nand_host *);
 136         void (*irq_control)(struct mxc_nand_host *, int);
 137         u32 (*get_ecc_status)(struct nand_chip *);
 138         const struct mtd_ooblayout_ops *ooblayout;
 139         void (*select_chip)(struct nand_chip *chip, int cs);
 140         int (*setup_interface)(struct nand_chip *chip, int csline,
 141                                const struct nand_interface_config *conf);
 142         void (*enable_hwecc)(struct nand_chip *chip, bool enable);
 143
 144         /*
 145          * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
 146          * (CONFIG1:INT_MSK is set). To handle this the driver uses
 147          * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
 148          */
 149         int irqpending_quirk;
 150         int needs_ip;
 151
 152         size_t regs_offset;
 153         size_t spare0_offset;
 154         size_t axi_offset;
 155
 156         int spare_len;
 157         int eccbytes;
 158         int eccsize;
 159         int ppb_shift;
 160 };
 161
 162 struct mxc_nand_host {
 163         struct nand_chip        nand;
 164         struct device           *dev;
 165
 166         void __iomem            *spare0;
 167         void __iomem            *main_area0;
 168
 169         void __iomem            *base;
 170         void __iomem            *regs;
 171         void __iomem            *regs_axi;
 172         void __iomem            *regs_ip;
 173         int                     status_request;
 174         struct clk              *clk;
 175         int                     clk_act;
 176         int                     irq;
 177         int                     eccsize;
 178         int                     used_oobsize;
 179         int                     active_cs;
 180         unsigned int            ecc_stats_v1;
 181
 182         struct completion       op_completion;
 183
 184         void                    *data_buf;
 185
 186         const struct mxc_nand_devtype_data *devtype_data;
 187 };
 188
 189 static const char * const part_probes[] = {
 190         "cmdlinepart", "RedBoot", "ofpart", NULL };
 191
 192 static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
 193 {
 194         int i;
 195         u32 *t = trg;
 196         const __iomem u32 *s = src;
 197
 198         for (i = 0; i < (size >> 2); i++)
 199                 *t++ = __raw_readl(s++);
 200 }
 201
 202 static void memcpy16_fromio(void *trg, const void __iomem  *src, size_t size)
 203 {
 204         int i;
 205         u16 *t = trg;
 206         const __iomem u16 *s = src;
 207
 208         /* We assume that src (IO) is always 32bit aligned */
 209         if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
 210                 memcpy32_fromio(trg, src, size);
 211                 return;
 212         }
 213
 214         for (i = 0; i < (size >> 1); i++)
 215                 *t++ = __raw_readw(s++);
 216 }
 217
 218 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
 219 {
 220         /* __iowrite32_copy use 32bit size values so divide by 4 */
 221         __iowrite32_copy(trg, src, size / 4);
 222 }
 223
 224 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
 225 {
 226         int i;
 227         __iomem u16 *t = trg;
 228         const u16 *s = src;
 229
 230         /* We assume that trg (IO) is always 32bit aligned */
 231         if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
 232                 memcpy32_toio(trg, src, size);
 233                 return;
 234         }
 235
 236         for (i = 0; i < (size >> 1); i++)
 237                 __raw_writew(*s++, t++);
 238 }
 239
 240 /*
 241  * The controller splits a page into data chunks of 512 bytes + partial oob.
 242  * There are writesize / 512 such chunks, the size of the partial oob parts is
 243  * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
 244  * contains additionally the byte lost by rounding (if any).
 245  * This function handles the needed shuffling between host->data_buf (which
 246  * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
 247  * spare) and the NFC buffer.
 248  */
 249 static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf)
 250 {
 251         struct nand_chip *this = mtd_to_nand(mtd);
 252         struct mxc_nand_host *host = nand_get_controller_data(this);
 253         u16 i, oob_chunk_size;
 254         u16 num_chunks = mtd->writesize / 512;
 255
 256         u8 *d = buf;
 257         u8 __iomem *s = host->spare0;
 258         u16 sparebuf_size = host->devtype_data->spare_len;
 259
 260         /* size of oob chunk for all but possibly the last one */
 261         oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
 262
 263         if (bfrom) {
 264                 for (i = 0; i < num_chunks - 1; i++)
 265                         memcpy16_fromio(d + i * oob_chunk_size,
 266                                         s + i * sparebuf_size,
 267                                         oob_chunk_size);
 268
 269                 /* the last chunk */
 270                 memcpy16_fromio(d + i * oob_chunk_size,
 271                                 s + i * sparebuf_size,
 272                                 host->used_oobsize - i * oob_chunk_size);
 273         } else {
 274                 for (i = 0; i < num_chunks - 1; i++)
 275                         memcpy16_toio(&s[i * sparebuf_size],
 276                                       &d[i * oob_chunk_size],
 277                                       oob_chunk_size);
 278
 279                 /* the last chunk */
 280                 memcpy16_toio(&s[i * sparebuf_size],
 281                               &d[i * oob_chunk_size],
 282                               host->used_oobsize - i * oob_chunk_size);
 283         }
 284 }
 285
 286 static int check_int_v3(struct mxc_nand_host *host)
 287 {
 288         uint32_t tmp;
 289
 290         tmp = readl(NFC_V3_IPC);
 291         if (!(tmp & NFC_V3_IPC_INT))
 292                 return 0;
 293
 294         tmp &= ~NFC_V3_IPC_INT;
 295         writel(tmp, NFC_V3_IPC);
 296
 297         return 1;
 298 }
 299
 300 static int check_int_v1_v2(struct mxc_nand_host *host)
 301 {
 302         uint32_t tmp;
 303
 304         tmp = readw(NFC_V1_V2_CONFIG2);
 305         if (!(tmp & NFC_V1_V2_CONFIG2_INT))
 306                 return 0;
 307
 308         if (!host->devtype_data->irqpending_quirk)
 309                 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
 310
 311         return 1;
 312 }
 313
 314 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
 315 {
 316         uint16_t tmp;
 317
 318         tmp = readw(NFC_V1_V2_CONFIG1);
 319
 320         if (activate)
 321                 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
 322         else
 323                 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
 324
 325         writew(tmp, NFC_V1_V2_CONFIG1);
 326 }
 327
 328 static void irq_control_v3(struct mxc_nand_host *host, int activate)
 329 {
 330         uint32_t tmp;
 331
 332         tmp = readl(NFC_V3_CONFIG2);
 333
 334         if (activate)
 335                 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
 336         else
 337                 tmp |= NFC_V3_CONFIG2_INT_MSK;
 338
 339         writel(tmp, NFC_V3_CONFIG2);
 340 }
 341
 342 static void irq_control(struct mxc_nand_host *host, int activate)
 343 {
 344         if (host->devtype_data->irqpending_quirk) {
 345                 if (activate)
 346                         enable_irq(host->irq);
 347                 else
 348                         disable_irq_nosync(host->irq);
 349         } else {
 350                 host->devtype_data->irq_control(host, activate);
 351         }
 352 }
 353
 354 static u32 get_ecc_status_v1(struct nand_chip *chip)
 355 {
 356         struct mtd_info *mtd = nand_to_mtd(chip);
 357         struct mxc_nand_host *host = nand_get_controller_data(chip);
 358         unsigned int ecc_stats, max_bitflips = 0;
 359         int no_subpages, i;
 360
 361         no_subpages = mtd->writesize >> 9;
 362
 363         ecc_stats = host->ecc_stats_v1;
 364
 365         for (i = 0; i < no_subpages; i++) {
 366                 switch (ecc_stats & 0x3) {
 367                 case 0:
 368                 default:
 369                         break;
 370                 case 1:
 371                         mtd->ecc_stats.corrected++;
 372                         max_bitflips = 1;
 373                         break;
 374                 case 2:
 375                         mtd->ecc_stats.failed++;
 376                         break;
 377                 }
 378
 379                 ecc_stats >>= 2;
 380         }
 381
 382         return max_bitflips;
 383 }
 384
 385 static u32 get_ecc_status_v2_v3(struct nand_chip *chip, unsigned int ecc_stat)
 386 {
 387         struct mtd_info *mtd = nand_to_mtd(chip);
 388         struct mxc_nand_host *host = nand_get_controller_data(chip);
 389         u8 ecc_bit_mask, err_limit;
 390         unsigned int max_bitflips = 0;
 391         int no_subpages, err;
 392
 393         ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
 394         err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
 395
 396         no_subpages = mtd->writesize >> 9;
 397
 398         do {
 399                 err = ecc_stat & ecc_bit_mask;
 400                 if (err > err_limit) {
 401                         mtd->ecc_stats.failed++;
 402                 } else {
 403                         mtd->ecc_stats.corrected += err;
 404                         max_bitflips = max_t(unsigned int, max_bitflips, err);
 405                 }
 406
 407                 ecc_stat >>= 4;
 408         } while (--no_subpages);
 409
 410         return max_bitflips;
 411 }
 412
 413 static u32 get_ecc_status_v2(struct nand_chip *chip)
 414 {
 415         struct mxc_nand_host *host = nand_get_controller_data(chip);
 416
 417         u32 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
 418
 419         return get_ecc_status_v2_v3(chip, ecc_stat);
 420 }
 421
 422 static u32 get_ecc_status_v3(struct nand_chip *chip)
 423 {
 424         struct mxc_nand_host *host = nand_get_controller_data(chip);
 425
 426         u32 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
 427
 428         return get_ecc_status_v2_v3(chip, ecc_stat);
 429 }
 430
 431 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 432 {
 433         struct mxc_nand_host *host = dev_id;
 434
 435         if (!host->devtype_data->check_int(host))
 436                 return IRQ_NONE;
 437
 438         irq_control(host, 0);
 439
 440         complete(&host->op_completion);
 441
 442         return IRQ_HANDLED;
 443 }
 444
 445 /* This function polls the NANDFC to wait for the basic operation to
 446  * complete by checking the INT bit of config2 register.
 447  */
 448 static int wait_op_done(struct mxc_nand_host *host, int useirq)
 449 {
 450         int ret = 0;
 451
 452         /*
 453          * If operation is already complete, don't bother to setup an irq or a
 454          * loop.
 455          */
 456         if (host->devtype_data->check_int(host))
 457                 return 0;
 458
 459         if (useirq) {
 460                 unsigned long time_left;
 461
 462                 reinit_completion(&host->op_completion);
 463
 464                 irq_control(host, 1);
 465
 466                 time_left = wait_for_completion_timeout(&host->op_completion, HZ);
 467                 if (!time_left && !host->devtype_data->check_int(host)) {
 468                         dev_dbg(host->dev, "timeout waiting for irq\n");
 469                         ret = -ETIMEDOUT;
 470                 }
 471         } else {
 472                 int max_retries = 8000;
 473                 int done;
 474
 475                 do {
 476                         udelay(1);
 477
 478                         done = host->devtype_data->check_int(host);
 479                         if (done)
 480                                 break;
 481
 482                 } while (--max_retries);
 483
 484                 if (!done) {
 485                         dev_dbg(host->dev, "timeout polling for completion\n");
 486                         ret = -ETIMEDOUT;
 487                 }
 488         }
 489
 490         WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
 491
 492         return ret;
 493 }
 494
 495 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 496 {
 497         /* fill command */
 498         writel(cmd, NFC_V3_FLASH_CMD);
 499
 500         /* send out command */
 501         writel(NFC_CMD, NFC_V3_LAUNCH);
 502
 503         /* Wait for operation to complete */
 504         wait_op_done(host, useirq);
 505 }
 506
 507 /* This function issues the specified command to the NAND device and
 508  * waits for completion. */
 509 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 510 {
 511         dev_dbg(host->dev, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 512
 513         writew(cmd, NFC_V1_V2_FLASH_CMD);
 514         writew(NFC_CMD, NFC_V1_V2_CONFIG2);
 515
 516         if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
 517                 int max_retries = 100;
 518                 /* Reset completion is indicated by NFC_CONFIG2 */
 519                 /* being set to 0 */
 520                 while (max_retries-- > 0) {
 521                         if (readw(NFC_V1_V2_CONFIG2) == 0) {
 522                                 break;
 523                         }
 524                         udelay(1);
 525                 }
 526                 if (max_retries < 0)
 527                         dev_dbg(host->dev, "%s: RESET failed\n", __func__);
 528         } else {
 529                 /* Wait for operation to complete */
 530                 wait_op_done(host, useirq);
 531         }
 532 }
 533
 534 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
 535 {
 536         /* fill address */
 537         writel(addr, NFC_V3_FLASH_ADDR0);
 538
 539         /* send out address */
 540         writel(NFC_ADDR, NFC_V3_LAUNCH);
 541
 542         wait_op_done(host, 0);
 543 }
 544
 545 /* This function sends an address (or partial address) to the
 546  * NAND device. The address is used to select the source/destination for
 547  * a NAND command. */
 548 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
 549 {
 550         dev_dbg(host->dev, "send_addr(host, 0x%x %d)\n", addr, islast);
 551
 552         writew(addr, NFC_V1_V2_FLASH_ADDR);
 553         writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
 554
 555         /* Wait for operation to complete */
 556         wait_op_done(host, islast);
 557 }
 558
 559 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
 560 {
 561         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 562         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 563         uint32_t tmp;
 564
 565         tmp = readl(NFC_V3_CONFIG1);
 566         tmp &= ~(7 << 4);
 567         writel(tmp, NFC_V3_CONFIG1);
 568
 569         /* transfer data from NFC ram to nand */
 570         writel(ops, NFC_V3_LAUNCH);
 571
 572         wait_op_done(host, false);
 573 }
 574
 575 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
 576 {
 577         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 578         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 579
 580         /* NANDFC buffer 0 is used for page read/write */
 581         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 582
 583         writew(ops, NFC_V1_V2_CONFIG2);
 584
 585         /* Wait for operation to complete */
 586         wait_op_done(host, true);
 587 }
 588
 589 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
 590 {
 591         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 592         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 593         int bufs, i;
 594
 595         if (mtd->writesize > 512)
 596                 bufs = 4;
 597         else
 598                 bufs = 1;
 599
 600         for (i = 0; i < bufs; i++) {
 601
 602                 /* NANDFC buffer 0 is used for page read/write */
 603                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
 604
 605                 writew(ops, NFC_V1_V2_CONFIG2);
 606
 607                 /* Wait for operation to complete */
 608                 wait_op_done(host, true);
 609         }
 610 }
 611
 612 static void send_read_id_v3(struct mxc_nand_host *host)
 613 {
 614         /* Read ID into main buffer */
 615         writel(NFC_ID, NFC_V3_LAUNCH);
 616
 617         wait_op_done(host, true);
 618
 619         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 620 }
 621
 622 /* Request the NANDFC to perform a read of the NAND device ID. */
 623 static void send_read_id_v1_v2(struct mxc_nand_host *host)
 624 {
 625         /* NANDFC buffer 0 is used for device ID output */
 626         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 627
 628         writew(NFC_ID, NFC_V1_V2_CONFIG2);
 629
 630         /* Wait for operation to complete */
 631         wait_op_done(host, true);
 632
 633         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 634 }
 635
 636 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
 637 {
 638         writew(NFC_STATUS, NFC_V3_LAUNCH);
 639         wait_op_done(host, true);
 640
 641         return readl(NFC_V3_CONFIG1) >> 16;
 642 }
 643
 644 /* This function requests the NANDFC to perform a read of the
 645  * NAND device status and returns the current status. */
 646 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
 647 {
 648         void __iomem *main_buf = host->main_area0;
 649         uint32_t store;
 650         uint16_t ret;
 651
 652         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 653
 654         /*
 655          * The device status is stored in main_area0. To
 656          * prevent corruption of the buffer save the value
 657          * and restore it afterwards.
 658          */
 659         store = readl(main_buf);
 660
 661         writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
 662         wait_op_done(host, true);
 663
 664         ret = readw(main_buf);
 665
 666         writel(store, main_buf);
 667
 668         return ret;
 669 }
 670
 671 static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable)
 672 {
 673         struct mxc_nand_host *host = nand_get_controller_data(chip);
 674         uint16_t config1;
 675
 676         if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
 677                 return;
 678
 679         config1 = readw(NFC_V1_V2_CONFIG1);
 680
 681         if (enable)
 682                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
 683         else
 684                 config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN;
 685
 686         writew(config1, NFC_V1_V2_CONFIG1);
 687 }
 688
 689 static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable)
 690 {
 691         struct mxc_nand_host *host = nand_get_controller_data(chip);
 692         uint32_t config2;
 693
 694         if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
 695                 return;
 696
 697         config2 = readl(NFC_V3_CONFIG2);
 698
 699         if (enable)
 700                 config2 |= NFC_V3_CONFIG2_ECC_EN;
 701         else
 702                 config2 &= ~NFC_V3_CONFIG2_ECC_EN;
 703
 704         writel(config2, NFC_V3_CONFIG2);
 705 }
 706
 707 static int mxc_nand_read_page_v1(struct nand_chip *chip)
 708 {
 709         struct mtd_info *mtd = nand_to_mtd(chip);
 710         struct mxc_nand_host *host = nand_get_controller_data(chip);
 711         int no_subpages;
 712         int i;
 713         unsigned int ecc_stats = 0;
 714
 715         if (mtd->writesize)
 716                 no_subpages = mtd->writesize >> 9;
 717         else
 718                 /* READ PARAMETER PAGE is called when mtd->writesize is not yet set */
 719                 no_subpages = 1;
 720
 721         for (i = 0; i < no_subpages; i++) {
 722                 /* NANDFC buffer 0 is used for page read/write */
 723                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
 724
 725                 writew(NFC_OUTPUT, NFC_V1_V2_CONFIG2);
 726
 727                 /* Wait for operation to complete */
 728                 wait_op_done(host, true);
 729
 730                 ecc_stats |= FIELD_GET(NFC_V1_V2_ECC_STATUS_RESULT_ERM,
 731                                        readw(NFC_V1_V2_ECC_STATUS_RESULT)) << i * 2;
 732         }
 733
 734         host->ecc_stats_v1 = ecc_stats;
 735
 736         return 0;
 737 }
 738
 739 static int mxc_nand_read_page_v2_v3(struct nand_chip *chip)
 740 {
 741         struct mtd_info *mtd = nand_to_mtd(chip);
 742         struct mxc_nand_host *host = nand_get_controller_data(chip);
 743
 744         host->devtype_data->send_page(mtd, NFC_OUTPUT);
 745
 746         return 0;
 747 }
 748
 749 static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf,
 750                               int oob_required, int page)
 751 {
 752         struct mtd_info *mtd = nand_to_mtd(chip);
 753         struct mxc_nand_host *host = nand_get_controller_data(chip);
 754         int ret;
 755
 756         host->devtype_data->enable_hwecc(chip, true);
 757
 758         ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
 759
 760         host->devtype_data->enable_hwecc(chip, false);
 761
 762         if (ret)
 763                 return ret;
 764
 765         if (oob_required)
 766                 copy_spare(mtd, true, chip->oob_poi);
 767
 768         return host->devtype_data->get_ecc_status(chip);
 769 }
 770
 771 static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf,
 772                                   int oob_required, int page)
 773 {
 774         struct mtd_info *mtd = nand_to_mtd(chip);
 775         int ret;
 776
 777         ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
 778         if (ret)
 779                 return ret;
 780
 781         if (oob_required)
 782                 copy_spare(mtd, true, chip->oob_poi);
 783
 784         return 0;
 785 }
 786
 787 static int mxc_nand_read_oob(struct nand_chip *chip, int page)
 788 {
 789         struct mtd_info *mtd = nand_to_mtd(chip);
 790         struct mxc_nand_host *host = nand_get_controller_data(chip);
 791         int ret;
 792
 793         ret = nand_read_page_op(chip, page, 0, host->data_buf, mtd->writesize);
 794         if (ret)
 795                 return ret;
 796
 797         copy_spare(mtd, true, chip->oob_poi);
 798
 799         return 0;
 800 }
 801
 802 static int mxc_nand_write_page_ecc(struct nand_chip *chip, const uint8_t *buf,
 803                                    int oob_required, int page)
 804 {
 805         struct mtd_info *mtd = nand_to_mtd(chip);
 806         struct mxc_nand_host *host = nand_get_controller_data(chip);
 807         int ret;
 808
 809         copy_spare(mtd, false, chip->oob_poi);
 810
 811         host->devtype_data->enable_hwecc(chip, true);
 812
 813         ret = nand_prog_page_op(chip, page, 0, buf, mtd->writesize);
 814
 815         host->devtype_data->enable_hwecc(chip, false);
 816
 817         return ret;
 818 }
 819
 820 static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
 821                                    int oob_required, int page)
 822 {
 823         struct mtd_info *mtd = nand_to_mtd(chip);
 824
 825         copy_spare(mtd, false, chip->oob_poi);
 826
 827         return nand_prog_page_op(chip, page, 0, buf, mtd->writesize);
 828 }
 829
 830 static int mxc_nand_write_oob(struct nand_chip *chip, int page)
 831 {
 832         struct mtd_info *mtd = nand_to_mtd(chip);
 833         struct mxc_nand_host *host = nand_get_controller_data(chip);
 834
 835         memset(host->data_buf, 0xff, mtd->writesize);
 836         copy_spare(mtd, false, chip->oob_poi);
 837
 838         return nand_prog_page_op(chip, page, 0, host->data_buf, mtd->writesize);
 839 }
 840
 841 /* This function is used by upper layer for select and
 842  * deselect of the NAND chip */
 843 static void mxc_nand_select_chip_v1_v3(struct nand_chip *nand_chip, int chip)
 844 {
 845         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 846
 847         if (chip == -1) {
 848                 /* Disable the NFC clock */
 849                 if (host->clk_act) {
 850                         clk_disable_unprepare(host->clk);
 851                         host->clk_act = 0;
 852                 }
 853                 return;
 854         }
 855
 856         if (!host->clk_act) {
 857                 /* Enable the NFC clock */
 858                 clk_prepare_enable(host->clk);
 859                 host->clk_act = 1;
 860         }
 861 }
 862
 863 static void mxc_nand_select_chip_v2(struct nand_chip *nand_chip, int chip)
 864 {
 865         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 866
 867         if (chip == -1) {
 868                 /* Disable the NFC clock */
 869                 if (host->clk_act) {
 870                         clk_disable_unprepare(host->clk);
 871                         host->clk_act = 0;
 872                 }
 873                 return;
 874         }
 875
 876         if (!host->clk_act) {
 877                 /* Enable the NFC clock */
 878                 clk_prepare_enable(host->clk);
 879                 host->clk_act = 1;
 880         }
 881
 882         host->active_cs = chip;
 883         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 884 }
 885
 886 #define MXC_V1_ECCBYTES         5
 887
 888 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
 889                                 struct mtd_oob_region *oobregion)
 890 {
 891         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 892
 893         if (section >= nand_chip->ecc.steps)
 894                 return -ERANGE;
 895
 896         oobregion->offset = (section * 16) + 6;
 897         oobregion->length = MXC_V1_ECCBYTES;
 898
 899         return 0;
 900 }
 901
 902 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section,
 903                                  struct mtd_oob_region *oobregion)
 904 {
 905         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 906
 907         if (section > nand_chip->ecc.steps)
 908                 return -ERANGE;
 909
 910         if (!section) {
 911                 if (mtd->writesize <= 512) {
 912                         oobregion->offset = 0;
 913                         oobregion->length = 5;
 914                 } else {
 915                         oobregion->offset = 2;
 916                         oobregion->length = 4;
 917                 }
 918         } else {
 919                 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;
 920                 if (section < nand_chip->ecc.steps)
 921                         oobregion->length = (section * 16) + 6 -
 922                                             oobregion->offset;
 923                 else
 924                         oobregion->length = mtd->oobsize - oobregion->offset;
 925         }
 926
 927         return 0;
 928 }
 929
 930 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = {
 931         .ecc = mxc_v1_ooblayout_ecc,
 932         .free = mxc_v1_ooblayout_free,
 933 };
 934
 935 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section,
 936                                 struct mtd_oob_region *oobregion)
 937 {
 938         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 939         int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
 940
 941         if (section >= nand_chip->ecc.steps)
 942                 return -ERANGE;
 943
 944         oobregion->offset = (section * stepsize) + 7;
 945         oobregion->length = nand_chip->ecc.bytes;
 946
 947         return 0;
 948 }
 949
 950 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section,
 951                                  struct mtd_oob_region *oobregion)
 952 {
 953         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 954         int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
 955
 956         if (section >= nand_chip->ecc.steps)
 957                 return -ERANGE;
 958
 959         if (!section) {
 960                 if (mtd->writesize <= 512) {
 961                         oobregion->offset = 0;
 962                         oobregion->length = 5;
 963                 } else {
 964                         oobregion->offset = 2;
 965                         oobregion->length = 4;
 966                 }
 967         } else {
 968                 oobregion->offset = section * stepsize;
 969                 oobregion->length = 7;
 970         }
 971
 972         return 0;
 973 }
 974
 975 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = {
 976         .ecc = mxc_v2_ooblayout_ecc,
 977         .free = mxc_v2_ooblayout_free,
 978 };
 979
 980 /*
 981  * v2 and v3 type controllers can do 4bit or 8bit ecc depending
 982  * on how much oob the nand chip has. For 8bit ecc we need at least
 983  * 26 bytes of oob data per 512 byte block.
 984  */
 985 static int get_eccsize(struct mtd_info *mtd)
 986 {
 987         int oobbytes_per_512 = 0;
 988
 989         oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
 990
 991         if (oobbytes_per_512 < 26)
 992                 return 4;
 993         else
 994                 return 8;
 995 }
 996
 997 static void preset_v1(struct mtd_info *mtd)
 998 {
 999         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1000         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1001         uint16_t config1 = 0;
1002
1003         if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST &&
1004             mtd->writesize)
1005                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1006
1007         if (!host->devtype_data->irqpending_quirk)
1008                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1009
1010         host->eccsize = 1;
1011
1012         writew(config1, NFC_V1_V2_CONFIG1);
1013         /* preset operation */
1014
1015         /* Unlock the internal RAM Buffer */
1016         writew(0x2, NFC_V1_V2_CONFIG);
1017
1018         /* Blocks to be unlocked */
1019         writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1020         writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1021
1022         /* Unlock Block Command for given address range */
1023         writew(0x4, NFC_V1_V2_WRPROT);
1024 }
1025
1026 static int mxc_nand_v2_setup_interface(struct nand_chip *chip, int csline,
1027                                        const struct nand_interface_config *conf)
1028 {
1029         struct mxc_nand_host *host = nand_get_controller_data(chip);
1030         int tRC_min_ns, tRC_ps, ret;
1031         unsigned long rate, rate_round;
1032         const struct nand_sdr_timings *timings;
1033         u16 config1;
1034
1035         timings = nand_get_sdr_timings(conf);
1036         if (IS_ERR(timings))
1037                 return -ENOTSUPP;
1038
1039         config1 = readw(NFC_V1_V2_CONFIG1);
1040
1041         tRC_min_ns = timings->tRC_min / 1000;
1042         rate = 1000000000 / tRC_min_ns;
1043
1044         /*
1045          * For tRC < 30ns we have to use EDO mode. In this case the controller
1046          * does one access per clock cycle. Otherwise the controller does one
1047          * access in two clock cycles, thus we have to double the rate to the
1048          * controller.
1049          */
1050         if (tRC_min_ns < 30) {
1051                 rate_round = clk_round_rate(host->clk, rate);
1052                 config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1053                 tRC_ps = 1000000000 / (rate_round / 1000);
1054         } else {
1055                 rate *= 2;
1056                 rate_round = clk_round_rate(host->clk, rate);
1057                 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1058                 tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1059         }
1060
1061         /*
1062          * The timing values compared against are from the i.MX25 Automotive
1063          * datasheet, Table 50. NFC Timing Parameters
1064          */
1065         if (timings->tCLS_min > tRC_ps - 1000 ||
1066             timings->tCLH_min > tRC_ps - 2000 ||
1067             timings->tCS_min > tRC_ps - 1000 ||
1068             timings->tCH_min > tRC_ps - 2000 ||
1069             timings->tWP_min > tRC_ps - 1500 ||
1070             timings->tALS_min > tRC_ps ||
1071             timings->tALH_min > tRC_ps - 3000 ||
1072             timings->tDS_min > tRC_ps ||
1073             timings->tDH_min > tRC_ps - 5000 ||
1074             timings->tWC_min > 2 * tRC_ps ||
1075             timings->tWH_min > tRC_ps - 2500 ||
1076             timings->tRR_min > 6 * tRC_ps ||
1077             timings->tRP_min > 3 * tRC_ps / 2 ||
1078             timings->tRC_min > 2 * tRC_ps ||
1079             timings->tREH_min > (tRC_ps / 2) - 2500) {
1080                 dev_dbg(host->dev, "Timing out of bounds\n");
1081                 return -EINVAL;
1082         }
1083
1084         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1085                 return 0;
1086
1087         ret = clk_set_rate(host->clk, rate);
1088         if (ret)
1089                 return ret;
1090
1091         writew(config1, NFC_V1_V2_CONFIG1);
1092
1093         dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1094                 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1095                 "normal");
1096
1097         return 0;
1098 }
1099
1100 static void preset_v2(struct mtd_info *mtd)
1101 {
1102         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1103         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1104         uint16_t config1 = 0;
1105
1106         config1 |= NFC_V2_CONFIG1_FP_INT;
1107
1108         if (!host->devtype_data->irqpending_quirk)
1109                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1110
1111         if (mtd->writesize) {
1112                 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1113
1114                 if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1115                         config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1116
1117                 host->eccsize = get_eccsize(mtd);
1118                 if (host->eccsize == 4)
1119                         config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1120
1121                 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1122         } else {
1123                 host->eccsize = 1;
1124         }
1125
1126         writew(config1, NFC_V1_V2_CONFIG1);
1127         /* preset operation */
1128
1129         /* spare area size in 16-bit half-words */
1130         writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA);
1131
1132         /* Unlock the internal RAM Buffer */
1133         writew(0x2, NFC_V1_V2_CONFIG);
1134
1135         /* Blocks to be unlocked */
1136         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1137         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1138         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1139         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1140         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1141         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1142         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1143         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1144
1145         /* Unlock Block Command for given address range */
1146         writew(0x4, NFC_V1_V2_WRPROT);
1147 }
1148
1149 static void preset_v3(struct mtd_info *mtd)
1150 {
1151         struct nand_chip *chip = mtd_to_nand(mtd);
1152         struct mxc_nand_host *host = nand_get_controller_data(chip);
1153         uint32_t config2, config3;
1154         int i, addr_phases;
1155
1156         writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1157         writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1158
1159         /* Unlock the internal RAM Buffer */
1160         writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1161                         NFC_V3_WRPROT);
1162
1163         /* Blocks to be unlocked */
1164         for (i = 0; i < NAND_MAX_CHIPS; i++)
1165                 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1166
1167         writel(0, NFC_V3_IPC);
1168
1169         config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1170                 NFC_V3_CONFIG2_2CMD_PHASES |
1171                 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1172                 NFC_V3_CONFIG2_ST_CMD(0x70) |
1173                 NFC_V3_CONFIG2_INT_MSK |
1174                 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1175
1176         addr_phases = fls(chip->pagemask) >> 3;
1177
1178         if (mtd->writesize == 2048) {
1179                 config2 |= NFC_V3_CONFIG2_PS_2048;
1180                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1181         } else if (mtd->writesize == 4096) {
1182                 config2 |= NFC_V3_CONFIG2_PS_4096;
1183                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1184         } else {
1185                 config2 |= NFC_V3_CONFIG2_PS_512;
1186                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1187         }
1188
1189         if (mtd->writesize) {
1190                 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1191                         config2 |= NFC_V3_CONFIG2_ECC_EN;
1192
1193                 config2 |= NFC_V3_CONFIG2_PPB(
1194                                 ffs(mtd->erasesize / mtd->writesize) - 6,
1195                                 host->devtype_data->ppb_shift);
1196                 host->eccsize = get_eccsize(mtd);
1197                 if (host->eccsize == 8)
1198                         config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1199         }
1200
1201         writel(config2, NFC_V3_CONFIG2);
1202
1203         config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1204                         NFC_V3_CONFIG3_NO_SDMA |
1205                         NFC_V3_CONFIG3_RBB_MODE |
1206                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1207                         NFC_V3_CONFIG3_ADD_OP(0);
1208
1209         if (!(chip->options & NAND_BUSWIDTH_16))
1210                 config3 |= NFC_V3_CONFIG3_FW8;
1211
1212         writel(config3, NFC_V3_CONFIG3);
1213
1214         writel(0, NFC_V3_DELAY_LINE);
1215 }
1216
1217 /*
1218  * The generic flash bbt descriptors overlap with our ecc
1219  * hardware, so define some i.MX specific ones.
1220  */
1221 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1222 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1223
1224 static struct nand_bbt_descr bbt_main_descr = {
1225         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1226             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1227         .offs = 0,
1228         .len = 4,
1229         .veroffs = 4,
1230         .maxblocks = 4,
1231         .pattern = bbt_pattern,
1232 };
1233
1234 static struct nand_bbt_descr bbt_mirror_descr = {
1235         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1236             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1237         .offs = 0,
1238         .len = 4,
1239         .veroffs = 4,
1240         .maxblocks = 4,
1241         .pattern = mirror_pattern,
1242 };
1243
1244 /* v1 + irqpending_quirk: i.MX21 */
1245 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1246         .preset = preset_v1,
1247         .read_page = mxc_nand_read_page_v1,
1248         .send_cmd = send_cmd_v1_v2,
1249         .send_addr = send_addr_v1_v2,
1250         .send_page = send_page_v1,
1251         .send_read_id = send_read_id_v1_v2,
1252         .get_dev_status = get_dev_status_v1_v2,
1253         .check_int = check_int_v1_v2,
1254         .irq_control = irq_control_v1_v2,
1255         .get_ecc_status = get_ecc_status_v1,
1256         .ooblayout = &mxc_v1_ooblayout_ops,
1257         .select_chip = mxc_nand_select_chip_v1_v3,
1258         .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1259         .irqpending_quirk = 1,
1260         .needs_ip = 0,
1261         .regs_offset = 0xe00,
1262         .spare0_offset = 0x800,
1263         .spare_len = 16,
1264         .eccbytes = 3,
1265         .eccsize = 1,
1266 };
1267
1268 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1269 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1270         .preset = preset_v1,
1271         .read_page = mxc_nand_read_page_v1,
1272         .send_cmd = send_cmd_v1_v2,
1273         .send_addr = send_addr_v1_v2,
1274         .send_page = send_page_v1,
1275         .send_read_id = send_read_id_v1_v2,
1276         .get_dev_status = get_dev_status_v1_v2,
1277         .check_int = check_int_v1_v2,
1278         .irq_control = irq_control_v1_v2,
1279         .get_ecc_status = get_ecc_status_v1,
1280         .ooblayout = &mxc_v1_ooblayout_ops,
1281         .select_chip = mxc_nand_select_chip_v1_v3,
1282         .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1283         .irqpending_quirk = 0,
1284         .needs_ip = 0,
1285         .regs_offset = 0xe00,
1286         .spare0_offset = 0x800,
1287         .axi_offset = 0,
1288         .spare_len = 16,
1289         .eccbytes = 3,
1290         .eccsize = 1,
1291 };
1292
1293 /* v21: i.MX25, i.MX35 */
1294 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1295         .preset = preset_v2,
1296         .read_page = mxc_nand_read_page_v2_v3,
1297         .send_cmd = send_cmd_v1_v2,
1298         .send_addr = send_addr_v1_v2,
1299         .send_page = send_page_v2,
1300         .send_read_id = send_read_id_v1_v2,
1301         .get_dev_status = get_dev_status_v1_v2,
1302         .check_int = check_int_v1_v2,
1303         .irq_control = irq_control_v1_v2,
1304         .get_ecc_status = get_ecc_status_v2,
1305         .ooblayout = &mxc_v2_ooblayout_ops,
1306         .select_chip = mxc_nand_select_chip_v2,
1307         .setup_interface = mxc_nand_v2_setup_interface,
1308         .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1309         .irqpending_quirk = 0,
1310         .needs_ip = 0,
1311         .regs_offset = 0x1e00,
1312         .spare0_offset = 0x1000,
1313         .axi_offset = 0,
1314         .spare_len = 64,
1315         .eccbytes = 9,
1316         .eccsize = 0,
1317 };
1318
1319 /* v3.2a: i.MX51 */
1320 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1321         .preset = preset_v3,
1322         .read_page = mxc_nand_read_page_v2_v3,
1323         .send_cmd = send_cmd_v3,
1324         .send_addr = send_addr_v3,
1325         .send_page = send_page_v3,
1326         .send_read_id = send_read_id_v3,
1327         .get_dev_status = get_dev_status_v3,
1328         .check_int = check_int_v3,
1329         .irq_control = irq_control_v3,
1330         .get_ecc_status = get_ecc_status_v3,
1331         .ooblayout = &mxc_v2_ooblayout_ops,
1332         .select_chip = mxc_nand_select_chip_v1_v3,
1333         .enable_hwecc = mxc_nand_enable_hwecc_v3,
1334         .irqpending_quirk = 0,
1335         .needs_ip = 1,
1336         .regs_offset = 0,
1337         .spare0_offset = 0x1000,
1338         .axi_offset = 0x1e00,
1339         .spare_len = 64,
1340         .eccbytes = 0,
1341         .eccsize = 0,
1342         .ppb_shift = 7,
1343 };
1344
1345 /* v3.2b: i.MX53 */
1346 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1347         .preset = preset_v3,
1348         .read_page = mxc_nand_read_page_v2_v3,
1349         .send_cmd = send_cmd_v3,
1350         .send_addr = send_addr_v3,
1351         .send_page = send_page_v3,
1352         .send_read_id = send_read_id_v3,
1353         .get_dev_status = get_dev_status_v3,
1354         .check_int = check_int_v3,
1355         .irq_control = irq_control_v3,
1356         .get_ecc_status = get_ecc_status_v3,
1357         .ooblayout = &mxc_v2_ooblayout_ops,
1358         .select_chip = mxc_nand_select_chip_v1_v3,
1359         .enable_hwecc = mxc_nand_enable_hwecc_v3,
1360         .irqpending_quirk = 0,
1361         .needs_ip = 1,
1362         .regs_offset = 0,
1363         .spare0_offset = 0x1000,
1364         .axi_offset = 0x1e00,
1365         .spare_len = 64,
1366         .eccbytes = 0,
1367         .eccsize = 0,
1368         .ppb_shift = 8,
1369 };
1370
1371 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1372 {
1373         return host->devtype_data == &imx21_nand_devtype_data;
1374 }
1375
1376 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1377 {
1378         return host->devtype_data == &imx27_nand_devtype_data;
1379 }
1380
1381 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1382 {
1383         return host->devtype_data == &imx25_nand_devtype_data;
1384 }
1385
1386 static const struct of_device_id mxcnd_dt_ids[] = {
1387         { .compatible = "fsl,imx21-nand", .data = &imx21_nand_devtype_data, },
1388         { .compatible = "fsl,imx27-nand", .data = &imx27_nand_devtype_data, },
1389         { .compatible = "fsl,imx25-nand", .data = &imx25_nand_devtype_data, },
1390         { .compatible = "fsl,imx51-nand", .data = &imx51_nand_devtype_data, },
1391         { .compatible = "fsl,imx53-nand", .data = &imx53_nand_devtype_data, },
1392         { /* sentinel */ }
1393 };
1394 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1395
1396 static int mxcnd_attach_chip(struct nand_chip *chip)
1397 {
1398         struct mtd_info *mtd = nand_to_mtd(chip);
1399         struct mxc_nand_host *host = nand_get_controller_data(chip);
1400         struct device *dev = mtd->dev.parent;
1401
1402         chip->ecc.bytes = host->devtype_data->eccbytes;
1403         host->eccsize = host->devtype_data->eccsize;
1404         chip->ecc.size = 512;
1405
1406         switch (chip->ecc.engine_type) {
1407         case NAND_ECC_ENGINE_TYPE_ON_HOST:
1408                 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1409                 chip->ecc.read_page = mxc_nand_read_page;
1410                 chip->ecc.read_page_raw = mxc_nand_read_page_raw;
1411                 chip->ecc.read_oob = mxc_nand_read_oob;
1412                 chip->ecc.write_page = mxc_nand_write_page_ecc;
1413                 chip->ecc.write_page_raw = mxc_nand_write_page_raw;
1414                 chip->ecc.write_oob = mxc_nand_write_oob;
1415                 break;
1416
1417         case NAND_ECC_ENGINE_TYPE_SOFT:
1418                 chip->ecc.write_page_raw = nand_monolithic_write_page_raw;
1419                 chip->ecc.read_page_raw = nand_monolithic_read_page_raw;
1420                 break;
1421
1422         default:
1423                 return -EINVAL;
1424         }
1425
1426         if (chip->bbt_options & NAND_BBT_USE_FLASH) {
1427                 chip->bbt_td = &bbt_main_descr;
1428                 chip->bbt_md = &bbt_mirror_descr;
1429         }
1430
1431         /* Allocate the right size buffer now */
1432         devm_kfree(dev, (void *)host->data_buf);
1433         host->data_buf = devm_kzalloc(dev, mtd->writesize + mtd->oobsize,
1434                                       GFP_KERNEL);
1435         if (!host->data_buf)
1436                 return -ENOMEM;
1437
1438         /* Call preset again, with correct writesize chip time */
1439         host->devtype_data->preset(mtd);
1440
1441         if (!chip->ecc.bytes) {
1442                 if (host->eccsize == 8)
1443                         chip->ecc.bytes = 18;
1444                 else if (host->eccsize == 4)
1445                         chip->ecc.bytes = 9;
1446         }
1447
1448         /*
1449          * Experimentation shows that i.MX NFC can only handle up to 218 oob
1450          * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1451          * into copying invalid data to/from the spare IO buffer, as this
1452          * might cause ECC data corruption when doing sub-page write to a
1453          * partially written page.
1454          */
1455         host->used_oobsize = min(mtd->oobsize, 218U);
1456
1457         if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
1458                 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1459                         chip->ecc.strength = 1;
1460                 else
1461                         chip->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int mxcnd_setup_interface(struct nand_chip *chip, int chipnr,
1468                                  const struct nand_interface_config *conf)
1469 {
1470         struct mxc_nand_host *host = nand_get_controller_data(chip);
1471
1472         return host->devtype_data->setup_interface(chip, chipnr, conf);
1473 }
1474
1475 static void memff16_toio(void *buf, int n)
1476 {
1477         __iomem u16 *t = buf;
1478         int i;
1479
1480         for (i = 0; i < (n >> 1); i++)
1481                 __raw_writew(0xffff, t++);
1482 }
1483
1484 static void copy_page_to_sram(struct mtd_info *mtd, const void *buf, int buf_len)
1485 {
1486         struct nand_chip *this = mtd_to_nand(mtd);
1487         struct mxc_nand_host *host = nand_get_controller_data(this);
1488         unsigned int no_subpages = mtd->writesize / 512;
1489         int oob_per_subpage, i;
1490
1491         oob_per_subpage = (mtd->oobsize / no_subpages) & ~1;
1492
1493         /*
1494          * During a page write the i.MX NAND controller will read 512b from
1495          * main_area0 SRAM, then oob_per_subpage bytes from spare0 SRAM, then
1496          * 512b from main_area1 SRAM and so on until the full page is written.
1497          * For software ECC we want to have a 1:1 mapping between the raw page
1498          * data on the NAND chip and the view of the NAND core. This is
1499          * necessary to make the NAND_CMD_RNDOUT read the data it expects.
1500          * To accomplish this we have to write the data in the order the controller
1501          * reads it. This is reversed in copy_page_from_sram() below.
1502          *
1503          * buf_len can either be the full page including the OOB or user data only.
1504          * When it's user data only make sure that we fill up the rest of the
1505          * SRAM with 0xff.
1506          */
1507         for (i = 0; i < no_subpages; i++) {
1508                 int now = min(buf_len, 512);
1509
1510                 if (now)
1511                         memcpy16_toio(host->main_area0 + i * 512, buf, now);
1512
1513                 if (now < 512)
1514                         memff16_toio(host->main_area0 + i * 512 + now, 512 - now);
1515
1516                 buf += 512;
1517                 buf_len -= now;
1518
1519                 now = min(buf_len, oob_per_subpage);
1520                 if (now)
1521                         memcpy16_toio(host->spare0 + i * host->devtype_data->spare_len,
1522                                       buf, now);
1523
1524                 if (now < oob_per_subpage)
1525                         memff16_toio(host->spare0 + i * host->devtype_data->spare_len + now,
1526                                      oob_per_subpage - now);
1527
1528                 buf += oob_per_subpage;
1529                 buf_len -= now;
1530         }
1531 }
1532
1533 static void copy_page_from_sram(struct mtd_info *mtd)
1534 {
1535         struct nand_chip *this = mtd_to_nand(mtd);
1536         struct mxc_nand_host *host = nand_get_controller_data(this);
1537         void *buf = host->data_buf;
1538         unsigned int no_subpages = mtd->writesize / 512;
1539         int oob_per_subpage, i;
1540
1541         /* mtd->writesize is not set during ident scanning */
1542         if (!no_subpages)
1543                 no_subpages = 1;
1544
1545         oob_per_subpage = (mtd->oobsize / no_subpages) & ~1;
1546
1547         for (i = 0; i < no_subpages; i++) {
1548                 memcpy16_fromio(buf, host->main_area0 + i * 512, 512);
1549                 buf += 512;
1550
1551                 memcpy16_fromio(buf, host->spare0 + i * host->devtype_data->spare_len,
1552                                 oob_per_subpage);
1553                 buf += oob_per_subpage;
1554         }
1555 }
1556
1557 static int mxcnd_do_exec_op(struct nand_chip *chip,
1558                             const struct nand_subop *op)
1559 {
1560         struct mxc_nand_host *host = nand_get_controller_data(chip);
1561         struct mtd_info *mtd = nand_to_mtd(chip);
1562         int i, j, buf_len;
1563         void *buf_read = NULL;
1564         const void *buf_write = NULL;
1565         const struct nand_op_instr *instr;
1566         bool readid = false;
1567         bool statusreq = false;
1568
1569         for (i = 0; i < op->ninstrs; i++) {
1570                 instr = &op->instrs[i];
1571
1572                 switch (instr->type) {
1573                 case NAND_OP_WAITRDY_INSTR:
1574                         /* NFC handles R/B internally, nothing to do here */
1575                         break;
1576                 case NAND_OP_CMD_INSTR:
1577                         host->devtype_data->send_cmd(host, instr->ctx.cmd.opcode, true);
1578
1579                         if (instr->ctx.cmd.opcode == NAND_CMD_READID)
1580                                 readid = true;
1581                         if (instr->ctx.cmd.opcode == NAND_CMD_STATUS)
1582                                 statusreq = true;
1583
1584                         break;
1585                 case NAND_OP_ADDR_INSTR:
1586                         for (j = 0; j < instr->ctx.addr.naddrs; j++) {
1587                                 bool islast = j == instr->ctx.addr.naddrs - 1;
1588                                 host->devtype_data->send_addr(host, instr->ctx.addr.addrs[j], islast);
1589                         }
1590                         break;
1591                 case NAND_OP_DATA_OUT_INSTR:
1592                         buf_write = instr->ctx.data.buf.out;
1593                         buf_len = instr->ctx.data.len;
1594
1595                         if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1596                                 memcpy32_toio(host->main_area0, buf_write, buf_len);
1597                         else
1598                                 copy_page_to_sram(mtd, buf_write, buf_len);
1599
1600                         host->devtype_data->send_page(mtd, NFC_INPUT);
1601
1602                         break;
1603                 case NAND_OP_DATA_IN_INSTR:
1604
1605                         buf_read = instr->ctx.data.buf.in;
1606                         buf_len = instr->ctx.data.len;
1607
1608                         if (readid) {
1609                                 host->devtype_data->send_read_id(host);
1610                                 readid = false;
1611
1612                                 memcpy32_fromio(host->data_buf, host->main_area0, buf_len * 2);
1613
1614                                 if (chip->options & NAND_BUSWIDTH_16) {
1615                                         u8 *bufr = buf_read;
1616                                         u16 *bufw = host->data_buf;
1617                                         for (j = 0; j < buf_len; j++)
1618                                                 bufr[j] = bufw[j];
1619                                 } else {
1620                                         memcpy(buf_read, host->data_buf, buf_len);
1621                                 }
1622                                 break;
1623                         }
1624
1625                         if (statusreq) {
1626                                 *(u8*)buf_read = host->devtype_data->get_dev_status(host);
1627                                 statusreq = false;
1628                                 break;
1629                         }
1630
1631                         host->devtype_data->read_page(chip);
1632
1633                         if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
1634                                 if (IS_ALIGNED(buf_len, 4)) {
1635                                         memcpy32_fromio(buf_read, host->main_area0, buf_len);
1636                                 } else {
1637                                         memcpy32_fromio(host->data_buf, host->main_area0, mtd->writesize);
1638                                         memcpy(buf_read, host->data_buf, buf_len);
1639                                 }
1640                         } else {
1641                                 copy_page_from_sram(mtd);
1642                                 memcpy(buf_read, host->data_buf, buf_len);
1643                         }
1644
1645                         break;
1646                 }
1647         }
1648
1649         return 0;
1650 }
1651
1652 #define MAX_DATA_SIZE   (4096 + 512)
1653
1654 static const struct nand_op_parser mxcnd_op_parser = NAND_OP_PARSER(
1655         NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op,
1656                                NAND_OP_PARSER_PAT_CMD_ELEM(false),
1657                                NAND_OP_PARSER_PAT_ADDR_ELEM(true, 7),
1658                                NAND_OP_PARSER_PAT_CMD_ELEM(true),
1659                                NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
1660                                NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, MAX_DATA_SIZE)),
1661         NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op,
1662                                NAND_OP_PARSER_PAT_CMD_ELEM(false),
1663                                NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7),
1664                                NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_DATA_SIZE),
1665                                NAND_OP_PARSER_PAT_CMD_ELEM(false),
1666                                NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
1667         NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op,
1668                                NAND_OP_PARSER_PAT_CMD_ELEM(false),
1669                                NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7),
1670                                NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_DATA_SIZE),
1671                                NAND_OP_PARSER_PAT_CMD_ELEM(true),
1672                                NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
1673         );
1674
1675 static int mxcnd_exec_op(struct nand_chip *chip,
1676                          const struct nand_operation *op, bool check_only)
1677 {
1678         return nand_op_parser_exec_op(chip, &mxcnd_op_parser,
1679                                       op, check_only);
1680 }
1681
1682 static const struct nand_controller_ops mxcnd_controller_ops = {
1683         .attach_chip = mxcnd_attach_chip,
1684         .setup_interface = mxcnd_setup_interface,
1685         .exec_op = mxcnd_exec_op,
1686 };
1687
1688 static int mxcnd_probe(struct platform_device *pdev)
1689 {
1690         struct nand_chip *this;
1691         struct mtd_info *mtd;
1692         struct mxc_nand_host *host;
1693         int err = 0;
1694
1695         /* Allocate memory for MTD device structure and private data */
1696         host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1697                         GFP_KERNEL);
1698         if (!host)
1699                 return -ENOMEM;
1700
1701         /* allocate a temporary buffer for the nand_scan_ident() */
1702         host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1703         if (!host->data_buf)
1704                 return -ENOMEM;
1705
1706         host->dev = &pdev->dev;
1707         /* structures must be linked */
1708         this = &host->nand;
1709         mtd = nand_to_mtd(this);
1710         mtd->dev.parent = &pdev->dev;
1711         mtd->name = DRIVER_NAME;
1712
1713         /* 50 us command delay time */
1714         this->legacy.chip_delay = 5;
1715
1716         nand_set_controller_data(this, host);
1717         nand_set_flash_node(this, pdev->dev.of_node);
1718
1719         host->clk = devm_clk_get(&pdev->dev, NULL);
1720         if (IS_ERR(host->clk))
1721                 return PTR_ERR(host->clk);
1722
1723         host->devtype_data = device_get_match_data(&pdev->dev);
1724
1725         if (!host->devtype_data->setup_interface)
1726                 this->options |= NAND_KEEP_TIMINGS;
1727
1728         if (host->devtype_data->needs_ip) {
1729                 host->regs_ip = devm_platform_ioremap_resource(pdev, 0);
1730                 if (IS_ERR(host->regs_ip))
1731                         return PTR_ERR(host->regs_ip);
1732
1733                 host->base = devm_platform_ioremap_resource(pdev, 1);
1734         } else {
1735                 host->base = devm_platform_ioremap_resource(pdev, 0);
1736         }
1737
1738         if (IS_ERR(host->base))
1739                 return PTR_ERR(host->base);
1740
1741         host->main_area0 = host->base;
1742
1743         if (host->devtype_data->regs_offset)
1744                 host->regs = host->base + host->devtype_data->regs_offset;
1745         host->spare0 = host->base + host->devtype_data->spare0_offset;
1746         if (host->devtype_data->axi_offset)
1747                 host->regs_axi = host->base + host->devtype_data->axi_offset;
1748
1749         this->legacy.select_chip = host->devtype_data->select_chip;
1750
1751         init_completion(&host->op_completion);
1752
1753         host->irq = platform_get_irq(pdev, 0);
1754         if (host->irq < 0)
1755                 return host->irq;
1756
1757         /*
1758          * Use host->devtype_data->irq_control() here instead of irq_control()
1759          * because we must not disable_irq_nosync without having requested the
1760          * irq.
1761          */
1762         host->devtype_data->irq_control(host, 0);
1763
1764         err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1765                         0, DRIVER_NAME, host);
1766         if (err)
1767                 return err;
1768
1769         err = clk_prepare_enable(host->clk);
1770         if (err)
1771                 return err;
1772         host->clk_act = 1;
1773
1774         /*
1775          * Now that we "own" the interrupt make sure the interrupt mask bit is
1776          * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1777          * on this machine.
1778          */
1779         if (host->devtype_data->irqpending_quirk) {
1780                 disable_irq_nosync(host->irq);
1781                 host->devtype_data->irq_control(host, 1);
1782         }
1783
1784         /* Scan the NAND device */
1785         this->legacy.dummy_controller.ops = &mxcnd_controller_ops;
1786         err = nand_scan(this, is_imx25_nfc(host) ? 4 : 1);
1787         if (err)
1788                 goto escan;
1789
1790         /* Register the partitions */
1791         err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
1792         if (err)
1793                 goto cleanup_nand;
1794
1795         platform_set_drvdata(pdev, host);
1796
1797         return 0;
1798
1799 cleanup_nand:
1800         nand_cleanup(this);
1801 escan:
1802         if (host->clk_act)
1803                 clk_disable_unprepare(host->clk);
1804
1805         return err;
1806 }
1807
1808 static void mxcnd_remove(struct platform_device *pdev)
1809 {
1810         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1811         struct nand_chip *chip = &host->nand;
1812         int ret;
1813
1814         ret = mtd_device_unregister(nand_to_mtd(chip));
1815         WARN_ON(ret);
1816         nand_cleanup(chip);
1817         if (host->clk_act)
1818                 clk_disable_unprepare(host->clk);
1819 }
1820
1821 static struct platform_driver mxcnd_driver = {
1822         .driver = {
1823                    .name = DRIVER_NAME,
1824                    .of_match_table = mxcnd_dt_ids,
1825         },
1826         .probe = mxcnd_probe,
1827         .remove = mxcnd_remove,
1828 };
1829 module_platform_driver(mxcnd_driver);
1830
1831 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1832 MODULE_DESCRIPTION("MXC NAND MTD driver");
1833 MODULE_LICENSE("GPL");