drivers/mmc/host/sdhci-esdhc-imx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Freescale eSDHC i.MX controller driver for the platform bus.
   4  *
   5  * derived from the OF-version.
   6  *
   7  * Copyright (c) 2010 Pengutronix e.K.
   8  *   Author: Wolfram Sang <[email protected]>
   9  */
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/module.h>
  18 #include <linux/slab.h>
  19 #include <linux/pm_qos.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/mmc.h>
  22 #include <linux/mmc/sdio.h>
  23 #include <linux/mmc/slot-gpio.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pinctrl/consumer.h>
  27 #include <linux/pm_runtime.h>
  28 #include "sdhci-cqhci.h"
  29 #include "sdhci-pltfm.h"
  30 #include "sdhci-esdhc.h"
  31 #include "cqhci.h"
  32
  33 #define ESDHC_SYS_CTRL_DTOCV_MASK       GENMASK(19, 16)
  34 #define ESDHC_SYS_CTRL_IPP_RST_N        BIT(23)
  35 #define ESDHC_CTRL_D3CD                 0x08
  36 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
  37 /* VENDOR SPEC register */
  38 #define ESDHC_VENDOR_SPEC               0xc0
  39 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  40 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  41 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  42 #define ESDHC_DEBUG_SEL_AND_STATUS_REG          0xc2
  43 #define ESDHC_DEBUG_SEL_REG                     0xc3
  44 #define ESDHC_DEBUG_SEL_MASK                    0xf
  45 #define ESDHC_DEBUG_SEL_CMD_STATE               1
  46 #define ESDHC_DEBUG_SEL_DATA_STATE              2
  47 #define ESDHC_DEBUG_SEL_TRANS_STATE             3
  48 #define ESDHC_DEBUG_SEL_DMA_STATE               4
  49 #define ESDHC_DEBUG_SEL_ADMA_STATE              5
  50 #define ESDHC_DEBUG_SEL_FIFO_STATE              6
  51 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE        7
  52 #define ESDHC_WTMK_LVL                  0x44
  53 #define  ESDHC_WTMK_DEFAULT_VAL         0x10401040
  54 #define  ESDHC_WTMK_LVL_RD_WML_MASK     0x000000FF
  55 #define  ESDHC_WTMK_LVL_RD_WML_SHIFT    0
  56 #define  ESDHC_WTMK_LVL_WR_WML_MASK     0x00FF0000
  57 #define  ESDHC_WTMK_LVL_WR_WML_SHIFT    16
  58 #define  ESDHC_WTMK_LVL_WML_VAL_DEF     64
  59 #define  ESDHC_WTMK_LVL_WML_VAL_MAX     128
  60 #define ESDHC_MIX_CTRL                  0x48
  61 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  62 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  63 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  64 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  65 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN    (1 << 24)
  66 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  67 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
  68 #define  ESDHC_MIX_CTRL_HS400_ES_EN     (1 << 27)
  69 /* Bits 3 and 6 are not SDHCI standard definitions */
  70 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  71 /* Tuning bits */
  72 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  73
  74 /* dll control register */
  75 #define ESDHC_DLL_CTRL                  0x60
  76 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  77 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  78
  79 /* tune control register */
  80 #define ESDHC_TUNE_CTRL_STATUS          0x68
  81 #define  ESDHC_TUNE_CTRL_STEP           1
  82 #define  ESDHC_TUNE_CTRL_MIN            0
  83 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  84
  85 /* strobe dll register */
  86 #define ESDHC_STROBE_DLL_CTRL           0x70
  87 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
  88 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
  89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT    0x7
  90 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
  91 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT    (4 << 20)
  92
  93 #define ESDHC_STROBE_DLL_STATUS         0x74
  94 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
  95 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
  96
  97 #define ESDHC_VEND_SPEC2                0xc8
  98 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ    (1 << 8)
  99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN      (1 << 4)
 100 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN      (0 << 4)
 101 #define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN      (2 << 4)
 102 #define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN       (1 << 6)
 103 #define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK    (7 << 4)
 104
 105 #define ESDHC_TUNING_CTRL               0xcc
 106 #define ESDHC_STD_TUNING_EN             (1 << 24)
 107 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
 108 #define ESDHC_TUNING_START_TAP_DEFAULT  0x1
 109 #define ESDHC_TUNING_START_TAP_MASK     0x7f
 110 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE      (1 << 7)
 111 #define ESDHC_TUNING_STEP_DEFAULT       0x1
 112 #define ESDHC_TUNING_STEP_MASK          0x00070000
 113 #define ESDHC_TUNING_STEP_SHIFT         16
 114
 115 /* pinctrl state */
 116 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
 117 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
 118
 119 /*
 120  * Our interpretation of the SDHCI_HOST_CONTROL register
 121  */
 122 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
 123 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
 124 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 125 #define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK)
 126
 127 /*
 128  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
 129  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 130  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 131  * Define this macro DMA error INT for fsl eSDHC
 132  */
 133 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
 134
 135 /* the address offset of CQHCI */
 136 #define ESDHC_CQHCI_ADDR_OFFSET         0x100
 137
 138 /*
 139  * The CMDTYPE of the CMD register (offset 0xE) should be set to
 140  * "11" when the STOP CMD12 is issued on imx53 to abort one
 141  * open ended multi-blk IO. Otherwise the TC INT wouldn't
 142  * be generated.
 143  * In exact block transfer, the controller doesn't complete the
 144  * operations automatically as required at the end of the
 145  * transfer and remains on hold if the abort command is not sent.
 146  * As a result, the TC flag is not asserted and SW received timeout
 147  * exception. Bit1 of Vendor Spec register is used to fix it.
 148  */
 149 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 150 /*
 151  * The flag tells that the ESDHC controller is an USDHC block that is
 152  * integrated on the i.MX6 series.
 153  */
 154 #define ESDHC_FLAG_USDHC                BIT(3)
 155 /* The IP supports manual tuning process */
 156 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 157 /* The IP supports standard tuning process */
 158 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 159 /* The IP has SDHCI_CAPABILITIES_1 register */
 160 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 161 /*
 162  * The IP has erratum ERR004536
 163  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 164  * when reading data from the card
 165  * This flag is also set for i.MX25 and i.MX35 in order to get
 166  * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
 167  */
 168 #define ESDHC_FLAG_ERR004536            BIT(7)
 169 /* The IP supports HS200 mode */
 170 #define ESDHC_FLAG_HS200                BIT(8)
 171 /* The IP supports HS400 mode */
 172 #define ESDHC_FLAG_HS400                BIT(9)
 173 /*
 174  * The IP has errata ERR010450
 175  * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card
 176  * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
 177  */
 178 #define ESDHC_FLAG_ERR010450            BIT(10)
 179 /* The IP supports HS400ES mode */
 180 #define ESDHC_FLAG_HS400_ES             BIT(11)
 181 /* The IP has Host Controller Interface for Command Queuing */
 182 #define ESDHC_FLAG_CQHCI                BIT(12)
 183 /* need request pmqos during low power */
 184 #define ESDHC_FLAG_PMQOS                BIT(13)
 185 /* The IP state got lost in low power mode */
 186 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE         BIT(14)
 187 /* The IP lost clock rate in PM_RUNTIME */
 188 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME  BIT(15)
 189 /*
 190  * The IP do not support the ACMD23 feature completely when use ADMA mode.
 191  * In ADMA mode, it only use the 16 bit block count of the register 0x4
 192  * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
 193  * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
 194  * write operation in RPMB, because RPMB reliable write need to set the bit31
 195  * of the CMD23's argument.
 196  * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
 197  * do not has this limitation. so when these SoC use ADMA mode, it need to
 198  * disable the ACMD23 feature.
 199  */
 200 #define ESDHC_FLAG_BROKEN_AUTO_CMD23    BIT(16)
 201
 202 /* ERR004536 is not applicable for the IP  */
 203 #define ESDHC_FLAG_SKIP_ERR004536       BIT(17)
 204
 205 /* The IP does not have GPIO CD wake capabilities */
 206 #define ESDHC_FLAG_SKIP_CD_WAKE         BIT(18)
 207
 208 enum wp_types {
 209         ESDHC_WP_NONE,          /* no WP, neither controller nor gpio */
 210         ESDHC_WP_CONTROLLER,    /* mmc controller internal WP */
 211         ESDHC_WP_GPIO,          /* external gpio pin for WP */
 212 };
 213
 214 enum cd_types {
 215         ESDHC_CD_NONE,          /* no CD, neither controller nor gpio */
 216         ESDHC_CD_CONTROLLER,    /* mmc controller internal CD */
 217         ESDHC_CD_GPIO,          /* external gpio pin for CD */
 218         ESDHC_CD_PERMANENT,     /* no CD, card permanently wired to host */
 219 };
 220
 221 /*
 222  * struct esdhc_platform_data - platform data for esdhc on i.MX
 223  *
 224  * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
 225  *
 226  * @wp_type:    type of write_protect method (see wp_types enum above)
 227  * @cd_type:    type of card_detect method (see cd_types enum above)
 228  */
 229
 230 struct esdhc_platform_data {
 231         enum wp_types wp_type;
 232         enum cd_types cd_type;
 233         int max_bus_width;
 234         unsigned int delay_line;
 235         unsigned int tuning_step;       /* The delay cell steps in tuning procedure */
 236         unsigned int tuning_start_tap;  /* The start delay cell point in tuning procedure */
 237         unsigned int strobe_dll_delay_target;   /* The delay cell for strobe pad (read clock) */
 238 };
 239
 240 struct esdhc_soc_data {
 241         u32 flags;
 242         u32 quirks;
 243 };
 244
 245 static const struct esdhc_soc_data esdhc_imx25_data = {
 246         .flags = ESDHC_FLAG_ERR004536,
 247 };
 248
 249 static const struct esdhc_soc_data esdhc_imx35_data = {
 250         .flags = ESDHC_FLAG_ERR004536,
 251 };
 252
 253 static const struct esdhc_soc_data esdhc_imx51_data = {
 254         .flags = 0,
 255 };
 256
 257 static const struct esdhc_soc_data esdhc_imx53_data = {
 258         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 259 };
 260
 261 static const struct esdhc_soc_data usdhc_imx6q_data = {
 262         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
 263                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 264 };
 265
 266 static const struct esdhc_soc_data usdhc_imx6sl_data = {
 267         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 268                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
 269                         | ESDHC_FLAG_HS200
 270                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 271 };
 272
 273 static const struct esdhc_soc_data usdhc_imx6sll_data = {
 274         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 275                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 276                         | ESDHC_FLAG_HS400
 277                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 278 };
 279
 280 static const struct esdhc_soc_data usdhc_imx6sx_data = {
 281         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 282                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 283                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 284                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 285 };
 286
 287 static const struct esdhc_soc_data usdhc_imx6ull_data = {
 288         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 289                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 290                         | ESDHC_FLAG_ERR010450
 291                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 292 };
 293
 294 static const struct esdhc_soc_data usdhc_imx7d_data = {
 295         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 296                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 297                         | ESDHC_FLAG_HS400
 298                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 299                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 300 };
 301
 302 static struct esdhc_soc_data usdhc_s32g2_data = {
 303         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
 304                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 305                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 306                         | ESDHC_FLAG_SKIP_ERR004536 | ESDHC_FLAG_SKIP_CD_WAKE,
 307         .quirks = SDHCI_QUIRK_NO_LED,
 308 };
 309
 310 static struct esdhc_soc_data usdhc_imx7ulp_data = {
 311         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 312                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 313                         | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
 314                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 315         .quirks = SDHCI_QUIRK_NO_LED,
 316 };
 317 static struct esdhc_soc_data usdhc_imxrt1050_data = {
 318         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 319                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
 320         .quirks = SDHCI_QUIRK_NO_LED,
 321 };
 322
 323 static struct esdhc_soc_data usdhc_imx8qxp_data = {
 324         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 325                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 326                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 327                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 328                         | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
 329         .quirks = SDHCI_QUIRK_NO_LED,
 330 };
 331
 332 static struct esdhc_soc_data usdhc_imx8mm_data = {
 333         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 334                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 335                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 336                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 337         .quirks = SDHCI_QUIRK_NO_LED,
 338 };
 339
 340 struct pltfm_imx_data {
 341         u32 scratchpad;
 342         struct pinctrl *pinctrl;
 343         struct pinctrl_state *pins_100mhz;
 344         struct pinctrl_state *pins_200mhz;
 345         const struct esdhc_soc_data *socdata;
 346         struct esdhc_platform_data boarddata;
 347         struct clk *clk_ipg;
 348         struct clk *clk_ahb;
 349         struct clk *clk_per;
 350         unsigned int actual_clock;
 351
 352         /*
 353          * USDHC has one limition, require the SDIO device a different
 354          * register setting. Driver has to recognize card type during
 355          * the card init, but at this stage, mmc_host->card is not
 356          * available. So involve this field to save the card type
 357          * during card init through usdhc_init_card().
 358          */
 359         unsigned int init_card_type;
 360
 361         enum {
 362                 NO_CMD_PENDING,      /* no multiblock command pending */
 363                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 364                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 365         } multiblock_status;
 366         u32 is_ddr;
 367         struct pm_qos_request pm_qos_req;
 368 };
 369
 370 static const struct of_device_id imx_esdhc_dt_ids[] = {
 371         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 372         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 373         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 374         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 375         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
 376         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 377         { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
 378         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 379         { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
 380         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
 381         { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
 382         { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
 383         { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
 384         { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
 385         { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
 386         { /* sentinel */ }
 387 };
 388 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 389
 390 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 391 {
 392         return data->socdata == &esdhc_imx25_data;
 393 }
 394
 395 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 396 {
 397         return data->socdata == &esdhc_imx53_data;
 398 }
 399
 400 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 401 {
 402         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 403 }
 404
 405 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 406 {
 407         void __iomem *base = host->ioaddr + (reg & ~0x3);
 408         u32 shift = (reg & 0x3) * 8;
 409
 410         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 411 }
 412
 413 #define DRIVER_NAME "sdhci-esdhc-imx"
 414 #define ESDHC_IMX_DUMP(f, x...) \
 415         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
 416 static void esdhc_dump_debug_regs(struct sdhci_host *host)
 417 {
 418         int i;
 419         char *debug_status[7] = {
 420                                  "cmd debug status",
 421                                  "data debug status",
 422                                  "trans debug status",
 423                                  "dma debug status",
 424                                  "adma debug status",
 425                                  "fifo debug status",
 426                                  "async fifo debug status"
 427         };
 428
 429         ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
 430         for (i = 0; i < 7; i++) {
 431                 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
 432                         ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
 433                 ESDHC_IMX_DUMP("%s:  0x%04x\n", debug_status[i],
 434                         readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
 435         }
 436
 437         esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
 438
 439 }
 440
 441 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
 442 {
 443         u32 present_state;
 444         int ret;
 445
 446         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
 447                                 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
 448         if (ret == -ETIMEDOUT)
 449                 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
 450 }
 451
 452 /* Enable the auto tuning circuit to check the CMD line and BUS line */
 453 static inline void usdhc_auto_tuning_mode_sel_and_en(struct sdhci_host *host)
 454 {
 455         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 456         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 457         u32 buswidth, auto_tune_buswidth;
 458         u32 reg;
 459
 460         buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL));
 461
 462         switch (buswidth) {
 463         case ESDHC_CTRL_8BITBUS:
 464                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN;
 465                 break;
 466         case ESDHC_CTRL_4BITBUS:
 467                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN;
 468                 break;
 469         default:        /* 1BITBUS */
 470                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
 471                 break;
 472         }
 473
 474         /*
 475          * For USDHC, auto tuning circuit can not handle the async sdio
 476          * device interrupt correctly. When sdio device use 4 data lines,
 477          * async sdio interrupt will use the shared DAT[1], if enable auto
 478          * tuning circuit check these 4 data lines, include the DAT[1],
 479          * this circuit will detect this interrupt, take this as a data on
 480          * DAT[1], and adjust the delay cell wrongly.
 481          * This is the hardware design limitation, to avoid this, for sdio
 482          * device, config the auto tuning circuit only check DAT[0] and CMD
 483          * line.
 484          */
 485         if (imx_data->init_card_type == MMC_TYPE_SDIO)
 486                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
 487
 488         esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK,
 489                         auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN,
 490                         ESDHC_VEND_SPEC2);
 491
 492         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 493         reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 494         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 495 }
 496
 497 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 498 {
 499         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 500         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 501         u32 val = readl(host->ioaddr + reg);
 502
 503         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 504                 u32 fsl_prss = val;
 505                 /* save the least 20 bits */
 506                 val = fsl_prss & 0x000FFFFF;
 507                 /* move dat[0-3] bits */
 508                 val |= (fsl_prss & 0x0F000000) >> 4;
 509                 /* move cmd line bit */
 510                 val |= (fsl_prss & 0x00800000) << 1;
 511         }
 512
 513         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 514                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 515                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 516                         val &= 0xffff0000;
 517
 518                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 519                  * ADMA2 capability of esdhc, but this bit is messed up on
 520                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 521                  * don't actually support ADMA2). So set the BROKEN_ADMA
 522                  * quirk on MX25/35 platforms.
 523                  */
 524
 525                 if (val & SDHCI_CAN_DO_ADMA1) {
 526                         val &= ~SDHCI_CAN_DO_ADMA1;
 527                         val |= SDHCI_CAN_DO_ADMA2;
 528                 }
 529         }
 530
 531         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 532                 if (esdhc_is_usdhc(imx_data)) {
 533                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 534                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 535                         else
 536                                 /* imx6q/dl does not have cap_1 register, fake one */
 537                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 538                                         | SDHCI_SUPPORT_SDR50
 539                                         | SDHCI_USE_SDR50_TUNING
 540                                         | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
 541                                                      SDHCI_TUNING_MODE_3);
 542
 543                         /*
 544                          * Do not advertise faster UHS modes if there are no
 545                          * pinctrl states for 100MHz/200MHz.
 546                          */
 547                         if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
 548                                 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
 549                         if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
 550                                 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
 551                 }
 552         }
 553
 554         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 555                 val = 0;
 556                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
 557                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
 558                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
 559         }
 560
 561         if (unlikely(reg == SDHCI_INT_STATUS)) {
 562                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 563                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 564                         val |= SDHCI_INT_ADMA_ERROR;
 565                 }
 566
 567                 /*
 568                  * mask off the interrupt we get in response to the manually
 569                  * sent CMD12
 570                  */
 571                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 572                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 573                         val &= ~SDHCI_INT_RESPONSE;
 574                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 575                                                    SDHCI_INT_STATUS);
 576                         imx_data->multiblock_status = NO_CMD_PENDING;
 577                 }
 578         }
 579
 580         return val;
 581 }
 582
 583 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 584 {
 585         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 586         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 587         u32 data;
 588
 589         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
 590                         reg == SDHCI_INT_STATUS)) {
 591                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
 592                         /*
 593                          * Clear and then set D3CD bit to avoid missing the
 594                          * card interrupt. This is an eSDHC controller problem
 595                          * so we need to apply the following workaround: clear
 596                          * and set D3CD bit will make eSDHC re-sample the card
 597                          * interrupt. In case a card interrupt was lost,
 598                          * re-sample it by the following steps.
 599                          */
 600                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 601                         data &= ~ESDHC_CTRL_D3CD;
 602                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 603                         data |= ESDHC_CTRL_D3CD;
 604                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 605                 }
 606
 607                 if (val & SDHCI_INT_ADMA_ERROR) {
 608                         val &= ~SDHCI_INT_ADMA_ERROR;
 609                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 610                 }
 611         }
 612
 613         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 614                                 && (reg == SDHCI_INT_STATUS)
 615                                 && (val & SDHCI_INT_DATA_END))) {
 616                         u32 v;
 617                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 618                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 619                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 620
 621                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 622                         {
 623                                 /* send a manual CMD12 with RESPTYP=none */
 624                                 data = MMC_STOP_TRANSMISSION << 24 |
 625                                        SDHCI_CMD_ABORTCMD << 16;
 626                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 627                                 imx_data->multiblock_status = WAIT_FOR_INT;
 628                         }
 629         }
 630
 631         writel(val, host->ioaddr + reg);
 632 }
 633
 634 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 635 {
 636         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 637         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 638         u16 ret = 0;
 639         u32 val;
 640
 641         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 642                 reg ^= 2;
 643                 if (esdhc_is_usdhc(imx_data)) {
 644                         /*
 645                          * The usdhc register returns a wrong host version.
 646                          * Correct it here.
 647                          */
 648                         return SDHCI_SPEC_300;
 649                 }
 650         }
 651
 652         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 653                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 654                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 655                         ret |= SDHCI_CTRL_VDD_180;
 656
 657                 if (esdhc_is_usdhc(imx_data)) {
 658                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 659                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 660                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 661                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 662                                 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 663                 }
 664
 665                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 666                         ret |= SDHCI_CTRL_EXEC_TUNING;
 667                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 668                         ret |= SDHCI_CTRL_TUNED_CLK;
 669
 670                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 671
 672                 return ret;
 673         }
 674
 675         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 676                 if (esdhc_is_usdhc(imx_data)) {
 677                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 678                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 679                         /* Swap AC23 bit */
 680                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 681                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 682                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 683                         }
 684                 } else {
 685                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 686                 }
 687
 688                 return ret;
 689         }
 690
 691         return readw(host->ioaddr + reg);
 692 }
 693
 694 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 695 {
 696         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 697         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 698         u32 new_val = 0;
 699
 700         switch (reg) {
 701         case SDHCI_CLOCK_CONTROL:
 702                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 703                 if (val & SDHCI_CLOCK_CARD_EN)
 704                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 705                 else
 706                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 707                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 708                 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
 709                         esdhc_wait_for_card_clock_gate_off(host);
 710                 return;
 711         case SDHCI_HOST_CONTROL2:
 712                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 713                 if (val & SDHCI_CTRL_VDD_180)
 714                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 715                 else
 716                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 717                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 718                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 719                         u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 720                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 721                         if (val & SDHCI_CTRL_TUNED_CLK) {
 722                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 723                         } else {
 724                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 725                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 726                         }
 727
 728                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 729                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 730                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 731                         } else {
 732                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 733                         }
 734
 735                         writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 736                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 737                 }
 738                 return;
 739         case SDHCI_TRANSFER_MODE:
 740                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 741                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 742                                 && (host->cmd->data->blocks > 1)
 743                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 744                         u32 v;
 745                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 746                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 747                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 748                 }
 749
 750                 if (esdhc_is_usdhc(imx_data)) {
 751                         u32 wml;
 752                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 753                         /* Swap AC23 bit */
 754                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 755                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 756                                 val |= ESDHC_MIX_CTRL_AC23EN;
 757                         }
 758                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 759                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 760
 761                         /* Set watermark levels for PIO access to maximum value
 762                          * (128 words) to accommodate full 512 bytes buffer.
 763                          * For DMA access restore the levels to default value.
 764                          */
 765                         m = readl(host->ioaddr + ESDHC_WTMK_LVL);
 766                         if (val & SDHCI_TRNS_DMA) {
 767                                 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
 768                         } else {
 769                                 u8 ctrl;
 770                                 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
 771
 772                                 /*
 773                                  * Since already disable DMA mode, so also need
 774                                  * to clear the DMASEL. Otherwise, for standard
 775                                  * tuning, when send tuning command, usdhc will
 776                                  * still prefetch the ADMA script from wrong
 777                                  * DMA address, then we will see IOMMU report
 778                                  * some error which show lack of TLB mapping.
 779                                  */
 780                                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 781                                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 782                                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 783                         }
 784                         m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
 785                                ESDHC_WTMK_LVL_WR_WML_MASK);
 786                         m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
 787                              (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
 788                         writel(m, host->ioaddr + ESDHC_WTMK_LVL);
 789                 } else {
 790                         /*
 791                          * Postpone this write, we must do it together with a
 792                          * command write that is down below.
 793                          */
 794                         imx_data->scratchpad = val;
 795                 }
 796                 return;
 797         case SDHCI_COMMAND:
 798                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 799                         val |= SDHCI_CMD_ABORTCMD;
 800
 801                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 802                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 803                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 804
 805                 if (esdhc_is_usdhc(imx_data))
 806                         writel(val << 16,
 807                                host->ioaddr + SDHCI_TRANSFER_MODE);
 808                 else
 809                         writel(val << 16 | imx_data->scratchpad,
 810                                host->ioaddr + SDHCI_TRANSFER_MODE);
 811                 return;
 812         case SDHCI_BLOCK_SIZE:
 813                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 814                 break;
 815         }
 816         esdhc_clrset_le(host, 0xffff, val, reg);
 817 }
 818
 819 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
 820 {
 821         u8 ret;
 822         u32 val;
 823
 824         switch (reg) {
 825         case SDHCI_HOST_CONTROL:
 826                 val = readl(host->ioaddr + reg);
 827
 828                 ret = val & SDHCI_CTRL_LED;
 829                 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
 830                 ret |= (val & ESDHC_CTRL_4BITBUS);
 831                 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
 832                 return ret;
 833         }
 834
 835         return readb(host->ioaddr + reg);
 836 }
 837
 838 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 839 {
 840         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 841         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 842         u32 new_val = 0;
 843         u32 mask;
 844
 845         switch (reg) {
 846         case SDHCI_POWER_CONTROL:
 847                 /*
 848                  * FSL put some DMA bits here
 849                  * If your board has a regulator, code should be here
 850                  */
 851                 return;
 852         case SDHCI_HOST_CONTROL:
 853                 /* FSL messed up here, so we need to manually compose it. */
 854                 new_val = val & SDHCI_CTRL_LED;
 855                 /* ensure the endianness */
 856                 new_val |= ESDHC_HOST_CONTROL_LE;
 857                 /* bits 8&9 are reserved on mx25 */
 858                 if (!is_imx25_esdhc(imx_data)) {
 859                         /* DMA mode bits are shifted */
 860                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 861                 }
 862
 863                 /*
 864                  * Do not touch buswidth bits here. This is done in
 865                  * esdhc_pltfm_bus_width.
 866                  * Do not touch the D3CD bit either which is used for the
 867                  * SDIO interrupt erratum workaround.
 868                  */
 869                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 870
 871                 esdhc_clrset_le(host, mask, new_val, reg);
 872                 return;
 873         case SDHCI_SOFTWARE_RESET:
 874                 if (val & SDHCI_RESET_DATA)
 875                         new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 876                 break;
 877         }
 878         esdhc_clrset_le(host, 0xff, val, reg);
 879
 880         if (reg == SDHCI_SOFTWARE_RESET) {
 881                 if (val & SDHCI_RESET_ALL) {
 882                         /*
 883                          * The esdhc has a design violation to SDHC spec which
 884                          * tells that software reset should not affect card
 885                          * detection circuit. But esdhc clears its SYSCTL
 886                          * register bits [0..2] during the software reset. This
 887                          * will stop those clocks that card detection circuit
 888                          * relies on. To work around it, we turn the clocks on
 889                          * back to keep card detection circuit functional.
 890                          */
 891                         esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 892                         /*
 893                          * The reset on usdhc fails to clear MIX_CTRL register.
 894                          * Do it manually here.
 895                          */
 896                         if (esdhc_is_usdhc(imx_data)) {
 897                                 /*
 898                                  * the tuning bits should be kept during reset
 899                                  */
 900                                 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 901                                 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 902                                                 host->ioaddr + ESDHC_MIX_CTRL);
 903                                 imx_data->is_ddr = 0;
 904                         }
 905                 } else if (val & SDHCI_RESET_DATA) {
 906                         /*
 907                          * The eSDHC DAT line software reset clears at least the
 908                          * data transfer width on i.MX25, so make sure that the
 909                          * Host Control register is unaffected.
 910                          */
 911                         esdhc_clrset_le(host, 0xff, new_val,
 912                                         SDHCI_HOST_CONTROL);
 913                 }
 914         }
 915 }
 916
 917 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 918 {
 919         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 920
 921         return pltfm_host->clock;
 922 }
 923
 924 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 925 {
 926         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 927
 928         return pltfm_host->clock / 256 / 16;
 929 }
 930
 931 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 932                                          unsigned int clock)
 933 {
 934         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 935         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 936         unsigned int host_clock = pltfm_host->clock;
 937         int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
 938         int pre_div = 1;
 939         int div = 1;
 940         int ret;
 941         u32 temp, val;
 942
 943         if (esdhc_is_usdhc(imx_data)) {
 944                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 945                 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 946                         host->ioaddr + ESDHC_VENDOR_SPEC);
 947                 esdhc_wait_for_card_clock_gate_off(host);
 948         }
 949
 950         if (clock == 0) {
 951                 host->mmc->actual_clock = 0;
 952                 return;
 953         }
 954
 955         /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
 956         if (is_imx53_esdhc(imx_data)) {
 957                 /*
 958                  * According to the i.MX53 reference manual, if DLLCTRL[10] can
 959                  * be set, then the controller is eSDHCv3, else it is eSDHCv2.
 960                  */
 961                 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
 962                 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
 963                 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
 964                 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
 965                 if (temp & BIT(10))
 966                         pre_div = 2;
 967         }
 968
 969         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 970         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 971                 | ESDHC_CLOCK_MASK);
 972         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 973
 974         if ((imx_data->socdata->flags & ESDHC_FLAG_ERR010450) &&
 975             (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) {
 976                 unsigned int max_clock;
 977
 978                 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
 979
 980                 clock = min(clock, max_clock);
 981         }
 982
 983         while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
 984                         pre_div < 256)
 985                 pre_div *= 2;
 986
 987         while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
 988                 div++;
 989
 990         host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
 991         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 992                 clock, host->mmc->actual_clock);
 993
 994         pre_div >>= 1;
 995         div--;
 996
 997         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 998         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 999                 | (div << ESDHC_DIVIDER_SHIFT)
1000                 | (pre_div << ESDHC_PREDIV_SHIFT));
1001         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
1002
1003         /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
1004         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
1005                                 (temp & ESDHC_CLOCK_STABLE), 2, 100);
1006         if (ret == -ETIMEDOUT)
1007                 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
1008
1009         if (esdhc_is_usdhc(imx_data)) {
1010                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
1011                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1012                         host->ioaddr + ESDHC_VENDOR_SPEC);
1013         }
1014
1015 }
1016
1017 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
1018 {
1019         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1020         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1021         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1022
1023         switch (boarddata->wp_type) {
1024         case ESDHC_WP_GPIO:
1025                 return mmc_gpio_get_ro(host->mmc);
1026         case ESDHC_WP_CONTROLLER:
1027                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
1028                                SDHCI_WRITE_PROTECT);
1029         case ESDHC_WP_NONE:
1030                 break;
1031         }
1032
1033         return -ENOSYS;
1034 }
1035
1036 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
1037 {
1038         u32 ctrl;
1039
1040         switch (width) {
1041         case MMC_BUS_WIDTH_8:
1042                 ctrl = ESDHC_CTRL_8BITBUS;
1043                 break;
1044         case MMC_BUS_WIDTH_4:
1045                 ctrl = ESDHC_CTRL_4BITBUS;
1046                 break;
1047         default:
1048                 ctrl = 0;
1049                 break;
1050         }
1051
1052         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
1053                         SDHCI_HOST_CONTROL);
1054 }
1055
1056 static void esdhc_reset_tuning(struct sdhci_host *host)
1057 {
1058         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1059         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1060         u32 ctrl;
1061         int ret;
1062
1063         /* Reset the tuning circuit */
1064         if (esdhc_is_usdhc(imx_data)) {
1065                 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1066                 ctrl &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1067                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1068                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1069                         ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1070                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1071                         writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1072                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1073                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1074                         ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1075                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1076                         ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1077                         writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1078                         /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
1079                         ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1080                                 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
1081                         if (ret == -ETIMEDOUT)
1082                                 dev_warn(mmc_dev(host->mmc),
1083                                  "Warning! clear execute tuning bit failed\n");
1084                         /*
1085                          * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
1086                          * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
1087                          * will finally make sure the normal data transfer logic correct.
1088                          */
1089                         ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1090                         ctrl |= SDHCI_INT_DATA_AVAIL;
1091                         writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1092                 }
1093         }
1094 }
1095
1096 static void usdhc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1097 {
1098         struct sdhci_host *host = mmc_priv(mmc);
1099         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1100         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1101
1102         imx_data->init_card_type = card->type;
1103 }
1104
1105 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1106 {
1107         struct sdhci_host *host = mmc_priv(mmc);
1108         int err;
1109
1110         /*
1111          * i.MX uSDHC internally already uses a fixed optimized timing for
1112          * DDR50, normally does not require tuning for DDR50 mode.
1113          */
1114         if (host->timing == MMC_TIMING_UHS_DDR50)
1115                 return 0;
1116
1117         /*
1118          * Reset tuning circuit logic. If not, the previous tuning result
1119          * will impact current tuning, make current tuning can't set the
1120          * correct delay cell.
1121          */
1122         esdhc_reset_tuning(host);
1123         err = sdhci_execute_tuning(mmc, opcode);
1124         /* If tuning done, enable auto tuning */
1125         if (!err && !host->tuning_err)
1126                 usdhc_auto_tuning_mode_sel_and_en(host);
1127
1128         return err;
1129 }
1130
1131 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
1132 {
1133         u32 reg;
1134         u8 sw_rst;
1135         int ret;
1136
1137         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
1138         mdelay(1);
1139
1140         /* IC suggest to reset USDHC before every tuning command */
1141         esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
1142         ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
1143                                 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
1144         if (ret == -ETIMEDOUT)
1145                 dev_warn(mmc_dev(host->mmc),
1146                 "warning! RESET_ALL never complete before sending tuning command\n");
1147
1148         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1149         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
1150                         ESDHC_MIX_CTRL_FBCLK_SEL;
1151         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1152         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1153         dev_dbg(mmc_dev(host->mmc),
1154                 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
1155                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
1156 }
1157
1158 static void esdhc_post_tuning(struct sdhci_host *host)
1159 {
1160         u32 reg;
1161
1162         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1163         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1164         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1165 }
1166
1167 /*
1168  * find the largest pass window, and use the average delay of this
1169  * largest window to get the best timing.
1170  */
1171 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1172 {
1173         int min, max, avg, ret;
1174         int win_length, target_min, target_max, target_win_length;
1175
1176         min = ESDHC_TUNE_CTRL_MIN;
1177         max = ESDHC_TUNE_CTRL_MIN;
1178         target_win_length = 0;
1179         while (max < ESDHC_TUNE_CTRL_MAX) {
1180                 /* find the mininum delay first which can pass tuning */
1181                 while (min < ESDHC_TUNE_CTRL_MAX) {
1182                         esdhc_prepare_tuning(host, min);
1183                         if (!mmc_send_tuning(host->mmc, opcode, NULL))
1184                                 break;
1185                         min += ESDHC_TUNE_CTRL_STEP;
1186                 }
1187
1188                 /* find the maxinum delay which can not pass tuning */
1189                 max = min + ESDHC_TUNE_CTRL_STEP;
1190                 while (max < ESDHC_TUNE_CTRL_MAX) {
1191                         esdhc_prepare_tuning(host, max);
1192                         if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1193                                 max -= ESDHC_TUNE_CTRL_STEP;
1194                                 break;
1195                         }
1196                         max += ESDHC_TUNE_CTRL_STEP;
1197                 }
1198
1199                 win_length = max - min + 1;
1200                 /* get the largest pass window */
1201                 if (win_length > target_win_length) {
1202                         target_win_length = win_length;
1203                         target_min = min;
1204                         target_max = max;
1205                 }
1206
1207                 /* continue to find the next pass window */
1208                 min = max + ESDHC_TUNE_CTRL_STEP;
1209         }
1210
1211         /* use average delay to get the best timing */
1212         avg = (target_min + target_max) / 2;
1213         esdhc_prepare_tuning(host, avg);
1214         ret = mmc_send_tuning(host->mmc, opcode, NULL);
1215         esdhc_post_tuning(host);
1216
1217         dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1218                 ret ? "failed" : "passed", avg, ret);
1219
1220         return ret;
1221 }
1222
1223 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1224 {
1225         struct sdhci_host *host = mmc_priv(mmc);
1226         u32 m;
1227
1228         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1229         if (ios->enhanced_strobe)
1230                 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1231         else
1232                 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1233         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1234 }
1235
1236 static int esdhc_change_pinstate(struct sdhci_host *host,
1237                                                 unsigned int uhs)
1238 {
1239         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1240         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1241         struct pinctrl_state *pinctrl;
1242
1243         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1244
1245         if (IS_ERR(imx_data->pinctrl) ||
1246                 IS_ERR(imx_data->pins_100mhz) ||
1247                 IS_ERR(imx_data->pins_200mhz))
1248                 return -EINVAL;
1249
1250         switch (uhs) {
1251         case MMC_TIMING_UHS_SDR50:
1252         case MMC_TIMING_UHS_DDR50:
1253                 pinctrl = imx_data->pins_100mhz;
1254                 break;
1255         case MMC_TIMING_UHS_SDR104:
1256         case MMC_TIMING_MMC_HS200:
1257         case MMC_TIMING_MMC_HS400:
1258                 pinctrl = imx_data->pins_200mhz;
1259                 break;
1260         default:
1261                 /* back to default state for other legacy timing */
1262                 return pinctrl_select_default_state(mmc_dev(host->mmc));
1263         }
1264
1265         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1266 }
1267
1268 /*
1269  * For HS400 eMMC, there is a data_strobe line. This signal is generated
1270  * by the device and used for data output and CRC status response output
1271  * in HS400 mode. The frequency of this signal follows the frequency of
1272  * CLK generated by host. The host receives the data which is aligned to the
1273  * edge of data_strobe line. Due to the time delay between CLK line and
1274  * data_strobe line, if the delay time is larger than one clock cycle,
1275  * then CLK and data_strobe line will be misaligned, read error shows up.
1276  */
1277 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1278 {
1279         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1280         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1281         u32 strobe_delay;
1282         u32 v;
1283         int ret;
1284
1285         /* disable clock before enabling strobe dll */
1286         writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1287                 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1288                 host->ioaddr + ESDHC_VENDOR_SPEC);
1289         esdhc_wait_for_card_clock_gate_off(host);
1290
1291         /* force a reset on strobe dll */
1292         writel(ESDHC_STROBE_DLL_CTRL_RESET,
1293                 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1294         /* clear the reset bit on strobe dll before any setting */
1295         writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1296
1297         /*
1298          * enable strobe dll ctrl and adjust the delay target
1299          * for the uSDHC loopback read clock
1300          */
1301         if (imx_data->boarddata.strobe_dll_delay_target)
1302                 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1303         else
1304                 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1305         v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1306                 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1307                 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1308         writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1309
1310         /* wait max 50us to get the REF/SLV lock */
1311         ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1312                 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1313         if (ret == -ETIMEDOUT)
1314                 dev_warn(mmc_dev(host->mmc),
1315                 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1316 }
1317
1318 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1319 {
1320         u32 m;
1321         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1322         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1323         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1324
1325         /* disable ddr mode and disable HS400 mode */
1326         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1327         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1328         imx_data->is_ddr = 0;
1329
1330         switch (timing) {
1331         case MMC_TIMING_UHS_SDR12:
1332         case MMC_TIMING_UHS_SDR25:
1333         case MMC_TIMING_UHS_SDR50:
1334         case MMC_TIMING_UHS_SDR104:
1335         case MMC_TIMING_MMC_HS:
1336         case MMC_TIMING_MMC_HS200:
1337                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1338                 break;
1339         case MMC_TIMING_UHS_DDR50:
1340         case MMC_TIMING_MMC_DDR52:
1341                 m |= ESDHC_MIX_CTRL_DDREN;
1342                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1343                 imx_data->is_ddr = 1;
1344                 if (boarddata->delay_line) {
1345                         u32 v;
1346                         v = boarddata->delay_line <<
1347                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1348                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1349                         if (is_imx53_esdhc(imx_data))
1350                                 v <<= 1;
1351                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1352                 }
1353                 break;
1354         case MMC_TIMING_MMC_HS400:
1355                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1356                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1357                 imx_data->is_ddr = 1;
1358                 /* update clock after enable DDR for strobe DLL lock */
1359                 host->ops->set_clock(host, host->clock);
1360                 esdhc_set_strobe_dll(host);
1361                 break;
1362         case MMC_TIMING_LEGACY:
1363         default:
1364                 esdhc_reset_tuning(host);
1365                 break;
1366         }
1367
1368         esdhc_change_pinstate(host, timing);
1369 }
1370
1371 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1372 {
1373         sdhci_and_cqhci_reset(host, mask);
1374
1375         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1376         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1377 }
1378
1379 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1380 {
1381         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1382         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1383
1384         /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1385         return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1386 }
1387
1388 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1389 {
1390         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1391         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1392
1393         /* use maximum timeout counter */
1394         esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1395                         esdhc_is_usdhc(imx_data) ? 0xF0000 : 0xE0000,
1396                         ESDHC_SYSTEM_CONTROL);
1397 }
1398
1399 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1400 {
1401         int cmd_error = 0;
1402         int data_error = 0;
1403
1404         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1405                 return intmask;
1406
1407         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1408
1409         return 0;
1410 }
1411
1412 static void esdhc_hw_reset(struct sdhci_host *host)
1413 {
1414         esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N, 0, ESDHC_SYSTEM_CONTROL);
1415         /* eMMC spec requires minimum 1us, here delay between 1-10us */
1416         usleep_range(1, 10);
1417         esdhc_clrset_le(host, ESDHC_SYS_CTRL_IPP_RST_N,
1418                         ESDHC_SYS_CTRL_IPP_RST_N, ESDHC_SYSTEM_CONTROL);
1419         /* eMMC spec requires minimum 200us, here delay between 200-300us */
1420         usleep_range(200, 300);
1421 }
1422
1423 static struct sdhci_ops sdhci_esdhc_ops = {
1424         .read_l = esdhc_readl_le,
1425         .read_w = esdhc_readw_le,
1426         .read_b = esdhc_readb_le,
1427         .write_l = esdhc_writel_le,
1428         .write_w = esdhc_writew_le,
1429         .write_b = esdhc_writeb_le,
1430         .set_clock = esdhc_pltfm_set_clock,
1431         .get_max_clock = esdhc_pltfm_get_max_clock,
1432         .get_min_clock = esdhc_pltfm_get_min_clock,
1433         .get_max_timeout_count = esdhc_get_max_timeout_count,
1434         .get_ro = esdhc_pltfm_get_ro,
1435         .set_timeout = esdhc_set_timeout,
1436         .set_bus_width = esdhc_pltfm_set_bus_width,
1437         .set_uhs_signaling = esdhc_set_uhs_signaling,
1438         .reset = esdhc_reset,
1439         .irq = esdhc_cqhci_irq,
1440         .dump_vendor_regs = esdhc_dump_debug_regs,
1441         .hw_reset = esdhc_hw_reset,
1442 };
1443
1444 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1445         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1446                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1447                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1448                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1449         .ops = &sdhci_esdhc_ops,
1450 };
1451
1452 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1453 {
1454         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1455         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1456         struct cqhci_host *cq_host = host->mmc->cqe_private;
1457         u32 tmp;
1458
1459         if (esdhc_is_usdhc(imx_data)) {
1460                 /*
1461                  * The imx6q ROM code will change the default watermark
1462                  * level setting to something insane.  Change it back here.
1463                  */
1464                 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1465
1466                 /*
1467                  * ROM code will change the bit burst_length_enable setting
1468                  * to zero if this usdhc is chosen to boot system. Change
1469                  * it back here, otherwise it will impact the performance a
1470                  * lot. This bit is used to enable/disable the burst length
1471                  * for the external AHB2AXI bridge. It's useful especially
1472                  * for INCR transfer because without burst length indicator,
1473                  * the AHB2AXI bridge does not know the burst length in
1474                  * advance. And without burst length indicator, AHB INCR
1475                  * transfer can only be converted to singles on the AXI side.
1476                  */
1477                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1478                         | ESDHC_BURST_LEN_EN_INCR,
1479                         host->ioaddr + SDHCI_HOST_CONTROL);
1480
1481                 /*
1482                  * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1483                  * TO1.1, it's harmless for MX6SL
1484                  */
1485                 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) {
1486                         writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1487                                 host->ioaddr + 0x6c);
1488                 }
1489
1490                 /* disable DLL_CTRL delay line settings */
1491                 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1492
1493                 /*
1494                  * For the case of command with busy, if set the bit
1495                  * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1496                  * transfer complete interrupt when busy is deasserted.
1497                  * When CQHCI use DCMD to send a CMD need R1b respons,
1498                  * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1499                  * otherwise DCMD will always meet timeout waiting for
1500                  * hardware interrupt issue.
1501                  */
1502                 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1503                         tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1504                         tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1505                         writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1506
1507                         host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1508                 }
1509
1510                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1511                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1512                         tmp |= ESDHC_STD_TUNING_EN;
1513
1514                         /*
1515                          * ROM code or bootloader may config the start tap
1516                          * and step, unmask them first.
1517                          */
1518                         tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK);
1519                         if (imx_data->boarddata.tuning_start_tap)
1520                                 tmp |= imx_data->boarddata.tuning_start_tap;
1521                         else
1522                                 tmp |= ESDHC_TUNING_START_TAP_DEFAULT;
1523
1524                         if (imx_data->boarddata.tuning_step) {
1525                                 tmp |= imx_data->boarddata.tuning_step
1526                                         << ESDHC_TUNING_STEP_SHIFT;
1527                         } else {
1528                                 tmp |= ESDHC_TUNING_STEP_DEFAULT
1529                                         << ESDHC_TUNING_STEP_SHIFT;
1530                         }
1531
1532                         /* Disable the CMD CRC check for tuning, if not, need to
1533                          * add some delay after every tuning command, because
1534                          * hardware standard tuning logic will directly go to next
1535                          * step once it detect the CMD CRC error, will not wait for
1536                          * the card side to finally send out the tuning data, trigger
1537                          * the buffer read ready interrupt immediately. If usdhc send
1538                          * the next tuning command some eMMC card will stuck, can't
1539                          * response, block the tuning procedure or the first command
1540                          * after the whole tuning procedure always can't get any response.
1541                          */
1542                         tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1543                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1544                 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1545                         /*
1546                          * ESDHC_STD_TUNING_EN may be configured in bootloader
1547                          * or ROM code, so clear this bit here to make sure
1548                          * the manual tuning can work.
1549                          */
1550                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1551                         tmp &= ~ESDHC_STD_TUNING_EN;
1552                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1553                 }
1554
1555                 /*
1556                  * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1557                  * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let
1558                  * the 1st linux configure power/clock for the 2nd Linux.
1559                  *
1560                  * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1561                  * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1562                  * After we clear the pending interrupt and halt CQCTL, issue gone.
1563                  */
1564                 if (cq_host) {
1565                         tmp = cqhci_readl(cq_host, CQHCI_IS);
1566                         cqhci_writel(cq_host, tmp, CQHCI_IS);
1567                         cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1568                 }
1569         }
1570 }
1571
1572 static void esdhc_cqe_enable(struct mmc_host *mmc)
1573 {
1574         struct sdhci_host *host = mmc_priv(mmc);
1575         struct cqhci_host *cq_host = mmc->cqe_private;
1576         u32 reg;
1577         u16 mode;
1578         int count = 10;
1579
1580         /*
1581          * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1582          * the case after tuning, so ensure the buffer is drained.
1583          */
1584         reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1585         while (reg & SDHCI_DATA_AVAILABLE) {
1586                 sdhci_readl(host, SDHCI_BUFFER);
1587                 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1588                 if (count-- == 0) {
1589                         dev_warn(mmc_dev(host->mmc),
1590                                 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1591                         break;
1592                 }
1593                 mdelay(1);
1594         }
1595
1596         /*
1597          * Runtime resume will reset the entire host controller, which
1598          * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1599          * Here set DMAEN and BCEN when enable CMDQ.
1600          */
1601         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1602         if (host->flags & SDHCI_REQ_USE_DMA)
1603                 mode |= SDHCI_TRNS_DMA;
1604         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1605                 mode |= SDHCI_TRNS_BLK_CNT_EN;
1606         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1607
1608         /*
1609          * Though Runtime resume reset the entire host controller,
1610          * but do not impact the CQHCI side, need to clear the
1611          * HALT bit, avoid CQHCI stuck in the first request when
1612          * system resume back.
1613          */
1614         cqhci_writel(cq_host, 0, CQHCI_CTL);
1615         if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT)
1616                 dev_err(mmc_dev(host->mmc),
1617                         "failed to exit halt state when enable CQE\n");
1618
1619
1620         sdhci_cqe_enable(mmc);
1621 }
1622
1623 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1624 {
1625         sdhci_dumpregs(mmc_priv(mmc));
1626 }
1627
1628 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1629         .enable         = esdhc_cqe_enable,
1630         .disable        = sdhci_cqe_disable,
1631         .dumpregs       = esdhc_sdhci_dumpregs,
1632 };
1633
1634 static int
1635 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1636                          struct sdhci_host *host,
1637                          struct pltfm_imx_data *imx_data)
1638 {
1639         struct device_node *np = pdev->dev.of_node;
1640         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1641         int ret;
1642
1643         if (of_property_read_bool(np, "fsl,wp-controller"))
1644                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1645
1646         /*
1647          * If we have this property, then activate WP check.
1648          * Retrieving and requesting the actual WP GPIO will happen
1649          * in the call to mmc_of_parse().
1650          */
1651         if (of_property_present(np, "wp-gpios"))
1652                 boarddata->wp_type = ESDHC_WP_GPIO;
1653
1654         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1655         of_property_read_u32(np, "fsl,tuning-start-tap",
1656                              &boarddata->tuning_start_tap);
1657
1658         of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1659                                 &boarddata->strobe_dll_delay_target);
1660         if (of_property_read_bool(np, "no-1-8-v"))
1661                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1662
1663         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1664                 boarddata->delay_line = 0;
1665
1666         mmc_of_parse_voltage(host->mmc, &host->ocr_mask);
1667
1668         if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1669                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1670                                                 ESDHC_PINCTRL_STATE_100MHZ);
1671                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1672                                                 ESDHC_PINCTRL_STATE_200MHZ);
1673         }
1674
1675         /* call to generic mmc_of_parse to support additional capabilities */
1676         ret = mmc_of_parse(host->mmc);
1677         if (ret)
1678                 return ret;
1679
1680         /* HS400/HS400ES require 8 bit bus */
1681         if (!(host->mmc->caps & MMC_CAP_8_BIT_DATA))
1682                 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
1683
1684         if (mmc_gpio_get_cd(host->mmc) >= 0)
1685                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1686
1687         return 0;
1688 }
1689
1690 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1691 {
1692         struct sdhci_pltfm_host *pltfm_host;
1693         struct sdhci_host *host;
1694         struct cqhci_host *cq_host;
1695         int err;
1696         struct pltfm_imx_data *imx_data;
1697
1698         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1699                                 sizeof(*imx_data));
1700         if (IS_ERR(host))
1701                 return PTR_ERR(host);
1702
1703         pltfm_host = sdhci_priv(host);
1704
1705         imx_data = sdhci_pltfm_priv(pltfm_host);
1706
1707         imx_data->socdata = device_get_match_data(&pdev->dev);
1708
1709         host->quirks |= imx_data->socdata->quirks;
1710         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1711                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1712
1713         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1714         if (IS_ERR(imx_data->clk_ipg)) {
1715                 err = PTR_ERR(imx_data->clk_ipg);
1716                 goto free_sdhci;
1717         }
1718
1719         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1720         if (IS_ERR(imx_data->clk_ahb)) {
1721                 err = PTR_ERR(imx_data->clk_ahb);
1722                 goto free_sdhci;
1723         }
1724
1725         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1726         if (IS_ERR(imx_data->clk_per)) {
1727                 err = PTR_ERR(imx_data->clk_per);
1728                 goto free_sdhci;
1729         }
1730
1731         pltfm_host->clk = imx_data->clk_per;
1732         err = clk_prepare_enable(imx_data->clk_per);
1733         if (err)
1734                 goto free_sdhci;
1735         err = clk_prepare_enable(imx_data->clk_ipg);
1736         if (err)
1737                 goto disable_per_clk;
1738         err = clk_prepare_enable(imx_data->clk_ahb);
1739         if (err)
1740                 goto disable_ipg_clk;
1741
1742         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1743         if (!pltfm_host->clock) {
1744                 dev_err(mmc_dev(host->mmc), "could not get clk rate\n");
1745                 err = -EINVAL;
1746                 goto disable_ahb_clk;
1747         }
1748
1749         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1750         if (IS_ERR(imx_data->pinctrl))
1751                 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1752
1753         if (esdhc_is_usdhc(imx_data)) {
1754                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1755                 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1756
1757                 /* GPIO CD can be set as a wakeup source */
1758                 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_CD_WAKE))
1759                         host->mmc->caps |= MMC_CAP_CD_WAKE;
1760
1761                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1762                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1763
1764                 /* clear tuning bits in case ROM has set it already */
1765                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1766                 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1767                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1768
1769                 /*
1770                  * Link usdhc specific mmc_host_ops execute_tuning function,
1771                  * to replace the standard one in sdhci_ops.
1772                  */
1773                 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1774
1775                 /*
1776                  * Link usdhc specific mmc_host_ops init card function,
1777                  * to distinguish the card type.
1778                  */
1779                 host->mmc_host_ops.init_card = usdhc_init_card;
1780         }
1781
1782         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1783                 sdhci_esdhc_ops.platform_execute_tuning =
1784                                         esdhc_executing_tuning;
1785
1786         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1787                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1788
1789         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1790                 host->mmc->caps2 |= MMC_CAP2_HS400;
1791
1792         if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1793                 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1794
1795         if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1796                 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1797                 host->mmc_host_ops.hs400_enhanced_strobe =
1798                                         esdhc_hs400_enhanced_strobe;
1799         }
1800
1801         if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1802                 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1803                 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1804                 if (!cq_host) {
1805                         err = -ENOMEM;
1806                         goto disable_ahb_clk;
1807                 }
1808
1809                 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1810                 cq_host->ops = &esdhc_cqhci_ops;
1811
1812                 err = cqhci_init(cq_host, host->mmc, false);
1813                 if (err)
1814                         goto disable_ahb_clk;
1815         }
1816
1817         err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1818         if (err)
1819                 goto disable_ahb_clk;
1820
1821         sdhci_esdhc_imx_hwinit(host);
1822
1823         err = sdhci_add_host(host);
1824         if (err)
1825                 goto disable_ahb_clk;
1826
1827         /*
1828          * Setup the wakeup capability here, let user to decide
1829          * whether need to enable this wakeup through sysfs interface.
1830          */
1831         if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) &&
1832                         (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ))
1833                 device_set_wakeup_capable(&pdev->dev, true);
1834
1835         pm_runtime_set_active(&pdev->dev);
1836         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1837         pm_runtime_use_autosuspend(&pdev->dev);
1838         pm_suspend_ignore_children(&pdev->dev, 1);
1839         pm_runtime_enable(&pdev->dev);
1840
1841         return 0;
1842
1843 disable_ahb_clk:
1844         clk_disable_unprepare(imx_data->clk_ahb);
1845 disable_ipg_clk:
1846         clk_disable_unprepare(imx_data->clk_ipg);
1847 disable_per_clk:
1848         clk_disable_unprepare(imx_data->clk_per);
1849 free_sdhci:
1850         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1851                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1852         sdhci_pltfm_free(pdev);
1853         return err;
1854 }
1855
1856 static void sdhci_esdhc_imx_remove(struct platform_device *pdev)
1857 {
1858         struct sdhci_host *host = platform_get_drvdata(pdev);
1859         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1860         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1861         int dead;
1862
1863         pm_runtime_get_sync(&pdev->dev);
1864         dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1865         pm_runtime_disable(&pdev->dev);
1866         pm_runtime_put_noidle(&pdev->dev);
1867
1868         sdhci_remove_host(host, dead);
1869
1870         clk_disable_unprepare(imx_data->clk_per);
1871         clk_disable_unprepare(imx_data->clk_ipg);
1872         clk_disable_unprepare(imx_data->clk_ahb);
1873
1874         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1875                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1876
1877         sdhci_pltfm_free(pdev);
1878 }
1879
1880 #ifdef CONFIG_PM_SLEEP
1881 static int sdhci_esdhc_suspend(struct device *dev)
1882 {
1883         struct sdhci_host *host = dev_get_drvdata(dev);
1884         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1885         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1886         int ret;
1887
1888         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1889                 ret = cqhci_suspend(host->mmc);
1890                 if (ret)
1891                         return ret;
1892         }
1893
1894         if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1895                 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1896                 mmc_retune_timer_stop(host->mmc);
1897                 mmc_retune_needed(host->mmc);
1898         }
1899
1900         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1901                 mmc_retune_needed(host->mmc);
1902
1903         ret = sdhci_suspend_host(host);
1904         if (ret)
1905                 return ret;
1906
1907         ret = pinctrl_pm_select_sleep_state(dev);
1908         if (ret)
1909                 return ret;
1910
1911         ret = mmc_gpio_set_cd_wake(host->mmc, true);
1912
1913         return ret;
1914 }
1915
1916 static int sdhci_esdhc_resume(struct device *dev)
1917 {
1918         struct sdhci_host *host = dev_get_drvdata(dev);
1919         int ret;
1920
1921         ret = pinctrl_pm_select_default_state(dev);
1922         if (ret)
1923                 return ret;
1924
1925         /* re-initialize hw state in case it's lost in low power mode */
1926         sdhci_esdhc_imx_hwinit(host);
1927
1928         ret = sdhci_resume_host(host);
1929         if (ret)
1930                 return ret;
1931
1932         if (host->mmc->caps2 & MMC_CAP2_CQE)
1933                 ret = cqhci_resume(host->mmc);
1934
1935         if (!ret)
1936                 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1937
1938         return ret;
1939 }
1940 #endif
1941
1942 #ifdef CONFIG_PM
1943 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1944 {
1945         struct sdhci_host *host = dev_get_drvdata(dev);
1946         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1947         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1948         int ret;
1949
1950         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1951                 ret = cqhci_suspend(host->mmc);
1952                 if (ret)
1953                         return ret;
1954         }
1955
1956         ret = sdhci_runtime_suspend_host(host);
1957         if (ret)
1958                 return ret;
1959
1960         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1961                 mmc_retune_needed(host->mmc);
1962
1963         imx_data->actual_clock = host->mmc->actual_clock;
1964         esdhc_pltfm_set_clock(host, 0);
1965         clk_disable_unprepare(imx_data->clk_per);
1966         clk_disable_unprepare(imx_data->clk_ipg);
1967         clk_disable_unprepare(imx_data->clk_ahb);
1968
1969         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1970                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1971
1972         return ret;
1973 }
1974
1975 static int sdhci_esdhc_runtime_resume(struct device *dev)
1976 {
1977         struct sdhci_host *host = dev_get_drvdata(dev);
1978         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1979         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1980         int err;
1981
1982         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1983                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1984
1985         if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1986                 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1987
1988         err = clk_prepare_enable(imx_data->clk_ahb);
1989         if (err)
1990                 goto remove_pm_qos_request;
1991
1992         err = clk_prepare_enable(imx_data->clk_per);
1993         if (err)
1994                 goto disable_ahb_clk;
1995
1996         err = clk_prepare_enable(imx_data->clk_ipg);
1997         if (err)
1998                 goto disable_per_clk;
1999
2000         esdhc_pltfm_set_clock(host, imx_data->actual_clock);
2001
2002         err = sdhci_runtime_resume_host(host, 0);
2003         if (err)
2004                 goto disable_ipg_clk;
2005
2006         if (host->mmc->caps2 & MMC_CAP2_CQE)
2007                 err = cqhci_resume(host->mmc);
2008
2009         return err;
2010
2011 disable_ipg_clk:
2012         clk_disable_unprepare(imx_data->clk_ipg);
2013 disable_per_clk:
2014         clk_disable_unprepare(imx_data->clk_per);
2015 disable_ahb_clk:
2016         clk_disable_unprepare(imx_data->clk_ahb);
2017 remove_pm_qos_request:
2018         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
2019                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
2020         return err;
2021 }
2022 #endif
2023
2024 static const struct dev_pm_ops sdhci_esdhc_pmops = {
2025         SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
2026         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
2027                                 sdhci_esdhc_runtime_resume, NULL)
2028 };
2029
2030 static struct platform_driver sdhci_esdhc_imx_driver = {
2031         .driver         = {
2032                 .name   = "sdhci-esdhc-imx",
2033                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2034                 .of_match_table = imx_esdhc_dt_ids,
2035                 .pm     = &sdhci_esdhc_pmops,
2036         },
2037         .probe          = sdhci_esdhc_imx_probe,
2038         .remove         = sdhci_esdhc_imx_remove,
2039 };
2040
2041 module_platform_driver(sdhci_esdhc_imx_driver);
2042
2043 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
2044 MODULE_AUTHOR("Wolfram Sang <[email protected]>");
2045 MODULE_LICENSE("GPL v2");