drivers/media/i2c/ov08x40.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2022 Intel Corporation.
   3
   4 #include <linux/unaligned.h>
   5 #include <linux/acpi.h>
   6 #include <linux/clk.h>
   7 #include <linux/i2c.h>
   8 #include <linux/gpio/consumer.h>
   9 #include <linux/module.h>
  10 #include <linux/delay.h>
  11 #include <linux/pm_runtime.h>
  12 #include <linux/regulator/consumer.h>
  13 #include <media/v4l2-ctrls.h>
  14 #include <media/v4l2-device.h>
  15 #include <media/v4l2-fwnode.h>
  16
  17 #define OV08X40_REG_VALUE_08BIT         1
  18 #define OV08X40_REG_VALUE_16BIT         2
  19 #define OV08X40_REG_VALUE_24BIT         3
  20
  21 #define OV08X40_REG_MODE_SELECT         0x0100
  22 #define OV08X40_MODE_STANDBY            0x00
  23 #define OV08X40_MODE_STREAMING          0x01
  24
  25 #define OV08X40_REG_AO_STANDBY          0x1000
  26 #define OV08X40_AO_STREAMING            0x04
  27
  28 #define OV08X40_REG_MS_SELECT           0x1001
  29 #define OV08X40_MS_STANDBY                      0x00
  30 #define OV08X40_MS_STREAMING            0x04
  31
  32 #define OV08X40_REG_SOFTWARE_RST        0x0103
  33 #define OV08X40_SOFTWARE_RST            0x01
  34
  35 /* Chip ID */
  36 #define OV08X40_REG_CHIP_ID             0x300a
  37 #define OV08X40_CHIP_ID                 0x560858
  38
  39 /* V_TIMING internal */
  40 #define OV08X40_REG_VTS                 0x380e
  41 #define OV08X40_VTS_30FPS               0x09c4  /* the VTS need to be half in normal mode */
  42 #define OV08X40_VTS_BIN_30FPS           0x115c
  43 #define OV08X40_VTS_MAX                 0x7fff
  44
  45 /* H TIMING internal */
  46 #define OV08X40_REG_HTS                 0x380c
  47 #define OV08X40_HTS_30FPS               0x0280
  48
  49 /* Exposure control */
  50 #define OV08X40_REG_EXPOSURE            0x3500
  51 #define OV08X40_EXPOSURE_MAX_MARGIN     8
  52 #define OV08X40_EXPOSURE_BIN_MAX_MARGIN 2
  53 #define OV08X40_EXPOSURE_MIN            4
  54 #define OV08X40_EXPOSURE_STEP           1
  55 #define OV08X40_EXPOSURE_DEFAULT        0x40
  56
  57 /* Short Exposure control */
  58 #define OV08X40_REG_SHORT_EXPOSURE      0x3540
  59
  60 /* Analog gain control */
  61 #define OV08X40_REG_ANALOG_GAIN         0x3508
  62 #define OV08X40_ANA_GAIN_MIN            0x80
  63 #define OV08X40_ANA_GAIN_MAX            0x07c0
  64 #define OV08X40_ANA_GAIN_STEP           1
  65 #define OV08X40_ANA_GAIN_DEFAULT        0x80
  66
  67 /* Digital gain control */
  68 #define OV08X40_REG_DGTL_GAIN_H         0x350a
  69 #define OV08X40_REG_DGTL_GAIN_M         0x350b
  70 #define OV08X40_REG_DGTL_GAIN_L         0x350c
  71
  72 #define OV08X40_DGTL_GAIN_MIN           1024         /* Min = 1 X */
  73 #define OV08X40_DGTL_GAIN_MAX           (4096 - 1)   /* Max = 4 X */
  74 #define OV08X40_DGTL_GAIN_DEFAULT       2560         /* Default gain = 2.5 X */
  75 #define OV08X40_DGTL_GAIN_STEP          1            /* Each step = 1/1024 */
  76
  77 #define OV08X40_DGTL_GAIN_L_SHIFT       6
  78 #define OV08X40_DGTL_GAIN_L_MASK        0x3
  79 #define OV08X40_DGTL_GAIN_M_SHIFT       2
  80 #define OV08X40_DGTL_GAIN_M_MASK        0xff
  81 #define OV08X40_DGTL_GAIN_H_SHIFT       10
  82 #define OV08X40_DGTL_GAIN_H_MASK        0x1F
  83
  84 /* Test Pattern Control */
  85 #define OV08X40_REG_TEST_PATTERN        0x50C1
  86 #define OV08X40_REG_ISP             0x5000
  87 #define OV08X40_REG_SHORT_TEST_PATTERN  0x53C1
  88 #define OV08X40_TEST_PATTERN_ENABLE     BIT(0)
  89 #define OV08X40_TEST_PATTERN_MASK       0xcf
  90 #define OV08X40_TEST_PATTERN_BAR_SHIFT  4
  91
  92 /* Flip Control */
  93 #define OV08X40_REG_VFLIP               0x3820
  94 #define OV08X40_REG_MIRROR              0x3821
  95
  96 /* Horizontal Window Offset */
  97 #define OV08X40_REG_H_WIN_OFFSET        0x3811
  98
  99 /* Vertical Window Offset */
 100 #define OV08X40_REG_V_WIN_OFFSET        0x3813
 101
 102 /* Burst Register */
 103 #define OV08X40_REG_XTALK_FIRST_A       0x5a80
 104 #define OV08X40_REG_XTALK_LAST_A        0x5b9f
 105 #define OV08X40_REG_XTALK_FIRST_B       0x5bc0
 106 #define OV08X40_REG_XTALK_LAST_B        0x5f1f
 107
 108 enum {
 109         OV08X40_LINK_FREQ_400MHZ_INDEX,
 110 };
 111
 112 struct ov08x40_reg {
 113         u16 address;
 114         u8 val;
 115 };
 116
 117 struct ov08x40_reg_list {
 118         u32 num_of_regs;
 119         const struct ov08x40_reg *regs;
 120 };
 121
 122 /* Link frequency config */
 123 struct ov08x40_link_freq_config {
 124         /* registers for this link frequency */
 125         struct ov08x40_reg_list reg_list;
 126 };
 127
 128 /* Mode : resolution and related config&values */
 129 struct ov08x40_mode {
 130         /* Frame width */
 131         u32 width;
 132         /* Frame height */
 133         u32 height;
 134
 135         u32 lanes;
 136         /* V-timing */
 137         u32 vts_def;
 138         u32 vts_min;
 139
 140         /* Line Length Pixels */
 141         u32 llp;
 142
 143         /* Index of Link frequency config to be used */
 144         u32 link_freq_index;
 145         /* Default register values */
 146         struct ov08x40_reg_list reg_list;
 147
 148         /* Exposure calculation */
 149         u16 exposure_margin;
 150         u16 exposure_shift;
 151 };
 152
 153 static const struct ov08x40_reg mipi_data_rate_800mbps[] = {
 154         {0x0103, 0x01},
 155         {0x1000, 0x00},
 156         {0x1601, 0xd0},
 157         {0x1001, 0x04},
 158         {0x5004, 0x53},
 159         {0x5110, 0x00},
 160         {0x5111, 0x14},
 161         {0x5112, 0x01},
 162         {0x5113, 0x7b},
 163         {0x5114, 0x00},
 164         {0x5152, 0xa3},
 165         {0x5a52, 0x1f},
 166         {0x5a1a, 0x0e},
 167         {0x5a1b, 0x10},
 168         {0x5a1f, 0x0e},
 169         {0x5a27, 0x0e},
 170         {0x6002, 0x2e},
 171 };
 172
 173 static const struct ov08x40_reg mode_3856x2416_regs[] = {
 174         {0x5000, 0x5d},
 175         {0x5001, 0x20},
 176         {0x5008, 0xb0},
 177         {0x50c1, 0x00},
 178         {0x53c1, 0x00},
 179         {0x5f40, 0x00},
 180         {0x5f41, 0x40},
 181         {0x0300, 0x3a},
 182         {0x0301, 0xc8},
 183         {0x0302, 0x31},
 184         {0x0303, 0x03},
 185         {0x0304, 0x01},
 186         {0x0305, 0xa1},
 187         {0x0306, 0x04},
 188         {0x0307, 0x01},
 189         {0x0308, 0x03},
 190         {0x0309, 0x03},
 191         {0x0310, 0x0a},
 192         {0x0311, 0x02},
 193         {0x0312, 0x01},
 194         {0x0313, 0x08},
 195         {0x0314, 0x66},
 196         {0x0315, 0x00},
 197         {0x0316, 0x34},
 198         {0x0320, 0x02},
 199         {0x0321, 0x03},
 200         {0x0323, 0x05},
 201         {0x0324, 0x01},
 202         {0x0325, 0xb8},
 203         {0x0326, 0x4a},
 204         {0x0327, 0x04},
 205         {0x0329, 0x00},
 206         {0x032a, 0x05},
 207         {0x032b, 0x00},
 208         {0x032c, 0x00},
 209         {0x032d, 0x00},
 210         {0x032e, 0x02},
 211         {0x032f, 0xa0},
 212         {0x0350, 0x00},
 213         {0x0360, 0x01},
 214         {0x1216, 0x60},
 215         {0x1217, 0x5b},
 216         {0x1218, 0x00},
 217         {0x1220, 0x24},
 218         {0x198a, 0x00},
 219         {0x198b, 0x01},
 220         {0x198e, 0x00},
 221         {0x198f, 0x01},
 222         {0x3009, 0x04},
 223         {0x3012, 0x41},
 224         {0x3015, 0x00},
 225         {0x3016, 0xb0},
 226         {0x3017, 0xf0},
 227         {0x3018, 0xf0},
 228         {0x3019, 0xd2},
 229         {0x301a, 0xb0},
 230         {0x301c, 0x81},
 231         {0x301d, 0x02},
 232         {0x301e, 0x80},
 233         {0x3022, 0xf0},
 234         {0x3025, 0x89},
 235         {0x3030, 0x03},
 236         {0x3044, 0xc2},
 237         {0x3050, 0x35},
 238         {0x3051, 0x60},
 239         {0x3052, 0x25},
 240         {0x3053, 0x00},
 241         {0x3054, 0x00},
 242         {0x3055, 0x02},
 243         {0x3056, 0x80},
 244         {0x3057, 0x80},
 245         {0x3058, 0x80},
 246         {0x3059, 0x00},
 247         {0x3107, 0x86},
 248         {0x3400, 0x1c},
 249         {0x3401, 0x80},
 250         {0x3402, 0x8c},
 251         {0x3419, 0x13},
 252         {0x341a, 0x89},
 253         {0x341b, 0x30},
 254         {0x3420, 0x00},
 255         {0x3421, 0x00},
 256         {0x3422, 0x00},
 257         {0x3423, 0x00},
 258         {0x3424, 0x00},
 259         {0x3425, 0x00},
 260         {0x3426, 0x00},
 261         {0x3427, 0x00},
 262         {0x3428, 0x0f},
 263         {0x3429, 0x00},
 264         {0x342a, 0x00},
 265         {0x342b, 0x00},
 266         {0x342c, 0x00},
 267         {0x342d, 0x00},
 268         {0x342e, 0x00},
 269         {0x342f, 0x11},
 270         {0x3430, 0x11},
 271         {0x3431, 0x10},
 272         {0x3432, 0x00},
 273         {0x3433, 0x00},
 274         {0x3434, 0x00},
 275         {0x3435, 0x00},
 276         {0x3436, 0x00},
 277         {0x3437, 0x00},
 278         {0x3442, 0x02},
 279         {0x3443, 0x02},
 280         {0x3444, 0x07},
 281         {0x3450, 0x00},
 282         {0x3451, 0x00},
 283         {0x3452, 0x18},
 284         {0x3453, 0x18},
 285         {0x3454, 0x00},
 286         {0x3455, 0x80},
 287         {0x3456, 0x08},
 288         {0x3500, 0x00},
 289         {0x3501, 0x02},
 290         {0x3502, 0x00},
 291         {0x3504, 0x4c},
 292         {0x3506, 0x30},
 293         {0x3507, 0x00},
 294         {0x3508, 0x01},
 295         {0x3509, 0x00},
 296         {0x350a, 0x01},
 297         {0x350b, 0x00},
 298         {0x350c, 0x00},
 299         {0x3540, 0x00},
 300         {0x3541, 0x01},
 301         {0x3542, 0x00},
 302         {0x3544, 0x4c},
 303         {0x3546, 0x30},
 304         {0x3547, 0x00},
 305         {0x3548, 0x01},
 306         {0x3549, 0x00},
 307         {0x354a, 0x01},
 308         {0x354b, 0x00},
 309         {0x354c, 0x00},
 310         {0x3688, 0x02},
 311         {0x368a, 0x2e},
 312         {0x368e, 0x71},
 313         {0x3696, 0xd1},
 314         {0x3699, 0x00},
 315         {0x369a, 0x00},
 316         {0x36a4, 0x00},
 317         {0x36a6, 0x00},
 318         {0x3711, 0x00},
 319         {0x3712, 0x51},
 320         {0x3713, 0x00},
 321         {0x3714, 0x24},
 322         {0x3716, 0x00},
 323         {0x3718, 0x07},
 324         {0x371a, 0x1c},
 325         {0x371b, 0x00},
 326         {0x3720, 0x08},
 327         {0x3725, 0x32},
 328         {0x3727, 0x05},
 329         {0x3760, 0x02},
 330         {0x3761, 0x17},
 331         {0x3762, 0x02},
 332         {0x3763, 0x02},
 333         {0x3764, 0x02},
 334         {0x3765, 0x2c},
 335         {0x3766, 0x04},
 336         {0x3767, 0x2c},
 337         {0x3768, 0x02},
 338         {0x3769, 0x00},
 339         {0x376b, 0x20},
 340         {0x376e, 0x03},
 341         {0x37b0, 0x00},
 342         {0x37b1, 0xab},
 343         {0x37b2, 0x01},
 344         {0x37b3, 0x82},
 345         {0x37b4, 0x00},
 346         {0x37b5, 0xe4},
 347         {0x37b6, 0x01},
 348         {0x37b7, 0xee},
 349         {0x3800, 0x00},
 350         {0x3801, 0x00},
 351         {0x3802, 0x00},
 352         {0x3803, 0x00},
 353         {0x3804, 0x0f},
 354         {0x3805, 0x1f},
 355         {0x3806, 0x09},
 356         {0x3807, 0x7f},
 357         {0x3808, 0x0f},
 358         {0x3809, 0x10},
 359         {0x380a, 0x09},
 360         {0x380b, 0x70},
 361         {0x380c, 0x02},
 362         {0x380d, 0x80},
 363         {0x380e, 0x13},
 364         {0x380f, 0x88},
 365         {0x3810, 0x00},
 366         {0x3811, 0x08},
 367         {0x3812, 0x00},
 368         {0x3813, 0x07},
 369         {0x3814, 0x11},
 370         {0x3815, 0x11},
 371         {0x3820, 0x00},
 372         {0x3821, 0x04},
 373         {0x3822, 0x00},
 374         {0x3823, 0x04},
 375         {0x3828, 0x0f},
 376         {0x382a, 0x80},
 377         {0x382e, 0x41},
 378         {0x3837, 0x08},
 379         {0x383a, 0x81},
 380         {0x383b, 0x81},
 381         {0x383c, 0x11},
 382         {0x383d, 0x11},
 383         {0x383e, 0x00},
 384         {0x383f, 0x38},
 385         {0x3840, 0x00},
 386         {0x3847, 0x00},
 387         {0x384a, 0x00},
 388         {0x384c, 0x02},
 389         {0x384d, 0x80},
 390         {0x3856, 0x50},
 391         {0x3857, 0x30},
 392         {0x3858, 0x80},
 393         {0x3859, 0x40},
 394         {0x3860, 0x00},
 395         {0x3888, 0x00},
 396         {0x3889, 0x00},
 397         {0x388a, 0x00},
 398         {0x388b, 0x00},
 399         {0x388c, 0x00},
 400         {0x388d, 0x00},
 401         {0x388e, 0x00},
 402         {0x388f, 0x00},
 403         {0x3894, 0x00},
 404         {0x3895, 0x00},
 405         {0x3c84, 0x00},
 406         {0x3d85, 0x8b},
 407         {0x3daa, 0x80},
 408         {0x3dab, 0x14},
 409         {0x3dac, 0x80},
 410         {0x3dad, 0xc8},
 411         {0x3dae, 0x81},
 412         {0x3daf, 0x7b},
 413         {0x3f00, 0x10},
 414         {0x3f01, 0x11},
 415         {0x3f06, 0x0d},
 416         {0x3f07, 0x0b},
 417         {0x3f08, 0x0d},
 418         {0x3f09, 0x0b},
 419         {0x3f0a, 0x01},
 420         {0x3f0b, 0x11},
 421         {0x3f0c, 0x33},
 422         {0x4001, 0x07},
 423         {0x4007, 0x20},
 424         {0x4008, 0x00},
 425         {0x4009, 0x05},
 426         {0x400a, 0x00},
 427         {0x400b, 0x08},
 428         {0x400c, 0x00},
 429         {0x400d, 0x08},
 430         {0x400e, 0x14},
 431         {0x4010, 0xf4},
 432         {0x4011, 0x03},
 433         {0x4012, 0x55},
 434         {0x4015, 0x00},
 435         {0x4016, 0x2d},
 436         {0x4017, 0x00},
 437         {0x4018, 0x0f},
 438         {0x401b, 0x08},
 439         {0x401c, 0x00},
 440         {0x401d, 0x10},
 441         {0x401e, 0x02},
 442         {0x401f, 0x00},
 443         {0x4050, 0x06},
 444         {0x4051, 0xff},
 445         {0x4052, 0xff},
 446         {0x4053, 0xff},
 447         {0x4054, 0xff},
 448         {0x4055, 0xff},
 449         {0x4056, 0xff},
 450         {0x4057, 0x7f},
 451         {0x4058, 0x00},
 452         {0x4059, 0x00},
 453         {0x405a, 0x00},
 454         {0x405b, 0x00},
 455         {0x405c, 0x07},
 456         {0x405d, 0xff},
 457         {0x405e, 0x07},
 458         {0x405f, 0xff},
 459         {0x4080, 0x78},
 460         {0x4081, 0x78},
 461         {0x4082, 0x78},
 462         {0x4083, 0x78},
 463         {0x4019, 0x00},
 464         {0x401a, 0x40},
 465         {0x4020, 0x04},
 466         {0x4021, 0x00},
 467         {0x4022, 0x04},
 468         {0x4023, 0x00},
 469         {0x4024, 0x04},
 470         {0x4025, 0x00},
 471         {0x4026, 0x04},
 472         {0x4027, 0x00},
 473         {0x4030, 0x00},
 474         {0x4031, 0x00},
 475         {0x4032, 0x00},
 476         {0x4033, 0x00},
 477         {0x4034, 0x00},
 478         {0x4035, 0x00},
 479         {0x4036, 0x00},
 480         {0x4037, 0x00},
 481         {0x4040, 0x00},
 482         {0x4041, 0x80},
 483         {0x4042, 0x00},
 484         {0x4043, 0x80},
 485         {0x4044, 0x00},
 486         {0x4045, 0x80},
 487         {0x4046, 0x00},
 488         {0x4047, 0x80},
 489         {0x4060, 0x00},
 490         {0x4061, 0x00},
 491         {0x4062, 0x00},
 492         {0x4063, 0x00},
 493         {0x4064, 0x00},
 494         {0x4065, 0x00},
 495         {0x4066, 0x00},
 496         {0x4067, 0x00},
 497         {0x4068, 0x00},
 498         {0x4069, 0x00},
 499         {0x406a, 0x00},
 500         {0x406b, 0x00},
 501         {0x406c, 0x00},
 502         {0x406d, 0x00},
 503         {0x406e, 0x00},
 504         {0x406f, 0x00},
 505         {0x4070, 0x00},
 506         {0x4071, 0x00},
 507         {0x4072, 0x00},
 508         {0x4073, 0x00},
 509         {0x4074, 0x00},
 510         {0x4075, 0x00},
 511         {0x4076, 0x00},
 512         {0x4077, 0x00},
 513         {0x4078, 0x00},
 514         {0x4079, 0x00},
 515         {0x407a, 0x00},
 516         {0x407b, 0x00},
 517         {0x407c, 0x00},
 518         {0x407d, 0x00},
 519         {0x407e, 0x00},
 520         {0x407f, 0x00},
 521         {0x40e0, 0x00},
 522         {0x40e1, 0x00},
 523         {0x40e2, 0x00},
 524         {0x40e3, 0x00},
 525         {0x40e4, 0x00},
 526         {0x40e5, 0x00},
 527         {0x40e6, 0x00},
 528         {0x40e7, 0x00},
 529         {0x40e8, 0x00},
 530         {0x40e9, 0x80},
 531         {0x40ea, 0x00},
 532         {0x40eb, 0x80},
 533         {0x40ec, 0x00},
 534         {0x40ed, 0x80},
 535         {0x40ee, 0x00},
 536         {0x40ef, 0x80},
 537         {0x40f0, 0x02},
 538         {0x40f1, 0x04},
 539         {0x4300, 0x00},
 540         {0x4301, 0x00},
 541         {0x4302, 0x00},
 542         {0x4303, 0x00},
 543         {0x4304, 0x00},
 544         {0x4305, 0x00},
 545         {0x4306, 0x00},
 546         {0x4307, 0x00},
 547         {0x4308, 0x00},
 548         {0x4309, 0x00},
 549         {0x430a, 0x00},
 550         {0x430b, 0xff},
 551         {0x430c, 0xff},
 552         {0x430d, 0x00},
 553         {0x430e, 0x00},
 554         {0x4315, 0x00},
 555         {0x4316, 0x00},
 556         {0x4317, 0x00},
 557         {0x4318, 0x00},
 558         {0x4319, 0x00},
 559         {0x431a, 0x00},
 560         {0x431b, 0x00},
 561         {0x431c, 0x00},
 562         {0x4500, 0x07},
 563         {0x4501, 0x00},
 564         {0x4502, 0x00},
 565         {0x4503, 0x0f},
 566         {0x4504, 0x80},
 567         {0x4506, 0x01},
 568         {0x4509, 0x05},
 569         {0x450c, 0x00},
 570         {0x450d, 0x20},
 571         {0x450e, 0x00},
 572         {0x450f, 0x00},
 573         {0x4510, 0x00},
 574         {0x4523, 0x00},
 575         {0x4526, 0x00},
 576         {0x4542, 0x00},
 577         {0x4543, 0x00},
 578         {0x4544, 0x00},
 579         {0x4545, 0x00},
 580         {0x4546, 0x00},
 581         {0x4547, 0x10},
 582         {0x4602, 0x00},
 583         {0x4603, 0x15},
 584         {0x460b, 0x07},
 585         {0x4680, 0x11},
 586         {0x4686, 0x00},
 587         {0x4687, 0x00},
 588         {0x4700, 0x00},
 589         {0x4800, 0x64},
 590         {0x4806, 0x40},
 591         {0x480b, 0x10},
 592         {0x480c, 0x80},
 593         {0x480f, 0x32},
 594         {0x4813, 0xe4},
 595         {0x4837, 0x14},
 596         {0x4850, 0x42},
 597         {0x4884, 0x04},
 598         {0x4c00, 0xf8},
 599         {0x4c01, 0x44},
 600         {0x4c03, 0x00},
 601         {0x4d00, 0x00},
 602         {0x4d01, 0x16},
 603         {0x4d04, 0x10},
 604         {0x4d05, 0x00},
 605         {0x4d06, 0x0c},
 606         {0x4d07, 0x00},
 607         {0x3d84, 0x04},
 608         {0x3680, 0xa4},
 609         {0x3682, 0x80},
 610         {0x3601, 0x40},
 611         {0x3602, 0x90},
 612         {0x3608, 0x0a},
 613         {0x3938, 0x09},
 614         {0x3a74, 0x84},
 615         {0x3a99, 0x84},
 616         {0x3ab9, 0xa6},
 617         {0x3aba, 0xba},
 618         {0x3b12, 0x84},
 619         {0x3b14, 0xbb},
 620         {0x3b15, 0xbf},
 621         {0x3a29, 0x26},
 622         {0x3a1f, 0x8a},
 623         {0x3a22, 0x91},
 624         {0x3a25, 0x96},
 625         {0x3a28, 0xb4},
 626         {0x3a2b, 0xba},
 627         {0x3a2e, 0xbf},
 628         {0x3a31, 0xc1},
 629         {0x3a20, 0x00},
 630         {0x3939, 0x9d},
 631         {0x3902, 0x0e},
 632         {0x3903, 0x0e},
 633         {0x3904, 0x0e},
 634         {0x3905, 0x0e},
 635         {0x3906, 0x07},
 636         {0x3907, 0x0d},
 637         {0x3908, 0x11},
 638         {0x3909, 0x12},
 639         {0x360f, 0x99},
 640         {0x390c, 0x33},
 641         {0x390d, 0x66},
 642         {0x390e, 0xaa},
 643         {0x3911, 0x90},
 644         {0x3913, 0x90},
 645         {0x3915, 0x90},
 646         {0x3917, 0x90},
 647         {0x3b3f, 0x9d},
 648         {0x3b45, 0x9d},
 649         {0x3b1b, 0xc9},
 650         {0x3b21, 0xc9},
 651         {0x3440, 0xa4},
 652         {0x3a23, 0x15},
 653         {0x3a26, 0x1d},
 654         {0x3a2c, 0x4a},
 655         {0x3a2f, 0x18},
 656         {0x3a32, 0x55},
 657         {0x3b0a, 0x01},
 658         {0x3b0b, 0x00},
 659         {0x3b0e, 0x01},
 660         {0x3b0f, 0x00},
 661         {0x392c, 0x02},
 662         {0x392d, 0x02},
 663         {0x392e, 0x04},
 664         {0x392f, 0x03},
 665         {0x3930, 0x08},
 666         {0x3931, 0x07},
 667         {0x3932, 0x10},
 668         {0x3933, 0x0c},
 669         {0x3609, 0x08},
 670         {0x3921, 0x0f},
 671         {0x3928, 0x15},
 672         {0x3929, 0x2a},
 673         {0x392a, 0x54},
 674         {0x392b, 0xa8},
 675         {0x3426, 0x10},
 676         {0x3407, 0x01},
 677         {0x3404, 0x01},
 678         {0x3500, 0x00},
 679         {0x3501, 0x10},
 680         {0x3502, 0x10},
 681         {0x3508, 0x0f},
 682         {0x3509, 0x80},
 683 };
 684
 685 static const struct ov08x40_reg mode_1928x1208_regs[] = {
 686         {0x5000, 0x55},
 687         {0x5001, 0x00},
 688         {0x5008, 0xb0},
 689         {0x50c1, 0x00},
 690         {0x53c1, 0x00},
 691         {0x5f40, 0x00},
 692         {0x5f41, 0x40},
 693         {0x0300, 0x3a},
 694         {0x0301, 0xc8},
 695         {0x0302, 0x31},
 696         {0x0303, 0x03},
 697         {0x0304, 0x01},
 698         {0x0305, 0xa1},
 699         {0x0306, 0x04},
 700         {0x0307, 0x01},
 701         {0x0308, 0x03},
 702         {0x0309, 0x03},
 703         {0x0310, 0x0a},
 704         {0x0311, 0x02},
 705         {0x0312, 0x01},
 706         {0x0313, 0x08},
 707         {0x0314, 0x66},
 708         {0x0315, 0x00},
 709         {0x0316, 0x34},
 710         {0x0320, 0x02},
 711         {0x0321, 0x03},
 712         {0x0323, 0x05},
 713         {0x0324, 0x01},
 714         {0x0325, 0xb8},
 715         {0x0326, 0x4a},
 716         {0x0327, 0x04},
 717         {0x0329, 0x00},
 718         {0x032a, 0x05},
 719         {0x032b, 0x00},
 720         {0x032c, 0x00},
 721         {0x032d, 0x00},
 722         {0x032e, 0x02},
 723         {0x032f, 0xa0},
 724         {0x0350, 0x00},
 725         {0x0360, 0x01},
 726         {0x1216, 0x60},
 727         {0x1217, 0x5b},
 728         {0x1218, 0x00},
 729         {0x1220, 0x24},
 730         {0x198a, 0x00},
 731         {0x198b, 0x01},
 732         {0x198e, 0x00},
 733         {0x198f, 0x01},
 734         {0x3009, 0x04},
 735         {0x3012, 0x41},
 736         {0x3015, 0x00},
 737         {0x3016, 0xb0},
 738         {0x3017, 0xf0},
 739         {0x3018, 0xf0},
 740         {0x3019, 0xd2},
 741         {0x301a, 0xb0},
 742         {0x301c, 0x81},
 743         {0x301d, 0x02},
 744         {0x301e, 0x80},
 745         {0x3022, 0xf0},
 746         {0x3025, 0x89},
 747         {0x3030, 0x03},
 748         {0x3044, 0xc2},
 749         {0x3050, 0x35},
 750         {0x3051, 0x60},
 751         {0x3052, 0x25},
 752         {0x3053, 0x00},
 753         {0x3054, 0x00},
 754         {0x3055, 0x02},
 755         {0x3056, 0x80},
 756         {0x3057, 0x80},
 757         {0x3058, 0x80},
 758         {0x3059, 0x00},
 759         {0x3107, 0x86},
 760         {0x3400, 0x1c},
 761         {0x3401, 0x80},
 762         {0x3402, 0x8c},
 763         {0x3419, 0x08},
 764         {0x341a, 0xaf},
 765         {0x341b, 0x30},
 766         {0x3420, 0x00},
 767         {0x3421, 0x00},
 768         {0x3422, 0x00},
 769         {0x3423, 0x00},
 770         {0x3424, 0x00},
 771         {0x3425, 0x00},
 772         {0x3426, 0x00},
 773         {0x3427, 0x00},
 774         {0x3428, 0x0f},
 775         {0x3429, 0x00},
 776         {0x342a, 0x00},
 777         {0x342b, 0x00},
 778         {0x342c, 0x00},
 779         {0x342d, 0x00},
 780         {0x342e, 0x00},
 781         {0x342f, 0x11},
 782         {0x3430, 0x11},
 783         {0x3431, 0x10},
 784         {0x3432, 0x00},
 785         {0x3433, 0x00},
 786         {0x3434, 0x00},
 787         {0x3435, 0x00},
 788         {0x3436, 0x00},
 789         {0x3437, 0x00},
 790         {0x3442, 0x02},
 791         {0x3443, 0x02},
 792         {0x3444, 0x07},
 793         {0x3450, 0x00},
 794         {0x3451, 0x00},
 795         {0x3452, 0x18},
 796         {0x3453, 0x18},
 797         {0x3454, 0x00},
 798         {0x3455, 0x80},
 799         {0x3456, 0x08},
 800         {0x3500, 0x00},
 801         {0x3501, 0x02},
 802         {0x3502, 0x00},
 803         {0x3504, 0x4c},
 804         {0x3506, 0x30},
 805         {0x3507, 0x00},
 806         {0x3508, 0x01},
 807         {0x3509, 0x00},
 808         {0x350a, 0x01},
 809         {0x350b, 0x00},
 810         {0x350c, 0x00},
 811         {0x3540, 0x00},
 812         {0x3541, 0x01},
 813         {0x3542, 0x00},
 814         {0x3544, 0x4c},
 815         {0x3546, 0x30},
 816         {0x3547, 0x00},
 817         {0x3548, 0x01},
 818         {0x3549, 0x00},
 819         {0x354a, 0x01},
 820         {0x354b, 0x00},
 821         {0x354c, 0x00},
 822         {0x3688, 0x02},
 823         {0x368a, 0x2e},
 824         {0x368e, 0x71},
 825         {0x3696, 0xd1},
 826         {0x3699, 0x00},
 827         {0x369a, 0x00},
 828         {0x36a4, 0x00},
 829         {0x36a6, 0x00},
 830         {0x3711, 0x00},
 831         {0x3712, 0x50},
 832         {0x3713, 0x00},
 833         {0x3714, 0x21},
 834         {0x3716, 0x00},
 835         {0x3718, 0x07},
 836         {0x371a, 0x1c},
 837         {0x371b, 0x00},
 838         {0x3720, 0x08},
 839         {0x3725, 0x32},
 840         {0x3727, 0x05},
 841         {0x3760, 0x02},
 842         {0x3761, 0x28},
 843         {0x3762, 0x02},
 844         {0x3763, 0x02},
 845         {0x3764, 0x02},
 846         {0x3765, 0x2c},
 847         {0x3766, 0x04},
 848         {0x3767, 0x2c},
 849         {0x3768, 0x02},
 850         {0x3769, 0x00},
 851         {0x376b, 0x20},
 852         {0x376e, 0x07},
 853         {0x37b0, 0x01},
 854         {0x37b1, 0x0f},
 855         {0x37b2, 0x01},
 856         {0x37b3, 0xd6},
 857         {0x37b4, 0x01},
 858         {0x37b5, 0x48},
 859         {0x37b6, 0x02},
 860         {0x37b7, 0x40},
 861         {0x3800, 0x00},
 862         {0x3801, 0x00},
 863         {0x3802, 0x00},
 864         {0x3803, 0x00},
 865         {0x3804, 0x0f},
 866         {0x3805, 0x1f},
 867         {0x3806, 0x09},
 868         {0x3807, 0x7f},
 869         {0x3808, 0x07},
 870         {0x3809, 0x88},
 871         {0x380a, 0x04},
 872         {0x380b, 0xb8},
 873         {0x380c, 0x02},
 874         {0x380d, 0xd0},
 875         {0x380e, 0x11},
 876         {0x380f, 0x5c},
 877         {0x3810, 0x00},
 878         {0x3811, 0x04},
 879         {0x3812, 0x00},
 880         {0x3813, 0x03},
 881         {0x3814, 0x11},
 882         {0x3815, 0x11},
 883         {0x3820, 0x02},
 884         {0x3821, 0x14},
 885         {0x3822, 0x00},
 886         {0x3823, 0x04},
 887         {0x3828, 0x0f},
 888         {0x382a, 0x80},
 889         {0x382e, 0x41},
 890         {0x3837, 0x08},
 891         {0x383a, 0x81},
 892         {0x383b, 0x81},
 893         {0x383c, 0x11},
 894         {0x383d, 0x11},
 895         {0x383e, 0x00},
 896         {0x383f, 0x38},
 897         {0x3840, 0x00},
 898         {0x3847, 0x00},
 899         {0x384a, 0x00},
 900         {0x384c, 0x02},
 901         {0x384d, 0xd0},
 902         {0x3856, 0x50},
 903         {0x3857, 0x30},
 904         {0x3858, 0x80},
 905         {0x3859, 0x40},
 906         {0x3860, 0x00},
 907         {0x3888, 0x00},
 908         {0x3889, 0x00},
 909         {0x388a, 0x00},
 910         {0x388b, 0x00},
 911         {0x388c, 0x00},
 912         {0x388d, 0x00},
 913         {0x388e, 0x00},
 914         {0x388f, 0x00},
 915         {0x3894, 0x00},
 916         {0x3895, 0x00},
 917         {0x3c84, 0x00},
 918         {0x3d85, 0x8b},
 919         {0x3daa, 0x80},
 920         {0x3dab, 0x14},
 921         {0x3dac, 0x80},
 922         {0x3dad, 0xc8},
 923         {0x3dae, 0x81},
 924         {0x3daf, 0x7b},
 925         {0x3f00, 0x10},
 926         {0x3f01, 0x11},
 927         {0x3f06, 0x0d},
 928         {0x3f07, 0x0b},
 929         {0x3f08, 0x0d},
 930         {0x3f09, 0x0b},
 931         {0x3f0a, 0x01},
 932         {0x3f0b, 0x11},
 933         {0x3f0c, 0x33},
 934         {0x4001, 0x07},
 935         {0x4007, 0x20},
 936         {0x4008, 0x00},
 937         {0x4009, 0x05},
 938         {0x400a, 0x00},
 939         {0x400b, 0x04},
 940         {0x400c, 0x00},
 941         {0x400d, 0x04},
 942         {0x400e, 0x14},
 943         {0x4010, 0xf4},
 944         {0x4011, 0x03},
 945         {0x4012, 0x55},
 946         {0x4015, 0x00},
 947         {0x4016, 0x27},
 948         {0x4017, 0x00},
 949         {0x4018, 0x0f},
 950         {0x401b, 0x08},
 951         {0x401c, 0x00},
 952         {0x401d, 0x10},
 953         {0x401e, 0x02},
 954         {0x401f, 0x00},
 955         {0x4050, 0x06},
 956         {0x4051, 0xff},
 957         {0x4052, 0xff},
 958         {0x4053, 0xff},
 959         {0x4054, 0xff},
 960         {0x4055, 0xff},
 961         {0x4056, 0xff},
 962         {0x4057, 0x7f},
 963         {0x4058, 0x00},
 964         {0x4059, 0x00},
 965         {0x405a, 0x00},
 966         {0x405b, 0x00},
 967         {0x405c, 0x07},
 968         {0x405d, 0xff},
 969         {0x405e, 0x07},
 970         {0x405f, 0xff},
 971         {0x4080, 0x78},
 972         {0x4081, 0x78},
 973         {0x4082, 0x78},
 974         {0x4083, 0x78},
 975         {0x4019, 0x00},
 976         {0x401a, 0x40},
 977         {0x4020, 0x04},
 978         {0x4021, 0x00},
 979         {0x4022, 0x04},
 980         {0x4023, 0x00},
 981         {0x4024, 0x04},
 982         {0x4025, 0x00},
 983         {0x4026, 0x04},
 984         {0x4027, 0x00},
 985         {0x4030, 0x00},
 986         {0x4031, 0x00},
 987         {0x4032, 0x00},
 988         {0x4033, 0x00},
 989         {0x4034, 0x00},
 990         {0x4035, 0x00},
 991         {0x4036, 0x00},
 992         {0x4037, 0x00},
 993         {0x4040, 0x00},
 994         {0x4041, 0x80},
 995         {0x4042, 0x00},
 996         {0x4043, 0x80},
 997         {0x4044, 0x00},
 998         {0x4045, 0x80},
 999         {0x4046, 0x00},
1000         {0x4047, 0x80},
1001         {0x4060, 0x00},
1002         {0x4061, 0x00},
1003         {0x4062, 0x00},
1004         {0x4063, 0x00},
1005         {0x4064, 0x00},
1006         {0x4065, 0x00},
1007         {0x4066, 0x00},
1008         {0x4067, 0x00},
1009         {0x4068, 0x00},
1010         {0x4069, 0x00},
1011         {0x406a, 0x00},
1012         {0x406b, 0x00},
1013         {0x406c, 0x00},
1014         {0x406d, 0x00},
1015         {0x406e, 0x00},
1016         {0x406f, 0x00},
1017         {0x4070, 0x00},
1018         {0x4071, 0x00},
1019         {0x4072, 0x00},
1020         {0x4073, 0x00},
1021         {0x4074, 0x00},
1022         {0x4075, 0x00},
1023         {0x4076, 0x00},
1024         {0x4077, 0x00},
1025         {0x4078, 0x00},
1026         {0x4079, 0x00},
1027         {0x407a, 0x00},
1028         {0x407b, 0x00},
1029         {0x407c, 0x00},
1030         {0x407d, 0x00},
1031         {0x407e, 0x00},
1032         {0x407f, 0x00},
1033         {0x40e0, 0x00},
1034         {0x40e1, 0x00},
1035         {0x40e2, 0x00},
1036         {0x40e3, 0x00},
1037         {0x40e4, 0x00},
1038         {0x40e5, 0x00},
1039         {0x40e6, 0x00},
1040         {0x40e7, 0x00},
1041         {0x40e8, 0x00},
1042         {0x40e9, 0x80},
1043         {0x40ea, 0x00},
1044         {0x40eb, 0x80},
1045         {0x40ec, 0x00},
1046         {0x40ed, 0x80},
1047         {0x40ee, 0x00},
1048         {0x40ef, 0x80},
1049         {0x40f0, 0x02},
1050         {0x40f1, 0x04},
1051         {0x4300, 0x00},
1052         {0x4301, 0x00},
1053         {0x4302, 0x00},
1054         {0x4303, 0x00},
1055         {0x4304, 0x00},
1056         {0x4305, 0x00},
1057         {0x4306, 0x00},
1058         {0x4307, 0x00},
1059         {0x4308, 0x00},
1060         {0x4309, 0x00},
1061         {0x430a, 0x00},
1062         {0x430b, 0xff},
1063         {0x430c, 0xff},
1064         {0x430d, 0x00},
1065         {0x430e, 0x00},
1066         {0x4315, 0x00},
1067         {0x4316, 0x00},
1068         {0x4317, 0x00},
1069         {0x4318, 0x00},
1070         {0x4319, 0x00},
1071         {0x431a, 0x00},
1072         {0x431b, 0x00},
1073         {0x431c, 0x00},
1074         {0x4500, 0x07},
1075         {0x4501, 0x10},
1076         {0x4502, 0x00},
1077         {0x4503, 0x0f},
1078         {0x4504, 0x80},
1079         {0x4506, 0x01},
1080         {0x4509, 0x05},
1081         {0x450c, 0x00},
1082         {0x450d, 0x20},
1083         {0x450e, 0x00},
1084         {0x450f, 0x00},
1085         {0x4510, 0x00},
1086         {0x4523, 0x00},
1087         {0x4526, 0x00},
1088         {0x4542, 0x00},
1089         {0x4543, 0x00},
1090         {0x4544, 0x00},
1091         {0x4545, 0x00},
1092         {0x4546, 0x00},
1093         {0x4547, 0x10},
1094         {0x4602, 0x00},
1095         {0x4603, 0x15},
1096         {0x460b, 0x07},
1097         {0x4680, 0x11},
1098         {0x4686, 0x00},
1099         {0x4687, 0x00},
1100         {0x4700, 0x00},
1101         {0x4800, 0x64},
1102         {0x4806, 0x40},
1103         {0x480b, 0x10},
1104         {0x480c, 0x80},
1105         {0x480f, 0x32},
1106         {0x4813, 0xe4},
1107         {0x4837, 0x14},
1108         {0x4850, 0x42},
1109         {0x4884, 0x04},
1110         {0x4c00, 0xf8},
1111         {0x4c01, 0x44},
1112         {0x4c03, 0x00},
1113         {0x4d00, 0x00},
1114         {0x4d01, 0x16},
1115         {0x4d04, 0x10},
1116         {0x4d05, 0x00},
1117         {0x4d06, 0x0c},
1118         {0x4d07, 0x00},
1119         {0x3d84, 0x04},
1120         {0x3680, 0xa4},
1121         {0x3682, 0x80},
1122         {0x3601, 0x40},
1123         {0x3602, 0x90},
1124         {0x3608, 0x0a},
1125         {0x3938, 0x09},
1126         {0x3a74, 0x84},
1127         {0x3a99, 0x84},
1128         {0x3ab9, 0xa6},
1129         {0x3aba, 0xba},
1130         {0x3b12, 0x84},
1131         {0x3b14, 0xbb},
1132         {0x3b15, 0xbf},
1133         {0x3a29, 0x26},
1134         {0x3a1f, 0x8a},
1135         {0x3a22, 0x91},
1136         {0x3a25, 0x96},
1137         {0x3a28, 0xb4},
1138         {0x3a2b, 0xba},
1139         {0x3a2e, 0xbf},
1140         {0x3a31, 0xc1},
1141         {0x3a20, 0x05},
1142         {0x3939, 0x6b},
1143         {0x3902, 0x10},
1144         {0x3903, 0x10},
1145         {0x3904, 0x10},
1146         {0x3905, 0x10},
1147         {0x3906, 0x01},
1148         {0x3907, 0x0b},
1149         {0x3908, 0x10},
1150         {0x3909, 0x13},
1151         {0x360f, 0x99},
1152         {0x390b, 0x11},
1153         {0x390c, 0x21},
1154         {0x390d, 0x32},
1155         {0x390e, 0x76},
1156         {0x3911, 0x90},
1157         {0x3913, 0x90},
1158         {0x3b3f, 0x9d},
1159         {0x3b45, 0x9d},
1160         {0x3b1b, 0xc9},
1161         {0x3b21, 0xc9},
1162         {0x3a1a, 0x1c},
1163         {0x3a23, 0x15},
1164         {0x3a26, 0x17},
1165         {0x3a2c, 0x50},
1166         {0x3a2f, 0x18},
1167         {0x3a32, 0x4f},
1168         {0x3ace, 0x01},
1169         {0x3ad2, 0x01},
1170         {0x3ad6, 0x01},
1171         {0x3ada, 0x01},
1172         {0x3ade, 0x01},
1173         {0x3ae2, 0x01},
1174         {0x3aee, 0x01},
1175         {0x3af2, 0x01},
1176         {0x3af6, 0x01},
1177         {0x3afa, 0x01},
1178         {0x3afe, 0x01},
1179         {0x3b02, 0x01},
1180         {0x3b06, 0x01},
1181         {0x3b0a, 0x01},
1182         {0x3b0b, 0x00},
1183         {0x3b0e, 0x01},
1184         {0x3b0f, 0x00},
1185         {0x392c, 0x02},
1186         {0x392d, 0x01},
1187         {0x392e, 0x04},
1188         {0x392f, 0x03},
1189         {0x3930, 0x09},
1190         {0x3931, 0x07},
1191         {0x3932, 0x10},
1192         {0x3933, 0x0d},
1193         {0x3609, 0x08},
1194         {0x3921, 0x0f},
1195         {0x3928, 0x15},
1196         {0x3929, 0x2a},
1197         {0x392a, 0x52},
1198         {0x392b, 0xa3},
1199         {0x340b, 0x1b},
1200         {0x3426, 0x10},
1201         {0x3407, 0x01},
1202         {0x3404, 0x01},
1203         {0x3500, 0x00},
1204         {0x3501, 0x08},
1205         {0x3502, 0x10},
1206         {0x3508, 0x04},
1207         {0x3509, 0x00},
1208 };
1209
1210 static const char * const ov08x40_test_pattern_menu[] = {
1211         "Disabled",
1212         "Vertical Color Bar Type 1",
1213         "Vertical Color Bar Type 2",
1214         "Vertical Color Bar Type 3",
1215         "Vertical Color Bar Type 4"
1216 };
1217
1218 /* Configurations for supported link frequencies */
1219 #define OV08X40_LINK_FREQ_400MHZ        400000000ULL
1220 #define OV08X40_SCLK_96MHZ              96000000ULL
1221 #define OV08X40_XVCLK                   19200000
1222 #define OV08X40_DATA_LANES              4
1223
1224 /*
1225  * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
1226  * data rate => double data rate; number of lanes => 4; bits per pixel => 10
1227  */
1228 static u64 link_freq_to_pixel_rate(u64 f)
1229 {
1230         f *= 2 * OV08X40_DATA_LANES;
1231         do_div(f, 10);
1232
1233         return f;
1234 }
1235
1236 /* Menu items for LINK_FREQ V4L2 control */
1237 static const s64 link_freq_menu_items[] = {
1238         OV08X40_LINK_FREQ_400MHZ,
1239 };
1240
1241 /* Link frequency configs */
1242 static const struct ov08x40_link_freq_config link_freq_configs[] = {
1243         [OV08X40_LINK_FREQ_400MHZ_INDEX] = {
1244                 .reg_list = {
1245                         .num_of_regs = ARRAY_SIZE(mipi_data_rate_800mbps),
1246                         .regs = mipi_data_rate_800mbps,
1247                 }
1248         },
1249 };
1250
1251 /* Mode configs */
1252 static const struct ov08x40_mode supported_modes[] = {
1253         {
1254                 .width = 3856,
1255                 .height = 2416,
1256                 .vts_def = OV08X40_VTS_30FPS,
1257                 .vts_min = OV08X40_VTS_30FPS,
1258                 .llp = 0x10aa, /* in normal mode, tline time = 2 * HTS / SCLK */
1259                 .lanes = 4,
1260                 .reg_list = {
1261                         .num_of_regs = ARRAY_SIZE(mode_3856x2416_regs),
1262                         .regs = mode_3856x2416_regs,
1263                 },
1264                 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX,
1265                 .exposure_shift = 1,
1266                 .exposure_margin = OV08X40_EXPOSURE_MAX_MARGIN,
1267         },
1268         {
1269                 .width = 1928,
1270                 .height = 1208,
1271                 .vts_def = OV08X40_VTS_BIN_30FPS,
1272                 .vts_min = OV08X40_VTS_BIN_30FPS,
1273                 .llp = 0x960,
1274                 .lanes = 4,
1275                 .reg_list = {
1276                         .num_of_regs = ARRAY_SIZE(mode_1928x1208_regs),
1277                         .regs = mode_1928x1208_regs,
1278                 },
1279                 .link_freq_index = OV08X40_LINK_FREQ_400MHZ_INDEX,
1280                 .exposure_shift = 0,
1281                 .exposure_margin = OV08X40_EXPOSURE_BIN_MAX_MARGIN,
1282         },
1283 };
1284
1285 static const char * const ov08x40_supply_names[] = {
1286         "dovdd",        /* Digital I/O power */
1287         "avdd",         /* Analog power */
1288         "dvdd",         /* Digital core power */
1289 };
1290
1291 struct ov08x40 {
1292         struct v4l2_subdev sd;
1293         struct media_pad pad;
1294
1295         struct v4l2_ctrl_handler ctrl_handler;
1296         /* V4L2 Controls */
1297         struct v4l2_ctrl *link_freq;
1298         struct v4l2_ctrl *pixel_rate;
1299         struct v4l2_ctrl *vblank;
1300         struct v4l2_ctrl *hblank;
1301         struct v4l2_ctrl *exposure;
1302
1303         struct clk              *xvclk;
1304         struct gpio_desc        *reset_gpio;
1305         struct regulator_bulk_data supplies[ARRAY_SIZE(ov08x40_supply_names)];
1306
1307         /* Current mode */
1308         const struct ov08x40_mode *cur_mode;
1309
1310         /* Mutex for serialized access */
1311         struct mutex mutex;
1312
1313         /* True if the device has been identified */
1314         bool identified;
1315 };
1316
1317 #define to_ov08x40(_sd) container_of(_sd, struct ov08x40, sd)
1318
1319 static int ov08x40_power_on(struct device *dev)
1320 {
1321         struct v4l2_subdev *sd = dev_get_drvdata(dev);
1322         struct ov08x40 *ov08x = to_ov08x40(sd);
1323         int ret;
1324
1325         if (is_acpi_node(dev_fwnode(dev)))
1326                 return 0;
1327
1328         ret = clk_prepare_enable(ov08x->xvclk);
1329         if (ret < 0) {
1330                 dev_err(dev, "failed to enable xvclk\n");
1331                 return ret;
1332         }
1333
1334         if (ov08x->reset_gpio) {
1335                 gpiod_set_value_cansleep(ov08x->reset_gpio, 1);
1336                 usleep_range(1000, 2000);
1337         }
1338
1339         ret = regulator_bulk_enable(ARRAY_SIZE(ov08x40_supply_names),
1340                                     ov08x->supplies);
1341         if (ret < 0) {
1342                 dev_err(dev, "failed to enable regulators\n");
1343                 goto disable_clk;
1344         }
1345
1346         gpiod_set_value_cansleep(ov08x->reset_gpio, 0);
1347         usleep_range(1500, 1800);
1348
1349         return 0;
1350
1351 disable_clk:
1352         gpiod_set_value_cansleep(ov08x->reset_gpio, 1);
1353         clk_disable_unprepare(ov08x->xvclk);
1354
1355         return ret;
1356 }
1357
1358 static int ov08x40_power_off(struct device *dev)
1359 {
1360         struct v4l2_subdev *sd = dev_get_drvdata(dev);
1361         struct ov08x40 *ov08x = to_ov08x40(sd);
1362
1363         if (is_acpi_node(dev_fwnode(dev)))
1364                 return 0;
1365
1366         gpiod_set_value_cansleep(ov08x->reset_gpio, 1);
1367         regulator_bulk_disable(ARRAY_SIZE(ov08x40_supply_names),
1368                                ov08x->supplies);
1369         clk_disable_unprepare(ov08x->xvclk);
1370
1371         return 0;
1372 }
1373
1374 /* Read registers up to 4 at a time */
1375 static int ov08x40_read_reg(struct ov08x40 *ov08x,
1376                             u16 reg, u32 len, u32 *val)
1377 {
1378         struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1379         struct i2c_msg msgs[2];
1380         u8 *data_be_p;
1381         int ret;
1382         __be32 data_be = 0;
1383         __be16 reg_addr_be = cpu_to_be16(reg);
1384
1385         if (len > 4)
1386                 return -EINVAL;
1387
1388         data_be_p = (u8 *)&data_be;
1389         /* Write register address */
1390         msgs[0].addr = client->addr;
1391         msgs[0].flags = 0;
1392         msgs[0].len = 2;
1393         msgs[0].buf = (u8 *)&reg_addr_be;
1394
1395         /* Read data from register */
1396         msgs[1].addr = client->addr;
1397         msgs[1].flags = I2C_M_RD;
1398         msgs[1].len = len;
1399         msgs[1].buf = &data_be_p[4 - len];
1400
1401         ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1402         if (ret != ARRAY_SIZE(msgs))
1403                 return -EIO;
1404
1405         *val = be32_to_cpu(data_be);
1406
1407         return 0;
1408 }
1409
1410 static int __ov08x40_burst_fill_regs(struct i2c_client *client, u16 first_reg,
1411                                      u16 last_reg, size_t num_regs, u8 val)
1412 {
1413         struct i2c_msg msgs;
1414         size_t i;
1415         int ret;
1416
1417         msgs.addr = client->addr;
1418         msgs.flags = 0;
1419         msgs.len = 2 + num_regs;
1420         msgs.buf = kmalloc(msgs.len, GFP_KERNEL);
1421
1422         if (!msgs.buf)
1423                 return -ENOMEM;
1424
1425         put_unaligned_be16(first_reg, msgs.buf);
1426
1427         for (i = 0; i < num_regs; ++i)
1428                 msgs.buf[2 + i] = val;
1429
1430         ret = i2c_transfer(client->adapter, &msgs, 1);
1431
1432         kfree(msgs.buf);
1433
1434         if (ret != 1) {
1435                 dev_err(&client->dev, "Failed regs transferred: %d\n", ret);
1436                 return -EIO;
1437         }
1438
1439         return 0;
1440 }
1441
1442 static int ov08x40_burst_fill_regs(struct ov08x40 *ov08x, u16 first_reg,
1443                                    u16 last_reg,  u8 val)
1444 {
1445         struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1446         size_t num_regs, num_write_regs;
1447         int ret;
1448
1449         num_regs = last_reg - first_reg + 1;
1450         num_write_regs = num_regs;
1451
1452         if (client->adapter->quirks && client->adapter->quirks->max_write_len)
1453                 num_write_regs = client->adapter->quirks->max_write_len - 2;
1454
1455         while (first_reg < last_reg) {
1456                 ret = __ov08x40_burst_fill_regs(client, first_reg, last_reg,
1457                                                 num_write_regs, val);
1458                 if (ret)
1459                         return ret;
1460
1461                 first_reg += num_write_regs;
1462         }
1463
1464         return 0;
1465 }
1466
1467 /* Write registers up to 4 at a time */
1468 static int ov08x40_write_reg(struct ov08x40 *ov08x,
1469                              u16 reg, u32 len, u32 __val)
1470 {
1471         struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1472         int buf_i, val_i;
1473         u8 buf[6], *val_p;
1474         __be32 val;
1475
1476         if (len > 4)
1477                 return -EINVAL;
1478
1479         buf[0] = reg >> 8;
1480         buf[1] = reg & 0xff;
1481
1482         val = cpu_to_be32(__val);
1483         val_p = (u8 *)&val;
1484         buf_i = 2;
1485         val_i = 4 - len;
1486
1487         while (val_i < 4)
1488                 buf[buf_i++] = val_p[val_i++];
1489
1490         if (i2c_master_send(client, buf, len + 2) != len + 2)
1491                 return -EIO;
1492
1493         return 0;
1494 }
1495
1496 /* Write a list of registers */
1497 static int ov08x40_write_regs(struct ov08x40 *ov08x,
1498                               const struct ov08x40_reg *regs, u32 len)
1499 {
1500         struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1501         int ret;
1502         u32 i;
1503
1504         for (i = 0; i < len; i++) {
1505                 ret = ov08x40_write_reg(ov08x, regs[i].address, 1,
1506                                         regs[i].val);
1507
1508                 if (ret) {
1509                         dev_err_ratelimited(&client->dev,
1510                                             "Failed to write reg 0x%4.4x. error = %d\n",
1511                                             regs[i].address, ret);
1512
1513                         return ret;
1514                 }
1515         }
1516
1517         return 0;
1518 }
1519
1520 static int ov08x40_write_reg_list(struct ov08x40 *ov08x,
1521                                   const struct ov08x40_reg_list *r_list)
1522 {
1523         return ov08x40_write_regs(ov08x, r_list->regs, r_list->num_of_regs);
1524 }
1525
1526 static int ov08x40_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1527 {
1528         const struct ov08x40_mode *default_mode = &supported_modes[0];
1529         struct ov08x40 *ov08x = to_ov08x40(sd);
1530         struct v4l2_mbus_framefmt *try_fmt =
1531                 v4l2_subdev_state_get_format(fh->state, 0);
1532
1533         mutex_lock(&ov08x->mutex);
1534
1535         /* Initialize try_fmt */
1536         try_fmt->width = default_mode->width;
1537         try_fmt->height = default_mode->height;
1538         try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1539         try_fmt->field = V4L2_FIELD_NONE;
1540
1541         /* No crop or compose */
1542         mutex_unlock(&ov08x->mutex);
1543
1544         return 0;
1545 }
1546
1547 static int ov08x40_update_digital_gain(struct ov08x40 *ov08x, u32 d_gain)
1548 {
1549         int ret;
1550         u32 val;
1551
1552         /*
1553          * 0x350C[1:0], 0x350B[7:0], 0x350A[4:0]
1554          */
1555
1556         val = (d_gain & OV08X40_DGTL_GAIN_L_MASK) << OV08X40_DGTL_GAIN_L_SHIFT;
1557         ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_L,
1558                                 OV08X40_REG_VALUE_08BIT, val);
1559         if (ret)
1560                 return ret;
1561
1562         val = (d_gain >> OV08X40_DGTL_GAIN_M_SHIFT) & OV08X40_DGTL_GAIN_M_MASK;
1563         ret = ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_M,
1564                                 OV08X40_REG_VALUE_08BIT, val);
1565         if (ret)
1566                 return ret;
1567
1568         val = (d_gain >> OV08X40_DGTL_GAIN_H_SHIFT) & OV08X40_DGTL_GAIN_H_MASK;
1569
1570         return ov08x40_write_reg(ov08x, OV08X40_REG_DGTL_GAIN_H,
1571                                  OV08X40_REG_VALUE_08BIT, val);
1572 }
1573
1574 static int ov08x40_enable_test_pattern(struct ov08x40 *ov08x, u32 pattern)
1575 {
1576         int ret;
1577         u32 val;
1578
1579         ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN,
1580                                OV08X40_REG_VALUE_08BIT, &val);
1581         if (ret)
1582                 return ret;
1583
1584         if (pattern) {
1585                 ret = ov08x40_read_reg(ov08x, OV08X40_REG_ISP,
1586                                        OV08X40_REG_VALUE_08BIT, &val);
1587                 if (ret)
1588                         return ret;
1589
1590                 ret = ov08x40_write_reg(ov08x, OV08X40_REG_ISP,
1591                                         OV08X40_REG_VALUE_08BIT,
1592                                         val | BIT(1));
1593                 if (ret)
1594                         return ret;
1595
1596                 ret = ov08x40_read_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN,
1597                                        OV08X40_REG_VALUE_08BIT, &val);
1598                 if (ret)
1599                         return ret;
1600
1601                 ret = ov08x40_write_reg(ov08x, OV08X40_REG_SHORT_TEST_PATTERN,
1602                                         OV08X40_REG_VALUE_08BIT,
1603                                         val | BIT(0));
1604                 if (ret)
1605                         return ret;
1606
1607                 ret = ov08x40_read_reg(ov08x, OV08X40_REG_TEST_PATTERN,
1608                                        OV08X40_REG_VALUE_08BIT, &val);
1609                 if (ret)
1610                         return ret;
1611
1612                 val &= OV08X40_TEST_PATTERN_MASK;
1613                 val |= ((pattern - 1) << OV08X40_TEST_PATTERN_BAR_SHIFT) |
1614                         OV08X40_TEST_PATTERN_ENABLE;
1615         } else {
1616                 val &= ~OV08X40_TEST_PATTERN_ENABLE;
1617         }
1618
1619         return ov08x40_write_reg(ov08x, OV08X40_REG_TEST_PATTERN,
1620                                  OV08X40_REG_VALUE_08BIT, val);
1621 }
1622
1623 static int ov08x40_set_ctrl_hflip(struct ov08x40 *ov08x, u32 ctrl_val)
1624 {
1625         int ret;
1626         u32 val;
1627
1628         ret = ov08x40_read_reg(ov08x, OV08X40_REG_MIRROR,
1629                                OV08X40_REG_VALUE_08BIT, &val);
1630         if (ret)
1631                 return ret;
1632
1633         return ov08x40_write_reg(ov08x, OV08X40_REG_MIRROR,
1634                                  OV08X40_REG_VALUE_08BIT,
1635                                  ctrl_val ? val | BIT(2) : val & ~BIT(2));
1636 }
1637
1638 static int ov08x40_set_ctrl_vflip(struct ov08x40 *ov08x, u32 ctrl_val)
1639 {
1640         int ret;
1641         u32 val;
1642
1643         ret = ov08x40_read_reg(ov08x, OV08X40_REG_VFLIP,
1644                                OV08X40_REG_VALUE_08BIT, &val);
1645         if (ret)
1646                 return ret;
1647
1648         return ov08x40_write_reg(ov08x, OV08X40_REG_VFLIP,
1649                                  OV08X40_REG_VALUE_08BIT,
1650                                  ctrl_val ? val | BIT(2) : val & ~BIT(2));
1651 }
1652
1653 static int ov08x40_set_ctrl(struct v4l2_ctrl *ctrl)
1654 {
1655         struct ov08x40 *ov08x = container_of(ctrl->handler,
1656                                              struct ov08x40, ctrl_handler);
1657         struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1658         s64 max;
1659         int exp;
1660         int fll;
1661         int ret = 0;
1662
1663         /* Propagate change of current control to all related controls */
1664         switch (ctrl->id) {
1665         case V4L2_CID_VBLANK:
1666                 /* Update max exposure while meeting expected vblanking */
1667                 /*
1668                  * because in normal mode, 1 HTS = 0.5 tline
1669                  * fps = sclk / hts / vts
1670                  * so the vts value needs to be double
1671                  */
1672                 max = ((ov08x->cur_mode->height + ctrl->val) <<
1673                         ov08x->cur_mode->exposure_shift) -
1674                         ov08x->cur_mode->exposure_margin;
1675
1676                 __v4l2_ctrl_modify_range(ov08x->exposure,
1677                                          ov08x->exposure->minimum,
1678                                          max, ov08x->exposure->step, max);
1679                 break;
1680         }
1681
1682         /*
1683          * Applying V4L2 control value only happens
1684          * when power is up for streaming
1685          */
1686         if (!pm_runtime_get_if_in_use(&client->dev))
1687                 return 0;
1688
1689         switch (ctrl->id) {
1690         case V4L2_CID_ANALOGUE_GAIN:
1691                 ret = ov08x40_write_reg(ov08x, OV08X40_REG_ANALOG_GAIN,
1692                                         OV08X40_REG_VALUE_16BIT,
1693                                         ctrl->val << 1);
1694                 break;
1695         case V4L2_CID_DIGITAL_GAIN:
1696                 ret = ov08x40_update_digital_gain(ov08x, ctrl->val);
1697                 break;
1698         case V4L2_CID_EXPOSURE:
1699                 exp = (ctrl->val << ov08x->cur_mode->exposure_shift) -
1700                         ov08x->cur_mode->exposure_margin;
1701
1702                 ret = ov08x40_write_reg(ov08x, OV08X40_REG_EXPOSURE,
1703                                         OV08X40_REG_VALUE_24BIT,
1704                                         exp);
1705                 break;
1706         case V4L2_CID_VBLANK:
1707                 fll = ((ov08x->cur_mode->height + ctrl->val) <<
1708                            ov08x->cur_mode->exposure_shift);
1709
1710                 ret = ov08x40_write_reg(ov08x, OV08X40_REG_VTS,
1711                                         OV08X40_REG_VALUE_16BIT,
1712                                         fll);
1713                 break;
1714         case V4L2_CID_TEST_PATTERN:
1715                 ret = ov08x40_enable_test_pattern(ov08x, ctrl->val);
1716                 break;
1717         case V4L2_CID_HFLIP:
1718                 ov08x40_set_ctrl_hflip(ov08x, ctrl->val);
1719                 break;
1720         case V4L2_CID_VFLIP:
1721                 ov08x40_set_ctrl_vflip(ov08x, ctrl->val);
1722                 break;
1723         default:
1724                 dev_info(&client->dev,
1725                          "ctrl(id:0x%x,val:0x%x) is not handled\n",
1726                          ctrl->id, ctrl->val);
1727                 break;
1728         }
1729
1730         pm_runtime_put(&client->dev);
1731
1732         return ret;
1733 }
1734
1735 static const struct v4l2_ctrl_ops ov08x40_ctrl_ops = {
1736         .s_ctrl = ov08x40_set_ctrl,
1737 };
1738
1739 static int ov08x40_enum_mbus_code(struct v4l2_subdev *sd,
1740                                   struct v4l2_subdev_state *sd_state,
1741                                   struct v4l2_subdev_mbus_code_enum *code)
1742 {
1743         /* Only one bayer order(GRBG) is supported */
1744         if (code->index > 0)
1745                 return -EINVAL;
1746
1747         code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1748
1749         return 0;
1750 }
1751
1752 static int ov08x40_enum_frame_size(struct v4l2_subdev *sd,
1753                                    struct v4l2_subdev_state *sd_state,
1754                                    struct v4l2_subdev_frame_size_enum *fse)
1755 {
1756         if (fse->index >= ARRAY_SIZE(supported_modes))
1757                 return -EINVAL;
1758
1759         if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1760                 return -EINVAL;
1761
1762         fse->min_width = supported_modes[fse->index].width;
1763         fse->max_width = fse->min_width;
1764         fse->min_height = supported_modes[fse->index].height;
1765         fse->max_height = fse->min_height;
1766
1767         return 0;
1768 }
1769
1770 static void ov08x40_update_pad_format(const struct ov08x40_mode *mode,
1771                                       struct v4l2_subdev_format *fmt)
1772 {
1773         fmt->format.width = mode->width;
1774         fmt->format.height = mode->height;
1775         fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1776         fmt->format.field = V4L2_FIELD_NONE;
1777 }
1778
1779 static int ov08x40_do_get_pad_format(struct ov08x40 *ov08x,
1780                                      struct v4l2_subdev_state *sd_state,
1781                                      struct v4l2_subdev_format *fmt)
1782 {
1783         struct v4l2_mbus_framefmt *framefmt;
1784
1785         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1786                 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1787                 fmt->format = *framefmt;
1788         } else {
1789                 ov08x40_update_pad_format(ov08x->cur_mode, fmt);
1790         }
1791
1792         return 0;
1793 }
1794
1795 static int ov08x40_get_pad_format(struct v4l2_subdev *sd,
1796                                   struct v4l2_subdev_state *sd_state,
1797                                   struct v4l2_subdev_format *fmt)
1798 {
1799         struct ov08x40 *ov08x = to_ov08x40(sd);
1800         int ret;
1801
1802         mutex_lock(&ov08x->mutex);
1803         ret = ov08x40_do_get_pad_format(ov08x, sd_state, fmt);
1804         mutex_unlock(&ov08x->mutex);
1805
1806         return ret;
1807 }
1808
1809 static int
1810 ov08x40_set_pad_format(struct v4l2_subdev *sd,
1811                        struct v4l2_subdev_state *sd_state,
1812                        struct v4l2_subdev_format *fmt)
1813 {
1814         struct ov08x40 *ov08x = to_ov08x40(sd);
1815         const struct ov08x40_mode *mode;
1816         struct v4l2_mbus_framefmt *framefmt;
1817         s32 vblank_def;
1818         s32 vblank_min;
1819         s64 h_blank;
1820         s64 pixel_rate;
1821         s64 link_freq;
1822         u64 steps;
1823
1824         mutex_lock(&ov08x->mutex);
1825
1826         /* Only one raw bayer(GRBG) order is supported */
1827         if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1828                 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1829
1830         mode = v4l2_find_nearest_size(supported_modes,
1831                                       ARRAY_SIZE(supported_modes),
1832                                       width, height,
1833                                       fmt->format.width, fmt->format.height);
1834         ov08x40_update_pad_format(mode, fmt);
1835         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1836                 framefmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
1837                 *framefmt = fmt->format;
1838         } else {
1839                 ov08x->cur_mode = mode;
1840                 __v4l2_ctrl_s_ctrl(ov08x->link_freq, mode->link_freq_index);
1841                 link_freq = link_freq_menu_items[mode->link_freq_index];
1842                 pixel_rate = link_freq_to_pixel_rate(link_freq);
1843                 __v4l2_ctrl_s_ctrl_int64(ov08x->pixel_rate, pixel_rate);
1844
1845                 /* Update limits and set FPS to default */
1846                 vblank_def = ov08x->cur_mode->vts_def -
1847                              ov08x->cur_mode->height;
1848                 vblank_min = ov08x->cur_mode->vts_min -
1849                              ov08x->cur_mode->height;
1850
1851                 /*
1852                  * The frame length line should be aligned to a multiple of 4,
1853                  * as provided by the sensor vendor, in normal mode.
1854                  */
1855                 steps = mode->exposure_shift == 1 ? 4 : 1;
1856
1857                 __v4l2_ctrl_modify_range(ov08x->vblank, vblank_min,
1858                                          OV08X40_VTS_MAX
1859                                          - ov08x->cur_mode->height,
1860                                          steps,
1861                                          vblank_def);
1862                 __v4l2_ctrl_s_ctrl(ov08x->vblank, vblank_def);
1863
1864                 h_blank = ov08x->cur_mode->llp - ov08x->cur_mode->width;
1865
1866                 __v4l2_ctrl_modify_range(ov08x->hblank, h_blank,
1867                                          h_blank, 1, h_blank);
1868         }
1869
1870         mutex_unlock(&ov08x->mutex);
1871
1872         return 0;
1873 }
1874
1875 static int ov08x40_start_streaming(struct ov08x40 *ov08x)
1876 {
1877         struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1878         const struct ov08x40_reg_list *reg_list;
1879         int ret, link_freq_index;
1880
1881         /* Get out of from software reset */
1882         ret = ov08x40_write_reg(ov08x, OV08X40_REG_SOFTWARE_RST,
1883                                 OV08X40_REG_VALUE_08BIT, OV08X40_SOFTWARE_RST);
1884         if (ret) {
1885                 dev_err(&client->dev, "%s failed to set powerup registers\n",
1886                         __func__);
1887                 return ret;
1888         }
1889
1890         link_freq_index = ov08x->cur_mode->link_freq_index;
1891         reg_list = &link_freq_configs[link_freq_index].reg_list;
1892
1893         ret = ov08x40_write_reg_list(ov08x, reg_list);
1894         if (ret) {
1895                 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1896                 return ret;
1897         }
1898
1899         /* Apply default values of current mode */
1900         reg_list = &ov08x->cur_mode->reg_list;
1901         ret = ov08x40_write_reg_list(ov08x, reg_list);
1902         if (ret) {
1903                 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1904                 return ret;
1905         }
1906
1907         /* Use i2c burst to write register on full size registers */
1908         if (ov08x->cur_mode->exposure_shift == 1) {
1909                 ret = ov08x40_burst_fill_regs(ov08x, OV08X40_REG_XTALK_FIRST_A,
1910                                               OV08X40_REG_XTALK_LAST_A, 0x75);
1911                 if (ret == 0)
1912                         ret = ov08x40_burst_fill_regs(ov08x,
1913                                                       OV08X40_REG_XTALK_FIRST_B,
1914                                                       OV08X40_REG_XTALK_LAST_B,
1915                                                       0x75);
1916         }
1917
1918         if (ret) {
1919                 dev_err(&client->dev, "%s failed to set regs\n", __func__);
1920                 return ret;
1921         }
1922
1923         /* Apply customized values from user */
1924         ret =  __v4l2_ctrl_handler_setup(ov08x->sd.ctrl_handler);
1925         if (ret)
1926                 return ret;
1927
1928         return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT,
1929                                  OV08X40_REG_VALUE_08BIT,
1930                                  OV08X40_MODE_STREAMING);
1931 }
1932
1933 /* Stop streaming */
1934 static int ov08x40_stop_streaming(struct ov08x40 *ov08x)
1935 {
1936         return ov08x40_write_reg(ov08x, OV08X40_REG_MODE_SELECT,
1937                                  OV08X40_REG_VALUE_08BIT, OV08X40_MODE_STANDBY);
1938 }
1939
1940 static int ov08x40_set_stream(struct v4l2_subdev *sd, int enable)
1941 {
1942         struct ov08x40 *ov08x = to_ov08x40(sd);
1943         struct i2c_client *client = v4l2_get_subdevdata(sd);
1944         int ret = 0;
1945
1946         mutex_lock(&ov08x->mutex);
1947
1948         if (enable) {
1949                 ret = pm_runtime_resume_and_get(&client->dev);
1950                 if (ret < 0)
1951                         goto err_unlock;
1952
1953                 /*
1954                  * Apply default & customized values
1955                  * and then start streaming.
1956                  */
1957                 ret = ov08x40_start_streaming(ov08x);
1958                 if (ret)
1959                         goto err_rpm_put;
1960         } else {
1961                 ov08x40_stop_streaming(ov08x);
1962                 pm_runtime_put(&client->dev);
1963         }
1964
1965         mutex_unlock(&ov08x->mutex);
1966
1967         return ret;
1968
1969 err_rpm_put:
1970         pm_runtime_put(&client->dev);
1971 err_unlock:
1972         mutex_unlock(&ov08x->mutex);
1973
1974         return ret;
1975 }
1976
1977 /* Verify chip ID */
1978 static int ov08x40_identify_module(struct ov08x40 *ov08x)
1979 {
1980         struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
1981         int ret;
1982         u32 val;
1983
1984         if (ov08x->identified)
1985                 return 0;
1986
1987         ret = ov08x40_read_reg(ov08x, OV08X40_REG_CHIP_ID,
1988                                OV08X40_REG_VALUE_24BIT, &val);
1989         if (ret)
1990                 return ret;
1991
1992         if (val != OV08X40_CHIP_ID) {
1993                 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1994                         OV08X40_CHIP_ID, val);
1995                 return -ENXIO;
1996         }
1997
1998         ov08x->identified = true;
1999
2000         return 0;
2001 }
2002
2003 static const struct v4l2_subdev_video_ops ov08x40_video_ops = {
2004         .s_stream = ov08x40_set_stream,
2005 };
2006
2007 static const struct v4l2_subdev_pad_ops ov08x40_pad_ops = {
2008         .enum_mbus_code = ov08x40_enum_mbus_code,
2009         .get_fmt = ov08x40_get_pad_format,
2010         .set_fmt = ov08x40_set_pad_format,
2011         .enum_frame_size = ov08x40_enum_frame_size,
2012 };
2013
2014 static const struct v4l2_subdev_ops ov08x40_subdev_ops = {
2015         .video = &ov08x40_video_ops,
2016         .pad = &ov08x40_pad_ops,
2017 };
2018
2019 static const struct media_entity_operations ov08x40_subdev_entity_ops = {
2020         .link_validate = v4l2_subdev_link_validate,
2021 };
2022
2023 static const struct v4l2_subdev_internal_ops ov08x40_internal_ops = {
2024         .open = ov08x40_open,
2025 };
2026
2027 static int ov08x40_init_controls(struct ov08x40 *ov08x)
2028 {
2029         struct i2c_client *client = v4l2_get_subdevdata(&ov08x->sd);
2030         struct v4l2_fwnode_device_properties props;
2031         struct v4l2_ctrl_handler *ctrl_hdlr;
2032         s64 exposure_max;
2033         s64 vblank_def;
2034         s64 vblank_min;
2035         s64 hblank;
2036         s64 pixel_rate_min;
2037         s64 pixel_rate_max;
2038         const struct ov08x40_mode *mode;
2039         u32 max;
2040         int ret;
2041
2042         ctrl_hdlr = &ov08x->ctrl_handler;
2043         ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
2044         if (ret)
2045                 return ret;
2046
2047         mutex_init(&ov08x->mutex);
2048         ctrl_hdlr->lock = &ov08x->mutex;
2049         max = ARRAY_SIZE(link_freq_menu_items) - 1;
2050         ov08x->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
2051                                                   &ov08x40_ctrl_ops,
2052                                                   V4L2_CID_LINK_FREQ,
2053                                                   max,
2054                                                   0,
2055                                                   link_freq_menu_items);
2056         if (ov08x->link_freq)
2057                 ov08x->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2058
2059         pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
2060         pixel_rate_min = 0;
2061         /* By default, PIXEL_RATE is read only */
2062         ov08x->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
2063                                               V4L2_CID_PIXEL_RATE,
2064                                               pixel_rate_min, pixel_rate_max,
2065                                               1, pixel_rate_max);
2066
2067         mode = ov08x->cur_mode;
2068         vblank_def = mode->vts_def - mode->height;
2069         vblank_min = mode->vts_min - mode->height;
2070         ov08x->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
2071                                           V4L2_CID_VBLANK,
2072                                           vblank_min,
2073                                           OV08X40_VTS_MAX - mode->height, 1,
2074                                           vblank_def);
2075
2076         hblank = ov08x->cur_mode->llp - ov08x->cur_mode->width;
2077
2078         ov08x->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
2079                                           V4L2_CID_HBLANK,
2080                                           hblank, hblank, 1, hblank);
2081         if (ov08x->hblank)
2082                 ov08x->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2083
2084         exposure_max = mode->vts_def - OV08X40_EXPOSURE_MAX_MARGIN;
2085         ov08x->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
2086                                             V4L2_CID_EXPOSURE,
2087                                             OV08X40_EXPOSURE_MIN,
2088                                             exposure_max, OV08X40_EXPOSURE_STEP,
2089                                             exposure_max);
2090
2091         v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
2092                           OV08X40_ANA_GAIN_MIN, OV08X40_ANA_GAIN_MAX,
2093                           OV08X40_ANA_GAIN_STEP, OV08X40_ANA_GAIN_DEFAULT);
2094
2095         /* Digital gain */
2096         v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
2097                           OV08X40_DGTL_GAIN_MIN, OV08X40_DGTL_GAIN_MAX,
2098                           OV08X40_DGTL_GAIN_STEP, OV08X40_DGTL_GAIN_DEFAULT);
2099
2100         v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov08x40_ctrl_ops,
2101                                      V4L2_CID_TEST_PATTERN,
2102                                      ARRAY_SIZE(ov08x40_test_pattern_menu) - 1,
2103                                      0, 0, ov08x40_test_pattern_menu);
2104
2105         v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
2106                           V4L2_CID_HFLIP, 0, 1, 1, 0);
2107         v4l2_ctrl_new_std(ctrl_hdlr, &ov08x40_ctrl_ops,
2108                           V4L2_CID_VFLIP, 0, 1, 1, 0);
2109
2110         if (ctrl_hdlr->error) {
2111                 ret = ctrl_hdlr->error;
2112                 dev_err(&client->dev, "%s control init failed (%d)\n",
2113                         __func__, ret);
2114                 goto error;
2115         }
2116
2117         ret = v4l2_fwnode_device_parse(&client->dev, &props);
2118         if (ret)
2119                 goto error;
2120
2121         ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov08x40_ctrl_ops,
2122                                               &props);
2123         if (ret)
2124                 goto error;
2125
2126         ov08x->sd.ctrl_handler = ctrl_hdlr;
2127
2128         return 0;
2129
2130 error:
2131         v4l2_ctrl_handler_free(ctrl_hdlr);
2132         mutex_destroy(&ov08x->mutex);
2133
2134         return ret;
2135 }
2136
2137 static void ov08x40_free_controls(struct ov08x40 *ov08x)
2138 {
2139         v4l2_ctrl_handler_free(ov08x->sd.ctrl_handler);
2140         mutex_destroy(&ov08x->mutex);
2141 }
2142
2143 static int ov08x40_check_hwcfg(struct ov08x40 *ov08x, struct device *dev)
2144 {
2145         struct v4l2_fwnode_endpoint bus_cfg = {
2146                 .bus_type = V4L2_MBUS_CSI2_DPHY
2147         };
2148         struct fwnode_handle *ep;
2149         struct fwnode_handle *fwnode = dev_fwnode(dev);
2150         unsigned int i, j;
2151         int ret;
2152         u32 xvclk_rate;
2153
2154         if (!fwnode)
2155                 return -ENXIO;
2156
2157         if (!is_acpi_node(fwnode)) {
2158                 ov08x->xvclk = devm_clk_get(dev, NULL);
2159                 if (IS_ERR(ov08x->xvclk)) {
2160                         dev_err(dev, "could not get xvclk clock (%pe)\n",
2161                                 ov08x->xvclk);
2162                         return PTR_ERR(ov08x->xvclk);
2163                 }
2164
2165                 xvclk_rate = clk_get_rate(ov08x->xvclk);
2166
2167                 ov08x->reset_gpio = devm_gpiod_get_optional(dev, "reset",
2168                                                             GPIOD_OUT_LOW);
2169                 if (IS_ERR(ov08x->reset_gpio))
2170                         return PTR_ERR(ov08x->reset_gpio);
2171
2172                 for (i = 0; i < ARRAY_SIZE(ov08x40_supply_names); i++)
2173                         ov08x->supplies[i].supply = ov08x40_supply_names[i];
2174
2175                 ret = devm_regulator_bulk_get(dev,
2176                                               ARRAY_SIZE(ov08x40_supply_names),
2177                                               ov08x->supplies);
2178                 if (ret)
2179                         return ret;
2180         } else {
2181                 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
2182                                                &xvclk_rate);
2183                 if (ret) {
2184                         dev_err(dev, "can't get clock frequency");
2185                         return ret;
2186                 }
2187         }
2188
2189         if (xvclk_rate != OV08X40_XVCLK) {
2190                 dev_err(dev, "external clock %d is not supported",
2191                         xvclk_rate);
2192                 return -EINVAL;
2193         }
2194
2195         ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
2196         if (!ep)
2197                 return -ENXIO;
2198
2199         ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
2200         fwnode_handle_put(ep);
2201         if (ret)
2202                 return ret;
2203
2204         if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV08X40_DATA_LANES) {
2205                 dev_err(dev, "number of CSI2 data lanes %d is not supported",
2206                         bus_cfg.bus.mipi_csi2.num_data_lanes);
2207                 ret = -EINVAL;
2208                 goto out_err;
2209         }
2210
2211         if (!bus_cfg.nr_of_link_frequencies) {
2212                 dev_err(dev, "no link frequencies defined");
2213                 ret = -EINVAL;
2214                 goto out_err;
2215         }
2216
2217         for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
2218                 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
2219                         if (link_freq_menu_items[i] ==
2220                                 bus_cfg.link_frequencies[j])
2221                                 break;
2222                 }
2223
2224                 if (j == bus_cfg.nr_of_link_frequencies) {
2225                         dev_err(dev, "no link frequency %lld supported",
2226                                 link_freq_menu_items[i]);
2227                         ret = -EINVAL;
2228                         goto out_err;
2229                 }
2230         }
2231
2232 out_err:
2233         v4l2_fwnode_endpoint_free(&bus_cfg);
2234
2235         return ret;
2236 }
2237
2238 static int ov08x40_probe(struct i2c_client *client)
2239 {       struct ov08x40 *ov08x;
2240         int ret;
2241         bool full_power;
2242
2243         ov08x = devm_kzalloc(&client->dev, sizeof(*ov08x), GFP_KERNEL);
2244         if (!ov08x)
2245                 return -ENOMEM;
2246
2247         /* Check HW config */
2248         ret = ov08x40_check_hwcfg(ov08x, &client->dev);
2249         if (ret) {
2250                 dev_err(&client->dev, "failed to check hwcfg: %d", ret);
2251                 return ret;
2252         }
2253
2254         /* Initialize subdev */
2255         v4l2_i2c_subdev_init(&ov08x->sd, client, &ov08x40_subdev_ops);
2256
2257         full_power = acpi_dev_state_d0(&client->dev);
2258         if (full_power) {
2259                 ret = ov08x40_power_on(&client->dev);
2260                 if (ret) {
2261                         dev_err(&client->dev, "failed to power on\n");
2262                         return ret;
2263                 }
2264
2265                 /* Check module identity */
2266                 ret = ov08x40_identify_module(ov08x);
2267                 if (ret) {
2268                         dev_err(&client->dev, "failed to find sensor: %d\n", ret);
2269                         goto probe_power_off;
2270                 }
2271         }
2272
2273         /* Set default mode to max resolution */
2274         ov08x->cur_mode = &supported_modes[0];
2275
2276         ret = ov08x40_init_controls(ov08x);
2277         if (ret)
2278                 goto probe_power_off;
2279
2280         /* Initialize subdev */
2281         ov08x->sd.internal_ops = &ov08x40_internal_ops;
2282         ov08x->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2283         ov08x->sd.entity.ops = &ov08x40_subdev_entity_ops;
2284         ov08x->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
2285
2286         /* Initialize source pad */
2287         ov08x->pad.flags = MEDIA_PAD_FL_SOURCE;
2288         ret = media_entity_pads_init(&ov08x->sd.entity, 1, &ov08x->pad);
2289         if (ret) {
2290                 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
2291                 goto error_handler_free;
2292         }
2293
2294         ret = v4l2_async_register_subdev_sensor(&ov08x->sd);
2295         if (ret < 0)
2296                 goto error_media_entity;
2297
2298         if (full_power)
2299                 pm_runtime_set_active(&client->dev);
2300         pm_runtime_enable(&client->dev);
2301         pm_runtime_idle(&client->dev);
2302
2303         return 0;
2304
2305 error_media_entity:
2306         media_entity_cleanup(&ov08x->sd.entity);
2307
2308 error_handler_free:
2309         ov08x40_free_controls(ov08x);
2310
2311 probe_power_off:
2312         ov08x40_power_off(&client->dev);
2313
2314         return ret;
2315 }
2316
2317 static void ov08x40_remove(struct i2c_client *client)
2318 {
2319         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2320         struct ov08x40 *ov08x = to_ov08x40(sd);
2321
2322         v4l2_async_unregister_subdev(sd);
2323         media_entity_cleanup(&sd->entity);
2324         ov08x40_free_controls(ov08x);
2325
2326         pm_runtime_disable(&client->dev);
2327         pm_runtime_set_suspended(&client->dev);
2328
2329         ov08x40_power_off(&client->dev);
2330 }
2331
2332 #ifdef CONFIG_ACPI
2333 static const struct acpi_device_id ov08x40_acpi_ids[] = {
2334         {"OVTI08F4"},
2335         { /* sentinel */ }
2336 };
2337
2338 MODULE_DEVICE_TABLE(acpi, ov08x40_acpi_ids);
2339 #endif
2340
2341 static const struct of_device_id ov08x40_of_match[] = {
2342         { .compatible = "ovti,ov08x40" },
2343         { /* sentinel */ }
2344 };
2345 MODULE_DEVICE_TABLE(of, ov08x40_of_match);
2346
2347 static struct i2c_driver ov08x40_i2c_driver = {
2348         .driver = {
2349                 .name = "ov08x40",
2350                 .acpi_match_table = ACPI_PTR(ov08x40_acpi_ids),
2351                 .of_match_table = ov08x40_of_match,
2352         },
2353         .probe = ov08x40_probe,
2354         .remove = ov08x40_remove,
2355         .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
2356 };
2357
2358 module_i2c_driver(ov08x40_i2c_driver);
2359
2360 MODULE_AUTHOR("Jason Chen <[email protected]>");
2361 MODULE_AUTHOR("Qingwu Zhang <[email protected]>");
2362 MODULE_AUTHOR("Shawn Tu");
2363 MODULE_DESCRIPTION("OmniVision OV08X40 sensor driver");
2364 MODULE_LICENSE("GPL");