drivers/media/i2c/imx290.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Sony IMX290 CMOS Image Sensor Driver
   4  *
   5  * Copyright (C) 2019 FRAMOS GmbH.
   6  *
   7  * Copyright (C) 2019 Linaro Ltd.
   8  * Author: Manivannan Sadhasivam <[email protected]>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/i2c.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/regmap.h>
  19 #include <linux/regulator/consumer.h>
  20
  21 #include <linux/unaligned.h>
  22
  23 #include <media/media-entity.h>
  24 #include <media/v4l2-cci.h>
  25 #include <media/v4l2-ctrls.h>
  26 #include <media/v4l2-device.h>
  27 #include <media/v4l2-fwnode.h>
  28 #include <media/v4l2-subdev.h>
  29
  30 #define IMX290_STANDBY                                  CCI_REG8(0x3000)
  31 #define IMX290_REGHOLD                                  CCI_REG8(0x3001)
  32 #define IMX290_XMSTA                                    CCI_REG8(0x3002)
  33 #define IMX290_ADBIT                                    CCI_REG8(0x3005)
  34 #define IMX290_ADBIT_10BIT                              (0 << 0)
  35 #define IMX290_ADBIT_12BIT                              (1 << 0)
  36 #define IMX290_CTRL_07                                  CCI_REG8(0x3007)
  37 #define IMX290_VREVERSE                                 BIT(0)
  38 #define IMX290_HREVERSE                                 BIT(1)
  39 #define IMX290_WINMODE_1080P                            (0 << 4)
  40 #define IMX290_WINMODE_720P                             (1 << 4)
  41 #define IMX290_WINMODE_CROP                             (4 << 4)
  42 #define IMX290_FR_FDG_SEL                               CCI_REG8(0x3009)
  43 #define IMX290_BLKLEVEL                                 CCI_REG16_LE(0x300a)
  44 #define IMX290_GAIN                                     CCI_REG8(0x3014)
  45 #define IMX290_VMAX                                     CCI_REG24_LE(0x3018)
  46 #define IMX290_VMAX_MAX                                 0x3ffff
  47 #define IMX290_HMAX                                     CCI_REG16_LE(0x301c)
  48 #define IMX290_HMAX_MAX                                 0xffff
  49 #define IMX290_SHS1                                     CCI_REG24_LE(0x3020)
  50 #define IMX290_WINWV_OB                                 CCI_REG8(0x303a)
  51 #define IMX290_WINPV                                    CCI_REG16_LE(0x303c)
  52 #define IMX290_WINWV                                    CCI_REG16_LE(0x303e)
  53 #define IMX290_WINPH                                    CCI_REG16_LE(0x3040)
  54 #define IMX290_WINWH                                    CCI_REG16_LE(0x3042)
  55 #define IMX290_OUT_CTRL                                 CCI_REG8(0x3046)
  56 #define IMX290_ODBIT_10BIT                              (0 << 0)
  57 #define IMX290_ODBIT_12BIT                              (1 << 0)
  58 #define IMX290_OPORTSEL_PARALLEL                        (0x0 << 4)
  59 #define IMX290_OPORTSEL_LVDS_2CH                        (0xd << 4)
  60 #define IMX290_OPORTSEL_LVDS_4CH                        (0xe << 4)
  61 #define IMX290_OPORTSEL_LVDS_8CH                        (0xf << 4)
  62 #define IMX290_XSOUTSEL                                 CCI_REG8(0x304b)
  63 #define IMX290_XSOUTSEL_XVSOUTSEL_HIGH                  (0 << 0)
  64 #define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC                 (2 << 0)
  65 #define IMX290_XSOUTSEL_XHSOUTSEL_HIGH                  (0 << 2)
  66 #define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC                 (2 << 2)
  67 #define IMX290_INCKSEL1                                 CCI_REG8(0x305c)
  68 #define IMX290_INCKSEL2                                 CCI_REG8(0x305d)
  69 #define IMX290_INCKSEL3                                 CCI_REG8(0x305e)
  70 #define IMX290_INCKSEL4                                 CCI_REG8(0x305f)
  71 #define IMX290_PGCTRL                                   CCI_REG8(0x308c)
  72 #define IMX290_ADBIT1                                   CCI_REG8(0x3129)
  73 #define IMX290_ADBIT1_10BIT                             0x1d
  74 #define IMX290_ADBIT1_12BIT                             0x00
  75 #define IMX290_INCKSEL5                                 CCI_REG8(0x315e)
  76 #define IMX290_INCKSEL6                                 CCI_REG8(0x3164)
  77 #define IMX290_ADBIT2                                   CCI_REG8(0x317c)
  78 #define IMX290_ADBIT2_10BIT                             0x12
  79 #define IMX290_ADBIT2_12BIT                             0x00
  80 #define IMX290_ADBIT3                                   CCI_REG8(0x31ec)
  81 #define IMX290_ADBIT3_10BIT                             0x37
  82 #define IMX290_ADBIT3_12BIT                             0x0e
  83 #define IMX290_REPETITION                               CCI_REG8(0x3405)
  84 #define IMX290_PHY_LANE_NUM                             CCI_REG8(0x3407)
  85 #define IMX290_OPB_SIZE_V                               CCI_REG8(0x3414)
  86 #define IMX290_Y_OUT_SIZE                               CCI_REG16_LE(0x3418)
  87 #define IMX290_CSI_DT_FMT                               CCI_REG16_LE(0x3441)
  88 #define IMX290_CSI_DT_FMT_RAW10                         0x0a0a
  89 #define IMX290_CSI_DT_FMT_RAW12                         0x0c0c
  90 #define IMX290_CSI_LANE_MODE                            CCI_REG8(0x3443)
  91 #define IMX290_EXTCK_FREQ                               CCI_REG16_LE(0x3444)
  92 #define IMX290_TCLKPOST                                 CCI_REG16_LE(0x3446)
  93 #define IMX290_THSZERO                                  CCI_REG16_LE(0x3448)
  94 #define IMX290_THSPREPARE                               CCI_REG16_LE(0x344a)
  95 #define IMX290_TCLKTRAIL                                CCI_REG16_LE(0x344c)
  96 #define IMX290_THSTRAIL                                 CCI_REG16_LE(0x344e)
  97 #define IMX290_TCLKZERO                                 CCI_REG16_LE(0x3450)
  98 #define IMX290_TCLKPREPARE                              CCI_REG16_LE(0x3452)
  99 #define IMX290_TLPX                                     CCI_REG16_LE(0x3454)
 100 #define IMX290_X_OUT_SIZE                               CCI_REG16_LE(0x3472)
 101 #define IMX290_INCKSEL7                                 CCI_REG8(0x3480)
 102
 103 #define IMX290_PGCTRL_REGEN                             BIT(0)
 104 #define IMX290_PGCTRL_THRU                              BIT(1)
 105 #define IMX290_PGCTRL_MODE(n)                           ((n) << 4)
 106
 107 /* Number of lines by which exposure must be less than VMAX */
 108 #define IMX290_EXPOSURE_OFFSET                          2
 109
 110 #define IMX290_PIXEL_RATE                               148500000
 111
 112 /*
 113  * The IMX290 pixel array is organized as follows:
 114  *
 115  *     +------------------------------------+
 116  *     |           Optical Black            |     }  Vertical effective optical black (10)
 117  * +---+------------------------------------+---+
 118  * |   |                                    |   | }  Effective top margin (8)
 119  * |   |   +----------------------------+   |   | \
 120  * |   |   |                            |   |   |  |
 121  * |   |   |                            |   |   |  |
 122  * |   |   |                            |   |   |  |
 123  * |   |   |    Recording Pixel Area    |   |   |  | Recommended height (1080)
 124  * |   |   |                            |   |   |  |
 125  * |   |   |                            |   |   |  |
 126  * |   |   |                            |   |   |  |
 127  * |   |   +----------------------------+   |   | /
 128  * |   |                                    |   | }  Effective bottom margin (9)
 129  * +---+------------------------------------+---+
 130  *  <-> <-> <--------------------------> <-> <->
 131  *                                            \----  Ignored right margin (4)
 132  *                                        \--------  Effective right margin (9)
 133  *                       \-------------------------  Recommended width (1920)
 134  *       \-----------------------------------------  Effective left margin (8)
 135  *   \---------------------------------------------  Ignored left margin (4)
 136  *
 137  * The optical black lines are output over CSI-2 with a separate data type.
 138  *
 139  * The pixel array is meant to have 1920x1080 usable pixels after image
 140  * processing in an ISP. It has 8 (9) extra active pixels usable for color
 141  * processing in the ISP on the top and left (bottom and right) sides of the
 142  * image. In addition, 4 additional pixels are present on the left and right
 143  * sides of the image, documented as "ignored area".
 144  *
 145  * As far as is understood, all pixels of the pixel array (ignored area, color
 146  * processing margins and recording area) can be output by the sensor.
 147  */
 148
 149 #define IMX290_PIXEL_ARRAY_WIDTH                        1945
 150 #define IMX290_PIXEL_ARRAY_HEIGHT                       1097
 151 #define IMX290_PIXEL_ARRAY_MARGIN_LEFT                  12
 152 #define IMX290_PIXEL_ARRAY_MARGIN_RIGHT                 13
 153 #define IMX290_PIXEL_ARRAY_MARGIN_TOP                   8
 154 #define IMX290_PIXEL_ARRAY_MARGIN_BOTTOM                9
 155 #define IMX290_PIXEL_ARRAY_RECORDING_WIDTH              1920
 156 #define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT             1080
 157
 158 /* Equivalent value for 16bpp */
 159 #define IMX290_BLACK_LEVEL_DEFAULT                      3840
 160
 161 #define IMX290_NUM_SUPPLIES                             3
 162
 163 enum imx290_colour_variant {
 164         IMX290_VARIANT_COLOUR,
 165         IMX290_VARIANT_MONO,
 166         IMX290_VARIANT_MAX
 167 };
 168
 169 enum imx290_model {
 170         IMX290_MODEL_IMX290LQR,
 171         IMX290_MODEL_IMX290LLR,
 172         IMX290_MODEL_IMX327LQR,
 173         IMX290_MODEL_IMX462LQR,
 174         IMX290_MODEL_IMX462LLR,
 175 };
 176
 177 struct imx290_model_info {
 178         enum imx290_colour_variant colour_variant;
 179         const struct cci_reg_sequence *init_regs;
 180         size_t init_regs_num;
 181         unsigned int max_analog_gain;
 182         const char *name;
 183 };
 184
 185 enum imx290_clk_freq {
 186         IMX290_CLK_37_125,
 187         IMX290_CLK_74_25,
 188         IMX290_NUM_CLK
 189 };
 190
 191 /*
 192  * Clock configuration for registers INCKSEL1 to INCKSEL6.
 193  */
 194 struct imx290_clk_cfg {
 195         u8 incksel1;
 196         u8 incksel2;
 197         u8 incksel3;
 198         u8 incksel4;
 199         u8 incksel5;
 200         u8 incksel6;
 201 };
 202
 203 struct imx290_mode {
 204         u32 width;
 205         u32 height;
 206         u32 hmax_min;
 207         u32 vmax_min;
 208         u8 link_freq_index;
 209         u8 ctrl_07;
 210
 211         const struct cci_reg_sequence *data;
 212         u32 data_size;
 213
 214         const struct imx290_clk_cfg *clk_cfg;
 215 };
 216
 217 struct imx290_csi_cfg {
 218         u16 repetition;
 219         u16 tclkpost;
 220         u16 thszero;
 221         u16 thsprepare;
 222         u16 tclktrail;
 223         u16 thstrail;
 224         u16 tclkzero;
 225         u16 tclkprepare;
 226         u16 tlpx;
 227 };
 228
 229 struct imx290 {
 230         struct device *dev;
 231         struct clk *xclk;
 232         struct regmap *regmap;
 233         enum imx290_clk_freq xclk_idx;
 234         u8 nlanes;
 235         const struct imx290_model_info *model;
 236
 237         struct v4l2_subdev sd;
 238         struct media_pad pad;
 239
 240         const struct imx290_mode *current_mode;
 241
 242         struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES];
 243         struct gpio_desc *rst_gpio;
 244
 245         struct v4l2_ctrl_handler ctrls;
 246         struct v4l2_ctrl *link_freq;
 247         struct v4l2_ctrl *hblank;
 248         struct v4l2_ctrl *vblank;
 249         struct v4l2_ctrl *exposure;
 250         struct {
 251                 struct v4l2_ctrl *hflip;
 252                 struct v4l2_ctrl *vflip;
 253         };
 254 };
 255
 256 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd)
 257 {
 258         return container_of(_sd, struct imx290, sd);
 259 }
 260
 261 /* -----------------------------------------------------------------------------
 262  * Modes and formats
 263  */
 264
 265 static const struct cci_reg_sequence imx290_global_init_settings[] = {
 266         { IMX290_WINWV_OB, 12 },
 267         { IMX290_WINPH, 0 },
 268         { IMX290_WINPV, 0 },
 269         { IMX290_WINWH, 1948 },
 270         { IMX290_WINWV, 1097 },
 271         { IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC |
 272                            IMX290_XSOUTSEL_XHSOUTSEL_HSYNC },
 273         { CCI_REG8(0x3012), 0x64 },
 274         { CCI_REG8(0x3013), 0x00 },
 275 };
 276
 277 static const struct cci_reg_sequence imx290_global_init_settings_290[] = {
 278         { CCI_REG8(0x300f), 0x00 },
 279         { CCI_REG8(0x3010), 0x21 },
 280         { CCI_REG8(0x3011), 0x00 },
 281         { CCI_REG8(0x3016), 0x09 },
 282         { CCI_REG8(0x3070), 0x02 },
 283         { CCI_REG8(0x3071), 0x11 },
 284         { CCI_REG8(0x309b), 0x10 },
 285         { CCI_REG8(0x309c), 0x22 },
 286         { CCI_REG8(0x30a2), 0x02 },
 287         { CCI_REG8(0x30a6), 0x20 },
 288         { CCI_REG8(0x30a8), 0x20 },
 289         { CCI_REG8(0x30aa), 0x20 },
 290         { CCI_REG8(0x30ac), 0x20 },
 291         { CCI_REG8(0x30b0), 0x43 },
 292         { CCI_REG8(0x3119), 0x9e },
 293         { CCI_REG8(0x311c), 0x1e },
 294         { CCI_REG8(0x311e), 0x08 },
 295         { CCI_REG8(0x3128), 0x05 },
 296         { CCI_REG8(0x313d), 0x83 },
 297         { CCI_REG8(0x3150), 0x03 },
 298         { CCI_REG8(0x317e), 0x00 },
 299         { CCI_REG8(0x32b8), 0x50 },
 300         { CCI_REG8(0x32b9), 0x10 },
 301         { CCI_REG8(0x32ba), 0x00 },
 302         { CCI_REG8(0x32bb), 0x04 },
 303         { CCI_REG8(0x32c8), 0x50 },
 304         { CCI_REG8(0x32c9), 0x10 },
 305         { CCI_REG8(0x32ca), 0x00 },
 306         { CCI_REG8(0x32cb), 0x04 },
 307         { CCI_REG8(0x332c), 0xd3 },
 308         { CCI_REG8(0x332d), 0x10 },
 309         { CCI_REG8(0x332e), 0x0d },
 310         { CCI_REG8(0x3358), 0x06 },
 311         { CCI_REG8(0x3359), 0xe1 },
 312         { CCI_REG8(0x335a), 0x11 },
 313         { CCI_REG8(0x3360), 0x1e },
 314         { CCI_REG8(0x3361), 0x61 },
 315         { CCI_REG8(0x3362), 0x10 },
 316         { CCI_REG8(0x33b0), 0x50 },
 317         { CCI_REG8(0x33b2), 0x1a },
 318         { CCI_REG8(0x33b3), 0x04 },
 319 };
 320
 321 static const struct cci_reg_sequence imx290_global_init_settings_462[] = {
 322         { CCI_REG8(0x300f), 0x00 },
 323         { CCI_REG8(0x3010), 0x21 },
 324         { CCI_REG8(0x3011), 0x02 },
 325         { CCI_REG8(0x3016), 0x09 },
 326         { CCI_REG8(0x3070), 0x02 },
 327         { CCI_REG8(0x3071), 0x11 },
 328         { CCI_REG8(0x309b), 0x10 },
 329         { CCI_REG8(0x309c), 0x22 },
 330         { CCI_REG8(0x30a2), 0x02 },
 331         { CCI_REG8(0x30a6), 0x20 },
 332         { CCI_REG8(0x30a8), 0x20 },
 333         { CCI_REG8(0x30aa), 0x20 },
 334         { CCI_REG8(0x30ac), 0x20 },
 335         { CCI_REG8(0x30b0), 0x43 },
 336         { CCI_REG8(0x3119), 0x9e },
 337         { CCI_REG8(0x311c), 0x1e },
 338         { CCI_REG8(0x311e), 0x08 },
 339         { CCI_REG8(0x3128), 0x05 },
 340         { CCI_REG8(0x313d), 0x83 },
 341         { CCI_REG8(0x3150), 0x03 },
 342         { CCI_REG8(0x317e), 0x00 },
 343         { CCI_REG8(0x32b8), 0x50 },
 344         { CCI_REG8(0x32b9), 0x10 },
 345         { CCI_REG8(0x32ba), 0x00 },
 346         { CCI_REG8(0x32bb), 0x04 },
 347         { CCI_REG8(0x32c8), 0x50 },
 348         { CCI_REG8(0x32c9), 0x10 },
 349         { CCI_REG8(0x32ca), 0x00 },
 350         { CCI_REG8(0x32cb), 0x04 },
 351         { CCI_REG8(0x332c), 0xd3 },
 352         { CCI_REG8(0x332d), 0x10 },
 353         { CCI_REG8(0x332e), 0x0d },
 354         { CCI_REG8(0x3358), 0x06 },
 355         { CCI_REG8(0x3359), 0xe1 },
 356         { CCI_REG8(0x335a), 0x11 },
 357         { CCI_REG8(0x3360), 0x1e },
 358         { CCI_REG8(0x3361), 0x61 },
 359         { CCI_REG8(0x3362), 0x10 },
 360         { CCI_REG8(0x33b0), 0x50 },
 361         { CCI_REG8(0x33b2), 0x1a },
 362         { CCI_REG8(0x33b3), 0x04 },
 363 };
 364
 365 #define IMX290_NUM_CLK_REGS     2
 366 static const struct cci_reg_sequence xclk_regs[][IMX290_NUM_CLK_REGS] = {
 367         [IMX290_CLK_37_125] = {
 368                 { IMX290_EXTCK_FREQ, (37125 * 256) / 1000 },
 369                 { IMX290_INCKSEL7, 0x49 },
 370         },
 371         [IMX290_CLK_74_25] = {
 372                 { IMX290_EXTCK_FREQ, (74250 * 256) / 1000 },
 373                 { IMX290_INCKSEL7, 0x92 },
 374         },
 375 };
 376
 377 static const struct cci_reg_sequence imx290_global_init_settings_327[] = {
 378         { CCI_REG8(0x3011), 0x02 },
 379         { CCI_REG8(0x309e), 0x4A },
 380         { CCI_REG8(0x309f), 0x4A },
 381         { CCI_REG8(0x313b), 0x61 },
 382 };
 383
 384 static const struct cci_reg_sequence imx290_1080p_settings[] = {
 385         /* mode settings */
 386         { IMX290_WINWV_OB, 12 },
 387         { IMX290_OPB_SIZE_V, 10 },
 388         { IMX290_X_OUT_SIZE, 1920 },
 389         { IMX290_Y_OUT_SIZE, 1080 },
 390 };
 391
 392 static const struct cci_reg_sequence imx290_720p_settings[] = {
 393         /* mode settings */
 394         { IMX290_WINWV_OB, 6 },
 395         { IMX290_OPB_SIZE_V, 4 },
 396         { IMX290_X_OUT_SIZE, 1280 },
 397         { IMX290_Y_OUT_SIZE, 720 },
 398 };
 399
 400 static const struct cci_reg_sequence imx290_10bit_settings[] = {
 401         { IMX290_ADBIT, IMX290_ADBIT_10BIT },
 402         { IMX290_OUT_CTRL, IMX290_ODBIT_10BIT },
 403         { IMX290_ADBIT1, IMX290_ADBIT1_10BIT },
 404         { IMX290_ADBIT2, IMX290_ADBIT2_10BIT },
 405         { IMX290_ADBIT3, IMX290_ADBIT3_10BIT },
 406         { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 },
 407 };
 408
 409 static const struct cci_reg_sequence imx290_12bit_settings[] = {
 410         { IMX290_ADBIT, IMX290_ADBIT_12BIT },
 411         { IMX290_OUT_CTRL, IMX290_ODBIT_12BIT },
 412         { IMX290_ADBIT1, IMX290_ADBIT1_12BIT },
 413         { IMX290_ADBIT2, IMX290_ADBIT2_12BIT },
 414         { IMX290_ADBIT3, IMX290_ADBIT3_12BIT },
 415         { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 },
 416 };
 417
 418 static const struct imx290_csi_cfg imx290_csi_222_75mhz = {
 419         /* 222.75MHz or 445.5Mbit/s per lane */
 420         .repetition = 0x10,
 421         .tclkpost = 87,
 422         .thszero = 55,
 423         .thsprepare = 31,
 424         .tclktrail = 31,
 425         .thstrail = 31,
 426         .tclkzero = 119,
 427         .tclkprepare = 31,
 428         .tlpx = 23,
 429 };
 430
 431 static const struct imx290_csi_cfg imx290_csi_445_5mhz = {
 432         /* 445.5MHz or 891Mbit/s per lane */
 433         .repetition = 0x00,
 434         .tclkpost = 119,
 435         .thszero = 103,
 436         .thsprepare = 71,
 437         .tclktrail = 55,
 438         .thstrail = 63,
 439         .tclkzero = 255,
 440         .tclkprepare = 63,
 441         .tlpx = 55,
 442 };
 443
 444 static const struct imx290_csi_cfg imx290_csi_148_5mhz = {
 445         /* 148.5MHz or 297Mbit/s per lane */
 446         .repetition = 0x10,
 447         .tclkpost = 79,
 448         .thszero = 47,
 449         .thsprepare = 23,
 450         .tclktrail = 23,
 451         .thstrail = 23,
 452         .tclkzero = 87,
 453         .tclkprepare = 23,
 454         .tlpx = 23,
 455 };
 456
 457 static const struct imx290_csi_cfg imx290_csi_297mhz = {
 458         /* 297MHz or 594Mbit/s per lane */
 459         .repetition = 0x00,
 460         .tclkpost = 103,
 461         .thszero = 87,
 462         .thsprepare = 47,
 463         .tclktrail = 39,
 464         .thstrail = 47,
 465         .tclkzero = 191,
 466         .tclkprepare = 47,
 467         .tlpx = 39,
 468 };
 469
 470 /* supported link frequencies */
 471 #define FREQ_INDEX_1080P        0
 472 #define FREQ_INDEX_720P         1
 473 static const s64 imx290_link_freq_2lanes[] = {
 474         [FREQ_INDEX_1080P] = 445500000,
 475         [FREQ_INDEX_720P] = 297000000,
 476 };
 477
 478 static const s64 imx290_link_freq_4lanes[] = {
 479         [FREQ_INDEX_1080P] = 222750000,
 480         [FREQ_INDEX_720P] = 148500000,
 481 };
 482
 483 /*
 484  * In this function and in the similar ones below We rely on imx290_probe()
 485  * to ensure that nlanes is either 2 or 4.
 486  */
 487 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290)
 488 {
 489         if (imx290->nlanes == 2)
 490                 return imx290_link_freq_2lanes;
 491         else
 492                 return imx290_link_freq_4lanes;
 493 }
 494
 495 static inline int imx290_link_freqs_num(const struct imx290 *imx290)
 496 {
 497         if (imx290->nlanes == 2)
 498                 return ARRAY_SIZE(imx290_link_freq_2lanes);
 499         else
 500                 return ARRAY_SIZE(imx290_link_freq_4lanes);
 501 }
 502
 503 static const struct imx290_clk_cfg imx290_1080p_clock_config[] = {
 504         [IMX290_CLK_37_125] = {
 505                 /* 37.125MHz clock config */
 506                 .incksel1 = 0x18,
 507                 .incksel2 = 0x03,
 508                 .incksel3 = 0x20,
 509                 .incksel4 = 0x01,
 510                 .incksel5 = 0x1a,
 511                 .incksel6 = 0x1a,
 512         },
 513         [IMX290_CLK_74_25] = {
 514                 /* 74.25MHz clock config */
 515                 .incksel1 = 0x0c,
 516                 .incksel2 = 0x03,
 517                 .incksel3 = 0x10,
 518                 .incksel4 = 0x01,
 519                 .incksel5 = 0x1b,
 520                 .incksel6 = 0x1b,
 521         },
 522 };
 523
 524 static const struct imx290_clk_cfg imx290_720p_clock_config[] = {
 525         [IMX290_CLK_37_125] = {
 526                 /* 37.125MHz clock config */
 527                 .incksel1 = 0x20,
 528                 .incksel2 = 0x00,
 529                 .incksel3 = 0x20,
 530                 .incksel4 = 0x01,
 531                 .incksel5 = 0x1a,
 532                 .incksel6 = 0x1a,
 533         },
 534         [IMX290_CLK_74_25] = {
 535                 /* 74.25MHz clock config */
 536                 .incksel1 = 0x10,
 537                 .incksel2 = 0x00,
 538                 .incksel3 = 0x10,
 539                 .incksel4 = 0x01,
 540                 .incksel5 = 0x1b,
 541                 .incksel6 = 0x1b,
 542         },
 543 };
 544
 545 /* Mode configs */
 546 static const struct imx290_mode imx290_modes_2lanes[] = {
 547         {
 548                 .width = 1920,
 549                 .height = 1080,
 550                 .hmax_min = 2200,
 551                 .vmax_min = 1125,
 552                 .link_freq_index = FREQ_INDEX_1080P,
 553                 .ctrl_07 = IMX290_WINMODE_1080P,
 554                 .data = imx290_1080p_settings,
 555                 .data_size = ARRAY_SIZE(imx290_1080p_settings),
 556                 .clk_cfg = imx290_1080p_clock_config,
 557         },
 558         {
 559                 .width = 1280,
 560                 .height = 720,
 561                 .hmax_min = 3300,
 562                 .vmax_min = 750,
 563                 .link_freq_index = FREQ_INDEX_720P,
 564                 .ctrl_07 = IMX290_WINMODE_720P,
 565                 .data = imx290_720p_settings,
 566                 .data_size = ARRAY_SIZE(imx290_720p_settings),
 567                 .clk_cfg = imx290_720p_clock_config,
 568         },
 569 };
 570
 571 static const struct imx290_mode imx290_modes_4lanes[] = {
 572         {
 573                 .width = 1920,
 574                 .height = 1080,
 575                 .hmax_min = 2200,
 576                 .vmax_min = 1125,
 577                 .link_freq_index = FREQ_INDEX_1080P,
 578                 .ctrl_07 = IMX290_WINMODE_1080P,
 579                 .data = imx290_1080p_settings,
 580                 .data_size = ARRAY_SIZE(imx290_1080p_settings),
 581                 .clk_cfg = imx290_1080p_clock_config,
 582         },
 583         {
 584                 .width = 1280,
 585                 .height = 720,
 586                 .hmax_min = 3300,
 587                 .vmax_min = 750,
 588                 .link_freq_index = FREQ_INDEX_720P,
 589                 .ctrl_07 = IMX290_WINMODE_720P,
 590                 .data = imx290_720p_settings,
 591                 .data_size = ARRAY_SIZE(imx290_720p_settings),
 592                 .clk_cfg = imx290_720p_clock_config,
 593         },
 594 };
 595
 596 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290)
 597 {
 598         if (imx290->nlanes == 2)
 599                 return imx290_modes_2lanes;
 600         else
 601                 return imx290_modes_4lanes;
 602 }
 603
 604 static inline int imx290_modes_num(const struct imx290 *imx290)
 605 {
 606         if (imx290->nlanes == 2)
 607                 return ARRAY_SIZE(imx290_modes_2lanes);
 608         else
 609                 return ARRAY_SIZE(imx290_modes_4lanes);
 610 }
 611
 612 struct imx290_format_info {
 613         u32 code[IMX290_VARIANT_MAX];
 614         u8 bpp;
 615         const struct cci_reg_sequence *regs;
 616         unsigned int num_regs;
 617 };
 618
 619 static const struct imx290_format_info imx290_formats[] = {
 620         {
 621                 .code = {
 622                         [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB10_1X10,
 623                         [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y10_1X10
 624                 },
 625                 .bpp = 10,
 626                 .regs = imx290_10bit_settings,
 627                 .num_regs = ARRAY_SIZE(imx290_10bit_settings),
 628         }, {
 629                 .code = {
 630                         [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB12_1X12,
 631                         [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y12_1X12
 632                 },
 633                 .bpp = 12,
 634                 .regs = imx290_12bit_settings,
 635                 .num_regs = ARRAY_SIZE(imx290_12bit_settings),
 636         }
 637 };
 638
 639 static const struct imx290_format_info *
 640 imx290_format_info(const struct imx290 *imx290, u32 code)
 641 {
 642         unsigned int i;
 643
 644         for (i = 0; i < ARRAY_SIZE(imx290_formats); ++i) {
 645                 const struct imx290_format_info *info = &imx290_formats[i];
 646
 647                 if (info->code[imx290->model->colour_variant] == code)
 648                         return info;
 649         }
 650
 651         return NULL;
 652 }
 653
 654 static int imx290_set_register_array(struct imx290 *imx290,
 655                                      const struct cci_reg_sequence *settings,
 656                                      unsigned int num_settings)
 657 {
 658         int ret;
 659
 660         ret = cci_multi_reg_write(imx290->regmap, settings, num_settings, NULL);
 661         if (ret < 0)
 662                 return ret;
 663
 664         /* Provide 10ms settle time */
 665         usleep_range(10000, 11000);
 666
 667         return 0;
 668 }
 669
 670 static int imx290_set_clock(struct imx290 *imx290)
 671 {
 672         const struct imx290_mode *mode = imx290->current_mode;
 673         enum imx290_clk_freq clk_idx = imx290->xclk_idx;
 674         const struct imx290_clk_cfg *clk_cfg = &mode->clk_cfg[clk_idx];
 675         int ret;
 676
 677         ret = imx290_set_register_array(imx290, xclk_regs[clk_idx],
 678                                         IMX290_NUM_CLK_REGS);
 679
 680         cci_write(imx290->regmap, IMX290_INCKSEL1, clk_cfg->incksel1, &ret);
 681         cci_write(imx290->regmap, IMX290_INCKSEL2, clk_cfg->incksel2, &ret);
 682         cci_write(imx290->regmap, IMX290_INCKSEL3, clk_cfg->incksel3, &ret);
 683         cci_write(imx290->regmap, IMX290_INCKSEL4, clk_cfg->incksel4, &ret);
 684         cci_write(imx290->regmap, IMX290_INCKSEL5, clk_cfg->incksel5, &ret);
 685         cci_write(imx290->regmap, IMX290_INCKSEL6, clk_cfg->incksel6, &ret);
 686
 687         return ret;
 688 }
 689
 690 static int imx290_set_data_lanes(struct imx290 *imx290)
 691 {
 692         int ret = 0;
 693
 694         cci_write(imx290->regmap, IMX290_PHY_LANE_NUM, imx290->nlanes - 1,
 695                   &ret);
 696         cci_write(imx290->regmap, IMX290_CSI_LANE_MODE, imx290->nlanes - 1,
 697                   &ret);
 698         cci_write(imx290->regmap, IMX290_FR_FDG_SEL, 0x01, &ret);
 699
 700         return ret;
 701 }
 702
 703 static int imx290_set_black_level(struct imx290 *imx290,
 704                                   const struct v4l2_mbus_framefmt *format,
 705                                   unsigned int black_level, int *err)
 706 {
 707         unsigned int bpp = imx290_format_info(imx290, format->code)->bpp;
 708
 709         return cci_write(imx290->regmap, IMX290_BLKLEVEL,
 710                          black_level >> (16 - bpp), err);
 711 }
 712
 713 static int imx290_set_csi_config(struct imx290 *imx290)
 714 {
 715         const s64 *link_freqs = imx290_link_freqs_ptr(imx290);
 716         const struct imx290_csi_cfg *csi_cfg;
 717         int ret = 0;
 718
 719         switch (link_freqs[imx290->current_mode->link_freq_index]) {
 720         case 445500000:
 721                 csi_cfg = &imx290_csi_445_5mhz;
 722                 break;
 723         case 297000000:
 724                 csi_cfg = &imx290_csi_297mhz;
 725                 break;
 726         case 222750000:
 727                 csi_cfg = &imx290_csi_222_75mhz;
 728                 break;
 729         case 148500000:
 730                 csi_cfg = &imx290_csi_148_5mhz;
 731                 break;
 732         default:
 733                 return -EINVAL;
 734         }
 735
 736         cci_write(imx290->regmap, IMX290_REPETITION, csi_cfg->repetition, &ret);
 737         cci_write(imx290->regmap, IMX290_TCLKPOST, csi_cfg->tclkpost, &ret);
 738         cci_write(imx290->regmap, IMX290_THSZERO, csi_cfg->thszero, &ret);
 739         cci_write(imx290->regmap, IMX290_THSPREPARE, csi_cfg->thsprepare, &ret);
 740         cci_write(imx290->regmap, IMX290_TCLKTRAIL, csi_cfg->tclktrail, &ret);
 741         cci_write(imx290->regmap, IMX290_THSTRAIL, csi_cfg->thstrail, &ret);
 742         cci_write(imx290->regmap, IMX290_TCLKZERO, csi_cfg->tclkzero, &ret);
 743         cci_write(imx290->regmap, IMX290_TCLKPREPARE, csi_cfg->tclkprepare,
 744                   &ret);
 745         cci_write(imx290->regmap, IMX290_TLPX, csi_cfg->tlpx, &ret);
 746
 747         return ret;
 748 }
 749
 750 static int imx290_setup_format(struct imx290 *imx290,
 751                                const struct v4l2_mbus_framefmt *format)
 752 {
 753         const struct imx290_format_info *info;
 754         int ret;
 755
 756         info = imx290_format_info(imx290, format->code);
 757
 758         ret = imx290_set_register_array(imx290, info->regs, info->num_regs);
 759         if (ret < 0) {
 760                 dev_err(imx290->dev, "Could not set format registers\n");
 761                 return ret;
 762         }
 763
 764         return imx290_set_black_level(imx290, format,
 765                                       IMX290_BLACK_LEVEL_DEFAULT, &ret);
 766 }
 767
 768 /* ----------------------------------------------------------------------------
 769  * Controls
 770  */
 771 static void imx290_exposure_update(struct imx290 *imx290,
 772                                    const struct imx290_mode *mode)
 773 {
 774         unsigned int exposure_max;
 775
 776         exposure_max = imx290->vblank->val + mode->height -
 777                        IMX290_EXPOSURE_OFFSET;
 778         __v4l2_ctrl_modify_range(imx290->exposure, 1, exposure_max, 1,
 779                                  exposure_max);
 780 }
 781
 782 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl)
 783 {
 784         struct imx290 *imx290 = container_of(ctrl->handler,
 785                                              struct imx290, ctrls);
 786         const struct v4l2_mbus_framefmt *format;
 787         struct v4l2_subdev_state *state;
 788         int ret = 0, vmax;
 789
 790         /*
 791          * Return immediately for controls that don't need to be applied to the
 792          * device.
 793          */
 794         if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY)
 795                 return 0;
 796
 797         if (ctrl->id == V4L2_CID_VBLANK) {
 798                 /* Changing vblank changes the allowed range for exposure. */
 799                 imx290_exposure_update(imx290, imx290->current_mode);
 800         }
 801
 802         /* V4L2 controls values will be applied only when power is already up */
 803         if (!pm_runtime_get_if_in_use(imx290->dev))
 804                 return 0;
 805
 806         state = v4l2_subdev_get_locked_active_state(&imx290->sd);
 807         format = v4l2_subdev_state_get_format(state, 0);
 808
 809         switch (ctrl->id) {
 810         case V4L2_CID_ANALOGUE_GAIN:
 811                 ret = cci_write(imx290->regmap, IMX290_GAIN, ctrl->val, NULL);
 812                 break;
 813
 814         case V4L2_CID_VBLANK:
 815                 ret = cci_write(imx290->regmap, IMX290_VMAX,
 816                                 ctrl->val + imx290->current_mode->height, NULL);
 817                 /*
 818                  * Due to the way that exposure is programmed in this sensor in
 819                  * relation to VMAX, we have to reprogramme it whenever VMAX is
 820                  * changed.
 821                  * Update ctrl so that the V4L2_CID_EXPOSURE case can refer to
 822                  * it.
 823                  */
 824                 ctrl = imx290->exposure;
 825                 fallthrough;
 826         case V4L2_CID_EXPOSURE:
 827                 vmax = imx290->vblank->val + imx290->current_mode->height;
 828                 ret = cci_write(imx290->regmap, IMX290_SHS1,
 829                                 vmax - ctrl->val - 1, NULL);
 830                 break;
 831
 832         case V4L2_CID_TEST_PATTERN:
 833                 if (ctrl->val) {
 834                         imx290_set_black_level(imx290, format, 0, &ret);
 835                         usleep_range(10000, 11000);
 836                         cci_write(imx290->regmap, IMX290_PGCTRL,
 837                                   (u8)(IMX290_PGCTRL_REGEN |
 838                                        IMX290_PGCTRL_THRU |
 839                                        IMX290_PGCTRL_MODE(ctrl->val)), &ret);
 840                 } else {
 841                         cci_write(imx290->regmap, IMX290_PGCTRL, 0x00, &ret);
 842                         usleep_range(10000, 11000);
 843                         imx290_set_black_level(imx290, format,
 844                                                IMX290_BLACK_LEVEL_DEFAULT, &ret);
 845                 }
 846                 break;
 847
 848         case V4L2_CID_HBLANK:
 849                 ret = cci_write(imx290->regmap, IMX290_HMAX,
 850                                 ctrl->val + imx290->current_mode->width, NULL);
 851                 break;
 852
 853         case V4L2_CID_HFLIP:
 854         case V4L2_CID_VFLIP:
 855         {
 856                 u32 reg;
 857
 858                 reg = imx290->current_mode->ctrl_07;
 859                 if (imx290->hflip->val)
 860                         reg |= IMX290_HREVERSE;
 861                 if (imx290->vflip->val)
 862                         reg |= IMX290_VREVERSE;
 863                 ret = cci_write(imx290->regmap, IMX290_CTRL_07, reg, NULL);
 864                 break;
 865         }
 866
 867         default:
 868                 ret = -EINVAL;
 869                 break;
 870         }
 871
 872         pm_runtime_mark_last_busy(imx290->dev);
 873         pm_runtime_put_autosuspend(imx290->dev);
 874
 875         return ret;
 876 }
 877
 878 static const struct v4l2_ctrl_ops imx290_ctrl_ops = {
 879         .s_ctrl = imx290_set_ctrl,
 880 };
 881
 882 static const char * const imx290_test_pattern_menu[] = {
 883         "Disabled",
 884         "Sequence Pattern 1",
 885         "Horizontal Color-bar Chart",
 886         "Vertical Color-bar Chart",
 887         "Sequence Pattern 2",
 888         "Gradation Pattern 1",
 889         "Gradation Pattern 2",
 890         "000/555h Toggle Pattern",
 891 };
 892
 893 static void imx290_ctrl_update(struct imx290 *imx290,
 894                                const struct imx290_mode *mode)
 895 {
 896         unsigned int hblank_min = mode->hmax_min - mode->width;
 897         unsigned int hblank_max = IMX290_HMAX_MAX - mode->width;
 898         unsigned int vblank_min = mode->vmax_min - mode->height;
 899         unsigned int vblank_max = IMX290_VMAX_MAX - mode->height;
 900
 901         __v4l2_ctrl_s_ctrl(imx290->link_freq, mode->link_freq_index);
 902
 903         __v4l2_ctrl_modify_range(imx290->hblank, hblank_min, hblank_max, 1,
 904                                  hblank_min);
 905         __v4l2_ctrl_modify_range(imx290->vblank, vblank_min, vblank_max, 1,
 906                                  vblank_min);
 907 }
 908
 909 static int imx290_ctrl_init(struct imx290 *imx290)
 910 {
 911         struct v4l2_fwnode_device_properties props;
 912         int ret;
 913
 914         ret = v4l2_fwnode_device_parse(imx290->dev, &props);
 915         if (ret < 0)
 916                 return ret;
 917
 918         v4l2_ctrl_handler_init(&imx290->ctrls, 11);
 919
 920         /*
 921          * The sensor has an analog gain and a digital gain, both controlled
 922          * through a single gain value, expressed in 0.3dB increments. Values
 923          * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values
 924          * up to 72.0dB (240) add further digital gain. Limit the range to
 925          * analog gain only, support for digital gain can be added separately
 926          * if needed.
 927          */
 928         v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
 929                           V4L2_CID_ANALOGUE_GAIN, 0,
 930                           imx290->model->max_analog_gain, 1, 0);
 931
 932         /*
 933          * Correct range will be determined through imx290_ctrl_update setting
 934          * V4L2_CID_VBLANK.
 935          */
 936         imx290->exposure = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
 937                                              V4L2_CID_EXPOSURE, 1, 65535, 1,
 938                                              65535);
 939
 940         /*
 941          * Set the link frequency, pixel rate, horizontal blanking and vertical
 942          * blanking to hardcoded values, they will be updated by
 943          * imx290_ctrl_update().
 944          */
 945         imx290->link_freq =
 946                 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,
 947                                        V4L2_CID_LINK_FREQ,
 948                                        imx290_link_freqs_num(imx290) - 1, 0,
 949                                        imx290_link_freqs_ptr(imx290));
 950         if (imx290->link_freq)
 951                 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 952
 953         v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, V4L2_CID_PIXEL_RATE,
 954                           IMX290_PIXEL_RATE, IMX290_PIXEL_RATE, 1,
 955                           IMX290_PIXEL_RATE);
 956
 957         v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops,
 958                                      V4L2_CID_TEST_PATTERN,
 959                                      ARRAY_SIZE(imx290_test_pattern_menu) - 1,
 960                                      0, 0, imx290_test_pattern_menu);
 961
 962         /*
 963          * Actual range will be set from imx290_ctrl_update later in the probe.
 964          */
 965         imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
 966                                            V4L2_CID_HBLANK, 1, 1, 1, 1);
 967
 968         imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
 969                                            V4L2_CID_VBLANK, 1, 1, 1, 1);
 970
 971         imx290->hflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
 972                                           V4L2_CID_HFLIP, 0, 1, 1, 0);
 973         imx290->vflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
 974                                           V4L2_CID_VFLIP, 0, 1, 1, 0);
 975         v4l2_ctrl_cluster(2, &imx290->hflip);
 976
 977         v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops,
 978                                         &props);
 979
 980         imx290->sd.ctrl_handler = &imx290->ctrls;
 981
 982         if (imx290->ctrls.error) {
 983                 ret = imx290->ctrls.error;
 984                 v4l2_ctrl_handler_free(&imx290->ctrls);
 985                 return ret;
 986         }
 987
 988         return 0;
 989 }
 990
 991 /* ----------------------------------------------------------------------------
 992  * Subdev operations
 993  */
 994
 995 /* Start streaming */
 996 static int imx290_start_streaming(struct imx290 *imx290,
 997                                   struct v4l2_subdev_state *state)
 998 {
 999         const struct v4l2_mbus_framefmt *format;
1000         int ret;
1001
1002         /* Set init register settings */
1003         ret = imx290_set_register_array(imx290, imx290_global_init_settings,
1004                                         ARRAY_SIZE(imx290_global_init_settings));
1005         if (ret < 0) {
1006                 dev_err(imx290->dev, "Could not set init registers\n");
1007                 return ret;
1008         }
1009
1010         /* Set mdel specific init register settings */
1011         ret = imx290_set_register_array(imx290, imx290->model->init_regs,
1012                                         imx290->model->init_regs_num);
1013         if (ret < 0) {
1014                 dev_err(imx290->dev, "Could not set model specific init registers\n");
1015                 return ret;
1016         }
1017
1018         /* Set clock parameters based on mode and xclk */
1019         ret = imx290_set_clock(imx290);
1020         if (ret < 0) {
1021                 dev_err(imx290->dev, "Could not set clocks - %d\n", ret);
1022                 return ret;
1023         }
1024
1025         /* Set data lane count */
1026         ret = imx290_set_data_lanes(imx290);
1027         if (ret < 0) {
1028                 dev_err(imx290->dev, "Could not set data lanes - %d\n", ret);
1029                 return ret;
1030         }
1031
1032         ret = imx290_set_csi_config(imx290);
1033         if (ret < 0) {
1034                 dev_err(imx290->dev, "Could not set csi cfg - %d\n", ret);
1035                 return ret;
1036         }
1037
1038         /* Apply the register values related to current frame format */
1039         format = v4l2_subdev_state_get_format(state, 0);
1040         ret = imx290_setup_format(imx290, format);
1041         if (ret < 0) {
1042                 dev_err(imx290->dev, "Could not set frame format - %d\n", ret);
1043                 return ret;
1044         }
1045
1046         /* Apply default values of current mode */
1047         ret = imx290_set_register_array(imx290, imx290->current_mode->data,
1048                                         imx290->current_mode->data_size);
1049         if (ret < 0) {
1050                 dev_err(imx290->dev, "Could not set current mode - %d\n", ret);
1051                 return ret;
1052         }
1053
1054         /* Apply customized values from user */
1055         ret = __v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler);
1056         if (ret) {
1057                 dev_err(imx290->dev, "Could not sync v4l2 controls - %d\n", ret);
1058                 return ret;
1059         }
1060
1061         cci_write(imx290->regmap, IMX290_STANDBY, 0x00, &ret);
1062
1063         msleep(30);
1064
1065         /* Start streaming */
1066         return cci_write(imx290->regmap, IMX290_XMSTA, 0x00, &ret);
1067 }
1068
1069 /* Stop streaming */
1070 static int imx290_stop_streaming(struct imx290 *imx290)
1071 {
1072         int ret = 0;
1073
1074         cci_write(imx290->regmap, IMX290_STANDBY, 0x01, &ret);
1075
1076         msleep(30);
1077
1078         return cci_write(imx290->regmap, IMX290_XMSTA, 0x01, &ret);
1079 }
1080
1081 static int imx290_set_stream(struct v4l2_subdev *sd, int enable)
1082 {
1083         struct imx290 *imx290 = to_imx290(sd);
1084         struct v4l2_subdev_state *state;
1085         int ret = 0;
1086
1087         state = v4l2_subdev_lock_and_get_active_state(sd);
1088
1089         if (enable) {
1090                 ret = pm_runtime_resume_and_get(imx290->dev);
1091                 if (ret < 0)
1092                         goto unlock;
1093
1094                 ret = imx290_start_streaming(imx290, state);
1095                 if (ret) {
1096                         dev_err(imx290->dev, "Start stream failed\n");
1097                         pm_runtime_put_sync(imx290->dev);
1098                         goto unlock;
1099                 }
1100         } else {
1101                 imx290_stop_streaming(imx290);
1102                 pm_runtime_mark_last_busy(imx290->dev);
1103                 pm_runtime_put_autosuspend(imx290->dev);
1104         }
1105
1106         /*
1107          * vflip and hflip should not be changed during streaming as the sensor
1108          * will produce an invalid frame.
1109          */
1110         __v4l2_ctrl_grab(imx290->vflip, enable);
1111         __v4l2_ctrl_grab(imx290->hflip, enable);
1112
1113 unlock:
1114         v4l2_subdev_unlock_state(state);
1115         return ret;
1116 }
1117
1118 static int imx290_enum_mbus_code(struct v4l2_subdev *sd,
1119                                  struct v4l2_subdev_state *sd_state,
1120                                  struct v4l2_subdev_mbus_code_enum *code)
1121 {
1122         const struct imx290 *imx290 = to_imx290(sd);
1123
1124         if (code->index >= ARRAY_SIZE(imx290_formats))
1125                 return -EINVAL;
1126
1127         code->code = imx290_formats[code->index].code[imx290->model->colour_variant];
1128
1129         return 0;
1130 }
1131
1132 static int imx290_enum_frame_size(struct v4l2_subdev *sd,
1133                                   struct v4l2_subdev_state *sd_state,
1134                                   struct v4l2_subdev_frame_size_enum *fse)
1135 {
1136         const struct imx290 *imx290 = to_imx290(sd);
1137         const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290);
1138
1139         if (!imx290_format_info(imx290, fse->code))
1140                 return -EINVAL;
1141
1142         if (fse->index >= imx290_modes_num(imx290))
1143                 return -EINVAL;
1144
1145         fse->min_width = imx290_modes[fse->index].width;
1146         fse->max_width = imx290_modes[fse->index].width;
1147         fse->min_height = imx290_modes[fse->index].height;
1148         fse->max_height = imx290_modes[fse->index].height;
1149
1150         return 0;
1151 }
1152
1153 static int imx290_set_fmt(struct v4l2_subdev *sd,
1154                           struct v4l2_subdev_state *sd_state,
1155                           struct v4l2_subdev_format *fmt)
1156 {
1157         struct imx290 *imx290 = to_imx290(sd);
1158         const struct imx290_mode *mode;
1159         struct v4l2_mbus_framefmt *format;
1160
1161         mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290),
1162                                       imx290_modes_num(imx290), width, height,
1163                                       fmt->format.width, fmt->format.height);
1164
1165         fmt->format.width = mode->width;
1166         fmt->format.height = mode->height;
1167
1168         if (!imx290_format_info(imx290, fmt->format.code))
1169                 fmt->format.code = imx290_formats[0].code[imx290->model->colour_variant];
1170
1171         fmt->format.field = V4L2_FIELD_NONE;
1172         fmt->format.colorspace = V4L2_COLORSPACE_RAW;
1173         fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601;
1174         fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE;
1175         fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
1176
1177         format = v4l2_subdev_state_get_format(sd_state, 0);
1178
1179         if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1180                 imx290->current_mode = mode;
1181
1182                 imx290_ctrl_update(imx290, mode);
1183                 imx290_exposure_update(imx290, mode);
1184         }
1185
1186         *format = fmt->format;
1187
1188         return 0;
1189 }
1190
1191 static int imx290_get_selection(struct v4l2_subdev *sd,
1192                                 struct v4l2_subdev_state *sd_state,
1193                                 struct v4l2_subdev_selection *sel)
1194 {
1195         struct imx290 *imx290 = to_imx290(sd);
1196         struct v4l2_mbus_framefmt *format;
1197
1198         switch (sel->target) {
1199         case V4L2_SEL_TGT_CROP: {
1200                 format = v4l2_subdev_state_get_format(sd_state, 0);
1201
1202                 /*
1203                  * The sensor moves the readout by 1 pixel based on flips to
1204                  * keep the Bayer order the same.
1205                  */
1206                 sel->r.top = IMX290_PIXEL_ARRAY_MARGIN_TOP
1207                            + (IMX290_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2
1208                            + imx290->vflip->val;
1209                 sel->r.left = IMX290_PIXEL_ARRAY_MARGIN_LEFT
1210                             + (IMX290_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2
1211                             + imx290->hflip->val;
1212                 sel->r.width = format->width;
1213                 sel->r.height = format->height;
1214
1215                 return 0;
1216         }
1217
1218         case V4L2_SEL_TGT_NATIVE_SIZE:
1219         case V4L2_SEL_TGT_CROP_BOUNDS:
1220                 sel->r.top = 0;
1221                 sel->r.left = 0;
1222                 sel->r.width = IMX290_PIXEL_ARRAY_WIDTH;
1223                 sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT;
1224
1225                 return 0;
1226
1227         case V4L2_SEL_TGT_CROP_DEFAULT:
1228                 sel->r.top = IMX290_PIXEL_ARRAY_MARGIN_TOP;
1229                 sel->r.left = IMX290_PIXEL_ARRAY_MARGIN_LEFT;
1230                 sel->r.width = IMX290_PIXEL_ARRAY_RECORDING_WIDTH;
1231                 sel->r.height = IMX290_PIXEL_ARRAY_RECORDING_HEIGHT;
1232
1233                 return 0;
1234
1235         default:
1236                 return -EINVAL;
1237         }
1238 }
1239
1240 static int imx290_entity_init_state(struct v4l2_subdev *subdev,
1241                                     struct v4l2_subdev_state *sd_state)
1242 {
1243         struct v4l2_subdev_format fmt = {
1244                 .which = V4L2_SUBDEV_FORMAT_TRY,
1245                 .format = {
1246                         .width = 1920,
1247                         .height = 1080,
1248                 },
1249         };
1250
1251         imx290_set_fmt(subdev, sd_state, &fmt);
1252
1253         return 0;
1254 }
1255
1256 static const struct v4l2_subdev_video_ops imx290_video_ops = {
1257         .s_stream = imx290_set_stream,
1258 };
1259
1260 static const struct v4l2_subdev_pad_ops imx290_pad_ops = {
1261         .enum_mbus_code = imx290_enum_mbus_code,
1262         .enum_frame_size = imx290_enum_frame_size,
1263         .get_fmt = v4l2_subdev_get_fmt,
1264         .set_fmt = imx290_set_fmt,
1265         .get_selection = imx290_get_selection,
1266 };
1267
1268 static const struct v4l2_subdev_ops imx290_subdev_ops = {
1269         .video = &imx290_video_ops,
1270         .pad = &imx290_pad_ops,
1271 };
1272
1273 static const struct v4l2_subdev_internal_ops imx290_internal_ops = {
1274         .init_state = imx290_entity_init_state,
1275 };
1276
1277 static const struct media_entity_operations imx290_subdev_entity_ops = {
1278         .link_validate = v4l2_subdev_link_validate,
1279 };
1280
1281 static int imx290_subdev_init(struct imx290 *imx290)
1282 {
1283         struct i2c_client *client = to_i2c_client(imx290->dev);
1284         struct v4l2_subdev_state *state;
1285         int ret;
1286
1287         imx290->current_mode = &imx290_modes_ptr(imx290)[0];
1288
1289         /*
1290          * After linking the subdev with the imx290 instance, we are allowed to
1291          * use the pm_runtime functions. Decrease the PM usage count. The device
1292          * will get suspended after the autosuspend delay, turning the power
1293          * off. However, the communication happening in imx290_ctrl_update()
1294          * will already be prevented even before the delay.
1295          */
1296         v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops);
1297         imx290->sd.dev = imx290->dev;
1298         pm_runtime_mark_last_busy(imx290->dev);
1299         pm_runtime_put_autosuspend(imx290->dev);
1300
1301         imx290->sd.internal_ops = &imx290_internal_ops;
1302         imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1303         imx290->sd.entity.ops = &imx290_subdev_entity_ops;
1304         imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1305
1306         imx290->pad.flags = MEDIA_PAD_FL_SOURCE;
1307         ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad);
1308         if (ret < 0) {
1309                 dev_err(imx290->dev, "Could not register media entity\n");
1310                 return ret;
1311         }
1312
1313         ret = imx290_ctrl_init(imx290);
1314         if (ret < 0) {
1315                 dev_err(imx290->dev, "Control initialization error %d\n", ret);
1316                 goto err_media;
1317         }
1318
1319         imx290->sd.state_lock = imx290->ctrls.lock;
1320
1321         ret = v4l2_subdev_init_finalize(&imx290->sd);
1322         if (ret < 0) {
1323                 dev_err(imx290->dev, "subdev initialization error %d\n", ret);
1324                 goto err_ctrls;
1325         }
1326
1327         state = v4l2_subdev_lock_and_get_active_state(&imx290->sd);
1328         imx290_ctrl_update(imx290, imx290->current_mode);
1329         v4l2_subdev_unlock_state(state);
1330
1331         return 0;
1332
1333 err_ctrls:
1334         v4l2_ctrl_handler_free(&imx290->ctrls);
1335 err_media:
1336         media_entity_cleanup(&imx290->sd.entity);
1337         return ret;
1338 }
1339
1340 static void imx290_subdev_cleanup(struct imx290 *imx290)
1341 {
1342         v4l2_subdev_cleanup(&imx290->sd);
1343         media_entity_cleanup(&imx290->sd.entity);
1344         v4l2_ctrl_handler_free(&imx290->ctrls);
1345 }
1346
1347 /* ----------------------------------------------------------------------------
1348  * Power management
1349  */
1350
1351 static int imx290_power_on(struct imx290 *imx290)
1352 {
1353         int ret;
1354
1355         ret = clk_prepare_enable(imx290->xclk);
1356         if (ret) {
1357                 dev_err(imx290->dev, "Failed to enable clock\n");
1358                 return ret;
1359         }
1360
1361         ret = regulator_bulk_enable(ARRAY_SIZE(imx290->supplies),
1362                                     imx290->supplies);
1363         if (ret) {
1364                 dev_err(imx290->dev, "Failed to enable regulators\n");
1365                 clk_disable_unprepare(imx290->xclk);
1366                 return ret;
1367         }
1368
1369         usleep_range(1, 2);
1370         gpiod_set_value_cansleep(imx290->rst_gpio, 0);
1371         usleep_range(30000, 31000);
1372
1373         return 0;
1374 }
1375
1376 static void imx290_power_off(struct imx290 *imx290)
1377 {
1378         clk_disable_unprepare(imx290->xclk);
1379         gpiod_set_value_cansleep(imx290->rst_gpio, 1);
1380         regulator_bulk_disable(ARRAY_SIZE(imx290->supplies), imx290->supplies);
1381 }
1382
1383 static int imx290_runtime_resume(struct device *dev)
1384 {
1385         struct v4l2_subdev *sd = dev_get_drvdata(dev);
1386         struct imx290 *imx290 = to_imx290(sd);
1387
1388         return imx290_power_on(imx290);
1389 }
1390
1391 static int imx290_runtime_suspend(struct device *dev)
1392 {
1393         struct v4l2_subdev *sd = dev_get_drvdata(dev);
1394         struct imx290 *imx290 = to_imx290(sd);
1395
1396         imx290_power_off(imx290);
1397
1398         return 0;
1399 }
1400
1401 static const struct dev_pm_ops imx290_pm_ops = {
1402         RUNTIME_PM_OPS(imx290_runtime_suspend, imx290_runtime_resume, NULL)
1403 };
1404
1405 /* ----------------------------------------------------------------------------
1406  * Probe & remove
1407  */
1408
1409 static const char * const imx290_supply_name[IMX290_NUM_SUPPLIES] = {
1410         "vdda",
1411         "vddd",
1412         "vdddo",
1413 };
1414
1415 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290)
1416 {
1417         unsigned int i;
1418
1419         for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++)
1420                 imx290->supplies[i].supply = imx290_supply_name[i];
1421
1422         return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx290->supplies),
1423                                        imx290->supplies);
1424 }
1425
1426 static int imx290_init_clk(struct imx290 *imx290)
1427 {
1428         u32 xclk_freq;
1429         int ret;
1430
1431         ret = device_property_read_u32(imx290->dev, "clock-frequency",
1432                                        &xclk_freq);
1433         if (ret) {
1434                 dev_err(imx290->dev, "Could not get xclk frequency\n");
1435                 return ret;
1436         }
1437
1438         /* external clock must be 37.125 MHz or 74.25MHz */
1439         switch (xclk_freq) {
1440         case 37125000:
1441                 imx290->xclk_idx = IMX290_CLK_37_125;
1442                 break;
1443         case 74250000:
1444                 imx290->xclk_idx = IMX290_CLK_74_25;
1445                 break;
1446         default:
1447                 dev_err(imx290->dev, "External clock frequency %u is not supported\n",
1448                         xclk_freq);
1449                 return -EINVAL;
1450         }
1451
1452         ret = clk_set_rate(imx290->xclk, xclk_freq);
1453         if (ret) {
1454                 dev_err(imx290->dev, "Could not set xclk frequency\n");
1455                 return ret;
1456         }
1457
1458         return 0;
1459 }
1460
1461 /*
1462  * Returns 0 if all link frequencies used by the driver for the given number
1463  * of MIPI data lanes are mentioned in the device tree, or the value of the
1464  * first missing frequency otherwise.
1465  */
1466 static s64 imx290_check_link_freqs(const struct imx290 *imx290,
1467                                    const struct v4l2_fwnode_endpoint *ep)
1468 {
1469         int i, j;
1470         const s64 *freqs = imx290_link_freqs_ptr(imx290);
1471         int freqs_count = imx290_link_freqs_num(imx290);
1472
1473         for (i = 0; i < freqs_count; i++) {
1474                 for (j = 0; j < ep->nr_of_link_frequencies; j++)
1475                         if (freqs[i] == ep->link_frequencies[j])
1476                                 break;
1477                 if (j == ep->nr_of_link_frequencies)
1478                         return freqs[i];
1479         }
1480         return 0;
1481 }
1482
1483 static const struct imx290_model_info imx290_models[] = {
1484         [IMX290_MODEL_IMX290LQR] = {
1485                 .colour_variant = IMX290_VARIANT_COLOUR,
1486                 .init_regs = imx290_global_init_settings_290,
1487                 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290),
1488                 .max_analog_gain = 100,
1489                 .name = "imx290",
1490         },
1491         [IMX290_MODEL_IMX290LLR] = {
1492                 .colour_variant = IMX290_VARIANT_MONO,
1493                 .init_regs = imx290_global_init_settings_290,
1494                 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290),
1495                 .max_analog_gain = 100,
1496                 .name = "imx290",
1497         },
1498         [IMX290_MODEL_IMX327LQR] = {
1499                 .colour_variant = IMX290_VARIANT_COLOUR,
1500                 .init_regs = imx290_global_init_settings_327,
1501                 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_327),
1502                 .max_analog_gain = 98,
1503                 .name = "imx327",
1504         },
1505         [IMX290_MODEL_IMX462LQR] = {
1506                 .colour_variant = IMX290_VARIANT_COLOUR,
1507                 .init_regs = imx290_global_init_settings_462,
1508                 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_462),
1509                 .max_analog_gain = 98,
1510                 .name = "imx462",
1511         },
1512         [IMX290_MODEL_IMX462LLR] = {
1513                 .colour_variant = IMX290_VARIANT_MONO,
1514                 .init_regs = imx290_global_init_settings_462,
1515                 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_462),
1516                 .max_analog_gain = 98,
1517                 .name = "imx462",
1518         },
1519 };
1520
1521 static int imx290_parse_dt(struct imx290 *imx290)
1522 {
1523         /* Only CSI2 is supported for now: */
1524         struct v4l2_fwnode_endpoint ep = {
1525                 .bus_type = V4L2_MBUS_CSI2_DPHY
1526         };
1527         struct fwnode_handle *endpoint;
1528         int ret;
1529         s64 fq;
1530
1531         imx290->model = of_device_get_match_data(imx290->dev);
1532
1533         endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(imx290->dev), NULL);
1534         if (!endpoint) {
1535                 dev_err(imx290->dev, "Endpoint node not found\n");
1536                 return -EINVAL;
1537         }
1538
1539         ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep);
1540         fwnode_handle_put(endpoint);
1541         if (ret == -ENXIO) {
1542                 dev_err(imx290->dev, "Unsupported bus type, should be CSI2\n");
1543                 goto done;
1544         } else if (ret) {
1545                 dev_err(imx290->dev, "Parsing endpoint node failed\n");
1546                 goto done;
1547         }
1548
1549         /* Get number of data lanes */
1550         imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes;
1551         if (imx290->nlanes != 2 && imx290->nlanes != 4) {
1552                 dev_err(imx290->dev, "Invalid data lanes: %d\n", imx290->nlanes);
1553                 ret = -EINVAL;
1554                 goto done;
1555         }
1556
1557         dev_dbg(imx290->dev, "Using %u data lanes\n", imx290->nlanes);
1558
1559         if (!ep.nr_of_link_frequencies) {
1560                 dev_err(imx290->dev, "link-frequency property not found in DT\n");
1561                 ret = -EINVAL;
1562                 goto done;
1563         }
1564
1565         /* Check that link frequences for all the modes are in device tree */
1566         fq = imx290_check_link_freqs(imx290, &ep);
1567         if (fq) {
1568                 dev_err(imx290->dev, "Link frequency of %lld is not supported\n",
1569                         fq);
1570                 ret = -EINVAL;
1571                 goto done;
1572         }
1573
1574         ret = 0;
1575
1576 done:
1577         v4l2_fwnode_endpoint_free(&ep);
1578         return ret;
1579 }
1580
1581 static int imx290_probe(struct i2c_client *client)
1582 {
1583         struct device *dev = &client->dev;
1584         struct imx290 *imx290;
1585         int ret;
1586
1587         imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL);
1588         if (!imx290)
1589                 return -ENOMEM;
1590
1591         imx290->dev = dev;
1592         imx290->regmap = devm_cci_regmap_init_i2c(client, 16);
1593         if (IS_ERR(imx290->regmap)) {
1594                 dev_err(dev, "Unable to initialize I2C\n");
1595                 return -ENODEV;
1596         }
1597
1598         ret = imx290_parse_dt(imx290);
1599         if (ret)
1600                 return ret;
1601
1602         /* Acquire resources. */
1603         imx290->xclk = devm_clk_get(dev, "xclk");
1604         if (IS_ERR(imx290->xclk))
1605                 return dev_err_probe(dev, PTR_ERR(imx290->xclk),
1606                                      "Could not get xclk\n");
1607
1608         ret = imx290_get_regulators(dev, imx290);
1609         if (ret < 0)
1610                 return dev_err_probe(dev, ret, "Cannot get regulators\n");
1611
1612         imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset",
1613                                                    GPIOD_OUT_HIGH);
1614         if (IS_ERR(imx290->rst_gpio))
1615                 return dev_err_probe(dev, PTR_ERR(imx290->rst_gpio),
1616                                      "Cannot get reset gpio\n");
1617
1618         /* Initialize external clock frequency. */
1619         ret = imx290_init_clk(imx290);
1620         if (ret)
1621                 return ret;
1622
1623         /*
1624          * Enable power management. The driver supports runtime PM, but needs to
1625          * work when runtime PM is disabled in the kernel. To that end, power
1626          * the sensor on manually here.
1627          */
1628         ret = imx290_power_on(imx290);
1629         if (ret < 0) {
1630                 dev_err(dev, "Could not power on the device\n");
1631                 return ret;
1632         }
1633
1634         /*
1635          * Enable runtime PM with autosuspend. As the device has been powered
1636          * manually, mark it as active, and increase the usage count without
1637          * resuming the device.
1638          */
1639         pm_runtime_set_active(dev);
1640         pm_runtime_get_noresume(dev);
1641         pm_runtime_enable(dev);
1642         pm_runtime_set_autosuspend_delay(dev, 1000);
1643         pm_runtime_use_autosuspend(dev);
1644
1645         /*
1646          * Make sure the sensor is available, in STANDBY and not streaming
1647          * before the V4L2 subdev is initialized.
1648          */
1649         ret = imx290_stop_streaming(imx290);
1650         if (ret) {
1651                 ret = dev_err_probe(dev, ret, "Could not initialize device\n");
1652                 goto err_pm;
1653         }
1654
1655         /* Initialize the V4L2 subdev. */
1656         ret = imx290_subdev_init(imx290);
1657         if (ret)
1658                 goto err_pm;
1659
1660         v4l2_i2c_subdev_set_name(&imx290->sd, client,
1661                                  imx290->model->name, NULL);
1662
1663         /*
1664          * Finally, register the V4L2 subdev. This must be done after
1665          * initializing everything as the subdev can be used immediately after
1666          * being registered.
1667          */
1668         ret = v4l2_async_register_subdev(&imx290->sd);
1669         if (ret < 0) {
1670                 dev_err(dev, "Could not register v4l2 device\n");
1671                 goto err_subdev;
1672         }
1673
1674         return 0;
1675
1676 err_subdev:
1677         imx290_subdev_cleanup(imx290);
1678 err_pm:
1679         pm_runtime_disable(dev);
1680         pm_runtime_put_noidle(dev);
1681         imx290_power_off(imx290);
1682         return ret;
1683 }
1684
1685 static void imx290_remove(struct i2c_client *client)
1686 {
1687         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1688         struct imx290 *imx290 = to_imx290(sd);
1689
1690         v4l2_async_unregister_subdev(sd);
1691         imx290_subdev_cleanup(imx290);
1692
1693         /*
1694          * Disable runtime PM. In case runtime PM is disabled in the kernel,
1695          * make sure to turn power off manually.
1696          */
1697         pm_runtime_disable(imx290->dev);
1698         if (!pm_runtime_status_suspended(imx290->dev))
1699                 imx290_power_off(imx290);
1700         pm_runtime_set_suspended(imx290->dev);
1701 }
1702
1703 static const struct of_device_id imx290_of_match[] = {
1704         {
1705                 /* Deprecated - synonym for "sony,imx290lqr" */
1706                 .compatible = "sony,imx290",
1707                 .data = &imx290_models[IMX290_MODEL_IMX290LQR],
1708         }, {
1709                 .compatible = "sony,imx290lqr",
1710                 .data = &imx290_models[IMX290_MODEL_IMX290LQR],
1711         }, {
1712                 .compatible = "sony,imx290llr",
1713                 .data = &imx290_models[IMX290_MODEL_IMX290LLR],
1714         }, {
1715                 .compatible = "sony,imx327lqr",
1716                 .data = &imx290_models[IMX290_MODEL_IMX327LQR],
1717         }, {
1718                 .compatible = "sony,imx462lqr",
1719                 .data = &imx290_models[IMX290_MODEL_IMX462LQR],
1720         }, {
1721                 .compatible = "sony,imx462llr",
1722                 .data = &imx290_models[IMX290_MODEL_IMX462LLR],
1723         },
1724         { /* sentinel */ },
1725 };
1726 MODULE_DEVICE_TABLE(of, imx290_of_match);
1727
1728 static struct i2c_driver imx290_i2c_driver = {
1729         .probe = imx290_probe,
1730         .remove = imx290_remove,
1731         .driver = {
1732                 .name = "imx290",
1733                 .pm = pm_ptr(&imx290_pm_ops),
1734                 .of_match_table = imx290_of_match,
1735         },
1736 };
1737
1738 module_i2c_driver(imx290_i2c_driver);
1739
1740 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver");
1741 MODULE_AUTHOR("FRAMOS GmbH");
1742 MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>");
1743 MODULE_LICENSE("GPL v2");