drivers/interconnect/qcom/sm8650.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * SM8650 interconnect IDs
   4  *
   5  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   6  * Copyright (c) 2023, Linaro Limited
   7  */
   8
   9 #ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H
  10 #define __DRIVERS_INTERCONNECT_QCOM_SM8650_H
  11
  12 #define SM8650_MASTER_A1NOC_SNOC                0
  13 #define SM8650_MASTER_A2NOC_SNOC                1
  14 #define SM8650_MASTER_ANOC_PCIE_GEM_NOC         2
  15 #define SM8650_MASTER_APPSS_PROC                3
  16 #define SM8650_MASTER_CAMNOC_HF                 4
  17 #define SM8650_MASTER_CAMNOC_ICP                5
  18 #define SM8650_MASTER_CAMNOC_SF                 6
  19 #define SM8650_MASTER_CDSP_HCP                  7
  20 #define SM8650_MASTER_CDSP_PROC                 8
  21 #define SM8650_MASTER_CNOC_CFG                  9
  22 #define SM8650_MASTER_CNOC_MNOC_CFG             10
  23 #define SM8650_MASTER_COMPUTE_NOC               11
  24 #define SM8650_MASTER_CRYPTO                    12
  25 #define SM8650_MASTER_GEM_NOC_CNOC              13
  26 #define SM8650_MASTER_GEM_NOC_PCIE_SNOC         14
  27 #define SM8650_MASTER_GFX3D                     15
  28 #define SM8650_MASTER_GIC                       16
  29 #define SM8650_MASTER_GPU_TCU                   17
  30 #define SM8650_MASTER_IPA                       18
  31 #define SM8650_MASTER_LLCC                      19
  32 #define SM8650_MASTER_LPASS_GEM_NOC             20
  33 #define SM8650_MASTER_LPASS_LPINOC              21
  34 #define SM8650_MASTER_LPASS_PROC                22
  35 #define SM8650_MASTER_LPIAON_NOC                23
  36 #define SM8650_MASTER_MDP                       24
  37 #define SM8650_MASTER_MNOC_HF_MEM_NOC           25
  38 #define SM8650_MASTER_MNOC_SF_MEM_NOC           26
  39 #define SM8650_MASTER_MSS_PROC                  27
  40 #define SM8650_MASTER_PCIE_0                    28
  41 #define SM8650_MASTER_PCIE_1                    29
  42 #define SM8650_MASTER_PCIE_ANOC_CFG             30
  43 #define SM8650_MASTER_QDSS_BAM                  31
  44 #define SM8650_MASTER_QDSS_ETR                  32
  45 #define SM8650_MASTER_QDSS_ETR_1                33
  46 #define SM8650_MASTER_QSPI_0                    34
  47 #define SM8650_MASTER_QUP_1                     35
  48 #define SM8650_MASTER_QUP_2                     36
  49 #define SM8650_MASTER_QUP_3                     37
  50 #define SM8650_MASTER_QUP_CORE_0                38
  51 #define SM8650_MASTER_QUP_CORE_1                39
  52 #define SM8650_MASTER_QUP_CORE_2                40
  53 #define SM8650_MASTER_SDCC_2                    41
  54 #define SM8650_MASTER_SDCC_4                    42
  55 #define SM8650_MASTER_SNOC_SF_MEM_NOC           43
  56 #define SM8650_MASTER_SP                        44
  57 #define SM8650_MASTER_SYS_TCU                   45
  58 #define SM8650_MASTER_UBWC_P                    46
  59 #define SM8650_MASTER_UBWC_P_TCU                47
  60 #define SM8650_MASTER_UFS_MEM                   48
  61 #define SM8650_MASTER_USB3_0                    49
  62 #define SM8650_MASTER_VIDEO                     50
  63 #define SM8650_MASTER_VIDEO_CV_PROC             51
  64 #define SM8650_MASTER_VIDEO_PROC                52
  65 #define SM8650_MASTER_VIDEO_V_PROC              53
  66 #define SM8650_SLAVE_A1NOC_SNOC                 54
  67 #define SM8650_SLAVE_A2NOC_SNOC                 55
  68 #define SM8650_SLAVE_AHB2PHY_NORTH              56
  69 #define SM8650_SLAVE_AHB2PHY_SOUTH              57
  70 #define SM8650_SLAVE_ANOC_PCIE_GEM_NOC          58
  71 #define SM8650_SLAVE_AOSS                       59
  72 #define SM8650_SLAVE_APPSS                      60
  73 #define SM8650_SLAVE_CAMERA_CFG                 61
  74 #define SM8650_SLAVE_CDSP_MEM_NOC               62
  75 #define SM8650_SLAVE_CLK_CTL                    63
  76 #define SM8650_SLAVE_CNOC_CFG                   64
  77 #define SM8650_SLAVE_CNOC_MNOC_CFG              65
  78 #define SM8650_SLAVE_CNOC_MSS                   66
  79 #define SM8650_SLAVE_CPR_HMX                    67
  80 #define SM8650_SLAVE_CPR_NSPCX                  68
  81 #define SM8650_SLAVE_CRYPTO_0_CFG               69
  82 #define SM8650_SLAVE_CX_RDPM                    70
  83 #define SM8650_SLAVE_DDRSS_CFG                  71
  84 #define SM8650_SLAVE_DISPLAY_CFG                72
  85 #define SM8650_SLAVE_EBI1                       73
  86 #define SM8650_SLAVE_GEM_NOC_CNOC               74
  87 #define SM8650_SLAVE_GFX3D_CFG                  75
  88 #define SM8650_SLAVE_I2C                        76
  89 #define SM8650_SLAVE_I3C_IBI0_CFG               77
  90 #define SM8650_SLAVE_I3C_IBI1_CFG               78
  91 #define SM8650_SLAVE_IMEM                       79
  92 #define SM8650_SLAVE_IMEM_CFG                   80
  93 #define SM8650_SLAVE_IPA_CFG                    81
  94 #define SM8650_SLAVE_IPC_ROUTER_CFG             82
  95 #define SM8650_SLAVE_LLCC                       83
  96 #define SM8650_SLAVE_LPASS_GEM_NOC              84
  97 #define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC    85
  98 #define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC       86
  99 #define SM8650_SLAVE_MEM_NOC_PCIE_SNOC          87
 100 #define SM8650_SLAVE_MNOC_HF_MEM_NOC            88
 101 #define SM8650_SLAVE_MNOC_SF_MEM_NOC            89
 102 #define SM8650_SLAVE_MX_2_RDPM                  90
 103 #define SM8650_SLAVE_MX_RDPM                    91
 104 #define SM8650_SLAVE_NSP_QTB_CFG                92
 105 #define SM8650_SLAVE_PCIE_0                     93
 106 #define SM8650_SLAVE_PCIE_1                     94
 107 #define SM8650_SLAVE_PCIE_0_CFG                 95
 108 #define SM8650_SLAVE_PCIE_1_CFG                 96
 109 #define SM8650_SLAVE_PCIE_ANOC_CFG              97
 110 #define SM8650_SLAVE_PCIE_RSCC                  98
 111 #define SM8650_SLAVE_PDM                        99
 112 #define SM8650_SLAVE_PRNG                       100
 113 #define SM8650_SLAVE_QDSS_CFG                   101
 114 #define SM8650_SLAVE_QDSS_STM                   102
 115 #define SM8650_SLAVE_QSPI_0                     103
 116 #define SM8650_SLAVE_QUP_1                      104
 117 #define SM8650_SLAVE_QUP_2                      105
 118 #define SM8650_SLAVE_QUP_3                      106
 119 #define SM8650_SLAVE_QUP_CORE_0                 107
 120 #define SM8650_SLAVE_QUP_CORE_1                 108
 121 #define SM8650_SLAVE_QUP_CORE_2                 109
 122 #define SM8650_SLAVE_RBCPR_CX_CFG               110
 123 #define SM8650_SLAVE_RBCPR_MMCX_CFG             111
 124 #define SM8650_SLAVE_RBCPR_MXA_CFG              112
 125 #define SM8650_SLAVE_RBCPR_MXC_CFG              113
 126 #define SM8650_SLAVE_SDCC_2                     114
 127 #define SM8650_SLAVE_SDCC_4                     115
 128 #define SM8650_SLAVE_SERVICE_CNOC               116
 129 #define SM8650_SLAVE_SERVICE_CNOC_CFG           117
 130 #define SM8650_SLAVE_SERVICE_MNOC               118
 131 #define SM8650_SLAVE_SERVICE_PCIE_ANOC          119
 132 #define SM8650_SLAVE_SNOC_GEM_NOC_SF            120
 133 #define SM8650_SLAVE_SPSS_CFG                   121
 134 #define SM8650_SLAVE_TCSR                       122
 135 #define SM8650_SLAVE_TCU                        123
 136 #define SM8650_SLAVE_TLMM                       124
 137 #define SM8650_SLAVE_TME_CFG                    125
 138 #define SM8650_SLAVE_UFS_MEM_CFG                126
 139 #define SM8650_SLAVE_USB3_0                     127
 140 #define SM8650_SLAVE_VENUS_CFG                  128
 141 #define SM8650_SLAVE_VSENSE_CTRL_CFG            129
 142
 143 #endif