drivers/infiniband/hw/bnxt_re/qplib_sp.c

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: Slow Path Operators
  37  */
  38
  39 #define dev_fmt(fmt) "QPLIB: " fmt
  40
  41 #include <linux/interrupt.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/sched.h>
  44 #include <linux/pci.h>
  45
  46 #include "roce_hsi.h"
  47
  48 #include "qplib_res.h"
  49 #include "qplib_rcfw.h"
  50 #include "qplib_sp.h"
  51 #include "qplib_tlv.h"
  52
  53 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0,
  54                                                      0, 0, 0, 0, 0, 0, 0, 0 } };
  55
  56 /* Device */
  57
  58 static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw)
  59 {
  60         u16 pcie_ctl2 = 0;
  61
  62         if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx))
  63                 return false;
  64
  65         pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2);
  66         return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ);
  67 }
  68
  69 static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw,
  70                                      char *fw_ver)
  71 {
  72         struct creq_query_version_resp resp = {};
  73         struct bnxt_qplib_cmdqmsg msg = {};
  74         struct cmdq_query_version req = {};
  75         int rc;
  76
  77         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
  78                                  CMDQ_BASE_OPCODE_QUERY_VERSION,
  79                                  sizeof(req));
  80
  81         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), sizeof(resp), 0);
  82         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
  83         if (rc)
  84                 return;
  85         fw_ver[0] = resp.fw_maj;
  86         fw_ver[1] = resp.fw_minor;
  87         fw_ver[2] = resp.fw_bld;
  88         fw_ver[3] = resp.fw_rsvd;
  89 }
  90
  91 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw)
  92 {
  93         struct bnxt_qplib_dev_attr *attr = rcfw->res->dattr;
  94         struct creq_query_func_resp resp = {};
  95         struct bnxt_qplib_cmdqmsg msg = {};
  96         struct creq_query_func_resp_sb *sb;
  97         struct bnxt_qplib_rcfw_sbuf sbuf;
  98         struct bnxt_qplib_chip_ctx *cctx;
  99         struct cmdq_query_func req = {};
 100         u8 *tqm_alloc;
 101         int i, rc;
 102         u32 temp;
 103
 104         cctx = rcfw->res->cctx;
 105         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 106                                  CMDQ_BASE_OPCODE_QUERY_FUNC,
 107                                  sizeof(req));
 108
 109         sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS);
 110         sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size,
 111                                      &sbuf.dma_addr, GFP_KERNEL);
 112         if (!sbuf.sb)
 113                 return -ENOMEM;
 114         sb = sbuf.sb;
 115         req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS;
 116         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req),
 117                                 sizeof(resp), 0);
 118         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 119         if (rc)
 120                 goto bail;
 121
 122         /* Extract the context from the side buffer */
 123         attr->max_qp = le32_to_cpu(sb->max_qp);
 124         /* max_qp value reported by FW doesn't include the QP1 */
 125         attr->max_qp += 1;
 126         attr->max_qp_rd_atom =
 127                 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ?
 128                 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom;
 129         attr->max_qp_init_rd_atom =
 130                 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ?
 131                 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom;
 132         attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr) - 1;
 133         if (!bnxt_qplib_is_chip_gen_p5_p7(rcfw->res->cctx)) {
 134                 /*
 135                  * 128 WQEs needs to be reserved for the HW (8916). Prevent
 136                  * reporting the max number on legacy devices
 137                  */
 138                 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS + 1;
 139         }
 140
 141         /* Adjust for max_qp_wqes for variable wqe */
 142         if (cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE)
 143                 attr->max_qp_wqes = BNXT_VAR_MAX_WQE - 1;
 144
 145         attr->max_qp_sges = cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE ?
 146                             min_t(u32, sb->max_sge_var_wqe, BNXT_VAR_MAX_SGE) : 6;
 147         attr->max_cq = le32_to_cpu(sb->max_cq);
 148         attr->max_cq_wqes = le32_to_cpu(sb->max_cqe);
 149         if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx))
 150                 attr->max_cq_wqes = min_t(u32, BNXT_QPLIB_MAX_CQ_WQES, attr->max_cq_wqes);
 151         attr->max_cq_sges = attr->max_qp_sges;
 152         attr->max_mr = le32_to_cpu(sb->max_mr);
 153         attr->max_mw = le32_to_cpu(sb->max_mw);
 154
 155         attr->max_mr_size = le64_to_cpu(sb->max_mr_size);
 156         attr->max_pd = 64 * 1024;
 157         attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp);
 158         attr->max_ah = le32_to_cpu(sb->max_ah);
 159
 160         attr->max_srq = le16_to_cpu(sb->max_srq);
 161         attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1;
 162         attr->max_srq_sges = sb->max_srq_sge;
 163         attr->max_pkey = 1;
 164         attr->max_inline_data = le32_to_cpu(sb->max_inline_data);
 165         if (!bnxt_qplib_is_chip_gen_p7(rcfw->res->cctx))
 166                 attr->l2_db_size = (sb->l2_db_space_size + 1) *
 167                                     (0x01 << RCFW_DBR_BASE_PAGE_SHIFT);
 168         /*
 169          * Read the max gid supported by HW.
 170          * For each entry in HW  GID in HW table, we consume 2
 171          * GID entries in the kernel GID table.  So max_gid reported
 172          * to stack can be up to twice the value reported by the HW, up to 256 gids.
 173          */
 174         attr->max_sgid = le32_to_cpu(sb->max_gid);
 175         attr->max_sgid = min_t(u32, BNXT_QPLIB_NUM_GIDS_SUPPORTED, 2 * attr->max_sgid);
 176         attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags);
 177         attr->dev_cap_flags2 = le16_to_cpu(sb->dev_cap_ext_flags_2);
 178
 179         bnxt_qplib_query_version(rcfw, attr->fw_ver);
 180
 181         for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) {
 182                 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]);
 183                 tqm_alloc = (u8 *)&temp;
 184                 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc;
 185                 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc);
 186                 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc);
 187                 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc);
 188         }
 189
 190         if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_DEV_ATTR_MAX_DPI)
 191                 attr->max_dpi = le32_to_cpu(sb->max_dpi);
 192
 193         attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw);
 194 bail:
 195         dma_free_coherent(&rcfw->pdev->dev, sbuf.size,
 196                           sbuf.sb, sbuf.dma_addr);
 197         return rc;
 198 }
 199
 200 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res,
 201                                   struct bnxt_qplib_rcfw *rcfw,
 202                                   struct bnxt_qplib_ctx *ctx)
 203 {
 204         struct creq_set_func_resources_resp resp = {};
 205         struct cmdq_set_func_resources req = {};
 206         struct bnxt_qplib_cmdqmsg msg = {};
 207         int rc;
 208
 209         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 210                                  CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES,
 211                                  sizeof(req));
 212
 213         req.number_of_qp = cpu_to_le32(ctx->qpc_count);
 214         req.number_of_mrw = cpu_to_le32(ctx->mrw_count);
 215         req.number_of_srq =  cpu_to_le32(ctx->srqc_count);
 216         req.number_of_cq = cpu_to_le32(ctx->cq_count);
 217
 218         req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf);
 219         req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf);
 220         req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf);
 221         req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf);
 222         req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf);
 223
 224         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
 225                                 sizeof(resp), 0);
 226         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 227         if (rc) {
 228                 dev_err(&res->pdev->dev, "Failed to set function resources\n");
 229         }
 230         return rc;
 231 }
 232
 233 /* SGID */
 234 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res,
 235                         struct bnxt_qplib_sgid_tbl *sgid_tbl, int index,
 236                         struct bnxt_qplib_gid *gid)
 237 {
 238         if (index >= sgid_tbl->max) {
 239                 dev_err(&res->pdev->dev,
 240                         "Index %d exceeded SGID table max (%d)\n",
 241                         index, sgid_tbl->max);
 242                 return -EINVAL;
 243         }
 244         memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid));
 245         return 0;
 246 }
 247
 248 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
 249                         struct bnxt_qplib_gid *gid, u16 vlan_id, bool update)
 250 {
 251         struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl,
 252                                                    struct bnxt_qplib_res,
 253                                                    sgid_tbl);
 254         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
 255         int index;
 256
 257         /* Do we need a sgid_lock here? */
 258         if (!sgid_tbl->active) {
 259                 dev_err(&res->pdev->dev, "SGID table has no active entries\n");
 260                 return -ENOMEM;
 261         }
 262         for (index = 0; index < sgid_tbl->max; index++) {
 263                 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) &&
 264                     vlan_id == sgid_tbl->tbl[index].vlan_id)
 265                         break;
 266         }
 267         if (index == sgid_tbl->max) {
 268                 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n");
 269                 return 0;
 270         }
 271         /* Remove GID from the SGID table */
 272         if (update) {
 273                 struct creq_delete_gid_resp resp = {};
 274                 struct bnxt_qplib_cmdqmsg msg = {};
 275                 struct cmdq_delete_gid req = {};
 276                 int rc;
 277
 278                 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 279                                          CMDQ_BASE_OPCODE_DELETE_GID,
 280                                          sizeof(req));
 281                 if (sgid_tbl->hw_id[index] == 0xFFFF) {
 282                         dev_err(&res->pdev->dev,
 283                                 "GID entry contains an invalid HW id\n");
 284                         return -EINVAL;
 285                 }
 286                 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]);
 287                 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
 288                                         sizeof(resp), 0);
 289                 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 290                 if (rc)
 291                         return rc;
 292         }
 293         memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero,
 294                sizeof(bnxt_qplib_gid_zero));
 295         sgid_tbl->tbl[index].vlan_id = 0xFFFF;
 296         sgid_tbl->vlan[index] = 0;
 297         sgid_tbl->active--;
 298         dev_dbg(&res->pdev->dev,
 299                 "SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n",
 300                  index, sgid_tbl->hw_id[index], sgid_tbl->active);
 301         sgid_tbl->hw_id[index] = (u16)-1;
 302
 303         /* unlock */
 304         return 0;
 305 }
 306
 307 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
 308                         struct bnxt_qplib_gid *gid, const u8 *smac,
 309                         u16 vlan_id, bool update, u32 *index)
 310 {
 311         struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl,
 312                                                    struct bnxt_qplib_res,
 313                                                    sgid_tbl);
 314         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
 315         int i, free_idx;
 316
 317         /* Do we need a sgid_lock here? */
 318         if (sgid_tbl->active == sgid_tbl->max) {
 319                 dev_err(&res->pdev->dev, "SGID table is full\n");
 320                 return -ENOMEM;
 321         }
 322         free_idx = sgid_tbl->max;
 323         for (i = 0; i < sgid_tbl->max; i++) {
 324                 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) &&
 325                     sgid_tbl->tbl[i].vlan_id == vlan_id) {
 326                         dev_dbg(&res->pdev->dev,
 327                                 "SGID entry already exist in entry %d!\n", i);
 328                         *index = i;
 329                         return -EALREADY;
 330                 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero,
 331                                    sizeof(bnxt_qplib_gid_zero)) &&
 332                            free_idx == sgid_tbl->max) {
 333                         free_idx = i;
 334                 }
 335         }
 336         if (free_idx == sgid_tbl->max) {
 337                 dev_err(&res->pdev->dev,
 338                         "SGID table is FULL but count is not MAX??\n");
 339                 return -ENOMEM;
 340         }
 341         if (update) {
 342                 struct creq_add_gid_resp resp = {};
 343                 struct bnxt_qplib_cmdqmsg msg = {};
 344                 struct cmdq_add_gid req = {};
 345                 int rc;
 346
 347                 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 348                                          CMDQ_BASE_OPCODE_ADD_GID,
 349                                          sizeof(req));
 350
 351                 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]);
 352                 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]);
 353                 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]);
 354                 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]);
 355                 /*
 356                  * driver should ensure that all RoCE traffic is always VLAN
 357                  * tagged if RoCE traffic is running on non-zero VLAN ID or
 358                  * RoCE traffic is running on non-zero Priority.
 359                  */
 360                 if ((vlan_id != 0xFFFF) || res->prio) {
 361                         if (vlan_id != 0xFFFF)
 362                                 req.vlan = cpu_to_le16
 363                                 (vlan_id & CMDQ_ADD_GID_VLAN_VLAN_ID_MASK);
 364                         req.vlan |= cpu_to_le16
 365                                         (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 |
 366                                          CMDQ_ADD_GID_VLAN_VLAN_EN);
 367                 }
 368
 369                 /* MAC in network format */
 370                 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]);
 371                 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]);
 372                 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]);
 373
 374                 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
 375                                         sizeof(resp), 0);
 376                 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 377                 if (rc)
 378                         return rc;
 379                 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid);
 380         }
 381         /* Add GID to the sgid_tbl */
 382         memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid));
 383         sgid_tbl->tbl[free_idx].vlan_id = vlan_id;
 384         sgid_tbl->active++;
 385         if (vlan_id != 0xFFFF)
 386                 sgid_tbl->vlan[free_idx] = 1;
 387
 388         dev_dbg(&res->pdev->dev,
 389                 "SGID added hw_id[0x%x] = 0x%x active = 0x%x\n",
 390                  free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active);
 391
 392         *index = free_idx;
 393         /* unlock */
 394         return 0;
 395 }
 396
 397 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
 398                            struct bnxt_qplib_gid *gid, u16 gid_idx,
 399                            const u8 *smac)
 400 {
 401         struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl,
 402                                                    struct bnxt_qplib_res,
 403                                                    sgid_tbl);
 404         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
 405         struct creq_modify_gid_resp resp = {};
 406         struct bnxt_qplib_cmdqmsg msg = {};
 407         struct cmdq_modify_gid req = {};
 408         int rc;
 409
 410         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 411                                  CMDQ_BASE_OPCODE_MODIFY_GID,
 412                                  sizeof(req));
 413
 414         req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]);
 415         req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]);
 416         req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]);
 417         req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]);
 418         if (res->prio) {
 419                 req.vlan |= cpu_to_le16
 420                         (CMDQ_ADD_GID_VLAN_TPID_TPID_8100 |
 421                          CMDQ_ADD_GID_VLAN_VLAN_EN);
 422         }
 423
 424         /* MAC in network format */
 425         req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]);
 426         req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]);
 427         req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]);
 428
 429         req.gid_index = cpu_to_le16(gid_idx);
 430
 431         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
 432                                 sizeof(resp), 0);
 433         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 434         return rc;
 435 }
 436
 437 /* AH */
 438 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,
 439                          bool block)
 440 {
 441         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
 442         struct creq_create_ah_resp resp = {};
 443         struct bnxt_qplib_cmdqmsg msg = {};
 444         struct cmdq_create_ah req = {};
 445         u32 temp32[4];
 446         u16 temp16[3];
 447         int rc;
 448
 449         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 450                                  CMDQ_BASE_OPCODE_CREATE_AH,
 451                                  sizeof(req));
 452
 453         memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid));
 454         req.dgid[0] = cpu_to_le32(temp32[0]);
 455         req.dgid[1] = cpu_to_le32(temp32[1]);
 456         req.dgid[2] = cpu_to_le32(temp32[2]);
 457         req.dgid[3] = cpu_to_le32(temp32[3]);
 458
 459         req.type = ah->nw_type;
 460         req.hop_limit = ah->hop_limit;
 461         req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]);
 462         req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label &
 463                                         CMDQ_CREATE_AH_FLOW_LABEL_MASK) |
 464                                         CMDQ_CREATE_AH_DEST_VLAN_ID_MASK);
 465         req.pd_id = cpu_to_le32(ah->pd->id);
 466         req.traffic_class = ah->traffic_class;
 467
 468         /* MAC in network format */
 469         memcpy(temp16, ah->dmac, 6);
 470         req.dest_mac[0] = cpu_to_le16(temp16[0]);
 471         req.dest_mac[1] = cpu_to_le16(temp16[1]);
 472         req.dest_mac[2] = cpu_to_le16(temp16[2]);
 473
 474         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
 475                                 sizeof(resp), block);
 476         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 477         if (rc)
 478                 return rc;
 479
 480         ah->id = le32_to_cpu(resp.xid);
 481         return 0;
 482 }
 483
 484 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah,
 485                           bool block)
 486 {
 487         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
 488         struct creq_destroy_ah_resp resp = {};
 489         struct bnxt_qplib_cmdqmsg msg = {};
 490         struct cmdq_destroy_ah req = {};
 491         int rc;
 492
 493         /* Clean up the AH table in the device */
 494         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 495                                  CMDQ_BASE_OPCODE_DESTROY_AH,
 496                                  sizeof(req));
 497
 498         req.ah_cid = cpu_to_le32(ah->id);
 499
 500         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
 501                                 sizeof(resp), block);
 502         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 503         return rc;
 504 }
 505
 506 /* MRW */
 507 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw)
 508 {
 509         struct creq_deallocate_key_resp resp = {};
 510         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
 511         struct cmdq_deallocate_key req = {};
 512         struct bnxt_qplib_cmdqmsg msg = {};
 513         int rc;
 514
 515         if (mrw->lkey == 0xFFFFFFFF) {
 516                 dev_info(&res->pdev->dev, "SP: Free a reserved lkey MRW\n");
 517                 return 0;
 518         }
 519
 520         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 521                                  CMDQ_BASE_OPCODE_DEALLOCATE_KEY,
 522                                  sizeof(req));
 523
 524         req.mrw_flags = mrw->type;
 525
 526         if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1)  ||
 527             (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) ||
 528             (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B))
 529                 req.key = cpu_to_le32(mrw->rkey);
 530         else
 531                 req.key = cpu_to_le32(mrw->lkey);
 532
 533         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
 534                                 sizeof(resp), 0);
 535         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 536         if (rc)
 537                 return rc;
 538
 539         /* Free the qplib's MRW memory */
 540         if (mrw->hwq.max_elements)
 541                 bnxt_qplib_free_hwq(res, &mrw->hwq);
 542
 543         return 0;
 544 }
 545
 546 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw)
 547 {
 548         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
 549         struct creq_allocate_mrw_resp resp = {};
 550         struct bnxt_qplib_cmdqmsg msg = {};
 551         struct cmdq_allocate_mrw req = {};
 552         unsigned long tmp;
 553         int rc;
 554
 555         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 556                                  CMDQ_BASE_OPCODE_ALLOCATE_MRW,
 557                                  sizeof(req));
 558
 559         req.pd_id = cpu_to_le32(mrw->pd->id);
 560         req.mrw_flags = mrw->type;
 561         if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR &&
 562              mrw->access_flags & BNXT_QPLIB_FR_PMR) ||
 563             mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A ||
 564             mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)
 565                 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY;
 566         tmp = (unsigned long)mrw;
 567         req.mrw_handle = cpu_to_le64(tmp);
 568
 569         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
 570                                 sizeof(resp), 0);
 571         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 572         if (rc)
 573                 return rc;
 574
 575         if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1)  ||
 576             (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) ||
 577             (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B))
 578                 mrw->rkey = le32_to_cpu(resp.xid);
 579         else
 580                 mrw->lkey = le32_to_cpu(resp.xid);
 581         return 0;
 582 }
 583
 584 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw,
 585                          bool block)
 586 {
 587         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
 588         struct creq_deregister_mr_resp resp = {};
 589         struct bnxt_qplib_cmdqmsg msg = {};
 590         struct cmdq_deregister_mr req = {};
 591         int rc;
 592
 593         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 594                                  CMDQ_BASE_OPCODE_DEREGISTER_MR,
 595                                  sizeof(req));
 596
 597         req.lkey = cpu_to_le32(mrw->lkey);
 598         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
 599                                 sizeof(resp), block);
 600         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 601         if (rc)
 602                 return rc;
 603
 604         /* Free the qplib's MR memory */
 605         if (mrw->hwq.max_elements) {
 606                 mrw->va = 0;
 607                 mrw->total_size = 0;
 608                 bnxt_qplib_free_hwq(res, &mrw->hwq);
 609         }
 610
 611         return 0;
 612 }
 613
 614 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr,
 615                       struct ib_umem *umem, int num_pbls, u32 buf_pg_size)
 616 {
 617         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
 618         struct bnxt_qplib_hwq_attr hwq_attr = {};
 619         struct bnxt_qplib_sg_info sginfo = {};
 620         struct creq_register_mr_resp resp = {};
 621         struct bnxt_qplib_cmdqmsg msg = {};
 622         struct cmdq_register_mr req = {};
 623         int pages, rc;
 624         u32 pg_size;
 625         u16 level;
 626
 627         if (num_pbls) {
 628                 pages = roundup_pow_of_two(num_pbls);
 629                 /* Allocate memory for the non-leaf pages to store buf ptrs.
 630                  * Non-leaf pages always uses system PAGE_SIZE
 631                  */
 632                 /* Free the hwq if it already exist, must be a rereg */
 633                 if (mr->hwq.max_elements)
 634                         bnxt_qplib_free_hwq(res, &mr->hwq);
 635                 hwq_attr.res = res;
 636                 hwq_attr.depth = pages;
 637                 hwq_attr.stride = sizeof(dma_addr_t);
 638                 hwq_attr.type = HWQ_TYPE_MR;
 639                 hwq_attr.sginfo = &sginfo;
 640                 hwq_attr.sginfo->umem = umem;
 641                 hwq_attr.sginfo->npages = pages;
 642                 hwq_attr.sginfo->pgsize = buf_pg_size;
 643                 hwq_attr.sginfo->pgshft = ilog2(buf_pg_size);
 644                 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr);
 645                 if (rc) {
 646                         dev_err(&res->pdev->dev,
 647                                 "SP: Reg MR memory allocation failed\n");
 648                         return -ENOMEM;
 649                 }
 650         }
 651
 652         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 653                                  CMDQ_BASE_OPCODE_REGISTER_MR,
 654                                  sizeof(req));
 655
 656         /* Configure the request */
 657         if (mr->hwq.level == PBL_LVL_MAX) {
 658                 /* No PBL provided, just use system PAGE_SIZE */
 659                 level = 0;
 660                 req.pbl = 0;
 661                 pg_size = PAGE_SIZE;
 662         } else {
 663                 level = mr->hwq.level;
 664                 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]);
 665         }
 666         pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE;
 667         req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) |
 668                                ((ilog2(pg_size) <<
 669                                  CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) &
 670                                 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK);
 671         req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) <<
 672                                  CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) &
 673                                 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK));
 674         req.access = (mr->access_flags & 0xFFFF);
 675         req.va = cpu_to_le64(mr->va);
 676         req.key = cpu_to_le32(mr->lkey);
 677         if (_is_alloc_mr_unified(res->dattr->dev_cap_flags))
 678                 req.key = cpu_to_le32(mr->pd->id);
 679         req.flags = cpu_to_le16(mr->flags);
 680         req.mr_size = cpu_to_le64(mr->total_size);
 681
 682         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req),
 683                                 sizeof(resp), 0);
 684         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 685         if (rc)
 686                 goto fail;
 687
 688         if (_is_alloc_mr_unified(res->dattr->dev_cap_flags)) {
 689                 mr->lkey = le32_to_cpu(resp.xid);
 690                 mr->rkey = mr->lkey;
 691         }
 692
 693         return 0;
 694
 695 fail:
 696         if (mr->hwq.max_elements)
 697                 bnxt_qplib_free_hwq(res, &mr->hwq);
 698         return rc;
 699 }
 700
 701 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res,
 702                                         struct bnxt_qplib_frpl *frpl,
 703                                         int max_pg_ptrs)
 704 {
 705         struct bnxt_qplib_hwq_attr hwq_attr = {};
 706         struct bnxt_qplib_sg_info sginfo = {};
 707         int pg_ptrs, pages, rc;
 708
 709         /* Re-calculate the max to fit the HWQ allocation model */
 710         pg_ptrs = roundup_pow_of_two(max_pg_ptrs);
 711         pages = pg_ptrs >> MAX_PBL_LVL_1_PGS_SHIFT;
 712         if (!pages)
 713                 pages++;
 714
 715         if (pages > MAX_PBL_LVL_1_PGS)
 716                 return -ENOMEM;
 717
 718         sginfo.pgsize = PAGE_SIZE;
 719         sginfo.nopte = true;
 720
 721         hwq_attr.res = res;
 722         hwq_attr.depth = pg_ptrs;
 723         hwq_attr.stride = PAGE_SIZE;
 724         hwq_attr.sginfo = &sginfo;
 725         hwq_attr.type = HWQ_TYPE_CTX;
 726         rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr);
 727         if (!rc)
 728                 frpl->max_pg_ptrs = pg_ptrs;
 729
 730         return rc;
 731 }
 732
 733 int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res,
 734                                        struct bnxt_qplib_frpl *frpl)
 735 {
 736         bnxt_qplib_free_hwq(res, &frpl->hwq);
 737         return 0;
 738 }
 739
 740 int bnxt_qplib_get_roce_stats(struct bnxt_qplib_rcfw *rcfw,
 741                               struct bnxt_qplib_roce_stats *stats)
 742 {
 743         struct creq_query_roce_stats_resp resp = {};
 744         struct creq_query_roce_stats_resp_sb *sb;
 745         struct cmdq_query_roce_stats req = {};
 746         struct bnxt_qplib_cmdqmsg msg = {};
 747         struct bnxt_qplib_rcfw_sbuf sbuf;
 748         int rc;
 749
 750         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 751                                  CMDQ_BASE_OPCODE_QUERY_ROCE_STATS,
 752                                  sizeof(req));
 753
 754         sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS);
 755         sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size,
 756                                      &sbuf.dma_addr, GFP_KERNEL);
 757         if (!sbuf.sb)
 758                 return -ENOMEM;
 759         sb = sbuf.sb;
 760
 761         req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS;
 762         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req),
 763                                 sizeof(resp), 0);
 764         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 765         if (rc)
 766                 goto bail;
 767         /* Extract the context from the side buffer */
 768         stats->to_retransmits = le64_to_cpu(sb->to_retransmits);
 769         stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd);
 770         stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded);
 771         stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd);
 772         stats->missing_resp = le64_to_cpu(sb->missing_resp);
 773         stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err);
 774         stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err);
 775         stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err);
 776         stats->local_protection_err = le64_to_cpu(sb->local_protection_err);
 777         stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err);
 778         stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err);
 779         stats->remote_access_err = le64_to_cpu(sb->remote_access_err);
 780         stats->remote_op_err = le64_to_cpu(sb->remote_op_err);
 781         stats->dup_req = le64_to_cpu(sb->dup_req);
 782         stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max);
 783         stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch);
 784         stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe);
 785         stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err);
 786         stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey);
 787         stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err);
 788         stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm);
 789         stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err);
 790         stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey);
 791         stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err);
 792         stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm);
 793         stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err);
 794         stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow);
 795         stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode);
 796         stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic);
 797         stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err);
 798         stats->res_mem_error = le64_to_cpu(sb->res_mem_error);
 799         stats->res_srq_err = le64_to_cpu(sb->res_srq_err);
 800         stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err);
 801         stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey);
 802         stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err);
 803         stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err);
 804         stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err);
 805         stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err);
 806         stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err);
 807         if (!rcfw->init_oos_stats) {
 808                 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count);
 809                 rcfw->init_oos_stats = 1;
 810         } else {
 811                 stats->res_oos_drop_count +=
 812                                 (le64_to_cpu(sb->res_oos_drop_count) -
 813                                  rcfw->oos_prev) & BNXT_QPLIB_OOS_COUNT_MASK;
 814                 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count);
 815         }
 816
 817 bail:
 818         dma_free_coherent(&rcfw->pdev->dev, sbuf.size,
 819                           sbuf.sb, sbuf.dma_addr);
 820         return rc;
 821 }
 822
 823 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid,
 824                          struct bnxt_qplib_ext_stat *estat)
 825 {
 826         struct creq_query_roce_stats_ext_resp resp = {};
 827         struct creq_query_roce_stats_ext_resp_sb *sb;
 828         struct cmdq_query_roce_stats_ext req = {};
 829         struct bnxt_qplib_cmdqmsg msg = {};
 830         struct bnxt_qplib_rcfw_sbuf sbuf;
 831         int rc;
 832
 833         sbuf.size = ALIGN(sizeof(*sb), BNXT_QPLIB_CMDQE_UNITS);
 834         sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size,
 835                                      &sbuf.dma_addr, GFP_KERNEL);
 836         if (!sbuf.sb)
 837                 return -ENOMEM;
 838
 839         sb = sbuf.sb;
 840         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
 841                                  CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS,
 842                                  sizeof(req));
 843
 844         req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS;
 845         req.resp_addr = cpu_to_le64(sbuf.dma_addr);
 846         req.function_id = cpu_to_le32(fid);
 847         req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID);
 848
 849         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req),
 850                                 sizeof(resp), 0);
 851         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
 852         if (rc)
 853                 goto bail;
 854
 855         estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts);
 856         estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts);
 857         estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts);
 858         estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts);
 859         estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts);
 860         estat->tx_roce_pkts = le64_to_cpu(sb->tx_roce_pkts);
 861         estat->tx_roce_bytes = le64_to_cpu(sb->tx_roce_bytes);
 862         estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts);
 863         estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts);
 864         estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts);
 865         estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts);
 866         estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts);
 867         estat->rx_roce_pkts = le64_to_cpu(sb->rx_roce_pkts);
 868         estat->rx_roce_bytes = le64_to_cpu(sb->rx_roce_bytes);
 869         estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts);
 870         estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes);
 871         estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts);
 872         estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts);
 873         estat->tx_cnp = le64_to_cpu(sb->tx_cnp_pkts);
 874         estat->rx_cnp = le64_to_cpu(sb->rx_cnp_pkts);
 875         estat->rx_ecn_marked = le64_to_cpu(sb->rx_ecn_marked_pkts);
 876
 877 bail:
 878         dma_free_coherent(&rcfw->pdev->dev, sbuf.size,
 879                           sbuf.sb, sbuf.dma_addr);
 880         return rc;
 881 }
 882
 883 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req,
 884                                     struct bnxt_qplib_cc_param_ext *cc_ext)
 885 {
 886         ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask);
 887         cc_ext->ext_mask = 0;
 888         ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi);
 889         ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp);
 890         ext_req->init_cp = cpu_to_le16(cc_ext->init_cp);
 891         ext_req->tr_update_mode = cc_ext->tr_update_mode;
 892         ext_req->tr_update_cycles = cc_ext->tr_update_cyls;
 893         ext_req->fr_num_rtts = cc_ext->fr_rtt;
 894         ext_req->ai_rate_increase = cc_ext->ai_rate_incr;
 895         ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th);
 896         ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th);
 897         ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th);
 898         ext_req->bw_avg_weight = cc_ext->bw_avg_weight;
 899         ext_req->actual_cr_factor = cc_ext->cr_factor;
 900         ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp);
 901         ext_req->cp_bias_en = cc_ext->cp_bias_en;
 902         ext_req->cp_bias = cc_ext->cp_bias;
 903         ext_req->cnp_ecn = cc_ext->cnp_ecn;
 904         ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en;
 905         ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec);
 906         ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th);
 907         ext_req->cr_width = cc_ext->cr_width;
 908         ext_req->quota_period_min = cc_ext->min_quota;
 909         ext_req->quota_period_max = cc_ext->max_quota;
 910         ext_req->quota_period_abs_max = cc_ext->abs_max_quota;
 911         ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb);
 912         ext_req->cr_prob_factor = cc_ext->cr_prob_fac;
 913         ext_req->tr_prob_factor = cc_ext->tr_prob_fac;
 914         ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th);
 915         ext_req->red_div = cc_ext->red_div;
 916         ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th;
 917         ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt);
 918         ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio;
 919         ext_req->use_rate_table = cc_ext->low_rate_en;
 920         ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th);
 921         ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1);
 922         ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2);
 923         ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th);
 924         ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1);
 925         ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2);
 926         ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt);
 927         ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes;
 928 }
 929
 930 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res,
 931                          struct bnxt_qplib_cc_param *cc_param)
 932 {
 933         struct bnxt_qplib_tlv_modify_cc_req tlv_req = {};
 934         struct creq_modify_roce_cc_resp resp = {};
 935         struct bnxt_qplib_cmdqmsg msg = {};
 936         struct cmdq_modify_roce_cc *req;
 937         int req_size;
 938         void *cmd;
 939         int rc;
 940
 941         /* Prepare the older base command */
 942         req = &tlv_req.base_req;
 943         cmd = req;
 944         req_size = sizeof(*req);
 945         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC,
 946                                  sizeof(*req));
 947         req->modify_mask = cpu_to_le32(cc_param->mask);
 948         req->enable_cc = cc_param->enable;
 949         req->g = cc_param->g;
 950         req->num_phases_per_state = cc_param->nph_per_state;
 951         req->time_per_phase = cc_param->time_pph;
 952         req->pkts_per_phase = cc_param->pkts_pph;
 953         req->init_cr = cpu_to_le16(cc_param->init_cr);
 954         req->init_tr = cpu_to_le16(cc_param->init_tr);
 955         req->tos_dscp_tos_ecn = (cc_param->tos_dscp << CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) |
 956                                 (cc_param->tos_ecn & CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK);
 957         req->alt_vlan_pcp = cc_param->alt_vlan_pcp;
 958         req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp);
 959         req->rtt = cpu_to_le16(cc_param->rtt);
 960         req->tcp_cp = cpu_to_le16(cc_param->tcp_cp);
 961         req->cc_mode = cc_param->cc_mode;
 962         req->inactivity_th = cpu_to_le16(cc_param->inact_th);
 963
 964         /* For chip gen P5 onwards fill extended cmd and header */
 965         if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) {
 966                 struct roce_tlv *hdr;
 967                 u32 payload;
 968                 u32 chunks;
 969
 970                 cmd = &tlv_req;
 971                 req_size = sizeof(tlv_req);
 972                 /* Prepare primary tlv header */
 973                 hdr = &tlv_req.tlv_hdr;
 974                 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req));
 975                 payload = sizeof(struct cmdq_modify_roce_cc);
 976                 __roce_1st_tlv_prep(hdr, chunks, payload, true);
 977                 /* Prepare secondary tlv header */
 978                 hdr = (struct roce_tlv *)&tlv_req.ext_req;
 979                 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) -
 980                           sizeof(struct roce_tlv);
 981                 __roce_ext_tlv_prep(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, false, true);
 982                 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext);
 983         }
 984
 985         bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size,
 986                                 sizeof(resp), 0);
 987         rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg);
 988         return rc;
 989 }
 990
 991 int bnxt_qplib_read_context(struct bnxt_qplib_rcfw *rcfw, u8 res_type,
 992                             u32 xid, u32 resp_size, void *resp_va)
 993 {
 994         struct creq_read_context resp = {};
 995         struct bnxt_qplib_cmdqmsg msg = {};
 996         struct cmdq_read_context req = {};
 997         struct bnxt_qplib_rcfw_sbuf sbuf;
 998         int rc;
 999
1000         sbuf.size = resp_size;
1001         sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size,
1002                                      &sbuf.dma_addr, GFP_KERNEL);
1003         if (!sbuf.sb)
1004                 return -ENOMEM;
1005
1006         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
1007                                  CMDQ_BASE_OPCODE_READ_CONTEXT, sizeof(req));
1008         req.resp_addr = cpu_to_le64(sbuf.dma_addr);
1009         req.resp_size = resp_size / BNXT_QPLIB_CMDQE_UNITS;
1010
1011         req.xid = cpu_to_le32(xid);
1012         req.type = res_type;
1013
1014         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req),
1015                                 sizeof(resp), 0);
1016         rc = bnxt_qplib_rcfw_send_message(rcfw, &msg);
1017         if (rc)
1018                 goto free_mem;
1019
1020         memcpy(resp_va, sbuf.sb, resp_size);
1021 free_mem:
1022         dma_free_coherent(&rcfw->pdev->dev, sbuf.size, sbuf.sb, sbuf.dma_addr);
1023         return rc;
1024 }
1025
1026 static void bnxt_qplib_read_cc_gen1(struct bnxt_qplib_cc_param_ext *cc_ext,
1027                                     struct creq_query_roce_cc_gen1_resp_sb_tlv *sb)
1028 {
1029         cc_ext->inact_th_hi = le16_to_cpu(sb->inactivity_th_hi);
1030         cc_ext->min_delta_cnp = le16_to_cpu(sb->min_time_between_cnps);
1031         cc_ext->init_cp = le16_to_cpu(sb->init_cp);
1032         cc_ext->tr_update_mode = sb->tr_update_mode;
1033         cc_ext->tr_update_cyls = sb->tr_update_cycles;
1034         cc_ext->fr_rtt = sb->fr_num_rtts;
1035         cc_ext->ai_rate_incr = sb->ai_rate_increase;
1036         cc_ext->rr_rtt_th = le16_to_cpu(sb->reduction_relax_rtts_th);
1037         cc_ext->ar_cr_th = le16_to_cpu(sb->additional_relax_cr_th);
1038         cc_ext->cr_min_th = le16_to_cpu(sb->cr_min_th);
1039         cc_ext->bw_avg_weight = sb->bw_avg_weight;
1040         cc_ext->cr_factor = sb->actual_cr_factor;
1041         cc_ext->cr_th_max_cp = le16_to_cpu(sb->max_cp_cr_th);
1042         cc_ext->cp_bias_en = sb->cp_bias_en;
1043         cc_ext->cp_bias = sb->cp_bias;
1044         cc_ext->cnp_ecn = sb->cnp_ecn;
1045         cc_ext->rtt_jitter_en = sb->rtt_jitter_en;
1046         cc_ext->bytes_per_usec = le16_to_cpu(sb->link_bytes_per_usec);
1047         cc_ext->cc_cr_reset_th = le16_to_cpu(sb->reset_cc_cr_th);
1048         cc_ext->cr_width = sb->cr_width;
1049         cc_ext->min_quota = sb->quota_period_min;
1050         cc_ext->max_quota = sb->quota_period_max;
1051         cc_ext->abs_max_quota = sb->quota_period_abs_max;
1052         cc_ext->tr_lb = le16_to_cpu(sb->tr_lower_bound);
1053         cc_ext->cr_prob_fac = sb->cr_prob_factor;
1054         cc_ext->tr_prob_fac = sb->tr_prob_factor;
1055         cc_ext->fair_cr_th = le16_to_cpu(sb->fairness_cr_th);
1056         cc_ext->red_div = sb->red_div;
1057         cc_ext->cnp_ratio_th = sb->cnp_ratio_th;
1058         cc_ext->ai_ext_rtt = le16_to_cpu(sb->exp_ai_rtts);
1059         cc_ext->exp_crcp_ratio = sb->exp_ai_cr_cp_ratio;
1060         cc_ext->low_rate_en = sb->use_rate_table;
1061         cc_ext->cpcr_update_th = le16_to_cpu(sb->cp_exp_update_th);
1062         cc_ext->ai_rtt_th1 = le16_to_cpu(sb->high_exp_ai_rtts_th1);
1063         cc_ext->ai_rtt_th2 = le16_to_cpu(sb->high_exp_ai_rtts_th2);
1064         cc_ext->cf_rtt_th = le16_to_cpu(sb->actual_cr_cong_free_rtts_th);
1065         cc_ext->sc_cr_th1 = le16_to_cpu(sb->severe_cong_cr_th1);
1066         cc_ext->sc_cr_th2 = le16_to_cpu(sb->severe_cong_cr_th2);
1067         cc_ext->l64B_per_rtt = le32_to_cpu(sb->link64B_per_rtt);
1068         cc_ext->cc_ack_bytes = sb->cc_ack_bytes;
1069         cc_ext->reduce_cf_rtt_th = le16_to_cpu(sb->reduce_init_cong_free_rtts_th);
1070 }
1071
1072 int bnxt_qplib_query_cc_param(struct bnxt_qplib_res *res,
1073                               struct bnxt_qplib_cc_param *cc_param)
1074 {
1075         struct bnxt_qplib_tlv_query_rcc_sb *ext_sb;
1076         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
1077         struct creq_query_roce_cc_resp resp = {};
1078         struct creq_query_roce_cc_resp_sb *sb;
1079         struct bnxt_qplib_cmdqmsg msg = {};
1080         struct cmdq_query_roce_cc req = {};
1081         struct bnxt_qplib_rcfw_sbuf sbuf;
1082         size_t resp_size;
1083         int rc;
1084
1085         /* Query the parameters from chip */
1086         bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, CMDQ_BASE_OPCODE_QUERY_ROCE_CC,
1087                                  sizeof(req));
1088         if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx))
1089                 resp_size = sizeof(*ext_sb);
1090         else
1091                 resp_size = sizeof(*sb);
1092
1093         sbuf.size = ALIGN(resp_size, BNXT_QPLIB_CMDQE_UNITS);
1094         sbuf.sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf.size,
1095                                      &sbuf.dma_addr, GFP_KERNEL);
1096         if (!sbuf.sb)
1097                 return -ENOMEM;
1098
1099         req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS;
1100         bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req),
1101                                 sizeof(resp), 0);
1102         rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg);
1103         if (rc)
1104                 goto out;
1105
1106         ext_sb = sbuf.sb;
1107         sb = bnxt_qplib_is_chip_gen_p5_p7(res->cctx) ? &ext_sb->base_sb :
1108                 (struct creq_query_roce_cc_resp_sb *)ext_sb;
1109
1110         cc_param->enable = sb->enable_cc & CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC;
1111         cc_param->tos_ecn = (sb->tos_dscp_tos_ecn &
1112                              CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK) >>
1113                             CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT;
1114         cc_param->tos_dscp = (sb->tos_dscp_tos_ecn &
1115                               CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK) >>
1116                              CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT;
1117         cc_param->alt_tos_dscp = sb->alt_tos_dscp;
1118         cc_param->alt_vlan_pcp = sb->alt_vlan_pcp;
1119
1120         cc_param->g = sb->g;
1121         cc_param->nph_per_state = sb->num_phases_per_state;
1122         cc_param->init_cr = le16_to_cpu(sb->init_cr);
1123         cc_param->init_tr = le16_to_cpu(sb->init_tr);
1124         cc_param->cc_mode = sb->cc_mode;
1125         cc_param->inact_th = le16_to_cpu(sb->inactivity_th);
1126         cc_param->rtt = le16_to_cpu(sb->rtt);
1127         cc_param->tcp_cp = le16_to_cpu(sb->tcp_cp);
1128         cc_param->time_pph = sb->time_per_phase;
1129         cc_param->pkts_pph = sb->pkts_per_phase;
1130         if (bnxt_qplib_is_chip_gen_p5_p7(res->cctx)) {
1131                 bnxt_qplib_read_cc_gen1(&cc_param->cc_ext, &ext_sb->gen1_sb);
1132                 cc_param->inact_th |= (cc_param->cc_ext.inact_th_hi & 0x3F) << 16;
1133         }
1134 out:
1135         dma_free_coherent(&rcfw->pdev->dev, sbuf.size, sbuf.sb, sbuf.dma_addr);
1136         return rc;
1137 }