drivers/i2c/busses/i2c-qcom-geni.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/clk.h>
   6 #include <linux/dmaengine.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/dma/qcom-gpi-dma.h>
   9 #include <linux/err.h>
  10 #include <linux/i2c.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/soc/qcom/geni-se.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/units.h>
  20
  21 #define SE_I2C_TX_TRANS_LEN             0x26c
  22 #define SE_I2C_RX_TRANS_LEN             0x270
  23 #define SE_I2C_SCL_COUNTERS             0x278
  24
  25 #define SE_I2C_ERR  (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
  26                         M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
  27 #define SE_I2C_ABORT            BIT(1)
  28
  29 /* M_CMD OP codes for I2C */
  30 #define I2C_WRITE               0x1
  31 #define I2C_READ                0x2
  32 #define I2C_WRITE_READ          0x3
  33 #define I2C_ADDR_ONLY           0x4
  34 #define I2C_BUS_CLEAR           0x6
  35 #define I2C_STOP_ON_BUS         0x7
  36 /* M_CMD params for I2C */
  37 #define PRE_CMD_DELAY           BIT(0)
  38 #define TIMESTAMP_BEFORE        BIT(1)
  39 #define STOP_STRETCH            BIT(2)
  40 #define TIMESTAMP_AFTER         BIT(3)
  41 #define POST_COMMAND_DELAY      BIT(4)
  42 #define IGNORE_ADD_NACK         BIT(6)
  43 #define READ_FINISHED_WITH_ACK  BIT(7)
  44 #define BYPASS_ADDR_PHASE       BIT(8)
  45 #define SLV_ADDR_MSK            GENMASK(15, 9)
  46 #define SLV_ADDR_SHFT           9
  47 /* I2C SCL COUNTER fields */
  48 #define HIGH_COUNTER_MSK        GENMASK(29, 20)
  49 #define HIGH_COUNTER_SHFT       20
  50 #define LOW_COUNTER_MSK         GENMASK(19, 10)
  51 #define LOW_COUNTER_SHFT        10
  52 #define CYCLE_COUNTER_MSK       GENMASK(9, 0)
  53
  54 #define I2C_PACK_TX             BIT(0)
  55 #define I2C_PACK_RX             BIT(1)
  56
  57 enum geni_i2c_err_code {
  58         GP_IRQ0,
  59         NACK,
  60         GP_IRQ2,
  61         BUS_PROTO,
  62         ARB_LOST,
  63         GP_IRQ5,
  64         GENI_OVERRUN,
  65         GENI_ILLEGAL_CMD,
  66         GENI_ABORT_DONE,
  67         GENI_TIMEOUT,
  68 };
  69
  70 #define DM_I2C_CB_ERR           ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
  71                                                                         << 5)
  72
  73 #define I2C_AUTO_SUSPEND_DELAY  250
  74 #define KHZ(freq)               (1000 * freq)
  75 #define PACKING_BYTES_PW        4
  76
  77 #define ABORT_TIMEOUT           HZ
  78 #define XFER_TIMEOUT            HZ
  79 #define RST_TIMEOUT             HZ
  80
  81 struct geni_i2c_dev {
  82         struct geni_se se;
  83         u32 tx_wm;
  84         int irq;
  85         int err;
  86         struct i2c_adapter adap;
  87         struct completion done;
  88         struct i2c_msg *cur;
  89         int cur_wr;
  90         int cur_rd;
  91         spinlock_t lock;
  92         struct clk *core_clk;
  93         u32 clk_freq_out;
  94         const struct geni_i2c_clk_fld *clk_fld;
  95         int suspended;
  96         void *dma_buf;
  97         size_t xfer_len;
  98         dma_addr_t dma_addr;
  99         struct dma_chan *tx_c;
 100         struct dma_chan *rx_c;
 101         bool gpi_mode;
 102         bool abort_done;
 103 };
 104
 105 struct geni_i2c_desc {
 106         bool has_core_clk;
 107         char *icc_ddr;
 108         bool no_dma_support;
 109         unsigned int tx_fifo_depth;
 110 };
 111
 112 struct geni_i2c_err_log {
 113         int err;
 114         const char *msg;
 115 };
 116
 117 static const struct geni_i2c_err_log gi2c_log[] = {
 118         [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
 119         [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
 120         [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
 121         [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"},
 122         [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
 123         [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
 124         [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
 125         [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
 126         [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
 127         [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
 128 };
 129
 130 struct geni_i2c_clk_fld {
 131         u32     clk_freq_out;
 132         u8      clk_div;
 133         u8      t_high_cnt;
 134         u8      t_low_cnt;
 135         u8      t_cycle_cnt;
 136 };
 137
 138 /*
 139  * Hardware uses the underlying formula to calculate time periods of
 140  * SCL clock cycle. Firmware uses some additional cycles excluded from the
 141  * below formula and it is confirmed that the time periods are within
 142  * specification limits.
 143  *
 144  * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
 145  * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
 146  * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
 147  * clk_freq_out = t / t_cycle
 148  * source_clock = 19.2 MHz
 149  */
 150 static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = {
 151         {KHZ(100), 7, 10, 11, 26},
 152         {KHZ(400), 2,  5, 12, 24},
 153         {KHZ(1000), 1, 3,  9, 18},
 154         {},
 155 };
 156
 157 /* source_clock = 32 MHz */
 158 static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
 159         {KHZ(100), 8, 14, 18, 40},
 160         {KHZ(400), 4,  3, 11, 20},
 161         {KHZ(1000), 2, 3,  6, 15},
 162         {},
 163 };
 164
 165 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
 166 {
 167         const struct geni_i2c_clk_fld *itr;
 168
 169         if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ)
 170                 itr = geni_i2c_clk_map_32mhz;
 171         else
 172                 itr = geni_i2c_clk_map_19p2mhz;
 173
 174         while (itr->clk_freq_out != 0) {
 175                 if (itr->clk_freq_out == gi2c->clk_freq_out) {
 176                         gi2c->clk_fld = itr;
 177                         return 0;
 178                 }
 179                 itr++;
 180         }
 181         return -EINVAL;
 182 }
 183
 184 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
 185 {
 186         const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
 187         u32 val;
 188
 189         writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
 190
 191         val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
 192         writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
 193
 194         val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
 195         val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
 196         val |= itr->t_cycle_cnt;
 197         writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
 198 }
 199
 200 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
 201 {
 202         u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
 203         u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
 204         u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
 205         u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
 206         u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
 207         u32 rx_st, tx_st;
 208
 209         if (dma) {
 210                 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
 211                 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
 212         } else {
 213                 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
 214                 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
 215         }
 216         dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
 217                 dma, tx_st, rx_st, m_stat);
 218         dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
 219                 m_cmd, geni_s, geni_ios);
 220 }
 221
 222 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
 223 {
 224         if (!gi2c->err)
 225                 gi2c->err = gi2c_log[err].err;
 226         if (gi2c->cur)
 227                 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
 228                         gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
 229
 230         switch (err) {
 231         case GENI_ABORT_DONE:
 232                 gi2c->abort_done = true;
 233                 break;
 234         case NACK:
 235         case GENI_TIMEOUT:
 236                 dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
 237                 break;
 238         default:
 239                 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
 240                 geni_i2c_err_misc(gi2c);
 241                 break;
 242         }
 243 }
 244
 245 static irqreturn_t geni_i2c_irq(int irq, void *dev)
 246 {
 247         struct geni_i2c_dev *gi2c = dev;
 248         void __iomem *base = gi2c->se.base;
 249         int j, p;
 250         u32 m_stat;
 251         u32 rx_st;
 252         u32 dm_tx_st;
 253         u32 dm_rx_st;
 254         u32 dma;
 255         u32 val;
 256         struct i2c_msg *cur;
 257
 258         spin_lock(&gi2c->lock);
 259         m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
 260         rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
 261         dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
 262         dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
 263         dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
 264         cur = gi2c->cur;
 265
 266         if (!cur ||
 267             m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
 268             dm_rx_st & (DM_I2C_CB_ERR)) {
 269                 if (m_stat & M_GP_IRQ_1_EN)
 270                         geni_i2c_err(gi2c, NACK);
 271                 if (m_stat & M_GP_IRQ_3_EN)
 272                         geni_i2c_err(gi2c, BUS_PROTO);
 273                 if (m_stat & M_GP_IRQ_4_EN)
 274                         geni_i2c_err(gi2c, ARB_LOST);
 275                 if (m_stat & M_CMD_OVERRUN_EN)
 276                         geni_i2c_err(gi2c, GENI_OVERRUN);
 277                 if (m_stat & M_ILLEGAL_CMD_EN)
 278                         geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
 279                 if (m_stat & M_CMD_ABORT_EN)
 280                         geni_i2c_err(gi2c, GENI_ABORT_DONE);
 281                 if (m_stat & M_GP_IRQ_0_EN)
 282                         geni_i2c_err(gi2c, GP_IRQ0);
 283
 284                 /* Disable the TX Watermark interrupt to stop TX */
 285                 if (!dma)
 286                         writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
 287         } else if (dma) {
 288                 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
 289                         dm_tx_st, dm_rx_st);
 290         } else if (cur->flags & I2C_M_RD &&
 291                    m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
 292                 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
 293
 294                 for (j = 0; j < rxcnt; j++) {
 295                         p = 0;
 296                         val = readl_relaxed(base + SE_GENI_RX_FIFOn);
 297                         while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
 298                                 cur->buf[gi2c->cur_rd++] = val & 0xff;
 299                                 val >>= 8;
 300                                 p++;
 301                         }
 302                         if (gi2c->cur_rd == cur->len)
 303                                 break;
 304                 }
 305         } else if (!(cur->flags & I2C_M_RD) &&
 306                    m_stat & M_TX_FIFO_WATERMARK_EN) {
 307                 for (j = 0; j < gi2c->tx_wm; j++) {
 308                         u32 temp;
 309
 310                         val = 0;
 311                         p = 0;
 312                         while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
 313                                 temp = cur->buf[gi2c->cur_wr++];
 314                                 val |= temp << (p * 8);
 315                                 p++;
 316                         }
 317                         writel_relaxed(val, base + SE_GENI_TX_FIFOn);
 318                         /* TX Complete, Disable the TX Watermark interrupt */
 319                         if (gi2c->cur_wr == cur->len) {
 320                                 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
 321                                 break;
 322                         }
 323                 }
 324         }
 325
 326         if (m_stat)
 327                 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
 328
 329         if (dma && dm_tx_st)
 330                 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
 331         if (dma && dm_rx_st)
 332                 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
 333
 334         /* if this is err with done-bit not set, handle that through timeout. */
 335         if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
 336             dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
 337             dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
 338                 complete(&gi2c->done);
 339
 340         spin_unlock(&gi2c->lock);
 341
 342         return IRQ_HANDLED;
 343 }
 344
 345 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
 346 {
 347         unsigned long time_left = ABORT_TIMEOUT;
 348         unsigned long flags;
 349
 350         spin_lock_irqsave(&gi2c->lock, flags);
 351         geni_i2c_err(gi2c, GENI_TIMEOUT);
 352         gi2c->cur = NULL;
 353         gi2c->abort_done = false;
 354         geni_se_abort_m_cmd(&gi2c->se);
 355         spin_unlock_irqrestore(&gi2c->lock, flags);
 356
 357         do {
 358                 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
 359         } while (!gi2c->abort_done && time_left);
 360
 361         if (!time_left)
 362                 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
 363 }
 364
 365 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
 366 {
 367         u32 val;
 368         unsigned long time_left = RST_TIMEOUT;
 369
 370         writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
 371         do {
 372                 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
 373                 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
 374         } while (!(val & RX_RESET_DONE) && time_left);
 375
 376         if (!(val & RX_RESET_DONE))
 377                 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
 378 }
 379
 380 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
 381 {
 382         u32 val;
 383         unsigned long time_left = RST_TIMEOUT;
 384
 385         writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
 386         do {
 387                 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
 388                 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
 389         } while (!(val & TX_RESET_DONE) && time_left);
 390
 391         if (!(val & TX_RESET_DONE))
 392                 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
 393 }
 394
 395 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c,
 396                                      struct i2c_msg *cur)
 397 {
 398         gi2c->cur_rd = 0;
 399         if (gi2c->dma_buf) {
 400                 if (gi2c->err)
 401                         geni_i2c_rx_fsm_rst(gi2c);
 402                 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
 403                 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
 404         }
 405 }
 406
 407 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c,
 408                                      struct i2c_msg *cur)
 409 {
 410         gi2c->cur_wr = 0;
 411         if (gi2c->dma_buf) {
 412                 if (gi2c->err)
 413                         geni_i2c_tx_fsm_rst(gi2c);
 414                 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
 415                 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
 416         }
 417 }
 418
 419 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
 420                                 u32 m_param)
 421 {
 422         dma_addr_t rx_dma = 0;
 423         unsigned long time_left;
 424         void *dma_buf;
 425         struct geni_se *se = &gi2c->se;
 426         size_t len = msg->len;
 427         struct i2c_msg *cur;
 428
 429         dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
 430         if (dma_buf)
 431                 geni_se_select_mode(se, GENI_SE_DMA);
 432         else
 433                 geni_se_select_mode(se, GENI_SE_FIFO);
 434
 435         writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
 436         geni_se_setup_m_cmd(se, I2C_READ, m_param);
 437
 438         if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
 439                 geni_se_select_mode(se, GENI_SE_FIFO);
 440                 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
 441                 dma_buf = NULL;
 442         } else {
 443                 gi2c->xfer_len = len;
 444                 gi2c->dma_addr = rx_dma;
 445                 gi2c->dma_buf = dma_buf;
 446         }
 447
 448         cur = gi2c->cur;
 449         time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
 450         if (!time_left)
 451                 geni_i2c_abort_xfer(gi2c);
 452
 453         geni_i2c_rx_msg_cleanup(gi2c, cur);
 454
 455         return gi2c->err;
 456 }
 457
 458 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
 459                                 u32 m_param)
 460 {
 461         dma_addr_t tx_dma = 0;
 462         unsigned long time_left;
 463         void *dma_buf;
 464         struct geni_se *se = &gi2c->se;
 465         size_t len = msg->len;
 466         struct i2c_msg *cur;
 467
 468         dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
 469         if (dma_buf)
 470                 geni_se_select_mode(se, GENI_SE_DMA);
 471         else
 472                 geni_se_select_mode(se, GENI_SE_FIFO);
 473
 474         writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
 475         geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
 476
 477         if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
 478                 geni_se_select_mode(se, GENI_SE_FIFO);
 479                 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
 480                 dma_buf = NULL;
 481         } else {
 482                 gi2c->xfer_len = len;
 483                 gi2c->dma_addr = tx_dma;
 484                 gi2c->dma_buf = dma_buf;
 485         }
 486
 487         if (!dma_buf) /* Get FIFO IRQ */
 488                 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
 489
 490         cur = gi2c->cur;
 491         time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
 492         if (!time_left)
 493                 geni_i2c_abort_xfer(gi2c);
 494
 495         geni_i2c_tx_msg_cleanup(gi2c, cur);
 496
 497         return gi2c->err;
 498 }
 499
 500 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result)
 501 {
 502         struct geni_i2c_dev *gi2c = cb;
 503
 504         if (result->result != DMA_TRANS_NOERROR) {
 505                 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result);
 506                 gi2c->err = -EIO;
 507         } else if (result->residue) {
 508                 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue);
 509         }
 510
 511         complete(&gi2c->done);
 512 }
 513
 514 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
 515                                void *tx_buf, dma_addr_t tx_addr,
 516                                void *rx_buf, dma_addr_t rx_addr)
 517 {
 518         if (tx_buf) {
 519                 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE);
 520                 i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err);
 521         }
 522
 523         if (rx_buf) {
 524                 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE);
 525                 i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err);
 526         }
 527 }
 528
 529 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
 530                         struct dma_slave_config *config, dma_addr_t *dma_addr_p,
 531                         void **buf, unsigned int op, struct dma_chan *dma_chan)
 532 {
 533         struct gpi_i2c_config *peripheral;
 534         unsigned int flags;
 535         void *dma_buf;
 536         dma_addr_t addr;
 537         enum dma_data_direction map_dirn;
 538         enum dma_transfer_direction dma_dirn;
 539         struct dma_async_tx_descriptor *desc;
 540         int ret;
 541
 542         peripheral = config->peripheral_config;
 543
 544         dma_buf = i2c_get_dma_safe_msg_buf(msg, 1);
 545         if (!dma_buf)
 546                 return -ENOMEM;
 547
 548         if (op == I2C_WRITE)
 549                 map_dirn = DMA_TO_DEVICE;
 550         else
 551                 map_dirn = DMA_FROM_DEVICE;
 552
 553         addr = dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn);
 554         if (dma_mapping_error(gi2c->se.dev->parent, addr)) {
 555                 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
 556                 return -ENOMEM;
 557         }
 558
 559         /* set the length as message for rx txn */
 560         peripheral->rx_len = msg->len;
 561         peripheral->op = op;
 562
 563         ret = dmaengine_slave_config(dma_chan, config);
 564         if (ret) {
 565                 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op);
 566                 goto err_config;
 567         }
 568
 569         peripheral->set_config = 0;
 570         peripheral->multi_msg = true;
 571         flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
 572
 573         if (op == I2C_WRITE)
 574                 dma_dirn = DMA_MEM_TO_DEV;
 575         else
 576                 dma_dirn = DMA_DEV_TO_MEM;
 577
 578         desc = dmaengine_prep_slave_single(dma_chan, addr, msg->len, dma_dirn, flags);
 579         if (!desc) {
 580                 dev_err(gi2c->se.dev, "prep_slave_sg failed\n");
 581                 ret = -EIO;
 582                 goto err_config;
 583         }
 584
 585         desc->callback_result = i2c_gpi_cb_result;
 586         desc->callback_param = gi2c;
 587
 588         dmaengine_submit(desc);
 589         *buf = dma_buf;
 590         *dma_addr_p = addr;
 591
 592         return 0;
 593
 594 err_config:
 595         dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn);
 596         i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
 597         return ret;
 598 }
 599
 600 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num)
 601 {
 602         struct dma_slave_config config = {};
 603         struct gpi_i2c_config peripheral = {};
 604         int i, ret = 0;
 605         unsigned long time_left;
 606         dma_addr_t tx_addr, rx_addr;
 607         void *tx_buf = NULL, *rx_buf = NULL;
 608         const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
 609
 610         config.peripheral_config = &peripheral;
 611         config.peripheral_size = sizeof(peripheral);
 612
 613         peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX;
 614         peripheral.cycle_count = itr->t_cycle_cnt;
 615         peripheral.high_count = itr->t_high_cnt;
 616         peripheral.low_count = itr->t_low_cnt;
 617         peripheral.clk_div = itr->clk_div;
 618         peripheral.set_config = 1;
 619         peripheral.multi_msg = false;
 620
 621         for (i = 0; i < num; i++) {
 622                 gi2c->cur = &msgs[i];
 623                 gi2c->err = 0;
 624                 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len);
 625
 626                 peripheral.stretch = 0;
 627                 if (i < num - 1)
 628                         peripheral.stretch = 1;
 629
 630                 peripheral.addr = msgs[i].addr;
 631
 632                 ret =  geni_i2c_gpi(gi2c, &msgs[i], &config,
 633                                     &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c);
 634                 if (ret)
 635                         goto err;
 636
 637                 if (msgs[i].flags & I2C_M_RD) {
 638                         ret =  geni_i2c_gpi(gi2c, &msgs[i], &config,
 639                                             &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c);
 640                         if (ret)
 641                                 goto err;
 642
 643                         dma_async_issue_pending(gi2c->rx_c);
 644                 }
 645
 646                 dma_async_issue_pending(gi2c->tx_c);
 647
 648                 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
 649                 if (!time_left)
 650                         gi2c->err = -ETIMEDOUT;
 651
 652                 if (gi2c->err) {
 653                         ret = gi2c->err;
 654                         goto err;
 655                 }
 656
 657                 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
 658         }
 659
 660         return num;
 661
 662 err:
 663         dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret);
 664         dmaengine_terminate_sync(gi2c->rx_c);
 665         dmaengine_terminate_sync(gi2c->tx_c);
 666         geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
 667         return ret;
 668 }
 669
 670 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c,
 671                               struct i2c_msg msgs[], int num)
 672 {
 673         int i, ret = 0;
 674
 675         for (i = 0; i < num; i++) {
 676                 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
 677
 678                 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
 679
 680                 gi2c->cur = &msgs[i];
 681                 if (msgs[i].flags & I2C_M_RD)
 682                         ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
 683                 else
 684                         ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
 685
 686                 if (ret)
 687                         return ret;
 688         }
 689
 690         return num;
 691 }
 692
 693 static int geni_i2c_xfer(struct i2c_adapter *adap,
 694                          struct i2c_msg msgs[],
 695                          int num)
 696 {
 697         struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
 698         int ret;
 699
 700         gi2c->err = 0;
 701         reinit_completion(&gi2c->done);
 702         ret = pm_runtime_get_sync(gi2c->se.dev);
 703         if (ret < 0) {
 704                 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
 705                 pm_runtime_put_noidle(gi2c->se.dev);
 706                 /* Set device in suspended since resume failed */
 707                 pm_runtime_set_suspended(gi2c->se.dev);
 708                 return ret;
 709         }
 710
 711         qcom_geni_i2c_conf(gi2c);
 712
 713         if (gi2c->gpi_mode)
 714                 ret = geni_i2c_gpi_xfer(gi2c, msgs, num);
 715         else
 716                 ret = geni_i2c_fifo_xfer(gi2c, msgs, num);
 717
 718         pm_runtime_mark_last_busy(gi2c->se.dev);
 719         pm_runtime_put_autosuspend(gi2c->se.dev);
 720         gi2c->cur = NULL;
 721         gi2c->err = 0;
 722         return ret;
 723 }
 724
 725 static u32 geni_i2c_func(struct i2c_adapter *adap)
 726 {
 727         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 728 }
 729
 730 static const struct i2c_algorithm geni_i2c_algo = {
 731         .master_xfer    = geni_i2c_xfer,
 732         .functionality  = geni_i2c_func,
 733 };
 734
 735 #ifdef CONFIG_ACPI
 736 static const struct acpi_device_id geni_i2c_acpi_match[] = {
 737         { "QCOM0220"},
 738         { "QCOM0411" },
 739         { }
 740 };
 741 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
 742 #endif
 743
 744 static void release_gpi_dma(struct geni_i2c_dev *gi2c)
 745 {
 746         if (gi2c->rx_c)
 747                 dma_release_channel(gi2c->rx_c);
 748
 749         if (gi2c->tx_c)
 750                 dma_release_channel(gi2c->tx_c);
 751 }
 752
 753 static int setup_gpi_dma(struct geni_i2c_dev *gi2c)
 754 {
 755         int ret;
 756
 757         geni_se_select_mode(&gi2c->se, GENI_GPI_DMA);
 758         gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx");
 759         if (IS_ERR(gi2c->tx_c)) {
 760                 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c),
 761                                     "Failed to get tx DMA ch\n");
 762                 goto err_tx;
 763         }
 764
 765         gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx");
 766         if (IS_ERR(gi2c->rx_c)) {
 767                 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c),
 768                                     "Failed to get rx DMA ch\n");
 769                 goto err_rx;
 770         }
 771
 772         dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n");
 773         return 0;
 774
 775 err_rx:
 776         dma_release_channel(gi2c->tx_c);
 777 err_tx:
 778         return ret;
 779 }
 780
 781 static int geni_i2c_probe(struct platform_device *pdev)
 782 {
 783         struct geni_i2c_dev *gi2c;
 784         u32 proto, tx_depth, fifo_disable;
 785         int ret;
 786         struct device *dev = &pdev->dev;
 787         const struct geni_i2c_desc *desc = NULL;
 788
 789         gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
 790         if (!gi2c)
 791                 return -ENOMEM;
 792
 793         gi2c->se.dev = dev;
 794         gi2c->se.wrapper = dev_get_drvdata(dev->parent);
 795         gi2c->se.base = devm_platform_ioremap_resource(pdev, 0);
 796         if (IS_ERR(gi2c->se.base))
 797                 return PTR_ERR(gi2c->se.base);
 798
 799         desc = device_get_match_data(&pdev->dev);
 800
 801         if (desc && desc->has_core_clk) {
 802                 gi2c->core_clk = devm_clk_get(dev, "core");
 803                 if (IS_ERR(gi2c->core_clk))
 804                         return PTR_ERR(gi2c->core_clk);
 805         }
 806
 807         gi2c->se.clk = devm_clk_get(dev, "se");
 808         if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
 809                 return PTR_ERR(gi2c->se.clk);
 810
 811         ret = device_property_read_u32(dev, "clock-frequency",
 812                                        &gi2c->clk_freq_out);
 813         if (ret) {
 814                 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
 815                 gi2c->clk_freq_out = KHZ(100);
 816         }
 817
 818         if (has_acpi_companion(dev))
 819                 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
 820
 821         gi2c->irq = platform_get_irq(pdev, 0);
 822         if (gi2c->irq < 0)
 823                 return gi2c->irq;
 824
 825         ret = geni_i2c_clk_map_idx(gi2c);
 826         if (ret)
 827                 return dev_err_probe(dev, ret, "Invalid clk frequency %d Hz\n",
 828                                      gi2c->clk_freq_out);
 829
 830         gi2c->adap.algo = &geni_i2c_algo;
 831         init_completion(&gi2c->done);
 832         spin_lock_init(&gi2c->lock);
 833         platform_set_drvdata(pdev, gi2c);
 834
 835         /* Keep interrupts disabled initially to allow for low-power modes */
 836         ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN,
 837                                dev_name(dev), gi2c);
 838         if (ret)
 839                 return dev_err_probe(dev, ret,
 840                                      "Request_irq failed: %d\n", gi2c->irq);
 841
 842         i2c_set_adapdata(&gi2c->adap, gi2c);
 843         gi2c->adap.dev.parent = dev;
 844         gi2c->adap.dev.of_node = dev->of_node;
 845         strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
 846
 847         ret = geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory");
 848         if (ret)
 849                 return ret;
 850         /*
 851          * Set the bus quota for core and cpu to a reasonable value for
 852          * register access.
 853          * Set quota for DDR based on bus speed.
 854          */
 855         gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
 856         gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
 857         if (!desc || desc->icc_ddr)
 858                 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
 859
 860         ret = geni_icc_set_bw(&gi2c->se);
 861         if (ret)
 862                 return ret;
 863
 864         ret = clk_prepare_enable(gi2c->core_clk);
 865         if (ret)
 866                 return ret;
 867
 868         ret = geni_se_resources_on(&gi2c->se);
 869         if (ret) {
 870                 dev_err_probe(dev, ret, "Error turning on resources\n");
 871                 goto err_clk;
 872         }
 873         proto = geni_se_read_proto(&gi2c->se);
 874         if (proto != GENI_SE_I2C) {
 875                 ret = dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto);
 876                 goto err_resources;
 877         }
 878
 879         if (desc && desc->no_dma_support)
 880                 fifo_disable = false;
 881         else
 882                 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
 883
 884         if (fifo_disable) {
 885                 /* FIFO is disabled, so we can only use GPI DMA */
 886                 gi2c->gpi_mode = true;
 887                 ret = setup_gpi_dma(gi2c);
 888                 if (ret)
 889                         goto err_resources;
 890
 891                 dev_dbg(dev, "Using GPI DMA mode for I2C\n");
 892         } else {
 893                 gi2c->gpi_mode = false;
 894                 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
 895
 896                 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */
 897                 if (!tx_depth && desc)
 898                         tx_depth = desc->tx_fifo_depth;
 899
 900                 if (!tx_depth) {
 901                         ret = dev_err_probe(dev, -EINVAL,
 902                                             "Invalid TX FIFO depth\n");
 903                         goto err_resources;
 904                 }
 905
 906                 gi2c->tx_wm = tx_depth - 1;
 907                 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
 908                 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE,
 909                                        PACKING_BYTES_PW, true, true, true);
 910
 911                 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
 912         }
 913
 914         clk_disable_unprepare(gi2c->core_clk);
 915         ret = geni_se_resources_off(&gi2c->se);
 916         if (ret) {
 917                 dev_err_probe(dev, ret, "Error turning off resources\n");
 918                 goto err_dma;
 919         }
 920
 921         ret = geni_icc_disable(&gi2c->se);
 922         if (ret)
 923                 goto err_dma;
 924
 925         gi2c->suspended = 1;
 926         pm_runtime_set_suspended(gi2c->se.dev);
 927         pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
 928         pm_runtime_use_autosuspend(gi2c->se.dev);
 929         pm_runtime_enable(gi2c->se.dev);
 930
 931         ret = i2c_add_adapter(&gi2c->adap);
 932         if (ret) {
 933                 dev_err_probe(dev, ret, "Error adding i2c adapter\n");
 934                 pm_runtime_disable(gi2c->se.dev);
 935                 goto err_dma;
 936         }
 937
 938         dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
 939
 940         return ret;
 941
 942 err_resources:
 943         geni_se_resources_off(&gi2c->se);
 944 err_clk:
 945         clk_disable_unprepare(gi2c->core_clk);
 946
 947         return ret;
 948
 949 err_dma:
 950         release_gpi_dma(gi2c);
 951
 952         return ret;
 953 }
 954
 955 static void geni_i2c_remove(struct platform_device *pdev)
 956 {
 957         struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
 958
 959         i2c_del_adapter(&gi2c->adap);
 960         release_gpi_dma(gi2c);
 961         pm_runtime_disable(gi2c->se.dev);
 962 }
 963
 964 static void geni_i2c_shutdown(struct platform_device *pdev)
 965 {
 966         struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
 967
 968         /* Make client i2c transfers start failing */
 969         i2c_mark_adapter_suspended(&gi2c->adap);
 970 }
 971
 972 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
 973 {
 974         int ret;
 975         struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
 976
 977         disable_irq(gi2c->irq);
 978         ret = geni_se_resources_off(&gi2c->se);
 979         if (ret) {
 980                 enable_irq(gi2c->irq);
 981                 return ret;
 982
 983         } else {
 984                 gi2c->suspended = 1;
 985         }
 986
 987         clk_disable_unprepare(gi2c->core_clk);
 988
 989         return geni_icc_disable(&gi2c->se);
 990 }
 991
 992 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
 993 {
 994         int ret;
 995         struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
 996
 997         ret = geni_icc_enable(&gi2c->se);
 998         if (ret)
 999                 return ret;
1000
1001         ret = clk_prepare_enable(gi2c->core_clk);
1002         if (ret)
1003                 goto out_icc_disable;
1004
1005         ret = geni_se_resources_on(&gi2c->se);
1006         if (ret)
1007                 goto out_clk_disable;
1008
1009         enable_irq(gi2c->irq);
1010         gi2c->suspended = 0;
1011
1012         return 0;
1013
1014 out_clk_disable:
1015         clk_disable_unprepare(gi2c->core_clk);
1016 out_icc_disable:
1017         geni_icc_disable(&gi2c->se);
1018
1019         return ret;
1020 }
1021
1022 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
1023 {
1024         struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1025
1026         i2c_mark_adapter_suspended(&gi2c->adap);
1027
1028         if (!gi2c->suspended) {
1029                 geni_i2c_runtime_suspend(dev);
1030                 pm_runtime_disable(dev);
1031                 pm_runtime_set_suspended(dev);
1032                 pm_runtime_enable(dev);
1033         }
1034         return 0;
1035 }
1036
1037 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
1038 {
1039         struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1040
1041         i2c_mark_adapter_resumed(&gi2c->adap);
1042         return 0;
1043 }
1044
1045 static const struct dev_pm_ops geni_i2c_pm_ops = {
1046         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq)
1047         SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
1048                                                                         NULL)
1049 };
1050
1051 static const struct geni_i2c_desc i2c_master_hub = {
1052         .has_core_clk = true,
1053         .icc_ddr = NULL,
1054         .no_dma_support = true,
1055         .tx_fifo_depth = 16,
1056 };
1057
1058 static const struct of_device_id geni_i2c_dt_match[] = {
1059         { .compatible = "qcom,geni-i2c" },
1060         { .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub },
1061         {}
1062 };
1063 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
1064
1065 static struct platform_driver geni_i2c_driver = {
1066         .probe  = geni_i2c_probe,
1067         .remove = geni_i2c_remove,
1068         .shutdown = geni_i2c_shutdown,
1069         .driver = {
1070                 .name = "geni_i2c",
1071                 .pm = &geni_i2c_pm_ops,
1072                 .of_match_table = geni_i2c_dt_match,
1073                 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
1074         },
1075 };
1076
1077 module_platform_driver(geni_i2c_driver);
1078
1079 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
1080 MODULE_LICENSE("GPL v2");