drivers/i2c/busses/i2c-microchip-corei2c.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Microchip CoreI2C I2C controller driver
   4  *
   5  * Copyright (c) 2018-2022 Microchip Corporation. All rights reserved.
   6  *
   7  * Author: Daire McNamara <[email protected]>
   8  * Author: Conor Dooley <[email protected]>
   9  */
  10 #include <linux/clk.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/err.h>
  13 #include <linux/i2c.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19
  20 #define CORE_I2C_CTRL   (0x00)
  21 #define  CTRL_CR0       BIT(0)
  22 #define  CTRL_CR1       BIT(1)
  23 #define  CTRL_AA        BIT(2)
  24 #define  CTRL_SI        BIT(3)
  25 #define  CTRL_STO       BIT(4)
  26 #define  CTRL_STA       BIT(5)
  27 #define  CTRL_ENS1      BIT(6)
  28 #define  CTRL_CR2       BIT(7)
  29
  30 #define STATUS_BUS_ERROR                        (0x00)
  31 #define STATUS_M_START_SENT                     (0x08)
  32 #define STATUS_M_REPEATED_START_SENT            (0x10)
  33 #define STATUS_M_SLAW_ACK                       (0x18)
  34 #define STATUS_M_SLAW_NACK                      (0x20)
  35 #define STATUS_M_TX_DATA_ACK                    (0x28)
  36 #define STATUS_M_TX_DATA_NACK                   (0x30)
  37 #define STATUS_M_ARB_LOST                       (0x38)
  38 #define STATUS_M_SLAR_ACK                       (0x40)
  39 #define STATUS_M_SLAR_NACK                      (0x48)
  40 #define STATUS_M_RX_DATA_ACKED                  (0x50)
  41 #define STATUS_M_RX_DATA_NACKED                 (0x58)
  42 #define STATUS_S_SLAW_ACKED                     (0x60)
  43 #define STATUS_S_ARB_LOST_SLAW_ACKED            (0x68)
  44 #define STATUS_S_GENERAL_CALL_ACKED             (0x70)
  45 #define STATUS_S_ARB_LOST_GENERAL_CALL_ACKED    (0x78)
  46 #define STATUS_S_RX_DATA_ACKED                  (0x80)
  47 #define STATUS_S_RX_DATA_NACKED                 (0x88)
  48 #define STATUS_S_GENERAL_CALL_RX_DATA_ACKED     (0x90)
  49 #define STATUS_S_GENERAL_CALL_RX_DATA_NACKED    (0x98)
  50 #define STATUS_S_RX_STOP                        (0xA0)
  51 #define STATUS_S_SLAR_ACKED                     (0xA8)
  52 #define STATUS_S_ARB_LOST_SLAR_ACKED            (0xB0)
  53 #define STATUS_S_TX_DATA_ACK                    (0xB8)
  54 #define STATUS_S_TX_DATA_NACK                   (0xC0)
  55 #define STATUS_LAST_DATA_ACK                    (0xC8)
  56 #define STATUS_M_SMB_MASTER_RESET               (0xD0)
  57 #define STATUS_S_SCL_LOW_TIMEOUT                (0xD8) /* 25 ms */
  58 #define STATUS_NO_STATE_INFO                    (0xF8)
  59
  60 #define CORE_I2C_STATUS         (0x04)
  61 #define CORE_I2C_DATA           (0x08)
  62 #define WRITE_BIT               (0x0)
  63 #define READ_BIT                (0x1)
  64 #define SLAVE_ADDR_SHIFT        (1)
  65 #define CORE_I2C_SLAVE0_ADDR    (0x0c)
  66 #define GENERAL_CALL_BIT        (0x0)
  67 #define CORE_I2C_SMBUS          (0x10)
  68 #define SMBALERT_INT_ENB        (0x0)
  69 #define SMBSUS_INT_ENB          (0x1)
  70 #define SMBUS_ENB               (0x2)
  71 #define SMBALERT_NI_STATUS      (0x3)
  72 #define SMBALERT_NO_CTRL        (0x4)
  73 #define SMBSUS_NI_STATUS        (0x5)
  74 #define SMBSUS_NO_CTRL          (0x6)
  75 #define SMBUS_RESET             (0x7)
  76 #define CORE_I2C_FREQ           (0x14)
  77 #define CORE_I2C_GLITCHREG      (0x18)
  78 #define CORE_I2C_SLAVE1_ADDR    (0x1c)
  79
  80 #define PCLK_DIV_960    (CTRL_CR2)
  81 #define PCLK_DIV_256    (0)
  82 #define PCLK_DIV_224    (CTRL_CR0)
  83 #define PCLK_DIV_192    (CTRL_CR1)
  84 #define PCLK_DIV_160    (CTRL_CR0 | CTRL_CR1)
  85 #define PCLK_DIV_120    (CTRL_CR0 | CTRL_CR2)
  86 #define PCLK_DIV_60     (CTRL_CR1 | CTRL_CR2)
  87 #define BCLK_DIV_8      (CTRL_CR0 | CTRL_CR1 | CTRL_CR2)
  88 #define CLK_MASK        (CTRL_CR0 | CTRL_CR1 | CTRL_CR2)
  89
  90 /**
  91  * struct mchp_corei2c_dev - Microchip CoreI2C device private data
  92  *
  93  * @base:               pointer to register struct
  94  * @dev:                device reference
  95  * @i2c_clk:            clock reference for i2c input clock
  96  * @msg_queue:          pointer to the messages requiring sending
  97  * @buf:                pointer to msg buffer for easier use
  98  * @msg_complete:       xfer completion object
  99  * @adapter:            core i2c abstraction
 100  * @msg_err:            error code for completed message
 101  * @bus_clk_rate:       current i2c bus clock rate
 102  * @isr_status:         cached copy of local ISR status
 103  * @total_num:          total number of messages to be sent/received
 104  * @current_num:        index of the current message being sent/received
 105  * @msg_len:            number of bytes transferred in msg
 106  * @addr:               address of the current slave
 107  * @restart_needed:     whether or not a repeated start is required after current message
 108  */
 109 struct mchp_corei2c_dev {
 110         void __iomem *base;
 111         struct device *dev;
 112         struct clk *i2c_clk;
 113         struct i2c_msg *msg_queue;
 114         u8 *buf;
 115         struct completion msg_complete;
 116         struct i2c_adapter adapter;
 117         int msg_err;
 118         int total_num;
 119         int current_num;
 120         u32 bus_clk_rate;
 121         u32 isr_status;
 122         u16 msg_len;
 123         u8 addr;
 124         bool restart_needed;
 125 };
 126
 127 static void mchp_corei2c_core_disable(struct mchp_corei2c_dev *idev)
 128 {
 129         u8 ctrl = readb(idev->base + CORE_I2C_CTRL);
 130
 131         ctrl &= ~CTRL_ENS1;
 132         writeb(ctrl, idev->base + CORE_I2C_CTRL);
 133 }
 134
 135 static void mchp_corei2c_core_enable(struct mchp_corei2c_dev *idev)
 136 {
 137         u8 ctrl = readb(idev->base + CORE_I2C_CTRL);
 138
 139         ctrl |= CTRL_ENS1;
 140         writeb(ctrl, idev->base + CORE_I2C_CTRL);
 141 }
 142
 143 static void mchp_corei2c_reset(struct mchp_corei2c_dev *idev)
 144 {
 145         mchp_corei2c_core_disable(idev);
 146         mchp_corei2c_core_enable(idev);
 147 }
 148
 149 static inline void mchp_corei2c_stop(struct mchp_corei2c_dev *idev)
 150 {
 151         u8 ctrl = readb(idev->base + CORE_I2C_CTRL);
 152
 153         ctrl |= CTRL_STO;
 154         writeb(ctrl, idev->base + CORE_I2C_CTRL);
 155 }
 156
 157 static inline int mchp_corei2c_set_divisor(u32 rate,
 158                                            struct mchp_corei2c_dev *idev)
 159 {
 160         u8 clkval, ctrl;
 161
 162         if (rate >= 960)
 163                 clkval = PCLK_DIV_960;
 164         else if (rate >= 256)
 165                 clkval = PCLK_DIV_256;
 166         else if (rate >= 224)
 167                 clkval = PCLK_DIV_224;
 168         else if (rate >= 192)
 169                 clkval = PCLK_DIV_192;
 170         else if (rate >= 160)
 171                 clkval = PCLK_DIV_160;
 172         else if (rate >= 120)
 173                 clkval = PCLK_DIV_120;
 174         else if (rate >= 60)
 175                 clkval = PCLK_DIV_60;
 176         else if (rate >= 8)
 177                 clkval = BCLK_DIV_8;
 178         else
 179                 return -EINVAL;
 180
 181         ctrl = readb(idev->base + CORE_I2C_CTRL);
 182         ctrl &= ~CLK_MASK;
 183         ctrl |= clkval;
 184         writeb(ctrl, idev->base + CORE_I2C_CTRL);
 185
 186         ctrl = readb(idev->base + CORE_I2C_CTRL);
 187         if ((ctrl & CLK_MASK) != clkval)
 188                 return -EIO;
 189
 190         return 0;
 191 }
 192
 193 static int mchp_corei2c_init(struct mchp_corei2c_dev *idev)
 194 {
 195         u32 clk_rate = clk_get_rate(idev->i2c_clk);
 196         u32 divisor = clk_rate / idev->bus_clk_rate;
 197         int ret;
 198
 199         ret = mchp_corei2c_set_divisor(divisor, idev);
 200         if (ret)
 201                 return ret;
 202
 203         mchp_corei2c_reset(idev);
 204
 205         return 0;
 206 }
 207
 208 static void mchp_corei2c_empty_rx(struct mchp_corei2c_dev *idev)
 209 {
 210         u8 ctrl;
 211
 212         if (idev->msg_len > 0) {
 213                 *idev->buf++ = readb(idev->base + CORE_I2C_DATA);
 214                 idev->msg_len--;
 215         }
 216
 217         if (idev->msg_len <= 1) {
 218                 ctrl = readb(idev->base + CORE_I2C_CTRL);
 219                 ctrl &= ~CTRL_AA;
 220                 writeb(ctrl, idev->base + CORE_I2C_CTRL);
 221         }
 222 }
 223
 224 static int mchp_corei2c_fill_tx(struct mchp_corei2c_dev *idev)
 225 {
 226         if (idev->msg_len > 0)
 227                 writeb(*idev->buf++, idev->base + CORE_I2C_DATA);
 228         idev->msg_len--;
 229
 230         return 0;
 231 }
 232
 233 static void mchp_corei2c_next_msg(struct mchp_corei2c_dev *idev)
 234 {
 235         struct i2c_msg *this_msg;
 236         u8 ctrl;
 237
 238         if (idev->current_num >= idev->total_num) {
 239                 complete(&idev->msg_complete);
 240                 return;
 241         }
 242
 243         /*
 244          * If there's been an error, the isr needs to return control
 245          * to the "main" part of the driver, so as not to keep sending
 246          * messages once it completes and clears the SI bit.
 247          */
 248         if (idev->msg_err) {
 249                 complete(&idev->msg_complete);
 250                 return;
 251         }
 252
 253         this_msg = idev->msg_queue++;
 254
 255         if (idev->current_num < (idev->total_num - 1)) {
 256                 struct i2c_msg *next_msg = idev->msg_queue;
 257
 258                 idev->restart_needed = next_msg->flags & I2C_M_RD;
 259         } else {
 260                 idev->restart_needed = false;
 261         }
 262
 263         idev->addr = i2c_8bit_addr_from_msg(this_msg);
 264         idev->msg_len = this_msg->len;
 265         idev->buf = this_msg->buf;
 266
 267         ctrl = readb(idev->base + CORE_I2C_CTRL);
 268         ctrl |= CTRL_STA;
 269         writeb(ctrl, idev->base + CORE_I2C_CTRL);
 270
 271         idev->current_num++;
 272 }
 273
 274 static irqreturn_t mchp_corei2c_handle_isr(struct mchp_corei2c_dev *idev)
 275 {
 276         u32 status = idev->isr_status;
 277         u8 ctrl;
 278         bool last_byte = false, finished = false;
 279
 280         if (!idev->buf)
 281                 return IRQ_NONE;
 282
 283         switch (status) {
 284         case STATUS_M_START_SENT:
 285         case STATUS_M_REPEATED_START_SENT:
 286                 ctrl = readb(idev->base + CORE_I2C_CTRL);
 287                 ctrl &= ~CTRL_STA;
 288                 writeb(idev->addr, idev->base + CORE_I2C_DATA);
 289                 writeb(ctrl, idev->base + CORE_I2C_CTRL);
 290                 break;
 291         case STATUS_M_ARB_LOST:
 292                 idev->msg_err = -EAGAIN;
 293                 finished = true;
 294                 break;
 295         case STATUS_M_SLAW_ACK:
 296         case STATUS_M_TX_DATA_ACK:
 297                 if (idev->msg_len > 0) {
 298                         mchp_corei2c_fill_tx(idev);
 299                 } else {
 300                         if (idev->restart_needed)
 301                                 finished = true;
 302                         else
 303                                 last_byte = true;
 304                 }
 305                 break;
 306         case STATUS_M_TX_DATA_NACK:
 307         case STATUS_M_SLAR_NACK:
 308         case STATUS_M_SLAW_NACK:
 309                 idev->msg_err = -ENXIO;
 310                 last_byte = true;
 311                 break;
 312         case STATUS_M_SLAR_ACK:
 313                 ctrl = readb(idev->base + CORE_I2C_CTRL);
 314                 if (idev->msg_len == 1u) {
 315                         ctrl &= ~CTRL_AA;
 316                         writeb(ctrl, idev->base + CORE_I2C_CTRL);
 317                 } else {
 318                         ctrl |= CTRL_AA;
 319                         writeb(ctrl, idev->base + CORE_I2C_CTRL);
 320                 }
 321                 if (idev->msg_len < 1u)
 322                         last_byte = true;
 323                 break;
 324         case STATUS_M_RX_DATA_ACKED:
 325                 mchp_corei2c_empty_rx(idev);
 326                 break;
 327         case STATUS_M_RX_DATA_NACKED:
 328                 mchp_corei2c_empty_rx(idev);
 329                 if (idev->msg_len == 0)
 330                         last_byte = true;
 331                 break;
 332         default:
 333                 break;
 334         }
 335
 336         /* On the last byte to be transmitted, send STOP */
 337         if (last_byte)
 338                 mchp_corei2c_stop(idev);
 339
 340         if (last_byte || finished)
 341                 mchp_corei2c_next_msg(idev);
 342
 343         return IRQ_HANDLED;
 344 }
 345
 346 static irqreturn_t mchp_corei2c_isr(int irq, void *_dev)
 347 {
 348         struct mchp_corei2c_dev *idev = _dev;
 349         irqreturn_t ret = IRQ_NONE;
 350         u8 ctrl;
 351
 352         ctrl = readb(idev->base + CORE_I2C_CTRL);
 353         if (ctrl & CTRL_SI) {
 354                 idev->isr_status = readb(idev->base + CORE_I2C_STATUS);
 355                 ret = mchp_corei2c_handle_isr(idev);
 356         }
 357
 358         ctrl = readb(idev->base + CORE_I2C_CTRL);
 359         ctrl &= ~CTRL_SI;
 360         writeb(ctrl, idev->base + CORE_I2C_CTRL);
 361
 362         return ret;
 363 }
 364
 365 static int mchp_corei2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 366                              int num)
 367 {
 368         struct mchp_corei2c_dev *idev = i2c_get_adapdata(adap);
 369         struct i2c_msg *this_msg = msgs;
 370         unsigned long time_left;
 371         u8 ctrl;
 372
 373         mchp_corei2c_core_enable(idev);
 374
 375         /*
 376          * The isr controls the flow of a transfer, this info needs to be saved
 377          * to a location that it can access the queue information from.
 378          */
 379         idev->restart_needed = false;
 380         idev->msg_queue = msgs;
 381         idev->total_num = num;
 382         idev->current_num = 0;
 383
 384         /*
 385          * But the first entry to the isr is triggered by the start in this
 386          * function, so the first message needs to be "dequeued".
 387          */
 388         idev->addr = i2c_8bit_addr_from_msg(this_msg);
 389         idev->msg_len = this_msg->len;
 390         idev->buf = this_msg->buf;
 391         idev->msg_err = 0;
 392
 393         if (idev->total_num > 1) {
 394                 struct i2c_msg *next_msg = msgs + 1;
 395
 396                 idev->restart_needed = next_msg->flags & I2C_M_RD;
 397         }
 398
 399         idev->current_num++;
 400         idev->msg_queue++;
 401
 402         reinit_completion(&idev->msg_complete);
 403
 404         /*
 405          * Send the first start to pass control to the isr
 406          */
 407         ctrl = readb(idev->base + CORE_I2C_CTRL);
 408         ctrl |= CTRL_STA;
 409         writeb(ctrl, idev->base + CORE_I2C_CTRL);
 410
 411         time_left = wait_for_completion_timeout(&idev->msg_complete,
 412                                                 idev->adapter.timeout);
 413         if (!time_left)
 414                 return -ETIMEDOUT;
 415
 416         if (idev->msg_err)
 417                 return idev->msg_err;
 418
 419         return num;
 420 }
 421
 422 static u32 mchp_corei2c_func(struct i2c_adapter *adap)
 423 {
 424         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 425 }
 426
 427 static const struct i2c_algorithm mchp_corei2c_algo = {
 428         .master_xfer = mchp_corei2c_xfer,
 429         .functionality = mchp_corei2c_func,
 430 };
 431
 432 static int mchp_corei2c_probe(struct platform_device *pdev)
 433 {
 434         struct mchp_corei2c_dev *idev;
 435         struct resource *res;
 436         int irq, ret;
 437
 438         idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
 439         if (!idev)
 440                 return -ENOMEM;
 441
 442         idev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 443         if (IS_ERR(idev->base))
 444                 return PTR_ERR(idev->base);
 445
 446         irq = platform_get_irq(pdev, 0);
 447         if (irq < 0)
 448                 return irq;
 449
 450         idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
 451         if (IS_ERR(idev->i2c_clk))
 452                 return dev_err_probe(&pdev->dev, PTR_ERR(idev->i2c_clk),
 453                                      "missing clock\n");
 454
 455         idev->dev = &pdev->dev;
 456         init_completion(&idev->msg_complete);
 457
 458         ret = device_property_read_u32(idev->dev, "clock-frequency",
 459                                        &idev->bus_clk_rate);
 460         if (ret || !idev->bus_clk_rate) {
 461                 dev_info(&pdev->dev, "default to 100kHz\n");
 462                 idev->bus_clk_rate = 100000;
 463         }
 464
 465         if (idev->bus_clk_rate > 400000)
 466                 return dev_err_probe(&pdev->dev, -EINVAL,
 467                                      "clock-frequency too high: %d\n",
 468                                      idev->bus_clk_rate);
 469
 470         /*
 471          * This driver supports both the hard peripherals & soft FPGA cores.
 472          * The hard peripherals do not have shared IRQs, but we don't have
 473          * control over what way the interrupts are wired for the soft cores.
 474          */
 475         ret = devm_request_irq(&pdev->dev, irq, mchp_corei2c_isr, IRQF_SHARED,
 476                                pdev->name, idev);
 477         if (ret)
 478                 return dev_err_probe(&pdev->dev, ret,
 479                                      "failed to claim irq %d\n", irq);
 480
 481         ret = clk_prepare_enable(idev->i2c_clk);
 482         if (ret)
 483                 return dev_err_probe(&pdev->dev, ret,
 484                                      "failed to enable clock\n");
 485
 486         ret = mchp_corei2c_init(idev);
 487         if (ret) {
 488                 clk_disable_unprepare(idev->i2c_clk);
 489                 return dev_err_probe(&pdev->dev, ret, "failed to program clock divider\n");
 490         }
 491
 492         i2c_set_adapdata(&idev->adapter, idev);
 493         snprintf(idev->adapter.name, sizeof(idev->adapter.name),
 494                  "Microchip I2C hw bus at %08lx", (unsigned long)res->start);
 495         idev->adapter.owner = THIS_MODULE;
 496         idev->adapter.algo = &mchp_corei2c_algo;
 497         idev->adapter.dev.parent = &pdev->dev;
 498         idev->adapter.dev.of_node = pdev->dev.of_node;
 499         idev->adapter.timeout = HZ;
 500
 501         platform_set_drvdata(pdev, idev);
 502
 503         ret = i2c_add_adapter(&idev->adapter);
 504         if (ret) {
 505                 clk_disable_unprepare(idev->i2c_clk);
 506                 return ret;
 507         }
 508
 509         dev_info(&pdev->dev, "registered CoreI2C bus driver\n");
 510
 511         return 0;
 512 }
 513
 514 static void mchp_corei2c_remove(struct platform_device *pdev)
 515 {
 516         struct mchp_corei2c_dev *idev = platform_get_drvdata(pdev);
 517
 518         clk_disable_unprepare(idev->i2c_clk);
 519         i2c_del_adapter(&idev->adapter);
 520 }
 521
 522 static const struct of_device_id mchp_corei2c_of_match[] = {
 523         { .compatible = "microchip,mpfs-i2c" },
 524         { .compatible = "microchip,corei2c-rtl-v7" },
 525         {},
 526 };
 527 MODULE_DEVICE_TABLE(of, mchp_corei2c_of_match);
 528
 529 static struct platform_driver mchp_corei2c_driver = {
 530         .probe = mchp_corei2c_probe,
 531         .remove = mchp_corei2c_remove,
 532         .driver = {
 533                 .name = "microchip-corei2c",
 534                 .of_match_table = mchp_corei2c_of_match,
 535         },
 536 };
 537
 538 module_platform_driver(mchp_corei2c_driver);
 539
 540 MODULE_DESCRIPTION("Microchip CoreI2C bus driver");
 541 MODULE_AUTHOR("Daire McNamara <[email protected]>");
 542 MODULE_AUTHOR("Conor Dooley <[email protected]>");
 543 MODULE_LICENSE("GPL");