drivers/hid/intel-ish-hid/ipc/hw-ish.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * H/W layer of ISHTP provider device (ISH)
   4  *
   5  * Copyright (c) 2014-2016, Intel Corporation.
   6  */
   7
   8 #ifndef _ISHTP_HW_ISH_H_
   9 #define _ISHTP_HW_ISH_H_
  10
  11 #include <linux/pci.h>
  12 #include <linux/interrupt.h>
  13 #include "hw-ish-regs.h"
  14 #include "ishtp-dev.h"
  15
  16 #define PCI_DEVICE_ID_INTEL_ISH_CHV             0x22D8
  17 #define PCI_DEVICE_ID_INTEL_ISH_BXT_Ax          0x0AA2
  18 #define PCI_DEVICE_ID_INTEL_ISH_BXT_Bx          0x1AA2
  19 #define PCI_DEVICE_ID_INTEL_ISH_APL_Ax          0x5AA2
  20 #define PCI_DEVICE_ID_INTEL_ISH_SPT_Ax          0x9D35
  21 #define PCI_DEVICE_ID_INTEL_ISH_CNL_Ax          0x9DFC
  22 #define PCI_DEVICE_ID_INTEL_ISH_GLK_Ax          0x31A2
  23 #define PCI_DEVICE_ID_INTEL_ISH_CNL_H           0xA37C
  24 #define PCI_DEVICE_ID_INTEL_ISH_ICL_MOBILE      0x34FC
  25 #define PCI_DEVICE_ID_INTEL_ISH_SPT_H           0xA135
  26 #define PCI_DEVICE_ID_INTEL_ISH_CML_LP          0x02FC
  27 #define PCI_DEVICE_ID_INTEL_ISH_CMP_H           0x06FC
  28 #define PCI_DEVICE_ID_INTEL_ISH_EHL_Ax          0x4BB3
  29 #define PCI_DEVICE_ID_INTEL_ISH_TGL_LP          0xA0FC
  30 #define PCI_DEVICE_ID_INTEL_ISH_TGL_H           0x43FC
  31 #define PCI_DEVICE_ID_INTEL_ISH_ADL_S           0x7AF8
  32 #define PCI_DEVICE_ID_INTEL_ISH_ADL_P           0x51FC
  33 #define PCI_DEVICE_ID_INTEL_ISH_ADL_N           0x54FC
  34 #define PCI_DEVICE_ID_INTEL_ISH_RPL_S           0x7A78
  35 #define PCI_DEVICE_ID_INTEL_ISH_MTL_P           0x7E45
  36 #define PCI_DEVICE_ID_INTEL_ISH_ARL_H           0x7745
  37 #define PCI_DEVICE_ID_INTEL_ISH_ARL_S           0x7F78
  38 #define PCI_DEVICE_ID_INTEL_ISH_LNL_M           0xA845
  39 #define PCI_DEVICE_ID_INTEL_ISH_PTL_H           0xE345
  40 #define PCI_DEVICE_ID_INTEL_ISH_PTL_P           0xE445
  41
  42 #define REVISION_ID_CHT_A0      0x6
  43 #define REVISION_ID_CHT_Ax_SI   0x0
  44 #define REVISION_ID_CHT_Bx_SI   0x10
  45 #define REVISION_ID_CHT_Kx_SI   0x20
  46 #define REVISION_ID_CHT_Dx_SI   0x30
  47 #define REVISION_ID_CHT_B0      0xB0
  48 #define REVISION_ID_SI_MASK     0x70
  49
  50 struct ipc_rst_payload_type {
  51         uint16_t        reset_id;
  52         uint16_t        reserved;
  53 };
  54
  55 struct time_sync_format {
  56         uint8_t ts1_source;
  57         uint8_t ts2_source;
  58         uint16_t reserved;
  59 } __packed;
  60
  61 struct ipc_time_update_msg {
  62         uint64_t primary_host_time;
  63         struct time_sync_format sync_info;
  64         uint64_t secondary_host_time;
  65 } __packed;
  66
  67 enum {
  68         HOST_UTC_TIME_USEC = 0,
  69         HOST_SYSTEM_TIME_USEC = 1
  70 };
  71
  72 struct ish_hw {
  73         void __iomem *mem_addr;
  74 };
  75
  76 /*
  77  * ISH FW status type
  78  */
  79 enum {
  80         FWSTS_AFTER_RESET               = 0,
  81         FWSTS_WAIT_FOR_HOST             = 4,
  82         FWSTS_START_KERNEL_DMA          = 5,
  83         FWSTS_FW_IS_RUNNING             = 7,
  84         FWSTS_SENSOR_APP_LOADED         = 8,
  85         FWSTS_SENSOR_APP_RUNNING        = 15
  86 };
  87
  88 #define to_ish_hw(dev) (struct ish_hw *)((dev)->hw)
  89
  90 irqreturn_t ish_irq_handler(int irq, void *dev_id);
  91 struct ishtp_device *ish_dev_init(struct pci_dev *pdev);
  92 int ish_hw_start(struct ishtp_device *dev);
  93 void ish_device_disable(struct ishtp_device *dev);
  94 int ish_disable_dma(struct ishtp_device *dev);
  95 void ish_set_host_ready(struct ishtp_device *dev);
  96
  97 #endif /* _ISHTP_HW_ISH_H_ */