drivers/gpu/drm/sun4i/sun8i_ui_layer.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) Icenowy Zheng <[email protected]>
   4  *
   5  * Based on sun4i_layer.h, which is:
   6  *   Copyright (C) 2015 Free Electrons
   7  *   Copyright (C) 2015 NextThing Co
   8  *
   9  *   Maxime Ripard <[email protected]>
  10  */
  11
  12 #include <drm/drm_atomic.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_blend.h>
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_fb_dma_helper.h>
  17 #include <drm/drm_fourcc.h>
  18 #include <drm/drm_framebuffer.h>
  19 #include <drm/drm_gem_atomic_helper.h>
  20 #include <drm/drm_gem_dma_helper.h>
  21 #include <drm/drm_probe_helper.h>
  22
  23 #include "sun8i_mixer.h"
  24 #include "sun8i_ui_layer.h"
  25 #include "sun8i_ui_scaler.h"
  26
  27 static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
  28                                         int overlay, struct drm_plane *plane)
  29 {
  30         u32 mask, val, ch_base;
  31
  32         ch_base = sun8i_channel_base(mixer, channel);
  33
  34         mask = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK |
  35                 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK;
  36
  37         val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA(plane->state->alpha >> 8);
  38
  39         val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ?
  40                 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_PIXEL :
  41                 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_COMBINED;
  42
  43         regmap_update_bits(mixer->engine.regs,
  44                            SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
  45                            mask, val);
  46 }
  47
  48 static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
  49                                        int overlay, struct drm_plane *plane,
  50                                        unsigned int zpos)
  51 {
  52         struct drm_plane_state *state = plane->state;
  53         u32 src_w, src_h, dst_w, dst_h;
  54         u32 bld_base, ch_base;
  55         u32 outsize, insize;
  56         u32 hphase, vphase;
  57
  58         DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n",
  59                          channel, overlay);
  60
  61         bld_base = sun8i_blender_base(mixer);
  62         ch_base = sun8i_channel_base(mixer, channel);
  63
  64         src_w = drm_rect_width(&state->src) >> 16;
  65         src_h = drm_rect_height(&state->src) >> 16;
  66         dst_w = drm_rect_width(&state->dst);
  67         dst_h = drm_rect_height(&state->dst);
  68
  69         hphase = state->src.x1 & 0xffff;
  70         vphase = state->src.y1 & 0xffff;
  71
  72         insize = SUN8I_MIXER_SIZE(src_w, src_h);
  73         outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
  74
  75         /* Set height and width */
  76         DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
  77                          state->src.x1 >> 16, state->src.y1 >> 16);
  78         DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
  79         regmap_write(mixer->engine.regs,
  80                      SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, overlay),
  81                      insize);
  82         regmap_write(mixer->engine.regs,
  83                      SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base),
  84                      insize);
  85
  86         if (insize != outsize || hphase || vphase) {
  87                 u32 hscale, vscale;
  88
  89                 DRM_DEBUG_DRIVER("HW scaling is enabled\n");
  90
  91                 hscale = state->src_w / state->crtc_w;
  92                 vscale = state->src_h / state->crtc_h;
  93
  94                 sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w,
  95                                       dst_h, hscale, vscale, hphase, vphase);
  96                 sun8i_ui_scaler_enable(mixer, channel, true);
  97         } else {
  98                 DRM_DEBUG_DRIVER("HW scaling is not needed\n");
  99                 sun8i_ui_scaler_enable(mixer, channel, false);
 100         }
 101
 102         /* Set base coordinates */
 103         DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
 104                          state->dst.x1, state->dst.y1);
 105         DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
 106         regmap_write(mixer->engine.regs,
 107                      SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
 108                      SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
 109         regmap_write(mixer->engine.regs,
 110                      SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
 111                      outsize);
 112
 113         return 0;
 114 }
 115
 116 static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
 117                                          int overlay, struct drm_plane *plane)
 118 {
 119         struct drm_plane_state *state = plane->state;
 120         const struct drm_format_info *fmt;
 121         u32 val, ch_base, hw_fmt;
 122         int ret;
 123
 124         ch_base = sun8i_channel_base(mixer, channel);
 125
 126         fmt = state->fb->format;
 127         ret = sun8i_mixer_drm_format_to_hw(fmt->format, &hw_fmt);
 128         if (ret || fmt->is_yuv) {
 129                 DRM_DEBUG_DRIVER("Invalid format\n");
 130                 return -EINVAL;
 131         }
 132
 133         val = hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
 134         regmap_update_bits(mixer->engine.regs,
 135                            SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
 136                            SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
 137
 138         return 0;
 139 }
 140
 141 static int sun8i_ui_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
 142                                         int overlay, struct drm_plane *plane)
 143 {
 144         struct drm_plane_state *state = plane->state;
 145         struct drm_framebuffer *fb = state->fb;
 146         struct drm_gem_dma_object *gem;
 147         dma_addr_t dma_addr;
 148         u32 ch_base;
 149         int bpp;
 150
 151         ch_base = sun8i_channel_base(mixer, channel);
 152
 153         /* Get the physical address of the buffer in memory */
 154         gem = drm_fb_dma_get_gem_obj(fb, 0);
 155
 156         DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->dma_addr);
 157
 158         /* Compute the start of the displayed memory */
 159         bpp = fb->format->cpp[0];
 160         dma_addr = gem->dma_addr + fb->offsets[0];
 161
 162         /* Fixup framebuffer address for src coordinates */
 163         dma_addr += (state->src.x1 >> 16) * bpp;
 164         dma_addr += (state->src.y1 >> 16) * fb->pitches[0];
 165
 166         /* Set the line width */
 167         DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
 168         regmap_write(mixer->engine.regs,
 169                      SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, overlay),
 170                      fb->pitches[0]);
 171
 172         DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &dma_addr);
 173
 174         regmap_write(mixer->engine.regs,
 175                      SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, overlay),
 176                      lower_32_bits(dma_addr));
 177
 178         return 0;
 179 }
 180
 181 static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
 182                                        struct drm_atomic_state *state)
 183 {
 184         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 185                                                                                  plane);
 186         struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
 187         struct drm_crtc *crtc = new_plane_state->crtc;
 188         struct drm_crtc_state *crtc_state;
 189         int min_scale, max_scale;
 190
 191         if (!crtc)
 192                 return 0;
 193
 194         crtc_state = drm_atomic_get_existing_crtc_state(state,
 195                                                         crtc);
 196         if (WARN_ON(!crtc_state))
 197                 return -EINVAL;
 198
 199         min_scale = DRM_PLANE_NO_SCALING;
 200         max_scale = DRM_PLANE_NO_SCALING;
 201
 202         if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
 203                 min_scale = SUN8I_UI_SCALER_SCALE_MIN;
 204                 max_scale = SUN8I_UI_SCALER_SCALE_MAX;
 205         }
 206
 207         return drm_atomic_helper_check_plane_state(new_plane_state,
 208                                                    crtc_state,
 209                                                    min_scale, max_scale,
 210                                                    true, true);
 211 }
 212
 213
 214 static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
 215                                          struct drm_atomic_state *state)
 216 {
 217         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 218                                                                            plane);
 219         struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
 220         unsigned int zpos = new_state->normalized_zpos;
 221         struct sun8i_mixer *mixer = layer->mixer;
 222
 223         if (!new_state->crtc || !new_state->visible)
 224                 return;
 225
 226         sun8i_ui_layer_update_coord(mixer, layer->channel,
 227                                     layer->overlay, plane, zpos);
 228         sun8i_ui_layer_update_alpha(mixer, layer->channel,
 229                                     layer->overlay, plane);
 230         sun8i_ui_layer_update_formats(mixer, layer->channel,
 231                                       layer->overlay, plane);
 232         sun8i_ui_layer_update_buffer(mixer, layer->channel,
 233                                      layer->overlay, plane);
 234 }
 235
 236 static const struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = {
 237         .atomic_check   = sun8i_ui_layer_atomic_check,
 238         .atomic_update  = sun8i_ui_layer_atomic_update,
 239 };
 240
 241 static const struct drm_plane_funcs sun8i_ui_layer_funcs = {
 242         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 243         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 244         .destroy                = drm_plane_cleanup,
 245         .disable_plane          = drm_atomic_helper_disable_plane,
 246         .reset                  = drm_atomic_helper_plane_reset,
 247         .update_plane           = drm_atomic_helper_update_plane,
 248 };
 249
 250 static const u32 sun8i_ui_layer_formats[] = {
 251         DRM_FORMAT_ABGR1555,
 252         DRM_FORMAT_ABGR4444,
 253         DRM_FORMAT_ABGR8888,
 254         DRM_FORMAT_ARGB1555,
 255         DRM_FORMAT_ARGB4444,
 256         DRM_FORMAT_ARGB8888,
 257         DRM_FORMAT_BGR565,
 258         DRM_FORMAT_BGR888,
 259         DRM_FORMAT_BGRA5551,
 260         DRM_FORMAT_BGRA4444,
 261         DRM_FORMAT_BGRA8888,
 262         DRM_FORMAT_BGRX8888,
 263         DRM_FORMAT_RGB565,
 264         DRM_FORMAT_RGB888,
 265         DRM_FORMAT_RGBA4444,
 266         DRM_FORMAT_RGBA5551,
 267         DRM_FORMAT_RGBA8888,
 268         DRM_FORMAT_RGBX8888,
 269         DRM_FORMAT_XBGR8888,
 270         DRM_FORMAT_XRGB8888,
 271 };
 272
 273 static const uint64_t sun8i_layer_modifiers[] = {
 274         DRM_FORMAT_MOD_LINEAR,
 275         DRM_FORMAT_MOD_INVALID
 276 };
 277
 278 struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
 279                                             struct sun8i_mixer *mixer,
 280                                             int index)
 281 {
 282         enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
 283         int channel = mixer->cfg->vi_num + index;
 284         struct sun8i_layer *layer;
 285         unsigned int plane_cnt;
 286         int ret;
 287
 288         layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
 289         if (!layer)
 290                 return ERR_PTR(-ENOMEM);
 291
 292         if (index == 0)
 293                 type = DRM_PLANE_TYPE_PRIMARY;
 294
 295         /* possible crtcs are set later */
 296         ret = drm_universal_plane_init(drm, &layer->plane, 0,
 297                                        &sun8i_ui_layer_funcs,
 298                                        sun8i_ui_layer_formats,
 299                                        ARRAY_SIZE(sun8i_ui_layer_formats),
 300                                        sun8i_layer_modifiers, type, NULL);
 301         if (ret) {
 302                 dev_err(drm->dev, "Couldn't initialize layer\n");
 303                 return ERR_PTR(ret);
 304         }
 305
 306         plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
 307
 308         ret = drm_plane_create_alpha_property(&layer->plane);
 309         if (ret) {
 310                 dev_err(drm->dev, "Couldn't add alpha property\n");
 311                 return ERR_PTR(ret);
 312         }
 313
 314         ret = drm_plane_create_zpos_property(&layer->plane, channel,
 315                                              0, plane_cnt - 1);
 316         if (ret) {
 317                 dev_err(drm->dev, "Couldn't add zpos property\n");
 318                 return ERR_PTR(ret);
 319         }
 320
 321         drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs);
 322         layer->mixer = mixer;
 323         layer->type = SUN8I_LAYER_TYPE_UI;
 324         layer->channel = channel;
 325         layer->overlay = 0;
 326
 327         return layer;
 328 }