drivers/gpu/drm/sun4i/sun4i_tcon.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 2015 Free Electrons
   4  * Copyright (C) 2015 NextThing Co
   5  *
   6  * Boris Brezillon <[email protected]>
   7  * Maxime Ripard <[email protected]>
   8  */
   9
  10 #ifndef __SUN4I_TCON_H__
  11 #define __SUN4I_TCON_H__
  12
  13 #include <drm/drm_crtc.h>
  14
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/mod_devicetable.h>
  18 #include <linux/reset.h>
  19
  20 #define SUN4I_TCON_GCTL_REG                     0x0
  21 #define SUN4I_TCON_GCTL_TCON_ENABLE                     BIT(31)
  22 #define SUN4I_TCON_GCTL_IOMAP_MASK                      BIT(0)
  23 #define SUN4I_TCON_GCTL_IOMAP_TCON1                     (1 << 0)
  24 #define SUN4I_TCON_GCTL_IOMAP_TCON0                     (0 << 0)
  25
  26 #define SUN4I_TCON_GINT0_REG                    0x4
  27 #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe)            BIT(31 - (pipe))
  28 #define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE        BIT(27)
  29 #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_ENABLE       BIT(26)
  30 #define SUN4I_TCON_GINT0_VBLANK_INT(pipe)               BIT(15 - (pipe))
  31 #define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT           BIT(11)
  32 #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT          BIT(10)
  33
  34 #define SUN4I_TCON_GINT1_REG                    0x8
  35
  36 #define SUN4I_TCON_FRM_CTL_REG                  0x10
  37 #define SUN4I_TCON0_FRM_CTL_EN                          BIT(31)
  38 #define SUN4I_TCON0_FRM_CTL_MODE_R                      BIT(6)
  39 #define SUN4I_TCON0_FRM_CTL_MODE_G                      BIT(5)
  40 #define SUN4I_TCON0_FRM_CTL_MODE_B                      BIT(4)
  41
  42 #define SUN4I_TCON0_FRM_SEED_PR_REG             0x14
  43 #define SUN4I_TCON0_FRM_SEED_PG_REG             0x18
  44 #define SUN4I_TCON0_FRM_SEED_PB_REG             0x1c
  45 #define SUN4I_TCON0_FRM_SEED_LR_REG             0x20
  46 #define SUN4I_TCON0_FRM_SEED_LG_REG             0x24
  47 #define SUN4I_TCON0_FRM_SEED_LB_REG             0x28
  48 #define SUN4I_TCON0_FRM_TBL0_REG                0x2c
  49 #define SUN4I_TCON0_FRM_TBL1_REG                0x30
  50 #define SUN4I_TCON0_FRM_TBL2_REG                0x34
  51 #define SUN4I_TCON0_FRM_TBL3_REG                0x38
  52
  53 #define SUN4I_TCON0_CTL_REG                     0x40
  54 #define SUN4I_TCON0_CTL_TCON_ENABLE                     BIT(31)
  55 #define SUN4I_TCON0_CTL_IF_MASK                         GENMASK(25, 24)
  56 #define SUN4I_TCON0_CTL_IF_8080                         (1 << 24)
  57 #define SUN4I_TCON0_CTL_CLK_DELAY_MASK                  GENMASK(8, 4)
  58 #define SUN4I_TCON0_CTL_CLK_DELAY(delay)                ((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
  59 #define SUN4I_TCON0_CTL_SRC_SEL_MASK                    GENMASK(2, 0)
  60
  61 #define SUN4I_TCON0_DCLK_REG                    0x44
  62 #define SUN4I_TCON0_DCLK_GATE_BIT                       (31)
  63 #define SUN4I_TCON0_DCLK_DIV_SHIFT                      (0)
  64 #define SUN4I_TCON0_DCLK_DIV_WIDTH                      (7)
  65
  66 #define SUN4I_TCON0_BASIC0_REG                  0x48
  67 #define SUN4I_TCON0_BASIC0_X(width)                     ((((width) - 1) & 0xfff) << 16)
  68 #define SUN4I_TCON0_BASIC0_Y(height)                    (((height) - 1) & 0xfff)
  69
  70 #define SUN4I_TCON0_BASIC1_REG                  0x4c
  71 #define SUN4I_TCON0_BASIC1_H_TOTAL(total)               ((((total) - 1) & 0x1fff) << 16)
  72 #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)              (((bp) - 1) & 0xfff)
  73
  74 #define SUN4I_TCON0_BASIC2_REG                  0x50
  75 #define SUN4I_TCON0_BASIC2_V_TOTAL(total)               (((total) & 0x1fff) << 16)
  76 #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)              (((bp) - 1) & 0xfff)
  77
  78 #define SUN4I_TCON0_BASIC3_REG                  0x54
  79 #define SUN4I_TCON0_BASIC3_H_SYNC(width)                ((((width) - 1) & 0x7ff) << 16)
  80 #define SUN4I_TCON0_BASIC3_V_SYNC(height)               (((height) - 1) & 0x7ff)
  81
  82 #define SUN4I_TCON0_HV_IF_REG                   0x58
  83
  84 #define SUN4I_TCON0_CPU_IF_REG                  0x60
  85 #define SUN4I_TCON0_CPU_IF_MODE_MASK                    GENMASK(31, 28)
  86 #define SUN4I_TCON0_CPU_IF_MODE_DSI                     (1 << 28)
  87 #define SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH               BIT(16)
  88 #define SUN4I_TCON0_CPU_IF_TRI_FIFO_EN                  BIT(2)
  89 #define SUN4I_TCON0_CPU_IF_TRI_EN                       BIT(0)
  90
  91 #define SUN4I_TCON0_CPU_WR_REG                  0x64
  92 #define SUN4I_TCON0_CPU_RD0_REG                 0x68
  93 #define SUN4I_TCON0_CPU_RDA_REG                 0x6c
  94 #define SUN4I_TCON0_TTL0_REG                    0x70
  95 #define SUN4I_TCON0_TTL1_REG                    0x74
  96 #define SUN4I_TCON0_TTL2_REG                    0x78
  97 #define SUN4I_TCON0_TTL3_REG                    0x7c
  98 #define SUN4I_TCON0_TTL4_REG                    0x80
  99
 100 #define SUN4I_TCON0_LVDS_IF_REG                 0x84
 101 #define SUN4I_TCON0_LVDS_IF_EN                          BIT(31)
 102 #define SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK               BIT(26)
 103 #define SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS             (1 << 26)
 104 #define SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS             (0 << 26)
 105 #define SUN4I_TCON0_LVDS_IF_CLK_SEL_MASK                BIT(20)
 106 #define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0               (1 << 20)
 107 #define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK                BIT(4)
 108 #define SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL              (1 << 4)
 109 #define SUN4I_TCON0_LVDS_IF_CLK_POL_INV                 (0 << 4)
 110 #define SUN4I_TCON0_LVDS_IF_DATA_POL_MASK               GENMASK(3, 0)
 111 #define SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL             (0xf)
 112 #define SUN4I_TCON0_LVDS_IF_DATA_POL_INV                (0)
 113
 114 #define SUN4I_TCON0_IO_POL_REG                  0x88
 115 #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase)            ((phase & 3) << 28)
 116 #define SUN4I_TCON0_IO_POL_DE_NEGATIVE                  BIT(27)
 117 #define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE           BIT(26)
 118 #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE               BIT(25)
 119 #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE               BIT(24)
 120
 121 #define SUN4I_TCON0_IO_TRI_REG                  0x8c
 122 #define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE                BIT(25)
 123 #define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE                BIT(24)
 124 #define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins)      GENMASK(pins, 0)
 125
 126 #define SUN4I_TCON1_CTL_REG                     0x90
 127 #define SUN4I_TCON1_CTL_TCON_ENABLE                     BIT(31)
 128 #define SUN4I_TCON1_CTL_INTERLACE_ENABLE                BIT(20)
 129 #define SUN4I_TCON1_CTL_CLK_DELAY_MASK                  GENMASK(8, 4)
 130 #define SUN4I_TCON1_CTL_CLK_DELAY(delay)                ((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK)
 131 #define SUN4I_TCON1_CTL_SRC_SEL_MASK                    GENMASK(1, 0)
 132
 133 #define SUN4I_TCON1_BASIC0_REG                  0x94
 134 #define SUN4I_TCON1_BASIC0_X(width)                     ((((width) - 1) & 0xfff) << 16)
 135 #define SUN4I_TCON1_BASIC0_Y(height)                    (((height) - 1) & 0xfff)
 136
 137 #define SUN4I_TCON1_BASIC1_REG                  0x98
 138 #define SUN4I_TCON1_BASIC1_X(width)                     ((((width) - 1) & 0xfff) << 16)
 139 #define SUN4I_TCON1_BASIC1_Y(height)                    (((height) - 1) & 0xfff)
 140
 141 #define SUN4I_TCON1_BASIC2_REG                  0x9c
 142 #define SUN4I_TCON1_BASIC2_X(width)                     ((((width) - 1) & 0xfff) << 16)
 143 #define SUN4I_TCON1_BASIC2_Y(height)                    (((height) - 1) & 0xfff)
 144
 145 #define SUN4I_TCON1_BASIC3_REG                  0xa0
 146 #define SUN4I_TCON1_BASIC3_H_TOTAL(total)               ((((total) - 1) & 0x1fff) << 16)
 147 #define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp)              (((bp) - 1) & 0xfff)
 148
 149 #define SUN4I_TCON1_BASIC4_REG                  0xa4
 150 #define SUN4I_TCON1_BASIC4_V_TOTAL(total)               (((total) & 0x1fff) << 16)
 151 #define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp)              (((bp) - 1) & 0xfff)
 152
 153 #define SUN4I_TCON1_BASIC5_REG                  0xa8
 154 #define SUN4I_TCON1_BASIC5_H_SYNC(width)                ((((width) - 1) & 0x3ff) << 16)
 155 #define SUN4I_TCON1_BASIC5_V_SYNC(height)               (((height) - 1) & 0x3ff)
 156
 157 #define SUN4I_TCON1_IO_POL_REG                  0xf0
 158 /* there is no documentation about this bit */
 159 #define SUN4I_TCON1_IO_POL_UNKNOWN                      BIT(26)
 160 #define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE               BIT(25)
 161 #define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE               BIT(24)
 162
 163 #define SUN4I_TCON1_IO_TRI_REG                  0xf4
 164
 165 #define SUN4I_TCON_ECC_FIFO_REG                 0xf8
 166 #define SUN4I_TCON_ECC_FIFO_EN                          BIT(3)
 167
 168 #define SUN4I_TCON_CEU_CTL_REG                  0x100
 169 #define SUN4I_TCON_CEU_MUL_RR_REG               0x110
 170 #define SUN4I_TCON_CEU_MUL_RG_REG               0x114
 171 #define SUN4I_TCON_CEU_MUL_RB_REG               0x118
 172 #define SUN4I_TCON_CEU_ADD_RC_REG               0x11c
 173 #define SUN4I_TCON_CEU_MUL_GR_REG               0x120
 174 #define SUN4I_TCON_CEU_MUL_GG_REG               0x124
 175 #define SUN4I_TCON_CEU_MUL_GB_REG               0x128
 176 #define SUN4I_TCON_CEU_ADD_GC_REG               0x12c
 177 #define SUN4I_TCON_CEU_MUL_BR_REG               0x130
 178 #define SUN4I_TCON_CEU_MUL_BG_REG               0x134
 179 #define SUN4I_TCON_CEU_MUL_BB_REG               0x138
 180 #define SUN4I_TCON_CEU_ADD_BC_REG               0x13c
 181 #define SUN4I_TCON_CEU_RANGE_R_REG              0x140
 182 #define SUN4I_TCON_CEU_RANGE_G_REG              0x144
 183 #define SUN4I_TCON_CEU_RANGE_B_REG              0x148
 184
 185 #define SUN4I_TCON0_CPU_TRI0_REG                0x160
 186 #define SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(space)         ((((space) - 1) & 0xfff) << 16)
 187 #define SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(size)           (((size) - 1) & 0xfff)
 188
 189 #define SUN4I_TCON0_CPU_TRI1_REG                0x164
 190 #define SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(num)             (((num) - 1) & 0xffff)
 191
 192 #define SUN4I_TCON0_CPU_TRI2_REG                0x168
 193 #define SUN4I_TCON0_CPU_TRI2_START_DELAY(delay)         (((delay) & 0xffff) << 16)
 194 #define SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(set)       ((set) & 0xfff)
 195
 196 #define SUN4I_TCON_SAFE_PERIOD_REG              0x1f0
 197 #define SUN4I_TCON_SAFE_PERIOD_NUM(num)                 (((num) & 0xfff) << 16)
 198 #define SUN4I_TCON_SAFE_PERIOD_MODE(mode)               ((mode) & 0x3)
 199
 200 #define SUN4I_TCON_MUX_CTRL_REG                 0x200
 201
 202 #define SUN4I_TCON0_LVDS_ANA0_REG               0x220
 203 #define SUN4I_TCON0_LVDS_ANA0_DCHS                      BIT(16)
 204 #define SUN4I_TCON0_LVDS_ANA0_PD                        (BIT(20) | BIT(21))
 205 #define SUN4I_TCON0_LVDS_ANA0_EN_MB                     BIT(22)
 206 #define SUN4I_TCON0_LVDS_ANA0_REG_C                     (BIT(24) | BIT(25))
 207 #define SUN4I_TCON0_LVDS_ANA0_REG_V                     (BIT(26) | BIT(27))
 208 #define SUN4I_TCON0_LVDS_ANA0_CK_EN                     (BIT(29) | BIT(28))
 209
 210 #define SUN6I_TCON0_LVDS_ANA0_EN_MB                     BIT(31)
 211 #define SUN6I_TCON0_LVDS_ANA0_EN_LDO                    BIT(30)
 212 #define SUN6I_TCON0_LVDS_ANA0_EN_DRVC                   BIT(24)
 213 #define SUN6I_TCON0_LVDS_ANA0_EN_DRVD(x)                (((x) & 0xf) << 20)
 214 #define SUN6I_TCON0_LVDS_ANA0_C(x)                      (((x) & 3) << 17)
 215 #define SUN6I_TCON0_LVDS_ANA0_V(x)                      (((x) & 3) << 8)
 216 #define SUN6I_TCON0_LVDS_ANA0_PD(x)                     (((x) & 3) << 4)
 217
 218 #define SUN4I_TCON0_LVDS_ANA1_REG               0x224
 219 #define SUN4I_TCON0_LVDS_ANA1_INIT                      (0x1f << 26 | 0x1f << 10)
 220 #define SUN4I_TCON0_LVDS_ANA1_UPDATE                    (0x1f << 16 | 0x1f << 00)
 221
 222 #define SUN4I_TCON1_FILL_CTL_REG                0x300
 223 #define SUN4I_TCON1_FILL_BEG0_REG               0x304
 224 #define SUN4I_TCON1_FILL_END0_REG               0x308
 225 #define SUN4I_TCON1_FILL_DATA0_REG              0x30c
 226 #define SUN4I_TCON1_FILL_BEG1_REG               0x310
 227 #define SUN4I_TCON1_FILL_END1_REG               0x314
 228 #define SUN4I_TCON1_FILL_DATA1_REG              0x318
 229 #define SUN4I_TCON1_FILL_BEG2_REG               0x31c
 230 #define SUN4I_TCON1_FILL_END2_REG               0x320
 231 #define SUN4I_TCON1_FILL_DATA2_REG              0x324
 232 #define SUN4I_TCON1_GAMMA_TABLE_REG             0x400
 233
 234 #define SUN4I_TCON_MAX_CHANNELS         2
 235
 236 struct sun4i_tcon;
 237
 238 struct sun4i_tcon_quirks {
 239         bool    has_channel_0;  /* a83t does not have channel 0 on second TCON */
 240         bool    has_channel_1;  /* a33 does not have channel 1 */
 241         bool    has_lvds_alt;   /* Does the LVDS clock have a parent other than the TCON clock? */
 242         bool    needs_de_be_mux; /* sun6i needs mux to select backend */
 243         bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
 244         bool    supports_lvds;   /* Does the TCON support an LVDS output? */
 245         bool    polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
 246         u8      dclk_min_div;   /* minimum divider for TCON0 DCLK */
 247
 248         /* callback to handle tcon muxing options */
 249         int     (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
 250         /* handler for LVDS setup routine */
 251         void    (*setup_lvds_phy)(struct sun4i_tcon *tcon,
 252                                   const struct drm_encoder *encoder);
 253 };
 254
 255 struct sun4i_tcon {
 256         struct device                   *dev;
 257         struct drm_device               *drm;
 258         struct regmap                   *regs;
 259
 260         /* Main bus clock */
 261         struct clk                      *clk;
 262
 263         /* Clocks for the TCON channels */
 264         struct clk                      *sclk0;
 265         struct clk                      *sclk1;
 266
 267         /* Possible mux for the LVDS clock */
 268         struct clk                      *lvds_pll;
 269
 270         /* Pixel clock */
 271         struct clk                      *dclk;
 272         u8                              dclk_max_div;
 273         u8                              dclk_min_div;
 274
 275         /* Reset control */
 276         struct reset_control            *lcd_rst;
 277         struct reset_control            *lvds_rst;
 278
 279         /* Platform adjustments */
 280         const struct sun4i_tcon_quirks  *quirks;
 281
 282         /* Associated crtc */
 283         struct sun4i_crtc               *crtc;
 284
 285         int                             id;
 286
 287         /* TCON list management */
 288         struct list_head                list;
 289 };
 290
 291 struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
 292 struct drm_panel *sun4i_tcon_find_panel(struct device_node *node);
 293
 294 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
 295 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
 296                          const struct drm_encoder *encoder,
 297                          const struct drm_display_mode *mode);
 298 void sun4i_tcon_set_status(struct sun4i_tcon *crtc,
 299                            const struct drm_encoder *encoder, bool enable);
 300
 301 extern const struct of_device_id sun4i_tcon_of_table[];
 302
 303 #endif /* __SUN4I_TCON_H__ */