drivers/gpu/drm/omapdrm/dss/dpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2009 Nokia Corporation
   4  * Author: Tomi Valkeinen <[email protected]>
   5  *
   6  * Some code and ideas taken from drivers/video/omap/ driver
   7  * by Imre Deak.
   8  */
   9
  10 #define DSS_SUBSYS_NAME "DPI"
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/errno.h>
  16 #include <linux/export.h>
  17 #include <linux/kernel.h>
  18 #include <linux/of.h>
  19 #include <linux/of_graph.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/string.h>
  23 #include <linux/sys_soc.h>
  24
  25 #include <drm/drm_bridge.h>
  26
  27 #include "dss.h"
  28 #include "omapdss.h"
  29
  30 struct dpi_data {
  31         struct platform_device *pdev;
  32         enum dss_model dss_model;
  33         struct dss_device *dss;
  34         unsigned int id;
  35
  36         struct regulator *vdds_dsi_reg;
  37         enum dss_clk_source clk_src;
  38         struct dss_pll *pll;
  39
  40         struct dss_lcd_mgr_config mgr_config;
  41         unsigned long pixelclock;
  42         int data_lines;
  43
  44         struct omap_dss_device output;
  45         struct drm_bridge bridge;
  46 };
  47
  48 #define drm_bridge_to_dpi(bridge) container_of(bridge, struct dpi_data, bridge)
  49
  50 /* -----------------------------------------------------------------------------
  51  * Clock Handling and PLL
  52  */
  53
  54 static enum dss_clk_source dpi_get_clk_src_dra7xx(struct dpi_data *dpi,
  55                                                   enum omap_channel channel)
  56 {
  57         /*
  58          * Possible clock sources:
  59          * LCD1: FCK/PLL1_1/HDMI_PLL
  60          * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3)
  61          * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1)
  62          */
  63
  64         switch (channel) {
  65         case OMAP_DSS_CHANNEL_LCD:
  66         {
  67                 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1))
  68                         return DSS_CLK_SRC_PLL1_1;
  69                 break;
  70         }
  71         case OMAP_DSS_CHANNEL_LCD2:
  72         {
  73                 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
  74                         return DSS_CLK_SRC_PLL1_3;
  75                 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3))
  76                         return DSS_CLK_SRC_PLL2_3;
  77                 break;
  78         }
  79         case OMAP_DSS_CHANNEL_LCD3:
  80         {
  81                 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1))
  82                         return DSS_CLK_SRC_PLL2_1;
  83                 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
  84                         return DSS_CLK_SRC_PLL1_3;
  85                 break;
  86         }
  87         default:
  88                 break;
  89         }
  90
  91         return DSS_CLK_SRC_FCK;
  92 }
  93
  94 static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi)
  95 {
  96         enum omap_channel channel = dpi->output.dispc_channel;
  97
  98         /*
  99          * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
 100          * would also be used for DISPC fclk. Meaning, when the DPI output is
 101          * disabled, DISPC clock will be disabled, and TV out will stop.
 102          */
 103         switch (dpi->dss_model) {
 104         case DSS_MODEL_OMAP2:
 105         case DSS_MODEL_OMAP3:
 106                 return DSS_CLK_SRC_FCK;
 107
 108         case DSS_MODEL_OMAP4:
 109                 switch (channel) {
 110                 case OMAP_DSS_CHANNEL_LCD:
 111                         return DSS_CLK_SRC_PLL1_1;
 112                 case OMAP_DSS_CHANNEL_LCD2:
 113                         return DSS_CLK_SRC_PLL2_1;
 114                 default:
 115                         return DSS_CLK_SRC_FCK;
 116                 }
 117
 118         case DSS_MODEL_OMAP5:
 119                 switch (channel) {
 120                 case OMAP_DSS_CHANNEL_LCD:
 121                         return DSS_CLK_SRC_PLL1_1;
 122                 case OMAP_DSS_CHANNEL_LCD3:
 123                         return DSS_CLK_SRC_PLL2_1;
 124                 case OMAP_DSS_CHANNEL_LCD2:
 125                 default:
 126                         return DSS_CLK_SRC_FCK;
 127                 }
 128
 129         case DSS_MODEL_DRA7:
 130                 return dpi_get_clk_src_dra7xx(dpi, channel);
 131
 132         default:
 133                 return DSS_CLK_SRC_FCK;
 134         }
 135 }
 136
 137 struct dpi_clk_calc_ctx {
 138         struct dpi_data *dpi;
 139         unsigned int clkout_idx;
 140
 141         /* inputs */
 142
 143         unsigned long pck_min, pck_max;
 144
 145         /* outputs */
 146
 147         struct dss_pll_clock_info pll_cinfo;
 148         unsigned long fck;
 149         struct dispc_clock_info dispc_cinfo;
 150 };
 151
 152 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
 153                 unsigned long pck, void *data)
 154 {
 155         struct dpi_clk_calc_ctx *ctx = data;
 156
 157         /*
 158          * Odd dividers give us uneven duty cycle, causing problem when level
 159          * shifted. So skip all odd dividers when the pixel clock is on the
 160          * higher side.
 161          */
 162         if (ctx->pck_min >= 100000000) {
 163                 if (lckd > 1 && lckd % 2 != 0)
 164                         return false;
 165
 166                 if (pckd > 1 && pckd % 2 != 0)
 167                         return false;
 168         }
 169
 170         ctx->dispc_cinfo.lck_div = lckd;
 171         ctx->dispc_cinfo.pck_div = pckd;
 172         ctx->dispc_cinfo.lck = lck;
 173         ctx->dispc_cinfo.pck = pck;
 174
 175         return true;
 176 }
 177
 178
 179 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
 180                 void *data)
 181 {
 182         struct dpi_clk_calc_ctx *ctx = data;
 183
 184         ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc;
 185         ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc;
 186
 187         return dispc_div_calc(ctx->dpi->dss->dispc, dispc,
 188                               ctx->pck_min, ctx->pck_max,
 189                               dpi_calc_dispc_cb, ctx);
 190 }
 191
 192
 193 static bool dpi_calc_pll_cb(int n, int m, unsigned long fint,
 194                 unsigned long clkdco,
 195                 void *data)
 196 {
 197         struct dpi_clk_calc_ctx *ctx = data;
 198
 199         ctx->pll_cinfo.n = n;
 200         ctx->pll_cinfo.m = m;
 201         ctx->pll_cinfo.fint = fint;
 202         ctx->pll_cinfo.clkdco = clkdco;
 203
 204         return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco,
 205                 ctx->pck_min, dss_get_max_fck_rate(ctx->dpi->dss),
 206                 dpi_calc_hsdiv_cb, ctx);
 207 }
 208
 209 static bool dpi_calc_dss_cb(unsigned long fck, void *data)
 210 {
 211         struct dpi_clk_calc_ctx *ctx = data;
 212
 213         ctx->fck = fck;
 214
 215         return dispc_div_calc(ctx->dpi->dss->dispc, fck,
 216                               ctx->pck_min, ctx->pck_max,
 217                               dpi_calc_dispc_cb, ctx);
 218 }
 219
 220 static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck,
 221                 struct dpi_clk_calc_ctx *ctx)
 222 {
 223         unsigned long clkin;
 224
 225         memset(ctx, 0, sizeof(*ctx));
 226         ctx->dpi = dpi;
 227         ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src);
 228
 229         clkin = clk_get_rate(dpi->pll->clkin);
 230
 231         if (dpi->pll->hw->type == DSS_PLL_TYPE_A) {
 232                 unsigned long pll_min, pll_max;
 233
 234                 ctx->pck_min = pck - 1000;
 235                 ctx->pck_max = pck + 1000;
 236
 237                 pll_min = 0;
 238                 pll_max = 0;
 239
 240                 return dss_pll_calc_a(ctx->dpi->pll, clkin,
 241                                 pll_min, pll_max,
 242                                 dpi_calc_pll_cb, ctx);
 243         } else { /* DSS_PLL_TYPE_B */
 244                 dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo);
 245
 246                 ctx->dispc_cinfo.lck_div = 1;
 247                 ctx->dispc_cinfo.pck_div = 1;
 248                 ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0];
 249                 ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck;
 250
 251                 return true;
 252         }
 253 }
 254
 255 static bool dpi_dss_clk_calc(struct dpi_data *dpi, unsigned long pck,
 256                              struct dpi_clk_calc_ctx *ctx)
 257 {
 258         int i;
 259
 260         /*
 261          * DSS fck gives us very few possibilities, so finding a good pixel
 262          * clock may not be possible. We try multiple times to find the clock,
 263          * each time widening the pixel clock range we look for, up to
 264          * +/- ~15MHz.
 265          */
 266
 267         for (i = 0; i < 25; ++i) {
 268                 bool ok;
 269
 270                 memset(ctx, 0, sizeof(*ctx));
 271                 ctx->dpi = dpi;
 272                 if (pck > 1000 * i * i * i)
 273                         ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
 274                 else
 275                         ctx->pck_min = 0;
 276                 ctx->pck_max = pck + 1000 * i * i * i;
 277
 278                 ok = dss_div_calc(dpi->dss, pck, ctx->pck_min,
 279                                   dpi_calc_dss_cb, ctx);
 280                 if (ok)
 281                         return ok;
 282         }
 283
 284         return false;
 285 }
 286
 287
 288
 289 static int dpi_set_pll_clk(struct dpi_data *dpi, unsigned long pck_req)
 290 {
 291         struct dpi_clk_calc_ctx ctx;
 292         int r;
 293         bool ok;
 294
 295         ok = dpi_pll_clk_calc(dpi, pck_req, &ctx);
 296         if (!ok)
 297                 return -EINVAL;
 298
 299         r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo);
 300         if (r)
 301                 return r;
 302
 303         dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel,
 304                                   dpi->clk_src);
 305
 306         dpi->mgr_config.clock_info = ctx.dispc_cinfo;
 307
 308         return 0;
 309 }
 310
 311 static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req)
 312 {
 313         struct dpi_clk_calc_ctx ctx;
 314         int r;
 315         bool ok;
 316
 317         ok = dpi_dss_clk_calc(dpi, pck_req, &ctx);
 318         if (!ok)
 319                 return -EINVAL;
 320
 321         r = dss_set_fck_rate(dpi->dss, ctx.fck);
 322         if (r)
 323                 return r;
 324
 325         dpi->mgr_config.clock_info = ctx.dispc_cinfo;
 326
 327         return 0;
 328 }
 329
 330 static int dpi_set_mode(struct dpi_data *dpi)
 331 {
 332         int r;
 333
 334         if (dpi->pll)
 335                 r = dpi_set_pll_clk(dpi, dpi->pixelclock);
 336         else
 337                 r = dpi_set_dispc_clk(dpi, dpi->pixelclock);
 338
 339         return r;
 340 }
 341
 342 static void dpi_config_lcd_manager(struct dpi_data *dpi)
 343 {
 344         dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
 345
 346         dpi->mgr_config.stallmode = false;
 347         dpi->mgr_config.fifohandcheck = false;
 348
 349         dpi->mgr_config.video_port_width = dpi->data_lines;
 350
 351         dpi->mgr_config.lcden_sig_polarity = 0;
 352
 353         dss_mgr_set_lcd_config(&dpi->output, &dpi->mgr_config);
 354 }
 355
 356 static int dpi_clock_update(struct dpi_data *dpi, unsigned long *clock)
 357 {
 358         int lck_div, pck_div;
 359         unsigned long fck;
 360         struct dpi_clk_calc_ctx ctx;
 361
 362         if (dpi->pll) {
 363                 if (!dpi_pll_clk_calc(dpi, *clock, &ctx))
 364                         return -EINVAL;
 365
 366                 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx];
 367         } else {
 368                 if (!dpi_dss_clk_calc(dpi, *clock, &ctx))
 369                         return -EINVAL;
 370
 371                 fck = ctx.fck;
 372         }
 373
 374         lck_div = ctx.dispc_cinfo.lck_div;
 375         pck_div = ctx.dispc_cinfo.pck_div;
 376
 377         *clock = fck / lck_div / pck_div;
 378
 379         return 0;
 380 }
 381
 382 static int dpi_verify_pll(struct dss_pll *pll)
 383 {
 384         int r;
 385
 386         /* do initial setup with the PLL to see if it is operational */
 387
 388         r = dss_pll_enable(pll);
 389         if (r)
 390                 return r;
 391
 392         dss_pll_disable(pll);
 393
 394         return 0;
 395 }
 396
 397 static void dpi_init_pll(struct dpi_data *dpi)
 398 {
 399         struct dss_pll *pll;
 400
 401         if (dpi->pll)
 402                 return;
 403
 404         dpi->clk_src = dpi_get_clk_src(dpi);
 405
 406         pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src);
 407         if (!pll)
 408                 return;
 409
 410         if (dpi_verify_pll(pll)) {
 411                 DSSWARN("PLL not operational\n");
 412                 return;
 413         }
 414
 415         dpi->pll = pll;
 416 }
 417
 418 /* -----------------------------------------------------------------------------
 419  * DRM Bridge Operations
 420  */
 421
 422 static int dpi_bridge_attach(struct drm_bridge *bridge,
 423                              enum drm_bridge_attach_flags flags)
 424 {
 425         struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
 426
 427         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
 428                 return -EINVAL;
 429
 430         dpi_init_pll(dpi);
 431
 432         return drm_bridge_attach(bridge->encoder, dpi->output.next_bridge,
 433                                  bridge, flags);
 434 }
 435
 436 static enum drm_mode_status
 437 dpi_bridge_mode_valid(struct drm_bridge *bridge,
 438                        const struct drm_display_info *info,
 439                        const struct drm_display_mode *mode)
 440 {
 441         struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
 442         unsigned long clock = mode->clock * 1000;
 443         int ret;
 444
 445         if (mode->hdisplay % 8 != 0)
 446                 return MODE_BAD_WIDTH;
 447
 448         if (mode->clock == 0)
 449                 return MODE_NOCLOCK;
 450
 451         ret = dpi_clock_update(dpi, &clock);
 452         if (ret < 0)
 453                 return MODE_CLOCK_RANGE;
 454
 455         return MODE_OK;
 456 }
 457
 458 static bool dpi_bridge_mode_fixup(struct drm_bridge *bridge,
 459                                    const struct drm_display_mode *mode,
 460                                    struct drm_display_mode *adjusted_mode)
 461 {
 462         struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
 463         unsigned long clock = mode->clock * 1000;
 464         int ret;
 465
 466         ret = dpi_clock_update(dpi, &clock);
 467         if (ret < 0)
 468                 return false;
 469
 470         adjusted_mode->clock = clock / 1000;
 471
 472         return true;
 473 }
 474
 475 static void dpi_bridge_mode_set(struct drm_bridge *bridge,
 476                                  const struct drm_display_mode *mode,
 477                                  const struct drm_display_mode *adjusted_mode)
 478 {
 479         struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
 480
 481         dpi->pixelclock = adjusted_mode->clock * 1000;
 482 }
 483
 484 static void dpi_bridge_enable(struct drm_bridge *bridge)
 485 {
 486         struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
 487         int r;
 488
 489         if (dpi->vdds_dsi_reg) {
 490                 r = regulator_enable(dpi->vdds_dsi_reg);
 491                 if (r)
 492                         return;
 493         }
 494
 495         r = dispc_runtime_get(dpi->dss->dispc);
 496         if (r)
 497                 goto err_get_dispc;
 498
 499         r = dss_dpi_select_source(dpi->dss, dpi->id, dpi->output.dispc_channel);
 500         if (r)
 501                 goto err_src_sel;
 502
 503         if (dpi->pll) {
 504                 r = dss_pll_enable(dpi->pll);
 505                 if (r)
 506                         goto err_pll_init;
 507         }
 508
 509         r = dpi_set_mode(dpi);
 510         if (r)
 511                 goto err_set_mode;
 512
 513         dpi_config_lcd_manager(dpi);
 514
 515         mdelay(2);
 516
 517         r = dss_mgr_enable(&dpi->output);
 518         if (r)
 519                 goto err_mgr_enable;
 520
 521         return;
 522
 523 err_mgr_enable:
 524 err_set_mode:
 525         if (dpi->pll)
 526                 dss_pll_disable(dpi->pll);
 527 err_pll_init:
 528 err_src_sel:
 529         dispc_runtime_put(dpi->dss->dispc);
 530 err_get_dispc:
 531         if (dpi->vdds_dsi_reg)
 532                 regulator_disable(dpi->vdds_dsi_reg);
 533 }
 534
 535 static void dpi_bridge_disable(struct drm_bridge *bridge)
 536 {
 537         struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
 538
 539         dss_mgr_disable(&dpi->output);
 540
 541         if (dpi->pll) {
 542                 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel,
 543                                           DSS_CLK_SRC_FCK);
 544                 dss_pll_disable(dpi->pll);
 545         }
 546
 547         dispc_runtime_put(dpi->dss->dispc);
 548
 549         if (dpi->vdds_dsi_reg)
 550                 regulator_disable(dpi->vdds_dsi_reg);
 551 }
 552
 553 static const struct drm_bridge_funcs dpi_bridge_funcs = {
 554         .attach = dpi_bridge_attach,
 555         .mode_valid = dpi_bridge_mode_valid,
 556         .mode_fixup = dpi_bridge_mode_fixup,
 557         .mode_set = dpi_bridge_mode_set,
 558         .enable = dpi_bridge_enable,
 559         .disable = dpi_bridge_disable,
 560 };
 561
 562 static void dpi_bridge_init(struct dpi_data *dpi)
 563 {
 564         dpi->bridge.funcs = &dpi_bridge_funcs;
 565         dpi->bridge.of_node = dpi->pdev->dev.of_node;
 566         dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
 567
 568         drm_bridge_add(&dpi->bridge);
 569 }
 570
 571 static void dpi_bridge_cleanup(struct dpi_data *dpi)
 572 {
 573         drm_bridge_remove(&dpi->bridge);
 574 }
 575
 576 /* -----------------------------------------------------------------------------
 577  * Initialisation and Cleanup
 578  */
 579
 580 /*
 581  * Return a hardcoded channel for the DPI output. This should work for
 582  * current use cases, but this can be later expanded to either resolve
 583  * the channel in some more dynamic manner, or get the channel as a user
 584  * parameter.
 585  */
 586 static enum omap_channel dpi_get_channel(struct dpi_data *dpi)
 587 {
 588         switch (dpi->dss_model) {
 589         case DSS_MODEL_OMAP2:
 590         case DSS_MODEL_OMAP3:
 591                 return OMAP_DSS_CHANNEL_LCD;
 592
 593         case DSS_MODEL_DRA7:
 594                 switch (dpi->id) {
 595                 case 2:
 596                         return OMAP_DSS_CHANNEL_LCD3;
 597                 case 1:
 598                         return OMAP_DSS_CHANNEL_LCD2;
 599                 case 0:
 600                 default:
 601                         return OMAP_DSS_CHANNEL_LCD;
 602                 }
 603
 604         case DSS_MODEL_OMAP4:
 605                 return OMAP_DSS_CHANNEL_LCD2;
 606
 607         case DSS_MODEL_OMAP5:
 608                 return OMAP_DSS_CHANNEL_LCD3;
 609
 610         default:
 611                 DSSWARN("unsupported DSS version\n");
 612                 return OMAP_DSS_CHANNEL_LCD;
 613         }
 614 }
 615
 616 static int dpi_init_output_port(struct dpi_data *dpi, struct device_node *port)
 617 {
 618         struct omap_dss_device *out = &dpi->output;
 619         u32 port_num = 0;
 620         int r;
 621
 622         dpi_bridge_init(dpi);
 623
 624         of_property_read_u32(port, "reg", &port_num);
 625         dpi->id = port_num <= 2 ? port_num : 0;
 626
 627         switch (port_num) {
 628         case 2:
 629                 out->name = "dpi.2";
 630                 break;
 631         case 1:
 632                 out->name = "dpi.1";
 633                 break;
 634         case 0:
 635         default:
 636                 out->name = "dpi.0";
 637                 break;
 638         }
 639
 640         out->dev = &dpi->pdev->dev;
 641         out->id = OMAP_DSS_OUTPUT_DPI;
 642         out->type = OMAP_DISPLAY_TYPE_DPI;
 643         out->dispc_channel = dpi_get_channel(dpi);
 644         out->of_port = port_num;
 645
 646         r = omapdss_device_init_output(out, &dpi->bridge);
 647         if (r < 0) {
 648                 dpi_bridge_cleanup(dpi);
 649                 return r;
 650         }
 651
 652         omapdss_device_register(out);
 653
 654         return 0;
 655 }
 656
 657 static void dpi_uninit_output_port(struct device_node *port)
 658 {
 659         struct dpi_data *dpi = port->data;
 660         struct omap_dss_device *out = &dpi->output;
 661
 662         omapdss_device_unregister(out);
 663         omapdss_device_cleanup_output(out);
 664
 665         dpi_bridge_cleanup(dpi);
 666 }
 667
 668 /* -----------------------------------------------------------------------------
 669  * Initialisation and Cleanup
 670  */
 671
 672 static const struct soc_device_attribute dpi_soc_devices[] = {
 673         { .machine = "OMAP3[456]*" },
 674         { .machine = "[AD]M37*" },
 675         { /* sentinel */ }
 676 };
 677
 678 static int dpi_init_regulator(struct dpi_data *dpi)
 679 {
 680         struct regulator *vdds_dsi;
 681
 682         /*
 683          * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and
 684          * DM37xx only.
 685          */
 686         if (!soc_device_match(dpi_soc_devices))
 687                 return 0;
 688
 689         vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi");
 690         if (IS_ERR(vdds_dsi)) {
 691                 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
 692                         DSSERR("can't get VDDS_DSI regulator\n");
 693                 return PTR_ERR(vdds_dsi);
 694         }
 695
 696         dpi->vdds_dsi_reg = vdds_dsi;
 697
 698         return 0;
 699 }
 700
 701 int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
 702                   struct device_node *port, enum dss_model dss_model)
 703 {
 704         struct dpi_data *dpi;
 705         struct device_node *ep;
 706         u32 datalines;
 707         int r;
 708
 709         dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
 710         if (!dpi)
 711                 return -ENOMEM;
 712
 713         ep = of_graph_get_next_port_endpoint(port, NULL);
 714         if (!ep)
 715                 return 0;
 716
 717         r = of_property_read_u32(ep, "data-lines", &datalines);
 718         of_node_put(ep);
 719         if (r) {
 720                 DSSERR("failed to parse datalines\n");
 721                 return r;
 722         }
 723
 724         dpi->data_lines = datalines;
 725
 726         dpi->pdev = pdev;
 727         dpi->dss_model = dss_model;
 728         dpi->dss = dss;
 729         port->data = dpi;
 730
 731         r = dpi_init_regulator(dpi);
 732         if (r)
 733                 return r;
 734
 735         return dpi_init_output_port(dpi, port);
 736 }
 737
 738 void dpi_uninit_port(struct device_node *port)
 739 {
 740         struct dpi_data *dpi = port->data;
 741
 742         if (!dpi)
 743                 return;
 744
 745         dpi_uninit_output_port(port);
 746 }