drivers/gpu/drm/i915/vlv_suspend.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <linux/string_helpers.h>
   7 #include <linux/kernel.h>
   8
   9 #include <drm/drm_print.h>
  10
  11 #include "i915_drv.h"
  12 #include "i915_reg.h"
  13 #include "i915_trace.h"
  14 #include "i915_utils.h"
  15 #include "intel_clock_gating.h"
  16 #include "intel_uncore_trace.h"
  17 #include "vlv_suspend.h"
  18
  19 #include "gt/intel_gt_regs.h"
  20
  21 struct vlv_s0ix_state {
  22         /* GAM */
  23         u32 wr_watermark;
  24         u32 gfx_prio_ctrl;
  25         u32 arb_mode;
  26         u32 gfx_pend_tlb0;
  27         u32 gfx_pend_tlb1;
  28         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
  29         u32 media_max_req_count;
  30         u32 gfx_max_req_count;
  31         u32 render_hwsp;
  32         u32 ecochk;
  33         u32 bsd_hwsp;
  34         u32 blt_hwsp;
  35         u32 tlb_rd_addr;
  36
  37         /* MBC */
  38         u32 g3dctl;
  39         u32 gsckgctl;
  40         u32 mbctl;
  41
  42         /* GCP */
  43         u32 ucgctl1;
  44         u32 ucgctl3;
  45         u32 rcgctl1;
  46         u32 rcgctl2;
  47         u32 rstctl;
  48         u32 misccpctl;
  49
  50         /* GPM */
  51         u32 gfxpause;
  52         u32 rpdeuhwtc;
  53         u32 rpdeuc;
  54         u32 ecobus;
  55         u32 pwrdwnupctl;
  56         u32 rp_down_timeout;
  57         u32 rp_deucsw;
  58         u32 rcubmabdtmr;
  59         u32 rcedata;
  60         u32 spare2gh;
  61
  62         /* Display 1 CZ domain */
  63         u32 gt_imr;
  64         u32 gt_ier;
  65         u32 pm_imr;
  66         u32 pm_ier;
  67         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
  68
  69         /* GT SA CZ domain */
  70         u32 tilectl;
  71         u32 gt_fifoctl;
  72         u32 gtlc_wake_ctrl;
  73         u32 gtlc_survive;
  74         u32 pmwgicz;
  75
  76         /* Display 2 CZ domain */
  77         u32 gu_ctl0;
  78         u32 gu_ctl1;
  79         u32 pcbr;
  80         u32 clock_gate_dis2;
  81 };
  82
  83 /*
  84  * Save all Gunit registers that may be lost after a D3 and a subsequent
  85  * S0i[R123] transition. The list of registers needing a save/restore is
  86  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
  87  * registers in the following way:
  88  * - Driver: saved/restored by the driver
  89  * - Punit : saved/restored by the Punit firmware
  90  * - No, w/o marking: no need to save/restore, since the register is R/O or
  91  *                    used internally by the HW in a way that doesn't depend
  92  *                    keeping the content across a suspend/resume.
  93  * - Debug : used for debugging
  94  *
  95  * We save/restore all registers marked with 'Driver', with the following
  96  * exceptions:
  97  * - Registers out of use, including also registers marked with 'Debug'.
  98  *   These have no effect on the driver's operation, so we don't save/restore
  99  *   them to reduce the overhead.
 100  * - Registers that are fully setup by an initialization function called from
 101  *   the resume path. For example many clock gating and RPS/RC6 registers.
 102  * - Registers that provide the right functionality with their reset defaults.
 103  *
 104  * TODO: Except for registers that based on the above 3 criteria can be safely
 105  * ignored, we save/restore all others, practically treating the HW context as
 106  * a black-box for the driver. Further investigation is needed to reduce the
 107  * saved/restored registers even further, by following the same 3 criteria.
 108  */
 109 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *i915)
 110 {
 111         struct vlv_s0ix_state *s = i915->vlv_s0ix_state;
 112         struct intel_uncore *uncore = &i915->uncore;
 113         int i;
 114
 115         if (!s)
 116                 return;
 117
 118         /* GAM 0x4000-0x4770 */
 119         s->wr_watermark = intel_uncore_read(uncore, GEN7_WR_WATERMARK);
 120         s->gfx_prio_ctrl = intel_uncore_read(uncore, GEN7_GFX_PRIO_CTRL);
 121         s->arb_mode = intel_uncore_read(uncore, ARB_MODE);
 122         s->gfx_pend_tlb0 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB0);
 123         s->gfx_pend_tlb1 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB1);
 124
 125         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
 126                 s->lra_limits[i] = intel_uncore_read(uncore, GEN7_LRA_LIMITS(i));
 127
 128         s->media_max_req_count = intel_uncore_read(uncore, GEN7_MEDIA_MAX_REQ_COUNT);
 129         s->gfx_max_req_count = intel_uncore_read(uncore, GEN7_GFX_MAX_REQ_COUNT);
 130
 131         s->render_hwsp = intel_uncore_read(uncore, RENDER_HWS_PGA_GEN7);
 132         s->ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
 133         s->bsd_hwsp = intel_uncore_read(uncore, BSD_HWS_PGA_GEN7);
 134         s->blt_hwsp = intel_uncore_read(uncore, BLT_HWS_PGA_GEN7);
 135
 136         s->tlb_rd_addr = intel_uncore_read(uncore, GEN7_TLB_RD_ADDR);
 137
 138         /* MBC 0x9024-0x91D0, 0x8500 */
 139         s->g3dctl = intel_uncore_read(uncore, VLV_G3DCTL);
 140         s->gsckgctl = intel_uncore_read(uncore, VLV_GSCKGCTL);
 141         s->mbctl = intel_uncore_read(uncore, GEN6_MBCTL);
 142
 143         /* GCP 0x9400-0x9424, 0x8100-0x810C */
 144         s->ucgctl1 = intel_uncore_read(uncore, GEN6_UCGCTL1);
 145         s->ucgctl3 = intel_uncore_read(uncore, GEN6_UCGCTL3);
 146         s->rcgctl1 = intel_uncore_read(uncore, GEN6_RCGCTL1);
 147         s->rcgctl2 = intel_uncore_read(uncore, GEN6_RCGCTL2);
 148         s->rstctl = intel_uncore_read(uncore, GEN6_RSTCTL);
 149         s->misccpctl = intel_uncore_read(uncore, GEN7_MISCCPCTL);
 150
 151         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
 152         s->gfxpause = intel_uncore_read(uncore, GEN6_GFXPAUSE);
 153         s->rpdeuhwtc = intel_uncore_read(uncore, GEN6_RPDEUHWTC);
 154         s->rpdeuc = intel_uncore_read(uncore, GEN6_RPDEUC);
 155         s->ecobus = intel_uncore_read(uncore, ECOBUS);
 156         s->pwrdwnupctl = intel_uncore_read(uncore, VLV_PWRDWNUPCTL);
 157         s->rp_down_timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_TIMEOUT);
 158         s->rp_deucsw = intel_uncore_read(uncore, GEN6_RPDEUCSW);
 159         s->rcubmabdtmr = intel_uncore_read(uncore, GEN6_RCUBMABDTMR);
 160         s->rcedata = intel_uncore_read(uncore, VLV_RCEDATA);
 161         s->spare2gh = intel_uncore_read(uncore, VLV_SPAREG2H);
 162
 163         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
 164         s->gt_imr = intel_uncore_read(uncore, GTIMR);
 165         s->gt_ier = intel_uncore_read(uncore, GTIER);
 166         s->pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
 167         s->pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
 168
 169         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
 170                 s->gt_scratch[i] = intel_uncore_read(uncore, GEN7_GT_SCRATCH(i));
 171
 172         /* GT SA CZ domain, 0x100000-0x138124 */
 173         s->tilectl = intel_uncore_read(uncore, TILECTL);
 174         s->gt_fifoctl = intel_uncore_read(uncore, GTFIFOCTL);
 175         s->gtlc_wake_ctrl = intel_uncore_read(uncore, VLV_GTLC_WAKE_CTRL);
 176         s->gtlc_survive = intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG);
 177         s->pmwgicz = intel_uncore_read(uncore, VLV_PMWGICZ);
 178
 179         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
 180         s->gu_ctl0 = intel_uncore_read(uncore, VLV_GU_CTL0);
 181         s->gu_ctl1 = intel_uncore_read(uncore, VLV_GU_CTL1);
 182         s->pcbr = intel_uncore_read(uncore, VLV_PCBR);
 183         s->clock_gate_dis2 = intel_uncore_read(uncore, VLV_GUNIT_CLOCK_GATE2);
 184
 185         /*
 186          * Not saving any of:
 187          * DFT,         0x9800-0x9EC0
 188          * SARB,        0xB000-0xB1FC
 189          * GAC,         0x5208-0x524C, 0x14000-0x14C000
 190          * PCI CFG
 191          */
 192 }
 193
 194 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *i915)
 195 {
 196         struct vlv_s0ix_state *s = i915->vlv_s0ix_state;
 197         struct intel_uncore *uncore = &i915->uncore;
 198         int i;
 199
 200         if (!s)
 201                 return;
 202
 203         /* GAM 0x4000-0x4770 */
 204         intel_uncore_write(uncore, GEN7_WR_WATERMARK, s->wr_watermark);
 205         intel_uncore_write(uncore, GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
 206         intel_uncore_write(uncore, ARB_MODE, s->arb_mode | (0xffff << 16));
 207         intel_uncore_write(uncore, GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
 208         intel_uncore_write(uncore, GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
 209
 210         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
 211                 intel_uncore_write(uncore, GEN7_LRA_LIMITS(i), s->lra_limits[i]);
 212
 213         intel_uncore_write(uncore, GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
 214         intel_uncore_write(uncore, GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
 215
 216         intel_uncore_write(uncore, RENDER_HWS_PGA_GEN7, s->render_hwsp);
 217         intel_uncore_write(uncore, GAM_ECOCHK, s->ecochk);
 218         intel_uncore_write(uncore, BSD_HWS_PGA_GEN7, s->bsd_hwsp);
 219         intel_uncore_write(uncore, BLT_HWS_PGA_GEN7, s->blt_hwsp);
 220
 221         intel_uncore_write(uncore, GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
 222
 223         /* MBC 0x9024-0x91D0, 0x8500 */
 224         intel_uncore_write(uncore, VLV_G3DCTL, s->g3dctl);
 225         intel_uncore_write(uncore, VLV_GSCKGCTL, s->gsckgctl);
 226         intel_uncore_write(uncore, GEN6_MBCTL, s->mbctl);
 227
 228         /* GCP 0x9400-0x9424, 0x8100-0x810C */
 229         intel_uncore_write(uncore, GEN6_UCGCTL1, s->ucgctl1);
 230         intel_uncore_write(uncore, GEN6_UCGCTL3, s->ucgctl3);
 231         intel_uncore_write(uncore, GEN6_RCGCTL1, s->rcgctl1);
 232         intel_uncore_write(uncore, GEN6_RCGCTL2, s->rcgctl2);
 233         intel_uncore_write(uncore, GEN6_RSTCTL, s->rstctl);
 234         intel_uncore_write(uncore, GEN7_MISCCPCTL, s->misccpctl);
 235
 236         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
 237         intel_uncore_write(uncore, GEN6_GFXPAUSE, s->gfxpause);
 238         intel_uncore_write(uncore, GEN6_RPDEUHWTC, s->rpdeuhwtc);
 239         intel_uncore_write(uncore, GEN6_RPDEUC, s->rpdeuc);
 240         intel_uncore_write(uncore, ECOBUS, s->ecobus);
 241         intel_uncore_write(uncore, VLV_PWRDWNUPCTL, s->pwrdwnupctl);
 242         intel_uncore_write(uncore, GEN6_RP_DOWN_TIMEOUT, s->rp_down_timeout);
 243         intel_uncore_write(uncore, GEN6_RPDEUCSW, s->rp_deucsw);
 244         intel_uncore_write(uncore, GEN6_RCUBMABDTMR, s->rcubmabdtmr);
 245         intel_uncore_write(uncore, VLV_RCEDATA, s->rcedata);
 246         intel_uncore_write(uncore, VLV_SPAREG2H, s->spare2gh);
 247
 248         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
 249         intel_uncore_write(uncore, GTIMR, s->gt_imr);
 250         intel_uncore_write(uncore, GTIER, s->gt_ier);
 251         intel_uncore_write(uncore, GEN6_PMIMR, s->pm_imr);
 252         intel_uncore_write(uncore, GEN6_PMIER, s->pm_ier);
 253
 254         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
 255                 intel_uncore_write(uncore, GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
 256
 257         /* GT SA CZ domain, 0x100000-0x138124 */
 258         intel_uncore_write(uncore, TILECTL, s->tilectl);
 259         intel_uncore_write(uncore, GTFIFOCTL, s->gt_fifoctl);
 260         /*
 261          * Preserve the GT allow wake and GFX force clock bit, they are not
 262          * be restored, as they are used to control the s0ix suspend/resume
 263          * sequence by the caller.
 264          */
 265         intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, ~VLV_GTLC_ALLOWWAKEREQ,
 266                          s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ);
 267
 268         intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG, ~VLV_GFX_CLK_FORCE_ON_BIT,
 269                          s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT);
 270
 271         intel_uncore_write(uncore, VLV_PMWGICZ, s->pmwgicz);
 272
 273         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
 274         intel_uncore_write(uncore, VLV_GU_CTL0, s->gu_ctl0);
 275         intel_uncore_write(uncore, VLV_GU_CTL1, s->gu_ctl1);
 276         intel_uncore_write(uncore, VLV_PCBR, s->pcbr);
 277         intel_uncore_write(uncore, VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
 278 }
 279
 280 static int vlv_wait_for_pw_status(struct drm_i915_private *i915,
 281                                   u32 mask, u32 val)
 282 {
 283         i915_reg_t reg = VLV_GTLC_PW_STATUS;
 284         u32 reg_value;
 285         int ret;
 286
 287         /* The HW does not like us polling for PW_STATUS frequently, so
 288          * use the sleeping loop rather than risk the busy spin within
 289          * intel_wait_for_register().
 290          *
 291          * Transitioning between RC6 states should be at most 2ms (see
 292          * valleyview_enable_rps) so use a 3ms timeout.
 293          */
 294         ret = wait_for(((reg_value =
 295                          intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
 296                        == val, 3);
 297
 298         /* just trace the final value */
 299         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
 300
 301         return ret;
 302 }
 303
 304 static int vlv_force_gfx_clock(struct drm_i915_private *i915, bool force_on)
 305 {
 306         struct intel_uncore *uncore = &i915->uncore;
 307         int err;
 308
 309         intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG, VLV_GFX_CLK_FORCE_ON_BIT,
 310                          force_on ? VLV_GFX_CLK_FORCE_ON_BIT : 0);
 311
 312         if (!force_on)
 313                 return 0;
 314
 315         err = intel_wait_for_register(uncore,
 316                                       VLV_GTLC_SURVIVABILITY_REG,
 317                                       VLV_GFX_CLK_STATUS_BIT,
 318                                       VLV_GFX_CLK_STATUS_BIT,
 319                                       20);
 320         if (err)
 321                 drm_err(&i915->drm,
 322                         "timeout waiting for GFX clock force-on (%08x)\n",
 323                         intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG));
 324
 325         return err;
 326 }
 327
 328 static int vlv_allow_gt_wake(struct drm_i915_private *i915, bool allow)
 329 {
 330         struct intel_uncore *uncore = &i915->uncore;
 331         u32 mask;
 332         u32 val;
 333         int err;
 334
 335         intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ,
 336                          allow ? VLV_GTLC_ALLOWWAKEREQ : 0);
 337         intel_uncore_posting_read(uncore, VLV_GTLC_WAKE_CTRL);
 338
 339         mask = VLV_GTLC_ALLOWWAKEACK;
 340         val = allow ? mask : 0;
 341
 342         err = vlv_wait_for_pw_status(i915, mask, val);
 343         if (err)
 344                 drm_err(&i915->drm, "timeout disabling GT waking\n");
 345
 346         return err;
 347 }
 348
 349 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
 350                                   bool wait_for_on)
 351 {
 352         u32 mask;
 353         u32 val;
 354
 355         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
 356         val = wait_for_on ? mask : 0;
 357
 358         /*
 359          * RC6 transitioning can be delayed up to 2 msec (see
 360          * valleyview_enable_rps), use 3 msec for safety.
 361          *
 362          * This can fail to turn off the rc6 if the GPU is stuck after a failed
 363          * reset and we are trying to force the machine to sleep.
 364          */
 365         if (vlv_wait_for_pw_status(dev_priv, mask, val))
 366                 drm_dbg(&dev_priv->drm,
 367                         "timeout waiting for GT wells to go %s\n",
 368                         str_on_off(wait_for_on));
 369 }
 370
 371 static void vlv_check_no_gt_access(struct drm_i915_private *i915)
 372 {
 373         struct intel_uncore *uncore = &i915->uncore;
 374
 375         if (!(intel_uncore_read(uncore, VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
 376                 return;
 377
 378         drm_dbg(&i915->drm, "GT register access while GT waking disabled\n");
 379         intel_uncore_write(uncore, VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
 380 }
 381
 382 int vlv_suspend_complete(struct drm_i915_private *dev_priv)
 383 {
 384         u32 mask;
 385         int err;
 386
 387         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
 388                 return 0;
 389
 390         /*
 391          * Bspec defines the following GT well on flags as debug only, so
 392          * don't treat them as hard failures.
 393          */
 394         vlv_wait_for_gt_wells(dev_priv, false);
 395
 396         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
 397         drm_WARN_ON(&dev_priv->drm,
 398                     (intel_uncore_read(&dev_priv->uncore, VLV_GTLC_WAKE_CTRL) & mask) != mask);
 399
 400         vlv_check_no_gt_access(dev_priv);
 401
 402         err = vlv_force_gfx_clock(dev_priv, true);
 403         if (err)
 404                 goto err1;
 405
 406         err = vlv_allow_gt_wake(dev_priv, false);
 407         if (err)
 408                 goto err2;
 409
 410         vlv_save_gunit_s0ix_state(dev_priv);
 411
 412         err = vlv_force_gfx_clock(dev_priv, false);
 413         if (err)
 414                 goto err2;
 415
 416         return 0;
 417
 418 err2:
 419         /* For safety always re-enable waking and disable gfx clock forcing */
 420         vlv_allow_gt_wake(dev_priv, true);
 421 err1:
 422         vlv_force_gfx_clock(dev_priv, false);
 423
 424         return err;
 425 }
 426
 427 int vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume)
 428 {
 429         int err;
 430         int ret;
 431
 432         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
 433                 return 0;
 434
 435         /*
 436          * If any of the steps fail just try to continue, that's the best we
 437          * can do at this point. Return the first error code (which will also
 438          * leave RPM permanently disabled).
 439          */
 440         ret = vlv_force_gfx_clock(dev_priv, true);
 441
 442         vlv_restore_gunit_s0ix_state(dev_priv);
 443
 444         err = vlv_allow_gt_wake(dev_priv, true);
 445         if (!ret)
 446                 ret = err;
 447
 448         err = vlv_force_gfx_clock(dev_priv, false);
 449         if (!ret)
 450                 ret = err;
 451
 452         vlv_check_no_gt_access(dev_priv);
 453
 454         if (rpm_resume)
 455                 intel_clock_gating_init(dev_priv);
 456
 457         return ret;
 458 }
 459
 460 int vlv_suspend_init(struct drm_i915_private *i915)
 461 {
 462         if (!IS_VALLEYVIEW(i915))
 463                 return 0;
 464
 465         /* we write all the values in the struct, so no need to zero it out */
 466         i915->vlv_s0ix_state = kmalloc(sizeof(*i915->vlv_s0ix_state),
 467                                        GFP_KERNEL);
 468         if (!i915->vlv_s0ix_state)
 469                 return -ENOMEM;
 470
 471         return 0;
 472 }
 473
 474 void vlv_suspend_cleanup(struct drm_i915_private *i915)
 475 {
 476         if (!i915->vlv_s0ix_state)
 477                 return;
 478
 479         kfree(i915->vlv_s0ix_state);
 480         i915->vlv_s0ix_state = NULL;
 481 }