1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2019 Intel Corporation
6 #include "i915_selftest.h"
7 #include "intel_engine_heartbeat.h"
8 #include "intel_engine_pm.h"
11 #include "gem/selftests/mock_context.h"
12 #include "selftests/igt_flush_test.h"
13 #include "selftests/mock_drm.h"
15 static int request_sync(struct i915_request *rq)
17 struct intel_timeline *tl = i915_request_timeline(rq);
21 intel_timeline_get(tl);
24 /* Opencode i915_request_add() so we can keep the timeline locked. */
25 __i915_request_commit(rq);
26 rq->sched.attr.priority = I915_PRIORITY_BARRIER;
27 __i915_request_queue_bh(rq);
29 timeout = i915_request_wait(rq, 0, HZ / 10);
33 i915_request_retire_upto(rq);
35 lockdep_unpin_lock(&tl->mutex, rq->cookie);
36 mutex_unlock(&tl->mutex);
39 intel_timeline_put(tl);
44 static int context_sync(struct intel_context *ce)
46 struct intel_timeline *tl = ce->timeline;
49 mutex_lock(&tl->mutex);
51 struct i915_request *rq;
54 if (list_empty(&tl->requests))
57 rq = list_last_entry(&tl->requests, typeof(*rq), link);
60 timeout = i915_request_wait(rq, 0, HZ / 10);
64 i915_request_retire_upto(rq);
68 mutex_unlock(&tl->mutex);
70 /* Wait for all barriers to complete (remote CPU) before we check */
71 i915_active_unlock_wait(&ce->active);
75 static int __live_context_size(struct intel_engine_cs *engine)
77 struct intel_context *ce;
78 struct i915_request *rq;
82 ce = intel_context_create(engine);
86 err = intel_context_pin(ce);
90 vaddr = i915_gem_object_pin_map_unlocked(ce->state->obj,
91 intel_gt_coherent_map_type(engine->gt,
96 intel_context_unpin(ce);
101 * Note that execlists also applies a redzone which it checks on
102 * context unpin when debugging. We are using the same location
103 * and same poison value so that our checks overlap. Despite the
104 * redundancy, we want to keep this little selftest so that we
105 * get coverage of any and all submission backends, and we can
106 * always extend this test to ensure we trick the HW into a
107 * compromising position wrt to the various sections that need
108 * to be written into the context state.
110 * TLDR; this overlaps with the execlists redzone.
112 vaddr += engine->context_size - I915_GTT_PAGE_SIZE;
113 memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
115 rq = intel_context_create_request(ce);
116 intel_context_unpin(ce);
122 err = request_sync(rq);
126 /* Force the context switch */
127 rq = intel_engine_create_kernel_request(engine);
132 err = request_sync(rq);
136 if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE)) {
137 pr_err("%s context overwrote trailing red-zone!", engine->name);
142 i915_gem_object_unpin_map(ce->state->obj);
144 intel_context_put(ce);
148 static int live_context_size(void *arg)
150 struct intel_gt *gt = arg;
151 struct intel_engine_cs *engine;
152 enum intel_engine_id id;
156 * Check that our context sizes are correct by seeing if the
157 * HW tries to write past the end of one.
160 for_each_engine(engine, gt, id) {
163 if (!engine->context_size)
166 intel_engine_pm_get(engine);
169 * Hide the old default state -- we lie about the context size
170 * and get confused when the default state is smaller than
171 * expected. For our do nothing request, inheriting the
172 * active state is sufficient, we are only checking that we
173 * don't use more than we planned.
175 saved = fetch_and_zero(&engine->default_state);
177 /* Overlaps with the execlists redzone */
178 engine->context_size += I915_GTT_PAGE_SIZE;
180 err = __live_context_size(engine);
182 engine->context_size -= I915_GTT_PAGE_SIZE;
184 engine->default_state = saved;
186 intel_engine_pm_put(engine);
195 static int __live_active_context(struct intel_engine_cs *engine)
197 unsigned long saved_heartbeat;
198 struct intel_context *ce;
203 * We keep active contexts alive until after a subsequent context
204 * switch as the final write from the context-save will be after
205 * we retire the final request. We track when we unpin the context,
206 * under the presumption that the final pin is from the last request,
207 * and instead of immediately unpinning the context, we add a task
208 * to unpin the context from the next idle-barrier.
210 * This test makes sure that the context is kept alive until a
211 * subsequent idle-barrier (emitted when the engine wakeref hits 0
212 * with no more outstanding requests).
214 * In GuC submission mode we don't use idle barriers and we instead
215 * get a message from the GuC to signal that it is safe to unpin the
216 * context from memory.
218 if (intel_engine_uses_guc(engine))
221 if (intel_engine_pm_is_awake(engine)) {
222 pr_err("%s is awake before starting %s!\n",
223 engine->name, __func__);
227 ce = intel_context_create(engine);
231 saved_heartbeat = engine->props.heartbeat_interval_ms;
232 engine->props.heartbeat_interval_ms = 0;
234 for (pass = 0; pass <= 2; pass++) {
235 struct i915_request *rq;
237 intel_engine_pm_get(engine);
239 rq = intel_context_create_request(ce);
245 err = request_sync(rq);
249 /* Context will be kept active until after an idle-barrier. */
250 if (i915_active_is_idle(&ce->active)) {
251 pr_err("context is not active; expected idle-barrier (%s pass %d)\n",
257 if (!intel_engine_pm_is_awake(engine)) {
258 pr_err("%s is asleep before idle-barrier\n",
265 intel_engine_pm_put(engine);
270 /* Now make sure our idle-barriers are flushed */
271 err = intel_engine_flush_barriers(engine);
275 /* Wait for the barrier and in the process wait for engine to park */
276 err = context_sync(engine->kernel_context);
280 if (!i915_active_is_idle(&ce->active)) {
281 pr_err("context is still active!");
285 intel_engine_pm_flush(engine);
287 if (intel_engine_pm_is_awake(engine)) {
288 struct drm_printer p = drm_dbg_printer(&engine->i915->drm,
289 DRM_UT_DRIVER, NULL);
291 intel_engine_dump(engine, &p,
292 "%s is still awake:%d after idle-barriers\n",
294 atomic_read(&engine->wakeref.count));
302 engine->props.heartbeat_interval_ms = saved_heartbeat;
303 intel_context_put(ce);
307 static int live_active_context(void *arg)
309 struct intel_gt *gt = arg;
310 struct intel_engine_cs *engine;
311 enum intel_engine_id id;
314 for_each_engine(engine, gt, id) {
315 err = __live_active_context(engine);
319 err = igt_flush_test(gt->i915);
327 static int __remote_sync(struct intel_context *ce, struct intel_context *remote)
329 struct i915_request *rq;
332 err = intel_context_pin(remote);
336 rq = intel_context_create_request(ce);
342 err = intel_context_prepare_remote_request(remote, rq);
344 i915_request_add(rq);
348 err = request_sync(rq);
351 intel_context_unpin(remote);
355 static int __live_remote_context(struct intel_engine_cs *engine)
357 struct intel_context *local, *remote;
358 unsigned long saved_heartbeat;
363 * Check that our idle barriers do not interfere with normal
364 * activity tracking. In particular, check that operating
365 * on the context image remotely (intel_context_prepare_remote_request),
366 * which inserts foreign fences into intel_context.active, does not
367 * clobber the idle-barrier.
369 * In GuC submission mode we don't use idle barriers.
371 if (intel_engine_uses_guc(engine))
374 if (intel_engine_pm_is_awake(engine)) {
375 pr_err("%s is awake before starting %s!\n",
376 engine->name, __func__);
380 remote = intel_context_create(engine);
382 return PTR_ERR(remote);
384 local = intel_context_create(engine);
386 err = PTR_ERR(local);
390 saved_heartbeat = engine->props.heartbeat_interval_ms;
391 engine->props.heartbeat_interval_ms = 0;
392 intel_engine_pm_get(engine);
394 for (pass = 0; pass <= 2; pass++) {
395 err = __remote_sync(local, remote);
399 err = __remote_sync(engine->kernel_context, remote);
403 if (i915_active_is_idle(&remote->active)) {
404 pr_err("remote context is not active; expected idle-barrier (%s pass %d)\n",
411 intel_engine_pm_put(engine);
412 engine->props.heartbeat_interval_ms = saved_heartbeat;
414 intel_context_put(local);
416 intel_context_put(remote);
420 static int live_remote_context(void *arg)
422 struct intel_gt *gt = arg;
423 struct intel_engine_cs *engine;
424 enum intel_engine_id id;
427 for_each_engine(engine, gt, id) {
428 err = __live_remote_context(engine);
432 err = igt_flush_test(gt->i915);
440 int intel_context_live_selftests(struct drm_i915_private *i915)
442 static const struct i915_subtest tests[] = {
443 SUBTEST(live_context_size),
444 SUBTEST(live_active_context),
445 SUBTEST(live_remote_context),
447 struct intel_gt *gt = to_gt(i915);
449 if (intel_gt_is_wedged(gt))
452 return intel_gt_live_subtests(tests, gt);