drivers/gpu/drm/i915/display/intel_vbt_defs.h

   1 /*
   2  * Copyright © 2006-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *
  26  */
  27
  28 /*
  29  * This information is private to VBT parsing in intel_bios.c.
  30  *
  31  * Please do NOT include anywhere else.
  32  */
  33 #ifndef _INTEL_BIOS_PRIVATE
  34 #error "intel_vbt_defs.h is private to intel_bios.c"
  35 #endif
  36
  37 #ifndef _INTEL_VBT_DEFS_H_
  38 #define _INTEL_VBT_DEFS_H_
  39
  40 #include "intel_bios.h"
  41
  42 /* EDID derived structures */
  43 struct bdb_edid_pnp_id {
  44         u16 mfg_name;
  45         u16 product_code;
  46         u32 serial;
  47         u8 mfg_week;
  48         u8 mfg_year;
  49 } __packed;
  50
  51 struct bdb_edid_product_name {
  52         char name[13];
  53 } __packed;
  54
  55 struct bdb_edid_dtd {
  56         u16 clock;              /**< In 10khz */
  57         u8 hactive_lo;
  58         u8 hblank_lo;
  59         u8 hblank_hi:4;
  60         u8 hactive_hi:4;
  61         u8 vactive_lo;
  62         u8 vblank_lo;
  63         u8 vblank_hi:4;
  64         u8 vactive_hi:4;
  65         u8 hsync_off_lo;
  66         u8 hsync_pulse_width_lo;
  67         u8 vsync_pulse_width_lo:4;
  68         u8 vsync_off_lo:4;
  69         u8 vsync_pulse_width_hi:2;
  70         u8 vsync_off_hi:2;
  71         u8 hsync_pulse_width_hi:2;
  72         u8 hsync_off_hi:2;
  73         u8 himage_lo;
  74         u8 vimage_lo;
  75         u8 vimage_hi:4;
  76         u8 himage_hi:4;
  77         u8 h_border;
  78         u8 v_border;
  79         u8 rsvd1:3;
  80         u8 digital:2;
  81         u8 vsync_positive:1;
  82         u8 hsync_positive:1;
  83         u8 non_interlaced:1;
  84 } __packed;
  85
  86 /**
  87  * struct vbt_header - VBT Header structure
  88  * @signature:          VBT signature, always starts with "$VBT"
  89  * @version:            Version of this structure
  90  * @header_size:        Size of this structure
  91  * @vbt_size:           Size of VBT (VBT Header, BDB Header and data blocks)
  92  * @vbt_checksum:       Checksum
  93  * @reserved0:          Reserved
  94  * @bdb_offset:         Offset of &struct bdb_header from beginning of VBT
  95  * @aim_offset:         Offsets of add-in data blocks from beginning of VBT
  96  */
  97 struct vbt_header {
  98         u8 signature[20];
  99         u16 version;
 100         u16 header_size;
 101         u16 vbt_size;
 102         u8 vbt_checksum;
 103         u8 reserved0;
 104         u32 bdb_offset;
 105         u32 aim_offset[4];
 106 } __packed;
 107
 108 /**
 109  * struct bdb_header - BDB Header structure
 110  * @signature:          BDB signature "BIOS_DATA_BLOCK"
 111  * @version:            Version of the data block definitions
 112  * @header_size:        Size of this structure
 113  * @bdb_size:           Size of BDB (BDB Header and data blocks)
 114  */
 115 struct bdb_header {
 116         u8 signature[16];
 117         u16 version;
 118         u16 header_size;
 119         u16 bdb_size;
 120 } __packed;
 121
 122 /*
 123  * BDB version number dependencies are documented as:
 124  *
 125  * <start>+
 126  *    indicates the field was introduced in version <start>
 127  *    and is still valid
 128  *
 129  * <start>-<end>
 130  *    indicates the field was introduced in version <start>
 131  *    and obsoleted in version <end>+1.
 132  *
 133  * ??? indicates the specific version number is unknown
 134  */
 135
 136 /*
 137  * There are several types of BIOS data blocks (BDBs), each block has
 138  * an ID and size in the first 3 bytes (ID in first, size in next 2).
 139  * Known types are listed below.
 140  */
 141 enum bdb_block_id {
 142         BDB_GENERAL_FEATURES            = 1,
 143         BDB_GENERAL_DEFINITIONS         = 2,
 144         BDB_DISPLAY_TOGGLE              = 3,
 145         BDB_MODE_SUPPORT_LIST           = 4,
 146         BDB_GENERIC_MODE_TABLE          = 5,
 147         BDB_EXT_MMIO_REGS               = 6, /* VBIOS only */
 148         BDB_SWF_IO                      = 7, /* VBIOS only */
 149         BDB_SWF_MMIO                    = 8, /* VBIOS only */
 150         BDB_DOT_CLOCK_OVERRIDE_ALM      = 9,
 151         BDB_PSR                         = 9, /* 165+ */
 152         BDB_MODE_REMOVAL_TABLE          = 10,
 153         BDB_CHILD_DEVICE_TABLE          = 11,
 154         BDB_DRIVER_FEATURES             = 12,
 155         BDB_DRIVER_PERSISTENCE          = 13,
 156         BDB_EXT_TABLE_PTRS              = 14, /* VBIOS only */
 157         BDB_DOT_CLOCK_OVERRIDE          = 15,
 158         BDB_DISPLAY_SELECT_OLD          = 16,
 159         BDB_SV_TEST_FUNCTIONS           = 17,
 160         BDB_DRIVER_ROTATION             = 18,
 161         BDB_DISPLAY_REMOVE_OLD          = 19,
 162         BDB_OEM_CUSTOM                  = 20,
 163         BDB_EFP_LIST                    = 21, /* workarounds for VGA hsync/vsync */
 164         BDB_SDVO_LVDS_OPTIONS           = 22,
 165         BDB_SDVO_LVDS_DTD               = 23,
 166         BDB_SDVO_LVDS_PNP_ID            = 24,
 167         BDB_SDVO_LVDS_PPS               = 25,
 168         BDB_TV_OPTIONS                  = 26,
 169         BDB_EDP                         = 27,
 170         BDB_EFP_DTD                     = 28, /* 161+ */
 171         BDB_DISPLAY_SELECT_IVB          = 29, /* 164+ */
 172         BDB_DISPLAY_REMOVE_IVB          = 30, /* 164+ */
 173         BDB_DISPLAY_SELECT_HSW          = 31, /* 166+ */
 174         BDB_DISPLAY_REMOVE_HSW          = 32, /* 166+ */
 175         BDB_LFP_OPTIONS                 = 40,
 176         BDB_LFP_DATA_PTRS               = 41,
 177         BDB_LFP_DATA                    = 42,
 178         BDB_LFP_BACKLIGHT               = 43,
 179         BDB_LFP_POWER                   = 44,
 180         BDB_EDP_BFI                     = 45, /* 160+ */
 181         BDB_CHROMATICITY                = 46, /* 169+ */
 182         BDB_MIPI                        = 50, /* 170-172 */
 183         BDB_FIXED_SET_MODE              = 51, /* 172+ */
 184         BDB_MIPI_CONFIG                 = 52, /* 175+ */
 185         BDB_MIPI_SEQUENCE               = 53, /* 177+ */
 186         BDB_RGB_PALETTE                 = 54, /* 180+ */
 187         BDB_COMPRESSION_PARAMETERS_OLD  = 55, /* 198-212 */
 188         BDB_COMPRESSION_PARAMETERS      = 56, /* 213+ */
 189         BDB_VSWING_PREEMPH              = 57, /* 218+ */
 190         BDB_GENERIC_DTD                 = 58, /* 229+ */
 191         BDB_INT15_HOOK                  = 252, /* VBIOS only */
 192         BDB_PRD_TABLE                   = 253,
 193         BDB_SKIP                        = 254, /* VBIOS only */
 194 };
 195
 196 /*
 197  * Block 1 - General Bit Definitions
 198  */
 199
 200 struct bdb_general_features {
 201         /* bits 1 */
 202         u8 panel_fitting:2;
 203         u8 flexaim:1;
 204         u8 msg_enable:1;
 205         u8 clear_screen:3;
 206         u8 color_flip:1;
 207
 208         /* bits 2 */
 209         u8 download_ext_vbt:1;
 210         u8 enable_ssc:1;
 211         u8 ssc_freq:1;
 212         u8 enable_lfp_on_override:1;
 213         u8 disable_ssc_ddt:1;
 214         u8 underscan_vga_timings:1;
 215         u8 display_clock_mode:1;
 216         u8 vbios_hotplug_support:1;
 217
 218         /* bits 3 */
 219         u8 disable_smooth_vision:1;
 220         u8 single_dvi:1;
 221         u8 rotate_180:1;                                        /* 181+ */
 222         u8 fdi_rx_polarity_inverted:1;
 223         u8 vbios_extended_mode:1;                               /* 160+ */
 224         u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1;                    /* 160+ */
 225         u8 panel_best_fit_timing:1;                             /* 160+ */
 226         u8 ignore_strap_state:1;                                /* 160+ */
 227
 228         /* bits 4 */
 229         u8 legacy_monitor_detect;
 230
 231         /* bits 5 */
 232         u8 int_crt_support:1;
 233         u8 int_tv_support:1;
 234         u8 int_efp_support:1;
 235         u8 dp_ssc_enable:1;     /* PCH attached eDP supports SSC */
 236         u8 dp_ssc_freq:1;       /* SSC freq for PCH attached eDP */
 237         u8 dp_ssc_dongle_supported:1;
 238         u8 rsvd11:2; /* finish byte */
 239
 240         /* bits 6 */
 241         u8 tc_hpd_retry_timeout:7;                              /* 242+ */
 242         u8 rsvd12:1;
 243
 244         /* bits 7 */
 245         u8 afc_startup_config:2;                                /* 249+ */
 246         u8 rsvd13:6;
 247 } __packed;
 248
 249 /*
 250  * Block 2 - General Bytes Definition
 251  */
 252
 253 /* pre-915 */
 254 #define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
 255 #define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
 256 #define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
 257 #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
 258
 259 /* Device handle */
 260 #define DEVICE_HANDLE_CRT       0x0001
 261 #define DEVICE_HANDLE_TV        0x0002 /* ???-214 */
 262 #define DEVICE_HANDLE_EFP1      0x0004
 263 #define DEVICE_HANDLE_EFP2      0x0040
 264 #define DEVICE_HANDLE_EFP3      0x0020
 265 #define DEVICE_HANDLE_EFP4      0x0010
 266 #define DEVICE_HANDLE_EFP5      0x0002 /* 215+ */
 267 #define DEVICE_HANDLE_EFP6      0x0001 /* 217+ */
 268 #define DEVICE_HANDLE_EFP7      0x0100 /* 217+ */
 269 #define DEVICE_HANDLE_EFP8      0x0200 /* 217+ */
 270 #define DEVICE_HANDLE_LFP1      0x0008
 271 #define DEVICE_HANDLE_LFP2      0x0080
 272
 273 /* Pre 915 */
 274 #define DEVICE_TYPE_NONE        0x00
 275 #define DEVICE_TYPE_CRT         0x01
 276 #define DEVICE_TYPE_TV          0x09
 277 #define DEVICE_TYPE_EFP         0x12
 278 #define DEVICE_TYPE_LFP         0x22
 279 /* On 915+ */
 280 #define DEVICE_TYPE_CRT_DPMS            0x6001
 281 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
 282 #define DEVICE_TYPE_TV_COMPOSITE        0x0209
 283 #define DEVICE_TYPE_TV_MACROVISION      0x0289
 284 #define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
 285 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
 286 #define DEVICE_TYPE_TV_SCART            0x0209
 287 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
 288 #define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
 289 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
 290 #define DEVICE_TYPE_EFP_DVI_I           0x6053
 291 #define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
 292 #define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
 293 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
 294 #define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
 295 #define DEVICE_TYPE_LFP_PANELLINK       0x5012
 296 #define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
 297 #define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
 298 #define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
 299 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
 300
 301 /* Add the device class for LFP, TV, HDMI */
 302 #define DEVICE_TYPE_INT_LFP             0x1022
 303 #define DEVICE_TYPE_INT_TV              0x1009
 304 #define DEVICE_TYPE_HDMI                0x60D2
 305 #define DEVICE_TYPE_DP                  0x68C6
 306 #define DEVICE_TYPE_DP_DUAL_MODE        0x60D6
 307 #define DEVICE_TYPE_eDP                 0x78C6
 308
 309 #define DEVICE_TYPE_CLASS_EXTENSION     (1 << 15)
 310 #define DEVICE_TYPE_POWER_MANAGEMENT    (1 << 14)
 311 #define DEVICE_TYPE_HOTPLUG_SIGNALING   (1 << 13)
 312 #define DEVICE_TYPE_INTERNAL_CONNECTOR  (1 << 12)
 313 #define DEVICE_TYPE_NOT_HDMI_OUTPUT     (1 << 11)
 314 #define DEVICE_TYPE_MIPI_OUTPUT         (1 << 10)
 315 #define DEVICE_TYPE_COMPOSITE_OUTPUT    (1 << 9)
 316 #define DEVICE_TYPE_DUAL_CHANNEL        (1 << 8)
 317 #define DEVICE_TYPE_HIGH_SPEED_LINK     (1 << 6)
 318 #define DEVICE_TYPE_LVDS_SIGNALING      (1 << 5)
 319 #define DEVICE_TYPE_TMDS_DVI_SIGNALING  (1 << 4)
 320 #define DEVICE_TYPE_VIDEO_SIGNALING     (1 << 3)
 321 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT  (1 << 2)
 322 #define DEVICE_TYPE_DIGITAL_OUTPUT      (1 << 1)
 323 #define DEVICE_TYPE_ANALOG_OUTPUT       (1 << 0)
 324
 325 #define DEVICE_CFG_NONE         0x00
 326 #define DEVICE_CFG_12BIT_DVOB   0x01
 327 #define DEVICE_CFG_12BIT_DVOC   0x02
 328 #define DEVICE_CFG_24BIT_DVOBC  0x09
 329 #define DEVICE_CFG_24BIT_DVOCB  0x0a
 330 #define DEVICE_CFG_DUAL_DVOB    0x11
 331 #define DEVICE_CFG_DUAL_DVOC    0x12
 332 #define DEVICE_CFG_DUAL_DVOBC   0x13
 333 #define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
 334 #define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
 335
 336 #define DEVICE_WIRE_NONE        0x00
 337 #define DEVICE_WIRE_DVOB        0x01
 338 #define DEVICE_WIRE_DVOC        0x02
 339 #define DEVICE_WIRE_DVOBC       0x03
 340 #define DEVICE_WIRE_DVOBB       0x05
 341 #define DEVICE_WIRE_DVOCC       0x06
 342 #define DEVICE_WIRE_DVOB_MASTER 0x0d
 343 #define DEVICE_WIRE_DVOC_MASTER 0x0e
 344
 345 /* dvo_port pre BDB 155 */
 346 #define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
 347 #define DEVICE_PORT_DVOB        0x01
 348 #define DEVICE_PORT_DVOC        0x02
 349
 350 /* dvo_port BDB 155+ */
 351 #define DVO_PORT_HDMIA          0
 352 #define DVO_PORT_HDMIB          1
 353 #define DVO_PORT_HDMIC          2
 354 #define DVO_PORT_HDMID          3
 355 #define DVO_PORT_LVDS           4
 356 #define DVO_PORT_TV             5
 357 #define DVO_PORT_CRT            6
 358 #define DVO_PORT_DPB            7
 359 #define DVO_PORT_DPC            8
 360 #define DVO_PORT_DPD            9
 361 #define DVO_PORT_DPA            10
 362 #define DVO_PORT_DPE            11                              /* 193+ */
 363 #define DVO_PORT_HDMIE          12                              /* 193+ */
 364 #define DVO_PORT_DPF            13                              /* N/A */
 365 #define DVO_PORT_HDMIF          14                              /* N/A */
 366 #define DVO_PORT_DPG            15                              /* 217+ */
 367 #define DVO_PORT_HDMIG          16                              /* 217+ */
 368 #define DVO_PORT_DPH            17                              /* 217+ */
 369 #define DVO_PORT_HDMIH          18                              /* 217+ */
 370 #define DVO_PORT_DPI            19                              /* 217+ */
 371 #define DVO_PORT_HDMII          20                              /* 217+ */
 372 #define DVO_PORT_MIPIA          21                              /* 171+ */
 373 #define DVO_PORT_MIPIB          22                              /* 171+ */
 374 #define DVO_PORT_MIPIC          23                              /* 171+ */
 375 #define DVO_PORT_MIPID          24                              /* 171+ */
 376
 377 #define HDMI_MAX_DATA_RATE_PLATFORM     0                       /* 204+ */
 378 #define HDMI_MAX_DATA_RATE_297          1                       /* 204+ */
 379 #define HDMI_MAX_DATA_RATE_165          2                       /* 204+ */
 380 #define HDMI_MAX_DATA_RATE_594          3                       /* 249+ */
 381 #define HDMI_MAX_DATA_RATE_340          4                       /* 249+ */
 382 #define HDMI_MAX_DATA_RATE_300          5                       /* 249+ */
 383
 384 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE         33
 385
 386 /* DDC Bus DDI Type 155+ */
 387 enum vbt_gmbus_ddi {
 388         DDC_BUS_DDI_B = 0x1,
 389         DDC_BUS_DDI_C,
 390         DDC_BUS_DDI_D,
 391         DDC_BUS_DDI_F,
 392         ICL_DDC_BUS_DDI_A = 0x1,
 393         ICL_DDC_BUS_DDI_B,
 394         TGL_DDC_BUS_DDI_C,
 395         RKL_DDC_BUS_DDI_D = 0x3,
 396         RKL_DDC_BUS_DDI_E,
 397         ICL_DDC_BUS_PORT_1 = 0x4,
 398         ICL_DDC_BUS_PORT_2,
 399         ICL_DDC_BUS_PORT_3,
 400         ICL_DDC_BUS_PORT_4,
 401         TGL_DDC_BUS_PORT_5,
 402         TGL_DDC_BUS_PORT_6,
 403         ADLS_DDC_BUS_PORT_TC1 = 0x2,
 404         ADLS_DDC_BUS_PORT_TC2,
 405         ADLS_DDC_BUS_PORT_TC3,
 406         ADLS_DDC_BUS_PORT_TC4,
 407         ADLP_DDC_BUS_PORT_TC1 = 0x3,
 408         ADLP_DDC_BUS_PORT_TC2,
 409         ADLP_DDC_BUS_PORT_TC3,
 410         ADLP_DDC_BUS_PORT_TC4
 411
 412 };
 413
 414 #define DP_AUX_A 0x40
 415 #define DP_AUX_B 0x10
 416 #define DP_AUX_C 0x20
 417 #define DP_AUX_D 0x30
 418 #define DP_AUX_E 0x50
 419 #define DP_AUX_F 0x60
 420 #define DP_AUX_G 0x70
 421 #define DP_AUX_H 0x80
 422 #define DP_AUX_I 0x90
 423
 424 /* DP max link rate 216+ */
 425 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR3       0
 426 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR2       1
 427 #define BDB_216_VBT_DP_MAX_LINK_RATE_HBR        2
 428 #define BDB_216_VBT_DP_MAX_LINK_RATE_LBR        3
 429
 430 /* DP max link rate 230+ */
 431 #define BDB_230_VBT_DP_MAX_LINK_RATE_DEF        0
 432 #define BDB_230_VBT_DP_MAX_LINK_RATE_LBR        1
 433 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR        2
 434 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR2       3
 435 #define BDB_230_VBT_DP_MAX_LINK_RATE_HBR3       4
 436 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10     5
 437 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5   6
 438 #define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20     7
 439
 440 /*
 441  * The child device config, aka the display device data structure, provides a
 442  * description of a port and its configuration on the platform.
 443  *
 444  * The child device config size has been increased, and fields have been added
 445  * and their meaning has changed over time. Care must be taken when accessing
 446  * basically any of the fields to ensure the correct interpretation for the BDB
 447  * version in question.
 448  *
 449  * When we copy the child device configs to dev_priv->display.vbt.child_dev, we
 450  * reserve space for the full structure below, and initialize the tail not
 451  * actually present in VBT to zeros. Accessing those fields is fine, as long as
 452  * the default zero is taken into account, again according to the BDB version.
 453  *
 454  * BDB versions 155 and below are considered legacy, and version 155 seems to be
 455  * a baseline for some of the VBT documentation. When adding new fields, please
 456  * include the BDB version when the field was added, if it's above that.
 457  */
 458 struct child_device_config {
 459         u16 handle;
 460         u16 device_type; /* See DEVICE_TYPE_* above */
 461
 462         union {
 463                 u8  device_id[10]; /* ascii string */
 464                 struct {
 465                         u8 i2c_speed;
 466                         u8 dp_onboard_redriver_preemph:3;       /* 158+ */
 467                         u8 dp_onboard_redriver_vswing:3;        /* 158+ */
 468                         u8 dp_onboard_redriver_present:1;       /* 158+ */
 469                         u8 reserved0:1;
 470                         u8 dp_ondock_redriver_preemph:3;        /* 158+ */
 471                         u8 dp_ondock_redriver_vswing:3;         /* 158+ */
 472                         u8 dp_ondock_redriver_present:1;        /* 158+ */
 473                         u8 reserved1:1;
 474                         u8 hdmi_level_shifter_value:5;          /* 158+ */
 475                         u8 hdmi_max_data_rate:3;                /* 204+ */
 476                         u16 dtd_buf_ptr;                        /* 161+ */
 477                         u8 edidless_efp:1;                      /* 161+ */
 478                         u8 compression_enable:1;                /* 198+ */
 479                         u8 compression_method_cps:1;            /* 198+ */
 480                         u8 ganged_edp:1;                        /* 202+ */
 481                         u8 lttpr_non_transparent:1;             /* 235+ */
 482                         u8 disable_compression_for_ext_disp:1;  /* 251+ */
 483                         u8 reserved2:2;
 484                         u8 compression_structure_index:4;       /* 198+ */
 485                         u8 reserved3:4;
 486                         u8 hdmi_max_frl_rate:4;                 /* 237+ */
 487                         u8 hdmi_max_frl_rate_valid:1;           /* 237+ */
 488                         u8 reserved4:3;                         /* 237+ */
 489                         u8 reserved5;
 490                 } __packed;
 491         } __packed;
 492
 493         u16 addin_offset;
 494         u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */
 495         u8 i2c_pin;
 496         u8 target_addr;
 497         u8 ddc_pin;
 498         u16 edid_ptr;
 499         u8 dvo_cfg; /* See DEVICE_CFG_* above */
 500
 501         union {
 502                 struct {
 503                         u8 dvo2_port;
 504                         u8 i2c2_pin;
 505                         u8 target2_addr;
 506                         u8 ddc2_pin;
 507                 } __packed;
 508                 struct {
 509                         u8 efp_routed:1;                        /* 158+ */
 510                         u8 lane_reversal:1;                     /* 184+ */
 511                         u8 lspcon:1;                            /* 192+ */
 512                         u8 iboost:1;                            /* 196+ */
 513                         u8 hpd_invert:1;                        /* 196+ */
 514                         u8 use_vbt_vswing:1;                    /* 218+ */
 515                         u8 dp_max_lane_count:2;                 /* 244+ */
 516                         u8 hdmi_support:1;                      /* 158+ */
 517                         u8 dp_support:1;                        /* 158+ */
 518                         u8 tmds_support:1;                      /* 158+ */
 519                         u8 support_reserved:5;
 520                         u8 aux_channel;
 521                         u8 dongle_detect;
 522                 } __packed;
 523         } __packed;
 524
 525         u8 pipe_cap:2;
 526         u8 sdvo_stall:1;                                        /* 158+ */
 527         u8 hpd_status:2;
 528         u8 integrated_encoder:1;
 529         u8 capabilities_reserved:2;
 530         u8 dvo_wiring; /* See DEVICE_WIRE_* above */
 531
 532         union {
 533                 u8 dvo2_wiring;
 534                 u8 mipi_bridge_type;                            /* 171+ */
 535         } __packed;
 536
 537         u16 extended_type;
 538         u8 dvo_function;
 539         u8 dp_usb_type_c:1;                                     /* 195+ */
 540         u8 tbt:1;                                               /* 209+ */
 541         u8 flags2_reserved:2;                                   /* 195+ */
 542         u8 dp_port_trace_length:4;                              /* 209+ */
 543         u8 dp_gpio_index;                                       /* 195+ */
 544         u16 dp_gpio_pin_num;                                    /* 195+ */
 545         u8 dp_iboost_level:4;                                   /* 196+ */
 546         u8 hdmi_iboost_level:4;                                 /* 196+ */
 547         u8 dp_max_link_rate:3;                                  /* 216+ */
 548         u8 dp_max_link_rate_reserved:5;                         /* 216+ */
 549         u8 efp_index;                                           /* 256+ */
 550 } __packed;
 551
 552 struct bdb_general_definitions {
 553         /* DDC GPIO */
 554         u8 crt_ddc_gmbus_pin;
 555
 556         /* DPMS bits */
 557         u8 dpms_non_acpi:1;
 558         u8 skip_boot_crt_detect:1;
 559         u8 dpms_aim:1;
 560         u8 rsvd1:5; /* finish byte */
 561
 562         /* boot device bits */
 563         u8 boot_display[2];
 564         u8 child_dev_size;
 565
 566         /*
 567          * Device info:
 568          * If TV is present, it'll be at devices[0].
 569          * LVDS will be next, either devices[0] or [1], if present.
 570          * On some platforms the number of device is 6. But could be as few as
 571          * 4 if both TV and LVDS are missing.
 572          * And the device num is related with the size of general definition
 573          * block. It is obtained by using the following formula:
 574          * number = (block_size - sizeof(bdb_general_definitions))/
 575          *           defs->child_dev_size;
 576          */
 577         u8 devices[];
 578 } __packed;
 579
 580 /*
 581  * Block 3 - Display Toggle Option Block
 582  */
 583
 584 struct bdb_display_toggle {
 585         u8 feature_bits;
 586         u16 num_entries;                                        /* ALM only */
 587         u16 list[];                                             /* ALM only */
 588 } __packed;
 589
 590 /*
 591  * Block 4 - Mode Support List
 592  */
 593
 594 struct bdb_mode_support_list {
 595         u8 intel_mode_number[0];
 596         u16 mode_list_length;
 597 } __packed;
 598
 599 /*
 600  * Block 5 - Generic Mode Table
 601  */
 602
 603 struct generic_mode_table {
 604         u16 x_res;
 605         u16 y_res;
 606         u8 color_depths;
 607         u8 refresh_rate[3];
 608         u8 reserved;
 609         u8 text_cols;
 610         u8 text_rows;
 611         u8 font_height;
 612         u16 page_size;
 613         u8 misc;
 614 } __packed;
 615
 616 struct generic_mode_timings {
 617         u32 dotclock_khz;
 618         u16 hdisplay;
 619         u16 htotal;
 620         u16 hblank_start;
 621         u16 hblank_end;
 622         u16 hsync_start;
 623         u16 hsync_end;
 624         u16 vdisplay;
 625         u16 vtotal;
 626         u16 vblank_start;
 627         u16 vblank_end;
 628         u16 vsync_start;
 629         u16 vsync_end;
 630 } __packed;
 631
 632 struct generic_mode_timings_alm {
 633         struct generic_mode_timings timings;
 634         u8 wm_8bpp;
 635         u8 burst_8bpp;
 636         u8 wm_16bpp;
 637         u8 burst_16bpp;
 638         u8 wm_32bpp;
 639         u8 burst_32bpp;
 640 } __packed;
 641
 642 struct bdb_generic_mode_table_alm {
 643         struct generic_mode_table table;
 644         struct generic_mode_timings_alm timings[3];
 645 } __packed;
 646
 647 struct bdb_generic_mode_table_mgm {
 648         u16 mode_flag;
 649         struct generic_mode_table table;
 650         struct generic_mode_timings timings[3];
 651 } __packed;
 652
 653 /*
 654  * Block 6 - Extended MMIO Register Table, VBIOS only
 655  * Block 7 - IO Software Flag Table, VBIOS only
 656  * Block 8 - MMIO SWF Register Table, VBIOS only
 657  */
 658 struct bdb_reg_table {
 659         u16 table_id;
 660         u8 data_access_size;
 661         /*
 662          * offset,value tuples:
 663          * data_access_size==0xce -> u8,u8
 664          * data_access_size==0x02 -> u32,u32
 665          */
 666         /* u16 table_end_marker; */
 667 } __packed;
 668
 669 /*
 670  * Block 9 - Undocumented table (ALM only)
 671  */
 672
 673 struct dot_clock_override_entry_gen2 {
 674         u32 dotclock;
 675         u8 n;
 676         u8 m1;
 677         u8 m2;
 678         u8 p1:5;
 679         u8 p1_div_by_2:1;
 680         u8 reserved:1;
 681         u8 p2_div_by_4:1;
 682 } __packed;
 683
 684 struct bdb_dot_clock_override_alm {
 685         struct dot_clock_override_entry_gen2 t[0];
 686 } __packed;
 687
 688 /*
 689  * Block 9 - SRD Feature Block
 690  */
 691
 692 struct psr_table {
 693         /* Feature bits */
 694         u8 full_link:1;                                         /* 165+ */
 695         u8 require_aux_to_wakeup:1;                             /* 165+ */
 696         u8 feature_bits_rsvd:6;
 697
 698         /* Wait times */
 699         u8 idle_frames:4;                                       /* 165+ */
 700         u8 lines_to_wait:3;                                     /* 165+ */
 701         u8 wait_times_rsvd:1;
 702
 703         /* TP wake up time in multiple of 100 */
 704         u16 tp1_wakeup_time;                                    /* 165+ */
 705         u16 tp2_tp3_wakeup_time;                                /* 165+ */
 706 } __packed;
 707
 708 struct bdb_psr {
 709         struct psr_table psr_table[16];
 710
 711         /* PSR2 TP2/TP3 wakeup time for 16 panels */
 712         u32 psr2_tp2_tp3_wakeup_time;                           /* 226+ */
 713 } __packed;
 714
 715 /*
 716  * Block 10 - Mode Removal Table
 717  */
 718
 719 struct mode_removal_table {
 720         u16 x_res;
 721         u16 y_res;
 722         u8 bpp;
 723         u16 refresh_rate;
 724         u8 removal_flags;
 725         u16 panel_flags;
 726 } __packed;
 727
 728 struct bdb_mode_removal {
 729         u8 row_size; /* 8 or 10 bytes */
 730         /*
 731          * VBT spec says this is always 20 entries,
 732          * but ALM seems to have only 15 entries.
 733          */
 734         struct mode_removal_table modes[];
 735         /* u16 terminator; 0x0000 */
 736 } __packed;
 737
 738 /*
 739  * Block 12 - Driver Features Data Block
 740  */
 741
 742 #define BDB_DRIVER_FEATURE_NO_LVDS              0
 743 #define BDB_DRIVER_FEATURE_INT_LVDS             1
 744 #define BDB_DRIVER_FEATURE_SDVO_LVDS            2
 745 #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS        3
 746
 747 struct bdb_driver_features {
 748         /* Driver bits */
 749         u8 boot_dev_algorithm:1;
 750         u8 allow_display_switch_dvd:1;
 751         u8 allow_display_switch_dos:1;
 752         u8 hotplug_dvo:1;
 753         u8 dual_view_zoom:1;
 754         u8 int15h_hook:1;
 755         u8 sprite_in_clone:1;
 756         u8 primary_lfp_id:1;
 757
 758         u16 boot_mode_x;
 759         u16 boot_mode_y;
 760         u8 boot_mode_bpp;
 761         u8 boot_mode_refresh;
 762
 763         /* Extended Driver Bits 1 */
 764         u16 enable_lfp_primary:1;
 765         u16 selective_mode_pruning:1;
 766         u16 dual_frequency:1;
 767         u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
 768         u16 nt_clone_support:1;
 769         u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
 770         u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
 771         u16 cui_aspect_scaling:1;
 772         u16 preserve_aspect_ratio:1;
 773         u16 sdvo_device_power_down:1;
 774         u16 crt_hotplug:1;
 775         u16 lvds_config:2;
 776         u16 tv_hotplug:1;
 777         u16 hdmi_config:2;
 778
 779         /* Driver Flags 1 */
 780         u8 static_display:1;                                    /* 163+ */
 781         u8 embedded_platform:1;                                 /* 163+ */
 782         u8 display_subsystem_enable:1;                          /* 163+ */
 783         u8 reserved0:5;
 784
 785         u16 legacy_crt_max_x;
 786         u16 legacy_crt_max_y;
 787         u8 legacy_crt_max_refresh;
 788
 789         /* Extended Driver Bits 2 */
 790         u8 hdmi_termination:1;
 791         u8 cea861d_hdmi_support:1;
 792         u8 self_refresh_enable:1;
 793         u8 reserved1:5;
 794
 795         u8 custom_vbt_version;                                  /* 155+ */
 796
 797         /* Driver Feature Flags */
 798         u16 rmpm_enabled:1;                                     /* 159+ */
 799         u16 s2ddt_enabled:1;                                    /* 159+ */
 800         u16 dpst_enabled:1;                                     /* 159-227 */
 801         u16 bltclt_enabled:1;                                   /* 159+ */
 802         u16 adb_enabled:1;                                      /* 159-227 */
 803         u16 drrs_enabled:1;                                     /* 159-227 */
 804         u16 grs_enabled:1;                                      /* 159+ */
 805         u16 gpmt_enabled:1;                                     /* 159+ */
 806         u16 tbt_enabled:1;                                      /* 159+ */
 807         u16 psr_enabled:1;                                      /* 165-227 */
 808         u16 ips_enabled:1;                                      /* 165+ */
 809         u16 dfps_enabled:1;                                     /* 165+ */
 810         u16 dmrrs_enabled:1;                                    /* 174-227 */
 811         u16 adt_enabled:1;                                      /* ???-228 */
 812         u16 hpd_wake:1;                                         /* 201-240 */
 813         u16 pc_feature_valid:1;                                 /* 159+ */
 814 } __packed;
 815
 816 /*
 817  * Block 13 - Driver Persistent Algorithm
 818  */
 819
 820 struct bdb_driver_persistence {
 821         u16 hotkey_persistent_algorithm:1;
 822         u16 lid_switch_persistent_algorithm:1;
 823         u16 power_management_persistent_algorithm:1;
 824         u16 hotkey_persistent_on_mds_twin:1;
 825         u16 hotkey_persistent_on_refresh_rate:1;
 826         u16 hotkey_persistent_on_restore_pipe:1;
 827         u16 hotkey_persistent_on_mode:1;
 828         u16 edid_persistent_on_mode:1;
 829         u16 dvo_hotplug_persistent_on_mode:1;
 830         u16 docking_persistent_algorithm:1;
 831         u16 rsvd:6;
 832         u8 persistent_max_config;
 833 } __packed;
 834
 835 /*
 836  * Block 15 - Dot Clock Override Table
 837  */
 838
 839 struct dot_clock_override_entry_gen3 {
 840         u32 dotclock;
 841         u8 n;
 842         u8 m1;
 843         u8 m2;
 844         u8 p1;
 845         u8 p2;
 846 } __packed;
 847
 848 struct bdb_dot_clock_override {
 849         u8 row_size; /* 8 == gen2, 9 == gen3+ */
 850         u8 num_rows;
 851         struct dot_clock_override_entry_gen3 table[]; /* or _gen2 */
 852 } __packed;
 853
 854 /*
 855  * Block 16 - Toggle List Block (pre-HSW)
 856  */
 857
 858 struct toggle_list_entry_old {
 859         u8 display_select_pipe_a;
 860         u8 display_select_pipe_b;
 861         u8 caps;
 862 } __packed;
 863
 864 struct toggle_list_table_old {
 865         u16 num_entries;
 866         u8 entry_size;
 867         struct toggle_list_entry_old list[];
 868 } __packed;
 869
 870 struct bdb_display_select_old {
 871         /* each table has variable size! */
 872         struct toggle_list_table_old tables[4];
 873 } __packed;
 874
 875 /*
 876  * Block 17 - SV Test Functions
 877  */
 878
 879 struct bdb_sv_test_functions {
 880         u8 sv_bits[8];
 881 } __packed;
 882
 883 /*
 884  * Block 18 - Driver Rotation
 885  */
 886
 887 struct bdb_driver_rotation {
 888         u8 rotation_enable;
 889         u8 rotation_flags_1;
 890         u16 rotation_flags_2;
 891         u32 rotation_flags_3;
 892         u32 rotation_flags_4;
 893 } __packed;
 894
 895 /*
 896  * Block 19 - Display Configuration Removal Table (pre-IVB)
 897  */
 898
 899 struct display_remove_entry_old {
 900         u8 display_select_pipe_a;
 901         u8 display_select_pipe_b;
 902 } __packed;
 903
 904 struct bdb_display_remove_old {
 905         u8 num_entries;
 906         u8 entry_size;
 907         struct display_remove_entry_old table[];
 908 } __packed;
 909
 910 /*
 911  * Block 20 - OEM Customizable Modes
 912  */
 913
 914 struct oem_mode {
 915         u8 enable_in_vbios:1;
 916         u8 enable_in_os:1;
 917         u8 enable_in_gop:1;                                     /* 207+ */
 918         u8 reserved:5;
 919         u8 display_flags;                                       /* ???-216 */
 920         u16 x_res;
 921         u16 y_res;
 922         u8 color_depth;
 923         u8 refresh_rate;
 924         struct bdb_edid_dtd dtd;
 925         u16 display_flags_2;                                    /* 217+ */
 926 } __packed;
 927
 928 struct bdb_oem_custom {
 929         u8 num_entries;
 930         u8 entry_size;
 931         struct oem_mode modes[];
 932 } __packed;
 933
 934 /*
 935  * Block 21 - EFP List
 936  */
 937
 938 struct efp_entry {
 939         u16 mfg_name;
 940         u16 product_code;
 941 } __packed;
 942
 943 struct bdb_efp_list {
 944         u8 num_entries;
 945         u8 entry_size;
 946         struct efp_entry efp[];
 947 } __packed;
 948
 949 /*
 950  * Block 22 - SDVO LVDS General Options
 951  */
 952
 953 struct bdb_sdvo_lvds_options {
 954         u8 panel_backlight;
 955         u8 h40_set_panel_type;
 956         u8 panel_type;
 957         u8 ssc_clk_freq;
 958         u16 als_low_trip;
 959         u16 als_high_trip;
 960         u8 sclalarcoeff_tab_row_num;
 961         u8 sclalarcoeff_tab_row_size;
 962         u8 coefficient[8];
 963         u8 panel_misc_bits_1;
 964         u8 panel_misc_bits_2;
 965         u8 panel_misc_bits_3;
 966         u8 panel_misc_bits_4;
 967 } __packed;
 968
 969 /*
 970  * Block 23 - SDVO LVDS DTD
 971  */
 972
 973 struct bdb_sdvo_lvds_dtd {
 974         struct bdb_edid_dtd dtd[4];
 975 } __packed;
 976
 977 /*
 978  * Block 24 - SDVO LVDS PnP ID
 979  */
 980
 981 struct bdb_sdvo_lvds_pnp_id {
 982         struct bdb_edid_pnp_id pnp_id[4];
 983 } __packed;
 984
 985 /*
 986  * Block 25 - SDVO LVDS PPS
 987  */
 988
 989 struct sdvo_lvds_pps {
 990         u16 t0; /* power on */
 991         u16 t1; /* backlight on */
 992         u16 t2; /* backlight off */
 993         u16 t3; /* power off */
 994         u16 t4; /* power cycle */
 995 } __packed;
 996
 997 struct bdb_sdvo_lvds_pps {
 998         struct sdvo_lvds_pps pps[4];
 999 } __packed;
1000
1001 /*
1002  * Block 26 - TV Options Block
1003  */
1004
1005 struct bdb_tv_options {
1006         u16 underscan_overscan_hdtv_component:2;
1007         u16 rsvd1:10;
1008         u16 underscan_overscan_hdtv_dvi:2;
1009         u16 add_modes_to_avoid_overscan_issue:1;
1010         u16 d_connector_support:1;
1011 } __packed;
1012
1013 /*
1014  * Block 27 - eDP VBT Block
1015  */
1016
1017 struct edp_power_seq {
1018         u16 t1_t3;
1019         u16 t8;
1020         u16 t9;
1021         u16 t10;
1022         u16 t11_t12;
1023 } __packed;
1024
1025 #define EDP_18BPP       0
1026 #define EDP_24BPP       1
1027 #define EDP_30BPP       2
1028 #define EDP_RATE_1_62   0
1029 #define EDP_RATE_2_7    1
1030 #define EDP_RATE_5_4    2
1031 #define EDP_LANE_1      0
1032 #define EDP_LANE_2      1
1033 #define EDP_LANE_4      3
1034 #define EDP_PREEMPHASIS_NONE    0
1035 #define EDP_PREEMPHASIS_3_5dB   1
1036 #define EDP_PREEMPHASIS_6dB     2
1037 #define EDP_PREEMPHASIS_9_5dB   3
1038 #define EDP_VSWING_0_4V         0
1039 #define EDP_VSWING_0_6V         1
1040 #define EDP_VSWING_0_8V         2
1041 #define EDP_VSWING_1_2V         3
1042
1043
1044 struct edp_fast_link_params {
1045         u8 rate:4;                                              /* ???-223 */
1046         u8 lanes:4;
1047         u8 preemphasis:4;
1048         u8 vswing:4;
1049 } __packed;
1050
1051 struct edp_pwm_delays {
1052         u16 pwm_on_to_backlight_enable;
1053         u16 backlight_disable_to_pwm_off;
1054 } __packed;
1055
1056 struct edp_full_link_params {
1057         u8 preemphasis:4;
1058         u8 vswing:4;
1059 } __packed;
1060
1061 struct edp_apical_params {
1062         u32 panel_oui;
1063         u32 dpcd_base_address;
1064         u32 dpcd_idridix_control_0;
1065         u32 dpcd_option_select;
1066         u32 dpcd_backlight;
1067         u32 ambient_light;
1068         u32 backlight_scale;
1069 } __packed;
1070
1071 struct bdb_edp {
1072         struct edp_power_seq power_seqs[16];
1073         u32 color_depth;
1074         struct edp_fast_link_params fast_link_params[16];
1075         u32 sdrrs_msa_timing_delay;
1076
1077         /* ith bit indicates enabled/disabled for (i+1)th panel */
1078         u16 edp_s3d_feature;                                    /* 162+ */
1079         u16 edp_t3_optimization;                                /* 165+ */
1080         u64 edp_vswing_preemph;                                 /* 173+ */
1081         u16 fast_link_training;                                 /* 182+ */
1082         u16 dpcd_600h_write_required;                           /* 185+ */
1083         struct edp_pwm_delays pwm_delays[16];                   /* 186+ */
1084         u16 full_link_params_provided;                          /* 199+ */
1085         struct edp_full_link_params full_link_params[16];       /* 199+ */
1086         u16 apical_enable;                                      /* 203+ */
1087         struct edp_apical_params apical_params[16];             /* 203+ */
1088         u16 edp_fast_link_training_rate[16];                    /* 224+ */
1089         u16 edp_max_port_link_rate[16];                         /* 244+ */
1090         u16 edp_dsc_disable;                                    /* 251+ */
1091         u16 t6_delay_support;                                   /* 260+ */
1092         u16 link_idle_time[16];                                 /* 260+ */
1093 } __packed;
1094
1095 /*
1096  * Block 28 - EFP DTD Block
1097  */
1098
1099 struct bdb_efp_dtd {
1100         struct bdb_edid_dtd dtd[3];
1101 } __packed;
1102
1103 /*
1104  * Block 29 - Toggle List Block (IVB)
1105  */
1106
1107 struct toggle_list_entry_ivb {
1108         u8 display_select;
1109 } __packed;
1110
1111 struct toggle_list_table_ivb {
1112         u16 num_entries;
1113         u8 entry_size;
1114         struct toggle_list_entry_ivb list[];
1115 } __packed;
1116
1117 struct bdb_display_select_ivb {
1118         /* each table has variable size! */
1119         struct toggle_list_table_ivb tables[4];
1120 } __packed;
1121
1122 /*
1123  * Block 30 - Display Configuration Removal Table (IVB)
1124  */
1125
1126 struct display_remove_entry_ivb {
1127         u8 display_select;
1128 } __packed;
1129
1130 struct bdb_display_remove_ivb {
1131         u8 num_entries;
1132         u8 entry_size;
1133         struct display_remove_entry_ivb table[];
1134 } __packed;
1135
1136 /*
1137  * Block 31 - Toggle List Block (HSW+)
1138  */
1139
1140 struct toggle_list_entry_hsw {
1141         u16 display_select;
1142 } __packed;
1143
1144 struct toggle_list_table_hsw {
1145         u16 num_entries;
1146         u8 entry_size;
1147         struct toggle_list_entry_hsw list[];
1148 } __packed;
1149
1150 struct bdb_display_select_hsw {
1151         /* each table has variable size! */
1152         struct toggle_list_table_hsw tables[4];
1153 } __packed;
1154
1155 /*
1156  * Block 32 - Display Configuration Removal Table (HSW+)
1157  */
1158
1159 struct display_remove_entry_hsw {
1160         u16 display_select;
1161 } __packed;
1162
1163 struct bdb_display_remove_hsw {
1164         u8 num_entries;
1165         u8 entry_size;
1166         struct display_remove_entry_hsw table[];
1167 } __packed;
1168
1169 /*
1170  * Block 40 - LFP Data Block
1171  */
1172
1173 struct bdb_lfp_options {
1174         u8 panel_type;
1175         u8 panel_type2;                                         /* 212+ */
1176         /* LVDS capabilities, stored in a dword */
1177         u8 pfit_mode:2;
1178         u8 pfit_text_mode_enhanced:1;
1179         u8 pfit_gfx_mode_enhanced:1;
1180         u8 pfit_ratio_auto:1;
1181         u8 pixel_dither:1;
1182         u8 lvds_edid:1;                                         /* ???-240 */
1183         u8 rsvd2:1;
1184         u8 rsvd4;
1185         /* LVDS Panel channel bits stored here */
1186         u32 lvds_panel_channel_bits;
1187         /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
1188         u16 ssc_bits;
1189         u16 ssc_freq;
1190         u16 ssc_ddt;
1191         /* Panel color depth defined here */
1192         u16 panel_color_depth;
1193         /* LVDS panel type bits stored here */
1194         u32 dps_panel_type_bits;
1195         /* LVDS backlight control type bits stored here */
1196         u32 blt_control_type_bits;                              /* ???-240 */
1197
1198         u16 lcdvcc_s0_enable;                                   /* 200+ */
1199         u32 rotation;                                           /* 228+ */
1200         u32 position;                                           /* 240+ */
1201 } __packed;
1202
1203 /*
1204  * Block 41 - LFP Data Table Pointers
1205  */
1206 struct lfp_data_ptr_table {
1207         u16 offset; /* offsets are from start of bdb */
1208         u8 table_size;
1209 } __packed;
1210
1211 /* LFP pointer table contains entries to the struct below */
1212 struct lfp_data_ptr {
1213         struct lfp_data_ptr_table fp_timing;
1214         struct lfp_data_ptr_table dvo_timing;
1215         struct lfp_data_ptr_table panel_pnp_id;
1216 } __packed;
1217
1218 struct bdb_lfp_data_ptrs {
1219         u8 num_entries;
1220         struct lfp_data_ptr ptr[16];
1221         struct lfp_data_ptr_table panel_name;           /* (156-163?)+ */
1222 } __packed;
1223
1224 /*
1225  * Block 42 - LFP Data Tables
1226  */
1227
1228 /* LFP data has 3 blocks per entry */
1229 struct fp_timing {
1230         u16 x_res;
1231         u16 y_res;
1232         u32 lvds_reg;
1233         u32 lvds_reg_val;
1234         u32 pp_on_reg;
1235         u32 pp_on_reg_val;
1236         u32 pp_off_reg;
1237         u32 pp_off_reg_val;
1238         u32 pp_cycle_reg;
1239         u32 pp_cycle_reg_val;
1240         u32 pfit_reg;
1241         u32 pfit_reg_val;
1242         u16 terminator;
1243 } __packed;
1244
1245 /*
1246  * For reference only. fp_timing has variable size so
1247  * the data must be accessed using the data table pointers.
1248  * Do not use this directly!
1249  */
1250 struct lfp_data_entry {
1251         struct fp_timing fp_timing;
1252         struct bdb_edid_dtd dvo_timing;
1253         struct bdb_edid_pnp_id pnp_id;
1254 } __packed;
1255
1256 struct bdb_lfp_data {
1257         struct lfp_data_entry data[16];
1258 } __packed;
1259
1260 struct lfp_black_border {
1261         u8 top;         /* 227+ */
1262         u8 bottom;      /* 227+ */
1263         u8 left;        /* 238+ */
1264         u8 right;       /* 238+ */
1265 } __packed;
1266
1267 struct bdb_lfp_data_tail {
1268         struct bdb_edid_product_name panel_name[16];            /* (156-163?)+ */
1269         u16 scaling_enable;                                     /* 187+ */
1270         u8 seamless_drrs_min_refresh_rate[16];                  /* 188+ */
1271         u8 pixel_overlap_count[16];                             /* 208+ */
1272         struct lfp_black_border black_border[16];               /* 227+ */
1273         u16 dual_lfp_port_sync_enable;                          /* 231+ */
1274         u16 gpu_dithering_for_banding_artifacts;                /* 245+ */
1275 } __packed;
1276
1277 /*
1278  * Block 43 - LFP Backlight Control Data Block
1279  */
1280
1281 #define BDB_BACKLIGHT_TYPE_NONE 0
1282 #define BDB_BACKLIGHT_TYPE_PWM  2
1283
1284 struct lfp_backlight_data_entry {
1285         u8 type:2;
1286         u8 active_low_pwm:1;
1287         u8 i2c_pin:3;                                           /* obsolete since ? */
1288         u8 i2c_speed:2;                                         /* obsolete since ? */
1289         u16 pwm_freq_hz;
1290         u8 min_brightness;                                      /* ???-233 */
1291         u8 i2c_address;                                         /* obsolete since ? */
1292         u8 i2c_command;                                         /* obsolete since ? */
1293 } __packed;
1294
1295 struct lfp_backlight_control_method {
1296         u8 type:4;
1297         u8 controller:4;
1298 } __packed;
1299
1300 struct lfp_brightness_level {
1301         u16 level;
1302         u16 reserved;
1303 } __packed;
1304
1305 struct bdb_lfp_backlight {
1306         u8 entry_size;
1307         struct lfp_backlight_data_entry data[16];
1308         u8 level[16];                                                   /* 162-233 */
1309         struct lfp_backlight_control_method backlight_control[16];      /* 191+ */
1310         struct lfp_brightness_level brightness_level[16];               /* 234+ */
1311         struct lfp_brightness_level brightness_min_level[16];           /* 234+ */
1312         u8 brightness_precision_bits[16];                               /* 236+ */
1313         u16 hdr_dpcd_refresh_timeout[16];                               /* 239+ */
1314 } __packed;
1315
1316 /*
1317  * Block 44 - LFP Power Conservation Features Block
1318  */
1319 struct lfp_power_features {
1320         u8 dpst_support:1;                                              /* ???-159 */
1321         u8 power_conservation_pref:3;
1322         u8 reserved2:1;
1323         u8 lace_enabled_status:1;                                       /* 210+ */
1324         u8 lace_support:1;                                              /* 210+ */
1325         u8 als_enable:1;
1326 } __packed;
1327
1328 struct als_data_entry {
1329         u16 backlight_adjust;
1330         u16 lux;
1331 } __packed;
1332
1333 struct aggressiveness_profile_entry {
1334         u8 dpst_aggressiveness : 4;             /* (228/252)-256 */
1335         u8 lace_aggressiveness : 4;
1336 } __packed;
1337
1338 struct aggressiveness_profile2_entry {
1339         u8 opst_aggressiveness : 4;
1340         u8 elp_aggressiveness : 4;
1341 } __packed;
1342
1343 struct aggressiveness_profile3_entry {
1344         u8 apd_aggressiveness:4;
1345         u8 pixoptix_aggressiveness:4;
1346 } __packed;
1347
1348 struct aggressiveness_profile4_entry {
1349         u8 xpst_aggressiveness:4;
1350         u8 tcon_aggressiveness:4;
1351 } __packed;
1352
1353 struct panel_identification {
1354         u8 panel_technology:4;
1355         u8 reserved:4;
1356 } __packed;
1357
1358 struct bdb_lfp_power {
1359         struct lfp_power_features features;                             /* ???-227 */
1360         struct als_data_entry als[5];
1361         u8 lace_aggressiveness_profile:3;                               /* 210-227 */
1362         u8 reserved1:5;
1363         u16 dpst;                                                       /* 228-256 */
1364         u16 psr;                                                        /* 228+ */
1365         u16 drrs;                                                       /* 228+ */
1366         u16 lace_support;                                               /* 228+ */
1367         u16 adt;                                                        /* 228+ */
1368         u16 dmrrs;                                                      /* 228+ */
1369         u16 adb;                                                        /* 228+ */
1370         u16 lace_enabled_status;                                        /* 228+ */
1371         struct aggressiveness_profile_entry aggressiveness[16];
1372         u16 hobl;                                                       /* 232+ */
1373         u16 vrr_feature_enabled;                                        /* 233+ */
1374         u16 elp;                                                        /* 247-256 */
1375         u16 opst;                                                       /* 247-256 */
1376         struct aggressiveness_profile2_entry aggressiveness2[16];       /* 247-256 */
1377         u16 apd;                                                        /* 253-256 */
1378         u16 pixoptix;                                                   /* 253-256 */
1379         struct aggressiveness_profile3_entry aggressiveness3[16];       /* 253-256 */
1380         struct panel_identification panel_identification[16];           /* 257+ */
1381         u16 xpst_support;                                               /* 257+ */
1382         u16 tcon_based_backlight_optimization;                          /* 257+ */
1383         struct aggressiveness_profile4_entry aggressiveness4[16];       /* 257+ */
1384         u16 tcon_backlight_xpst_coexistence;                            /* 257+ */
1385 } __packed;
1386
1387 /*
1388  * Block 45 - eDP BFI Block
1389  */
1390
1391 struct edp_bfi {
1392         u8 enable_bfi_in_driver:1;
1393         u8 enable_brightness_control_in_cui:1;
1394         u8 reserved:6;
1395         u8 brightness_percentage_when_bfi_disabled;
1396 } __packed;
1397
1398 struct bdb_edp_bfi {
1399         u8 bfi_structure_size;
1400         struct edp_bfi bfi[16];
1401 } __packed;
1402
1403 /*
1404  * Block 46 - Chromaticity For Narrow Gamut Panel Configuration Block
1405  */
1406
1407 struct chromaticity {
1408         u8 chromaticity_enable:1;
1409         u8 chromaticity_from_edid_base_block:1;
1410         u8 rsvd:6;
1411
1412         u8 green_y_lo:2;
1413         u8 green_x_lo:2;
1414         u8 red_y_lo:2;
1415         u8 red_x_lo:2;
1416         u8 white_y_lo:2;
1417         u8 white_x_lo:2;
1418         u8 blue_y_lo:2;
1419         u8 blue_x_lo:2;
1420
1421         u8 red_x_hi;
1422         u8 red_y_hi;
1423         u8 green_x_hi;
1424         u8 green_y_hi;
1425         u8 blue_x_hi;
1426         u8 blue_y_hi;
1427         u8 white_x_hi;
1428         u8 white_y_hi;
1429 } __packed;
1430
1431 struct luminance_and_gamma {
1432         u8 luminance_enable:1;                                          /* 211+ */
1433         u8 gamma_enable:1;                                              /* 211+ */
1434         u8 rsvd:6;
1435
1436         u16 min_luminance;                                              /* 211+ */
1437         u16 max_luminance;                                              /* 211+ */
1438         u16 one_percent_max_luminance;                                  /* 211+ */
1439         u8 gamma;                                                       /* 211+ */
1440 } __packed;
1441
1442 struct bdb_chromaticity {
1443         struct chromaticity chromaticity[16];
1444         struct luminance_and_gamma luminance_and_gamma[16];             /* 211+ */
1445 } __packed;
1446
1447 /*
1448  * Block 50 - MIPI Block
1449  */
1450
1451 struct mipi_data {
1452         u16 panel_identifier;
1453         u16 bridge_revision;
1454
1455         u32 dithering:1;
1456         u32 pixel_format_18bpp:1;
1457         u32 reserved1:1;
1458         u32 dphy_params_valid:1;
1459         u32 reserved2:28;
1460
1461         u16 port_info;
1462
1463         u16 reserved3:2;
1464         u16 num_lanes:2;
1465         u16 reserved4:12;
1466
1467         u16 virtual_channel_num:2;
1468         u16 video_transfer_mode:2;
1469         u16 reserved5:12;
1470
1471         u32 dsi_ddr_clock;
1472         u32 renesas_bridge_ref_clock;
1473         u16 power_conservation;
1474
1475         u32 prepare_count:5;
1476         u32 reserved6:3;
1477         u32 clk_zero_count:8;
1478         u32 trail_count:5;
1479         u32 reserved7:3;
1480         u32 exit_zero_count:6;
1481         u32 reserved8:2;
1482
1483         u32 high_low_switch_count;
1484         u32 lp_byte_clock;
1485         u32 clock_lane_switch_time_counter;
1486         u32 panel_color_depth;
1487 } __packed;
1488
1489 struct bdb_mipi {
1490         struct mipi_data mipi[16];
1491 } __packed;
1492
1493 /*
1494  * Block 51 - Fixed Set Mode Table
1495  */
1496
1497 struct bdb_fixed_set_mode {
1498         u8 enable;
1499         u32 x_res;
1500         u32 y_res;
1501 } __packed;
1502
1503 /*
1504  * Block 52 - MIPI Configuration Block
1505  */
1506
1507 #define MAX_MIPI_CONFIGURATIONS 6
1508
1509 struct bdb_mipi_config {
1510         struct mipi_config config[MAX_MIPI_CONFIGURATIONS];             /* 175+ */
1511         struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];              /* 177+ */
1512         struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS];      /* 186+ */
1513         u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS];                /* 190+ */
1514 } __packed;
1515
1516 /*
1517  * Block 53 - MIPI Sequence Block
1518  */
1519
1520 struct bdb_mipi_sequence {
1521         u8 version;
1522         u8 data[]; /* up to 6 variable length blocks */
1523 } __packed;
1524
1525 /*
1526  * Block 55 - RGB Palette Table
1527  */
1528
1529 struct bdb_rgb_palette {
1530         u8 is_enabled;
1531         u8 red[256];
1532         u8 blue[256];
1533         u8 green[256];
1534 } __packed;
1535
1536 /*
1537  * Block 56 - Compression Parameters
1538  */
1539
1540 #define VBT_RC_BUFFER_BLOCK_SIZE_1KB    0
1541 #define VBT_RC_BUFFER_BLOCK_SIZE_4KB    1
1542 #define VBT_RC_BUFFER_BLOCK_SIZE_16KB   2
1543 #define VBT_RC_BUFFER_BLOCK_SIZE_64KB   3
1544
1545 #define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value)    ((vbt_value) + 8) /* bits */
1546 #define VBT_DSC_MAX_BPP(vbt_value)              (6 + (vbt_value) * 2)
1547
1548 struct dsc_compression_parameters_entry {
1549         u8 version_major:4;
1550         u8 version_minor:4;
1551
1552         u8 rc_buffer_block_size:2;
1553         u8 reserved1:6;
1554
1555         /*
1556          * Buffer size in bytes:
1557          *
1558          * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes
1559          */
1560         u8 rc_buffer_size;
1561         u32 slices_per_line;
1562
1563         u8 line_buffer_depth:4;
1564         u8 reserved2:4;
1565
1566         /* Flag Bits 1 */
1567         u8 block_prediction_enable:1;
1568         u8 reserved3:7;
1569
1570         u8 max_bpp; /* mapping */
1571
1572         /* Color depth capabilities */
1573         u8 reserved4:1;
1574         u8 support_8bpc:1;
1575         u8 support_10bpc:1;
1576         u8 support_12bpc:1;
1577         u8 reserved5:4;
1578
1579         u16 slice_height;
1580 } __packed;
1581
1582 struct bdb_compression_parameters {
1583         u16 entry_size;
1584         struct dsc_compression_parameters_entry data[16];
1585 } __packed;
1586
1587 /*
1588  * Block 57 -  Vswing PreEmphasis Table
1589  */
1590
1591 struct bdb_vswing_preemph {
1592         u8 num_tables;
1593         u8 num_columns;
1594         u32 tables[];
1595 } __packed;
1596
1597 /*
1598  * Block 58 - Generic DTD Block
1599  */
1600
1601 struct generic_dtd_entry {
1602         u32 pixel_clock;
1603         u16 hactive;
1604         u16 hblank;
1605         u16 hfront_porch;
1606         u16 hsync;
1607         u16 vactive;
1608         u16 vblank;
1609         u16 vfront_porch;
1610         u16 vsync;
1611         u16 width_mm;
1612         u16 height_mm;
1613
1614         /* Flags */
1615         u8 rsvd_flags:6;
1616         u8 vsync_positive_polarity:1;
1617         u8 hsync_positive_polarity:1;
1618
1619         u8 rsvd[3];
1620 } __packed;
1621
1622 struct bdb_generic_dtd {
1623         u16 gdtd_size;
1624         struct generic_dtd_entry dtd[]; /* up to 24 DTD's */
1625 } __packed;
1626
1627 /*
1628  * Block 253 - PRD Table
1629  */
1630
1631 struct prd_entry_old {
1632         u8 displays_attached;
1633         u8 display_in_pipe_a;
1634         u8 display_in_pipe_b;
1635 } __packed;
1636
1637 struct bdb_prd_table_old {
1638         struct prd_entry_old list[0];                           /* ???-216 */
1639         u16 num_entries;                                        /* ???-216 */
1640 } __packed;
1641
1642 struct prd_entry_new {
1643         u16 primary_display;
1644         u16 secondary_display;
1645 } __packed;
1646
1647 struct bdb_prd_table_new {
1648         u16 num_entries;                                        /* 217+ */
1649         struct prd_entry_new list[];                            /* 217+ */
1650 } __packed;
1651
1652 #endif /* _INTEL_VBT_DEFS_H_ */