drivers/gpu/drm/i915/display/intel_pch_display.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2021 Intel Corporation
   4  */
   5
   6 #include "g4x_dp.h"
   7 #include "i915_drv.h"
   8 #include "i915_reg.h"
   9 #include "intel_crt.h"
  10 #include "intel_crt_regs.h"
  11 #include "intel_de.h"
  12 #include "intel_display_types.h"
  13 #include "intel_dpll.h"
  14 #include "intel_fdi.h"
  15 #include "intel_fdi_regs.h"
  16 #include "intel_lvds.h"
  17 #include "intel_lvds_regs.h"
  18 #include "intel_pch_display.h"
  19 #include "intel_pch_refclk.h"
  20 #include "intel_pps.h"
  21 #include "intel_sdvo.h"
  22
  23 bool intel_has_pch_trancoder(struct drm_i915_private *i915,
  24                              enum pipe pch_transcoder)
  25 {
  26         return HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915) ||
  27                 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A);
  28 }
  29
  30 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
  31 {
  32         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
  33
  34         if (HAS_PCH_LPT(i915))
  35                 return PIPE_A;
  36         else
  37                 return crtc->pipe;
  38 }
  39
  40 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  41                                    enum pipe pipe, enum port port,
  42                                    i915_reg_t dp_reg)
  43 {
  44         struct intel_display *display = &dev_priv->display;
  45         enum pipe port_pipe;
  46         bool state;
  47
  48         state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
  49
  50         INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
  51                                  "PCH DP %c enabled on transcoder %c, should be disabled\n",
  52                                  port_name(port), pipe_name(pipe));
  53
  54         INTEL_DISPLAY_STATE_WARN(display,
  55                                  HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
  56                                  "IBX PCH DP %c still using transcoder B\n",
  57                                  port_name(port));
  58 }
  59
  60 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  61                                      enum pipe pipe, enum port port,
  62                                      i915_reg_t hdmi_reg)
  63 {
  64         struct intel_display *display = &dev_priv->display;
  65         enum pipe port_pipe;
  66         bool state;
  67
  68         state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
  69
  70         INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
  71                                  "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
  72                                  port_name(port), pipe_name(pipe));
  73
  74         INTEL_DISPLAY_STATE_WARN(display,
  75                                  HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
  76                                  "IBX PCH HDMI %c still using transcoder B\n",
  77                                  port_name(port));
  78 }
  79
  80 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  81                                       enum pipe pipe)
  82 {
  83         struct intel_display *display = &dev_priv->display;
  84         enum pipe port_pipe;
  85
  86         assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
  87         assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
  88         assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
  89
  90         INTEL_DISPLAY_STATE_WARN(display,
  91                                  intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,
  92                                  "PCH VGA enabled on transcoder %c, should be disabled\n",
  93                                  pipe_name(pipe));
  94
  95         INTEL_DISPLAY_STATE_WARN(display,
  96                                  intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe,
  97                                  "PCH LVDS enabled on transcoder %c, should be disabled\n",
  98                                  pipe_name(pipe));
  99
 100         /* PCH SDVOB multiplex with HDMIB */
 101         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
 102         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
 103         assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
 104 }
 105
 106 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 107                                            enum pipe pipe)
 108 {
 109         struct intel_display *display = &dev_priv->display;
 110         u32 val;
 111         bool enabled;
 112
 113         val = intel_de_read(display, PCH_TRANSCONF(pipe));
 114         enabled = !!(val & TRANS_ENABLE);
 115         INTEL_DISPLAY_STATE_WARN(display, enabled,
 116                                  "transcoder assertion failed, should be off on pipe %c but is still active\n",
 117                                  pipe_name(pipe));
 118 }
 119
 120 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
 121                                        enum port port, i915_reg_t hdmi_reg)
 122 {
 123         u32 val = intel_de_read(dev_priv, hdmi_reg);
 124
 125         if (val & SDVO_ENABLE ||
 126             (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
 127                 return;
 128
 129         drm_dbg_kms(&dev_priv->drm,
 130                     "Sanitizing transcoder select for HDMI %c\n",
 131                     port_name(port));
 132
 133         val &= ~SDVO_PIPE_SEL_MASK;
 134         val |= SDVO_PIPE_SEL(PIPE_A);
 135
 136         intel_de_write(dev_priv, hdmi_reg, val);
 137 }
 138
 139 static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv,
 140                                      enum port port, i915_reg_t dp_reg)
 141 {
 142         u32 val = intel_de_read(dev_priv, dp_reg);
 143
 144         if (val & DP_PORT_EN ||
 145             (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
 146                 return;
 147
 148         drm_dbg_kms(&dev_priv->drm,
 149                     "Sanitizing transcoder select for DP %c\n",
 150                     port_name(port));
 151
 152         val &= ~DP_PIPE_SEL_MASK;
 153         val |= DP_PIPE_SEL(PIPE_A);
 154
 155         intel_de_write(dev_priv, dp_reg, val);
 156 }
 157
 158 static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv)
 159 {
 160         /*
 161          * The BIOS may select transcoder B on some of the PCH
 162          * ports even it doesn't enable the port. This would trip
 163          * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
 164          * Sanitize the transcoder select bits to prevent that. We
 165          * assume that the BIOS never actually enabled the port,
 166          * because if it did we'd actually have to toggle the port
 167          * on and back off to make the transcoder A select stick
 168          * (see. intel_dp_link_down(), intel_disable_hdmi(),
 169          * intel_disable_sdvo()).
 170          */
 171         ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B);
 172         ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C);
 173         ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D);
 174
 175         /* PCH SDVOB multiplex with HDMIB */
 176         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB);
 177         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC);
 178         ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID);
 179 }
 180
 181 static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
 182                                            const struct intel_link_m_n *m_n)
 183 {
 184         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 185         enum pipe pipe = crtc->pipe;
 186
 187         intel_set_m_n(dev_priv, m_n,
 188                       PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
 189                       PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
 190 }
 191
 192 static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
 193                                            const struct intel_link_m_n *m_n)
 194 {
 195         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 196         enum pipe pipe = crtc->pipe;
 197
 198         intel_set_m_n(dev_priv, m_n,
 199                       PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
 200                       PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
 201 }
 202
 203 void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
 204                                     struct intel_link_m_n *m_n)
 205 {
 206         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 207         enum pipe pipe = crtc->pipe;
 208
 209         intel_get_m_n(dev_priv, m_n,
 210                       PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
 211                       PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
 212 }
 213
 214 void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
 215                                     struct intel_link_m_n *m_n)
 216 {
 217         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 218         enum pipe pipe = crtc->pipe;
 219
 220         intel_get_m_n(dev_priv, m_n,
 221                       PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
 222                       PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
 223 }
 224
 225 static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
 226                                            enum pipe pch_transcoder)
 227 {
 228         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 229         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 230         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 231
 232         intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
 233                        intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)));
 234         intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
 235                        intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder)));
 236         intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
 237                        intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)));
 238
 239         intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
 240                        intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)));
 241         intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
 242                        intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder)));
 243         intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
 244                        intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)));
 245         intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
 246                        intel_de_read(dev_priv, TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder)));
 247 }
 248
 249 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 250 {
 251         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 252         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 253         enum pipe pipe = crtc->pipe;
 254         i915_reg_t reg;
 255         u32 val, pipeconf_val;
 256
 257         /* Make sure PCH DPLL is enabled */
 258         assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
 259
 260         /* FDI must be feeding us bits for PCH ports */
 261         assert_fdi_tx_enabled(dev_priv, pipe);
 262         assert_fdi_rx_enabled(dev_priv, pipe);
 263
 264         if (HAS_PCH_CPT(dev_priv)) {
 265                 reg = TRANS_CHICKEN2(pipe);
 266                 val = intel_de_read(dev_priv, reg);
 267                 /*
 268                  * Workaround: Set the timing override bit
 269                  * before enabling the pch transcoder.
 270                  */
 271                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 272                 /* Configure frame start delay to match the CPU */
 273                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
 274                 val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
 275                 intel_de_write(dev_priv, reg, val);
 276         }
 277
 278         reg = PCH_TRANSCONF(pipe);
 279         val = intel_de_read(dev_priv, reg);
 280         pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe));
 281
 282         if (HAS_PCH_IBX(dev_priv)) {
 283                 /* Configure frame start delay to match the CPU */
 284                 val &= ~TRANS_FRAME_START_DELAY_MASK;
 285                 val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
 286
 287                 /*
 288                  * Make the BPC in transcoder be consistent with
 289                  * that in pipeconf reg. For HDMI we must use 8bpc
 290                  * here for both 8bpc and 12bpc.
 291                  */
 292                 val &= ~TRANSCONF_BPC_MASK;
 293                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 294                         val |= TRANSCONF_BPC_8;
 295                 else
 296                         val |= pipeconf_val & TRANSCONF_BPC_MASK;
 297         }
 298
 299         val &= ~TRANS_INTERLACE_MASK;
 300         if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) {
 301                 if (HAS_PCH_IBX(dev_priv) &&
 302                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
 303                         val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
 304                 else
 305                         val |= TRANS_INTERLACE_INTERLACED;
 306         } else {
 307                 val |= TRANS_INTERLACE_PROGRESSIVE;
 308         }
 309
 310         intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
 311         if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
 312                 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
 313                         pipe_name(pipe));
 314 }
 315
 316 static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
 317 {
 318         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 319         enum pipe pipe = crtc->pipe;
 320         i915_reg_t reg;
 321
 322         /* FDI relies on the transcoder */
 323         assert_fdi_tx_disabled(dev_priv, pipe);
 324         assert_fdi_rx_disabled(dev_priv, pipe);
 325
 326         /* Ports must be off as well */
 327         assert_pch_ports_disabled(dev_priv, pipe);
 328
 329         reg = PCH_TRANSCONF(pipe);
 330         intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0);
 331         /* wait for PCH transcoder off, transcoder state */
 332         if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
 333                 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
 334                         pipe_name(pipe));
 335
 336         if (HAS_PCH_CPT(dev_priv))
 337                 /* Workaround: Clear the timing override chicken bit again. */
 338                 intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe),
 339                              TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
 340 }
 341
 342 void ilk_pch_pre_enable(struct intel_atomic_state *state,
 343                         struct intel_crtc *crtc)
 344 {
 345         const struct intel_crtc_state *crtc_state =
 346                 intel_atomic_get_new_crtc_state(state, crtc);
 347
 348         /*
 349          * Note: FDI PLL enabling _must_ be done before we enable the
 350          * cpu pipes, hence this is separate from all the other fdi/pch
 351          * enabling.
 352          */
 353         ilk_fdi_pll_enable(crtc_state);
 354 }
 355
 356 /*
 357  * Enable PCH resources required for PCH ports:
 358  *   - PCH PLLs
 359  *   - FDI training & RX/TX
 360  *   - update transcoder timings
 361  *   - DP transcoding bits
 362  *   - transcoder
 363  */
 364 void ilk_pch_enable(struct intel_atomic_state *state,
 365                     struct intel_crtc *crtc)
 366 {
 367         struct intel_display *display = to_intel_display(state);
 368         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 369         const struct intel_crtc_state *crtc_state =
 370                 intel_atomic_get_new_crtc_state(state, crtc);
 371         enum pipe pipe = crtc->pipe;
 372         u32 temp;
 373
 374         assert_pch_transcoder_disabled(dev_priv, pipe);
 375
 376         /* For PCH output, training FDI link */
 377         intel_fdi_link_train(crtc, crtc_state);
 378
 379         /*
 380          * We need to program the right clock selection
 381          * before writing the pixel multiplier into the DPLL.
 382          */
 383         if (HAS_PCH_CPT(dev_priv)) {
 384                 u32 sel;
 385
 386                 temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
 387                 temp |= TRANS_DPLL_ENABLE(pipe);
 388                 sel = TRANS_DPLLB_SEL(pipe);
 389                 if (crtc_state->shared_dpll ==
 390                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
 391                         temp |= sel;
 392                 else
 393                         temp &= ~sel;
 394                 intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
 395         }
 396
 397         /*
 398          * XXX: pch pll's can be enabled any time before we enable the PCH
 399          * transcoder, and we actually should do this to not upset any PCH
 400          * transcoder that already use the clock when we share it.
 401          *
 402          * Note that enable_shared_dpll tries to do the right thing, but
 403          * get_shared_dpll unconditionally resets the pll - we need that
 404          * to have the right LVDS enable sequence.
 405          */
 406         intel_enable_shared_dpll(crtc_state);
 407
 408         /* set transcoder timing, panel must allow it */
 409         assert_pps_unlocked(display, pipe);
 410         if (intel_crtc_has_dp_encoder(crtc_state)) {
 411                 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);
 412                 intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);
 413         }
 414         ilk_pch_transcoder_set_timings(crtc_state, pipe);
 415
 416         intel_fdi_normal_train(crtc);
 417
 418         /* For PCH DP, enable TRANS_DP_CTL */
 419         if (HAS_PCH_CPT(dev_priv) &&
 420             intel_crtc_has_dp_encoder(crtc_state)) {
 421                 const struct drm_display_mode *adjusted_mode =
 422                         &crtc_state->hw.adjusted_mode;
 423                 u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;
 424                 i915_reg_t reg = TRANS_DP_CTL(pipe);
 425                 enum port port;
 426
 427                 temp = intel_de_read(dev_priv, reg);
 428                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
 429                           TRANS_DP_VSYNC_ACTIVE_HIGH |
 430                           TRANS_DP_HSYNC_ACTIVE_HIGH |
 431                           TRANS_DP_BPC_MASK);
 432                 temp |= TRANS_DP_OUTPUT_ENABLE;
 433                 temp |= bpc << 9; /* same format but at 11:9 */
 434
 435                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 436                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
 437                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 438                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 439
 440                 port = intel_get_crtc_new_encoder(state, crtc_state)->port;
 441                 drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
 442                 temp |= TRANS_DP_PORT_SEL(port);
 443
 444                 intel_de_write(dev_priv, reg, temp);
 445         }
 446
 447         ilk_enable_pch_transcoder(crtc_state);
 448 }
 449
 450 void ilk_pch_disable(struct intel_atomic_state *state,
 451                      struct intel_crtc *crtc)
 452 {
 453         ilk_fdi_disable(crtc);
 454 }
 455
 456 void ilk_pch_post_disable(struct intel_atomic_state *state,
 457                           struct intel_crtc *crtc)
 458 {
 459         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 460         enum pipe pipe = crtc->pipe;
 461
 462         ilk_disable_pch_transcoder(crtc);
 463
 464         if (HAS_PCH_CPT(dev_priv)) {
 465                 /* disable TRANS_DP_CTL */
 466                 intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe),
 467                              TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK,
 468                              TRANS_DP_PORT_SEL_NONE);
 469
 470                 /* disable DPLL_SEL */
 471                 intel_de_rmw(dev_priv, PCH_DPLL_SEL,
 472                              TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0);
 473         }
 474
 475         ilk_fdi_pll_disable(crtc);
 476 }
 477
 478 static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
 479 {
 480         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 481         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 482
 483         /* read out port_clock from the DPLL */
 484         i9xx_crtc_clock_get(crtc_state);
 485
 486         /*
 487          * In case there is an active pipe without active ports,
 488          * we may need some idea for the dotclock anyway.
 489          * Calculate one based on the FDI configuration.
 490          */
 491         crtc_state->hw.adjusted_mode.crtc_clock =
 492                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state),
 493                                          &crtc_state->fdi_m_n);
 494 }
 495
 496 void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
 497 {
 498         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 499         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 500         struct intel_shared_dpll *pll;
 501         enum pipe pipe = crtc->pipe;
 502         enum intel_dpll_id pll_id;
 503         bool pll_active;
 504         u32 tmp;
 505
 506         if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
 507                 return;
 508
 509         crtc_state->has_pch_encoder = true;
 510
 511         tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
 512         crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
 513                                  FDI_DP_PORT_WIDTH_SHIFT) + 1;
 514
 515         intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
 516                                        &crtc_state->fdi_m_n);
 517
 518         if (HAS_PCH_IBX(dev_priv)) {
 519                 /*
 520                  * The pipe->pch transcoder and pch transcoder->pll
 521                  * mapping is fixed.
 522                  */
 523                 pll_id = (enum intel_dpll_id) pipe;
 524         } else {
 525                 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
 526                 if (tmp & TRANS_DPLLB_SEL(pipe))
 527                         pll_id = DPLL_ID_PCH_PLL_B;
 528                 else
 529                         pll_id = DPLL_ID_PCH_PLL_A;
 530         }
 531
 532         crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
 533         pll = crtc_state->shared_dpll;
 534
 535         pll_active = intel_dpll_get_hw_state(dev_priv, pll,
 536                                              &crtc_state->dpll_hw_state);
 537         drm_WARN_ON(&dev_priv->drm, !pll_active);
 538
 539         tmp = crtc_state->dpll_hw_state.i9xx.dpll;
 540         crtc_state->pixel_multiplier =
 541                 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
 542                  >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
 543
 544         ilk_pch_clock_get(crtc_state);
 545 }
 546
 547 static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 548 {
 549         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 550         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 551         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 552         u32 val, pipeconf_val;
 553
 554         /* FDI must be feeding us bits for PCH ports */
 555         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
 556         assert_fdi_rx_enabled(dev_priv, PIPE_A);
 557
 558         val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
 559         /* Workaround: set timing override bit. */
 560         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 561         /* Configure frame start delay to match the CPU */
 562         val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
 563         val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
 564         intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
 565
 566         val = TRANS_ENABLE;
 567         pipeconf_val = intel_de_read(dev_priv,
 568                                      TRANSCONF(dev_priv, cpu_transcoder));
 569
 570         if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK)
 571                 val |= TRANS_INTERLACE_INTERLACED;
 572         else
 573                 val |= TRANS_INTERLACE_PROGRESSIVE;
 574
 575         intel_de_write(dev_priv, LPT_TRANSCONF, val);
 576         if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
 577                                   TRANS_STATE_ENABLE, 100))
 578                 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n");
 579 }
 580
 581 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
 582 {
 583         intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0);
 584         /* wait for PCH transcoder off, transcoder state */
 585         if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
 586                                     TRANS_STATE_ENABLE, 50))
 587                 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
 588
 589         /* Workaround: clear timing override bit. */
 590         intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
 591 }
 592
 593 void lpt_pch_enable(struct intel_atomic_state *state,
 594                     struct intel_crtc *crtc)
 595 {
 596         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 597         const struct intel_crtc_state *crtc_state =
 598                 intel_atomic_get_new_crtc_state(state, crtc);
 599
 600         assert_pch_transcoder_disabled(dev_priv, PIPE_A);
 601
 602         lpt_program_iclkip(crtc_state);
 603
 604         /* Set transcoder timing. */
 605         ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
 606
 607         lpt_enable_pch_transcoder(crtc_state);
 608 }
 609
 610 void lpt_pch_disable(struct intel_atomic_state *state,
 611                      struct intel_crtc *crtc)
 612 {
 613         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 614
 615         lpt_disable_pch_transcoder(dev_priv);
 616
 617         lpt_disable_iclkip(dev_priv);
 618 }
 619
 620 void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
 621 {
 622         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 623         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 624         u32 tmp;
 625
 626         if ((intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
 627                 return;
 628
 629         crtc_state->has_pch_encoder = true;
 630
 631         tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
 632         crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
 633                                  FDI_DP_PORT_WIDTH_SHIFT) + 1;
 634
 635         intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
 636                                        &crtc_state->fdi_m_n);
 637
 638         crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 639 }
 640
 641 void intel_pch_sanitize(struct drm_i915_private *i915)
 642 {
 643         if (HAS_PCH_IBX(i915))
 644                 ibx_sanitize_pch_ports(i915);
 645 }