drivers/gpu/drm/i915/display/intel_dsb_regs.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2023 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_DSB_REGS_H__
   7 #define __INTEL_DSB_REGS_H__
   8
   9 #include "intel_display_reg_defs.h"
  10
  11 /* This register controls the Display State Buffer (DSB) engines. */
  12 #define _DSBSL_INSTANCE_BASE            0x70B00
  13 #define DSBSL_INSTANCE(pipe, id)        (_DSBSL_INSTANCE_BASE + \
  14                                          (pipe) * 0x1000 + (id) * 0x100)
  15 #define DSB_HEAD(pipe, id)              _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
  16 #define DSB_TAIL(pipe, id)              _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
  17 #define DSB_CTRL(pipe, id)              _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
  18 #define   DSB_ENABLE                    REG_BIT(31)
  19 #define   DSB_BUF_REITERATE             REG_BIT(29)
  20 #define   DSB_WAIT_FOR_VBLANK           REG_BIT(28)
  21 #define   DSB_WAIT_FOR_LINE_IN          REG_BIT(27)
  22 #define   DSB_HALT                      REG_BIT(16)
  23 #define   DSB_NON_POSTED                REG_BIT(8)
  24 #define   DSB_STATUS_BUSY               REG_BIT(0)
  25 #define DSB_MMIOCTRL(pipe, id)          _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)
  26 #define   DSB_MMIO_DEAD_CLOCKS_ENABLE   REG_BIT(31)
  27 #define   DSB_MMIO_DEAD_CLOCKS_COUNT_MASK       REG_GENMASK(15, 8)
  28 #define   DSB_MMIO_DEAD_CLOCKS_COUNT(x) REG_FIELD_PREP(DSB_MMIO_DEAD_CLOCK_COUNT_MASK, (x))
  29 #define   DSB_MMIO_CYCLES_MASK          REG_GENMASK(7, 0)
  30 #define   DSB_MMIO_CYCLES(x)            REG_FIELD_PREP(DSB_MMIO_CYCLES_MASK, (x))
  31 #define DSB_POLLFUNC(pipe, id)          _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)
  32 #define   DSB_POLL_ENABLE               REG_BIT(31)
  33 #define   DSB_POLL_WAIT_MASK            REG_GENMASK(30, 23)
  34 #define   DSB_POLL_WAIT(x)              REG_FIELD_PREP(DSB_POLL_WAIT_MASK, (x)) /* usec */
  35 #define   DSB_POLL_COUNT_MASK           REG_GENMASK(22, 15)
  36 #define   DSB_POLL_COUNT(x)             REG_FIELD_PREP(DSB_POLL_COUNT_MASK, (x))
  37 #define DSB_DEBUG(pipe, id)             _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)
  38 #define DSB_POLLMASK(pipe, id)          _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
  39 #define DSB_STATUS(pipe, id)            _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)
  40 #define   DSB_HP_IDLE_STATUS            REG_BIT(31)
  41 #define   DSB_DEWAKE_STATUS             REG_BIT(30)
  42 #define   DSB_REQARB_SM_STATE_MASK      REG_GENMASK(29, 27)
  43 #define   DSB_SAFE_WINDOW_LIVE          REG_BIT(26)
  44 #define   DSB_VTDFAULT_ARB_SM_STATE_MASK        REG_GENMASK(25, 23)
  45 #define   DSB_TLBTRANS_SM_STATE_MASK    REG_GENMASK(21, 20)
  46 #define   DSB_SAFE_WINDOW               REG_BIT(19)
  47 #define   DSB_POINTERS_SM_STATE_MASK    REG_GENMASK(18, 17)
  48 #define   DSB_BUSY_DURING_DELAYED_VBLANK        REG_BIT(16)
  49 #define   DSB_MMIO_ARB_SM_STATE_MASK    REG_GENMASK(15, 13)
  50 #define   DSB_MMIO_INST_SM_STATE_MASK   REG_GENMASK(11, 7)
  51 #define   DSB_RESET_SM_STATE_MASK       REG_GENMASK(5, 4)
  52 #define   DSB_RUN_SM_STATE_MASK         REG_GENMASK(2, 0)
  53 #define DSB_INTERRUPT(pipe, id)         _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
  54 #define   DSB_ATS_FAULT_INT_EN          REG_BIT(20) /* mtl+ */
  55 #define   DSB_GTT_FAULT_INT_EN          REG_BIT(19)
  56 #define   DSB_RSPTIMEOUT_INT_EN         REG_BIT(18)
  57 #define   DSB_POLL_ERR_INT_EN           REG_BIT(17)
  58 #define   DSB_PROG_INT_EN               REG_BIT(16)
  59 #define   DSB_ATS_FAULT_INT_STATUS      REG_BIT(4) /* mtl+ */
  60 #define   DSB_GTT_FAULT_INT_STATUS      REG_BIT(3)
  61 #define   DSB_RSPTIMEOUT_INT_STATUS     REG_BIT(2)
  62 #define   DSB_POLL_ERR_INT_STATUS       REG_BIT(1)
  63 #define   DSB_PROG_INT_STATUS           REG_BIT(0)
  64 #define DSB_CURRENT_HEAD(pipe, id)      _MMIO(DSBSL_INSTANCE(pipe, id) + 0x2c)
  65 #define DSB_RM_TIMEOUT(pipe, id)        _MMIO(DSBSL_INSTANCE(pipe, id) + 0x30)
  66 #define   DSB_RM_CLAIM_TIMEOUT          REG_BIT(31)
  67 #define   DSB_RM_READY_TIMEOUT          REG_BIT(30)
  68 #define   DSB_RM_CLAIM_TIMEOUT_COUNT_MASK       REG_GENMASK(23, 16)
  69 #define   DSB_RM_CLAIM_TIMEOUT_COUNT(x) REG_FIELD_PREP(DSB_RM_CLAIM_TIMEOUT_COUNT_MASK, (x)) /* clocks */
  70 #define   DSB_RM_READY_TIMEOUT_VALUE_MASK       REG_GENMASK(15, 0)
  71 #define   DSB_RM_READY_TIMEOUT_VALUE(x) REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */
  72 #define DSB_RMTIMEOUTREG_CAPTURE(pipe, id)      _MMIO(DSBSL_INSTANCE(pipe, id) + 0x34)
  73 #define DSB_PMCTRL(pipe, id)            _MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)
  74 #define   DSB_ENABLE_DEWAKE             REG_BIT(31)
  75 #define   DSB_SCANLINE_FOR_DEWAKE_MASK  REG_GENMASK(30, 0)
  76 #define   DSB_SCANLINE_FOR_DEWAKE(x)    REG_FIELD_PREP(DSB_SCANLINE_FOR_DEWAKE_MASK, (x))
  77 #define DSB_PMCTRL_2(pipe, id)          _MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c)
  78 #define   DSB_MMIOGEN_DEWAKE_DIS        REG_BIT(31)
  79 #define   DSB_FORCE_DEWAKE              REG_BIT(23)
  80 #define   DSB_BLOCK_DEWAKE_EXTENSION    REG_BIT(15)
  81 #define   DSB_OVERRIDE_DC5_DC6_OK       REG_BIT(7)
  82 #define DSB_PF_LN_LOWER(pipe, id)       _MMIO(DSBSL_INSTANCE(pipe, id) + 0x40)
  83 #define DSB_PF_LN_UPPER(pipe, id)       _MMIO(DSBSL_INSTANCE(pipe, id) + 0x44)
  84 #define DSB_BUFRPT_CNT(pipe, id)        _MMIO(DSBSL_INSTANCE(pipe, id) + 0x48)
  85 #define DSB_CHICKEN(pipe, id)           _MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0)
  86 #define   DSB_FORCE_DMA_SYNC_RESET      REG_BIT(31)
  87 #define   DSB_FORCE_VTD_ENGIE_RESET     REG_BIT(30)
  88 #define   DSB_DISABLE_IPC_DEMOTE        REG_BIT(29)
  89 #define   DSB_SKIP_WAITS_EN             REG_BIT(23)
  90 #define   DSB_EXTEND_HP_IDLE            REG_BIT(16)
  91 #define   DSB_CTRL_WAIT_SAFE_WINDOW     REG_BIT(15)
  92 #define   DSB_CTRL_NO_WAIT_VBLANK       REG_BIT(14)
  93 #define   DSB_INST_WAIT_SAFE_WINDOW     REG_BIT(7)
  94 #define   DSB_INST_NO_WAIT_VBLANK       REG_BIT(6)
  95 #define   DSB_MMIOGEN_DEWAKE_DIS_CHICKEN        REG_BIT(2)
  96 #define   DSB_DISABLE_MMIO_COUNT_FOR_INDEXED    REG_BIT(0)
  97
  98 #endif /* __INTEL_DSB_REGS_H__ */