drivers/gpu/drm/i915/display/intel_display_device.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2023 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_DISPLAY_DEVICE_H__
   7 #define __INTEL_DISPLAY_DEVICE_H__
   8
   9 #include <linux/bitops.h>
  10 #include <linux/types.h>
  11
  12 #include "intel_display_conversion.h"
  13 #include "intel_display_limits.h"
  14
  15 struct drm_printer;
  16 struct intel_display;
  17 struct pci_dev;
  18
  19 /*
  20  * Display platforms and subplatforms. Keep platforms in display version based
  21  * order, chronological order within a version, and subplatforms next to the
  22  * platform.
  23  */
  24 #define INTEL_DISPLAY_PLATFORMS(func) \
  25         /* Platform group aliases */ \
  26         func(g4x) /* g45 and gm45 */ \
  27         func(mobile) /* mobile platforms */ \
  28         func(dgfx) /* discrete graphics */ \
  29         /* Display ver 2 */ \
  30         func(i830) \
  31         func(i845g) \
  32         func(i85x) \
  33         func(i865g) \
  34         /* Display ver 3 */ \
  35         func(i915g) \
  36         func(i915gm) \
  37         func(i945g) \
  38         func(i945gm) \
  39         func(g33) \
  40         func(pineview) \
  41         /* Display ver 4 */ \
  42         func(i965g) \
  43         func(i965gm) \
  44         func(g45) \
  45         func(gm45) \
  46         /* Display ver 5 */ \
  47         func(ironlake) \
  48         /* Display ver 6 */ \
  49         func(sandybridge) \
  50         /* Display ver 7 */ \
  51         func(ivybridge) \
  52         func(valleyview) \
  53         func(haswell) \
  54         func(haswell_ult) \
  55         func(haswell_ulx) \
  56         /* Display ver 8 */ \
  57         func(broadwell) \
  58         func(broadwell_ult) \
  59         func(broadwell_ulx) \
  60         func(cherryview) \
  61         /* Display ver 9 */ \
  62         func(skylake) \
  63         func(skylake_ult) \
  64         func(skylake_ulx) \
  65         func(broxton) \
  66         func(kabylake) \
  67         func(kabylake_ult) \
  68         func(kabylake_ulx) \
  69         func(geminilake) \
  70         func(coffeelake) \
  71         func(coffeelake_ult) \
  72         func(coffeelake_ulx) \
  73         func(cometlake) \
  74         func(cometlake_ult) \
  75         func(cometlake_ulx) \
  76         /* Display ver 11 */ \
  77         func(icelake) \
  78         func(icelake_port_f) \
  79         func(jasperlake) \
  80         func(elkhartlake) \
  81         /* Display ver 12 */ \
  82         func(tigerlake) \
  83         func(tigerlake_uy) \
  84         func(rocketlake) \
  85         func(dg1) \
  86         func(alderlake_s) \
  87         func(alderlake_s_raptorlake_s) \
  88         /* Display ver 13 */ \
  89         func(alderlake_p) \
  90         func(alderlake_p_alderlake_n) \
  91         func(alderlake_p_raptorlake_p) \
  92         func(alderlake_p_raptorlake_u) \
  93         func(dg2) \
  94         func(dg2_g10) \
  95         func(dg2_g11) \
  96         func(dg2_g12) \
  97         /* Display ver 14 (based on GMD ID) */ \
  98         func(meteorlake) \
  99         /* Display ver 20 (based on GMD ID) */ \
 100         func(lunarlake) \
 101         /* Display ver 14.1 (based on GMD ID) */ \
 102         func(battlemage) \
 103         /* Display ver 30 (based on GMD ID) */ \
 104         func(pantherlake)
 105
 106 #define __MEMBER(name) unsigned long name:1;
 107 #define __COUNT(x) 1 +
 108
 109 #define __NUM_PLATFORMS (INTEL_DISPLAY_PLATFORMS(__COUNT) 0)
 110
 111 struct intel_display_platforms {
 112         union {
 113                 struct {
 114                         INTEL_DISPLAY_PLATFORMS(__MEMBER);
 115                 };
 116                 DECLARE_BITMAP(bitmap, __NUM_PLATFORMS);
 117         };
 118 };
 119
 120 #undef __MEMBER
 121 #undef __COUNT
 122 #undef __NUM_PLATFORMS
 123
 124 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
 125         /* Keep in alphabetical order */ \
 126         func(cursor_needs_physical); \
 127         func(has_cdclk_crawl); \
 128         func(has_cdclk_squash); \
 129         func(has_ddi); \
 130         func(has_dp_mst); \
 131         func(has_dsb); \
 132         func(has_fpga_dbg); \
 133         func(has_gmch); \
 134         func(has_hotplug); \
 135         func(has_hti); \
 136         func(has_ipc); \
 137         func(has_overlay); \
 138         func(has_psr); \
 139         func(has_psr_hw_tracking); \
 140         func(overlay_needs_physical); \
 141         func(supports_tv);
 142
 143 #define HAS_4TILE(__display)            ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
 144 #define HAS_ASYNC_FLIPS(__display)      (DISPLAY_VER(__display) >= 5)
 145 #define HAS_BIGJOINER(__display)        (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
 146 #define HAS_CDCLK_CRAWL(__display)      (DISPLAY_INFO(__display)->has_cdclk_crawl)
 147 #define HAS_CDCLK_SQUASH(__display)     (DISPLAY_INFO(__display)->has_cdclk_squash)
 148 #define HAS_CUR_FBC(__display)          (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
 149 #define HAS_D12_PLANE_MINIMIZATION(__display)   ((__display)->platform.rocketlake || (__display)->platform.alderlake_s)
 150 #define HAS_DBUF_OVERLAP_DETECTION(__display)   (DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection)
 151 #define HAS_DDI(__display)              (DISPLAY_INFO(__display)->has_ddi)
 152 #define HAS_DISPLAY(__display)          (DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0)
 153 #define HAS_DMC(__display)              (DISPLAY_RUNTIME_INFO(__display)->has_dmc)
 154 #define HAS_DMC_WAKELOCK(__display)     (DISPLAY_VER(__display) >= 20)
 155 #define HAS_DOUBLE_BUFFERED_M_N(__display)      (DISPLAY_VER(__display) >= 9 || (__display)->platform.broadwell)
 156 #define HAS_DOUBLE_WIDE(__display)      (DISPLAY_VER(__display) < 4)
 157 #define HAS_DP_MST(__display)           (DISPLAY_INFO(__display)->has_dp_mst)
 158 #define HAS_DP20(__display)             ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
 159 #define HAS_DPT(__display)              (DISPLAY_VER(__display) >= 13)
 160 #define HAS_DSB(__display)              (DISPLAY_INFO(__display)->has_dsb)
 161 #define HAS_DSC(__display)              (DISPLAY_RUNTIME_INFO(__display)->has_dsc)
 162 #define HAS_DSC_MST(__display)          (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
 163 #define HAS_FBC(__display)              (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
 164 #define HAS_FPGA_DBG_UNCLAIMED(__display)       (DISPLAY_INFO(__display)->has_fpga_dbg)
 165 #define HAS_FW_BLC(__display)           (DISPLAY_VER(__display) >= 3)
 166 #define HAS_GMBUS_IRQ(__display)        (DISPLAY_VER(__display) >= 4)
 167 #define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
 168 #define HAS_GMCH(__display)             (DISPLAY_INFO(__display)->has_gmch)
 169 #define HAS_HW_SAGV_WM(__display)       (DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx)
 170 #define HAS_IPC(__display)              (DISPLAY_INFO(__display)->has_ipc)
 171 #define HAS_IPS(__display)              ((__display)->platform.haswell_ult || (__display)->platform.broadwell)
 172 #define HAS_LRR(__display)              (DISPLAY_VER(__display) >= 12)
 173 #define HAS_LSPCON(__display)           (IS_DISPLAY_VER(__display, 9, 10))
 174 #define HAS_MBUS_JOINING(__display)     ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
 175 #define HAS_MSO(__display)              (DISPLAY_VER(__display) >= 12)
 176 #define HAS_OVERLAY(__display)          (DISPLAY_INFO(__display)->has_overlay)
 177 #define HAS_PSR(__display)              (DISPLAY_INFO(__display)->has_psr)
 178 #define HAS_PSR_HW_TRACKING(__display)  (DISPLAY_INFO(__display)->has_psr_hw_tracking)
 179 #define HAS_PSR2_SEL_FETCH(__display)   (DISPLAY_VER(__display) >= 12)
 180 #define HAS_SAGV(__display)             (DISPLAY_VER(__display) >= 9 && \
 181                                          !(__display)->platform.broxton && !(__display)->platform.geminilake)
 182 #define HAS_TRANSCODER(__display, trans)        ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \
 183                                                   BIT(trans)) != 0)
 184 #define HAS_UNCOMPRESSED_JOINER(__display)      (DISPLAY_VER(__display) >= 13)
 185 #define HAS_ULTRAJOINER(__display)      ((DISPLAY_VER(__display) >= 20 || \
 186                                           ((__display)->platform.dgfx && DISPLAY_VER(__display) == 14)) && \
 187                                          HAS_DSC(__display))
 188 #define HAS_VRR(__display)              (DISPLAY_VER(__display) >= 11)
 189 #define HAS_AS_SDP(__display)           (DISPLAY_VER(__display) >= 13)
 190 #define HAS_CMRR(__display)             (DISPLAY_VER(__display) >= 20)
 191 #define INTEL_NUM_PIPES(__display)      (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
 192 #define I915_HAS_HOTPLUG(__display)     (DISPLAY_INFO(__display)->has_hotplug)
 193 #define OVERLAY_NEEDS_PHYSICAL(__display)       (DISPLAY_INFO(__display)->overlay_needs_physical)
 194 #define SUPPORTS_TV(__display)          (DISPLAY_INFO(__display)->supports_tv)
 195
 196 /* Check that device has a display IP version within the specific range. */
 197 #define IS_DISPLAY_VERx100(__display, from, until) ( \
 198         BUILD_BUG_ON_ZERO((from) < 200) + \
 199         (DISPLAY_VERx100(__display) >= (from) && \
 200          DISPLAY_VERx100(__display) <= (until)))
 201
 202 /*
 203  * Check if a device has a specific IP version as well as a stepping within the
 204  * specified range [from, until).  The lower bound is inclusive, the upper
 205  * bound is exclusive.  The most common use-case of this macro is for checking
 206  * bounds for workarounds, which usually have a stepping ("from") at which the
 207  * hardware issue is first present and another stepping ("until") at which a
 208  * hardware fix is present and the software workaround is no longer necessary.
 209  * E.g.,
 210  *
 211  *    IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B2)
 212  *    IS_DISPLAY_VERx100_STEP(display, 1400, STEP_C0, STEP_FOREVER)
 213  *
 214  * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
 215  * stepping bound for the specified IP version.
 216  */
 217 #define IS_DISPLAY_VERx100_STEP(__display, ipver, from, until) \
 218         (IS_DISPLAY_VERx100((__display), (ipver), (ipver)) && \
 219          IS_DISPLAY_STEP((__display), (from), (until)))
 220
 221 #define DISPLAY_INFO(__display)         (__to_intel_display(__display)->info.__device_info)
 222 #define DISPLAY_RUNTIME_INFO(__display) (&__to_intel_display(__display)->info.__runtime_info)
 223
 224 #define DISPLAY_VER(__display)          (DISPLAY_RUNTIME_INFO(__display)->ip.ver)
 225 #define DISPLAY_VERx100(__display)      (DISPLAY_RUNTIME_INFO(__display)->ip.ver * 100 + \
 226                                          DISPLAY_RUNTIME_INFO(__display)->ip.rel)
 227 #define IS_DISPLAY_VER(__display, from, until) \
 228         (DISPLAY_VER(__display) >= (from) && DISPLAY_VER(__display) <= (until))
 229
 230 #define INTEL_DISPLAY_STEP(__display)   (DISPLAY_RUNTIME_INFO(__display)->step)
 231
 232 #define IS_DISPLAY_STEP(__display, since, until) \
 233         (drm_WARN_ON(__to_intel_display(__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \
 234          INTEL_DISPLAY_STEP(__display) >= (since) && INTEL_DISPLAY_STEP(__display) < (until))
 235
 236 struct intel_display_runtime_info {
 237         struct intel_display_ip_ver {
 238                 u16 ver;
 239                 u16 rel;
 240                 u16 step; /* hardware */
 241         } ip;
 242         int step; /* symbolic */
 243
 244         u32 rawclk_freq;
 245
 246         u8 pipe_mask;
 247         u8 cpu_transcoder_mask;
 248         u16 port_mask;
 249
 250         u8 num_sprites[I915_MAX_PIPES];
 251         u8 num_scalers[I915_MAX_PIPES];
 252
 253         u8 fbc_mask;
 254
 255         bool has_hdcp;
 256         bool has_dmc;
 257         bool has_dsc;
 258         bool edp_typec_support;
 259         bool has_dbuf_overlap_detection;
 260 };
 261
 262 struct intel_display_device_info {
 263         /* Initial runtime info. */
 264         const struct intel_display_runtime_info __runtime_defaults;
 265
 266         u8 abox_mask;
 267
 268         struct {
 269                 u16 size; /* in blocks */
 270                 u8 slice_mask;
 271         } dbuf;
 272
 273 #define DEFINE_FLAG(name) u8 name:1
 274         DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 275 #undef DEFINE_FLAG
 276
 277         /* Global register offset for the display engine */
 278         u32 mmio_offset;
 279
 280         /* Register offsets for the various display pipes and transcoders */
 281         u32 pipe_offsets[I915_MAX_TRANSCODERS];
 282         u32 trans_offsets[I915_MAX_TRANSCODERS];
 283         u32 cursor_offsets[I915_MAX_PIPES];
 284
 285         struct {
 286                 u32 degamma_lut_size;
 287                 u32 gamma_lut_size;
 288                 u32 degamma_lut_tests;
 289                 u32 gamma_lut_tests;
 290         } color;
 291 };
 292
 293 bool intel_display_device_enabled(struct intel_display *display);
 294 struct intel_display *intel_display_device_probe(struct pci_dev *pdev);
 295 void intel_display_device_remove(struct intel_display *display);
 296 void intel_display_device_info_runtime_init(struct intel_display *display);
 297
 298 void intel_display_device_info_print(const struct intel_display_device_info *info,
 299                                      const struct intel_display_runtime_info *runtime,
 300                                      struct drm_printer *p);
 301
 302 #endif