drivers/gpu/drm/i915/display/i9xx_plane.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5 #include <linux/kernel.h>
   6
   7 #include <drm/drm_atomic_helper.h>
   8 #include <drm/drm_blend.h>
   9 #include <drm/drm_fourcc.h>
  10
  11 #include "i915_drv.h"
  12 #include "i915_reg.h"
  13 #include "i9xx_plane.h"
  14 #include "i9xx_plane_regs.h"
  15 #include "intel_atomic.h"
  16 #include "intel_atomic_plane.h"
  17 #include "intel_de.h"
  18 #include "intel_display_irq.h"
  19 #include "intel_display_types.h"
  20 #include "intel_fb.h"
  21 #include "intel_fbc.h"
  22 #include "intel_frontbuffer.h"
  23 #include "intel_sprite.h"
  24
  25 /* Primary plane formats for gen <= 3 */
  26 static const u32 i8xx_primary_formats[] = {
  27         DRM_FORMAT_C8,
  28         DRM_FORMAT_XRGB1555,
  29         DRM_FORMAT_RGB565,
  30         DRM_FORMAT_XRGB8888,
  31 };
  32
  33 /* Primary plane formats for ivb (no fp16 due to hw issue) */
  34 static const u32 ivb_primary_formats[] = {
  35         DRM_FORMAT_C8,
  36         DRM_FORMAT_RGB565,
  37         DRM_FORMAT_XRGB8888,
  38         DRM_FORMAT_XBGR8888,
  39         DRM_FORMAT_XRGB2101010,
  40         DRM_FORMAT_XBGR2101010,
  41 };
  42
  43 /* Primary plane formats for gen >= 4, except ivb */
  44 static const u32 i965_primary_formats[] = {
  45         DRM_FORMAT_C8,
  46         DRM_FORMAT_RGB565,
  47         DRM_FORMAT_XRGB8888,
  48         DRM_FORMAT_XBGR8888,
  49         DRM_FORMAT_XRGB2101010,
  50         DRM_FORMAT_XBGR2101010,
  51         DRM_FORMAT_XBGR16161616F,
  52 };
  53
  54 /* Primary plane formats for vlv/chv */
  55 static const u32 vlv_primary_formats[] = {
  56         DRM_FORMAT_C8,
  57         DRM_FORMAT_RGB565,
  58         DRM_FORMAT_XRGB8888,
  59         DRM_FORMAT_XBGR8888,
  60         DRM_FORMAT_ARGB8888,
  61         DRM_FORMAT_ABGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64         DRM_FORMAT_ARGB2101010,
  65         DRM_FORMAT_ABGR2101010,
  66         DRM_FORMAT_XBGR16161616F,
  67 };
  68
  69 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
  70                                             u32 format, u64 modifier)
  71 {
  72         if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
  73                 return false;
  74
  75         switch (format) {
  76         case DRM_FORMAT_C8:
  77         case DRM_FORMAT_RGB565:
  78         case DRM_FORMAT_XRGB1555:
  79         case DRM_FORMAT_XRGB8888:
  80                 return modifier == DRM_FORMAT_MOD_LINEAR ||
  81                         modifier == I915_FORMAT_MOD_X_TILED;
  82         default:
  83                 return false;
  84         }
  85 }
  86
  87 static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
  88                                             u32 format, u64 modifier)
  89 {
  90         if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
  91                 return false;
  92
  93         switch (format) {
  94         case DRM_FORMAT_C8:
  95         case DRM_FORMAT_RGB565:
  96         case DRM_FORMAT_XRGB8888:
  97         case DRM_FORMAT_XBGR8888:
  98         case DRM_FORMAT_ARGB8888:
  99         case DRM_FORMAT_ABGR8888:
 100         case DRM_FORMAT_XRGB2101010:
 101         case DRM_FORMAT_XBGR2101010:
 102         case DRM_FORMAT_ARGB2101010:
 103         case DRM_FORMAT_ABGR2101010:
 104         case DRM_FORMAT_XBGR16161616F:
 105                 return modifier == DRM_FORMAT_MOD_LINEAR ||
 106                         modifier == I915_FORMAT_MOD_X_TILED;
 107         default:
 108                 return false;
 109         }
 110 }
 111
 112 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
 113                                enum i9xx_plane_id i9xx_plane)
 114 {
 115         if (!HAS_FBC(dev_priv))
 116                 return false;
 117
 118         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
 119                 return i9xx_plane == PLANE_A; /* tied to pipe A */
 120         else if (IS_IVYBRIDGE(dev_priv))
 121                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
 122                         i9xx_plane == PLANE_C;
 123         else if (DISPLAY_VER(dev_priv) >= 4)
 124                 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
 125         else
 126                 return i9xx_plane == PLANE_A;
 127 }
 128
 129 static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv,
 130                                         enum i9xx_plane_id i9xx_plane)
 131 {
 132         if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
 133                 return dev_priv->display.fbc[INTEL_FBC_A];
 134         else
 135                 return NULL;
 136 }
 137
 138 static bool i9xx_plane_has_windowing(struct intel_plane *plane)
 139 {
 140         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 141         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
 142
 143         if (IS_CHERRYVIEW(dev_priv))
 144                 return i9xx_plane == PLANE_B;
 145         else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
 146                 return false;
 147         else if (DISPLAY_VER(dev_priv) == 4)
 148                 return i9xx_plane == PLANE_C;
 149         else
 150                 return i9xx_plane == PLANE_B ||
 151                         i9xx_plane == PLANE_C;
 152 }
 153
 154 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
 155                           const struct intel_plane_state *plane_state)
 156 {
 157         struct drm_i915_private *dev_priv =
 158                 to_i915(plane_state->uapi.plane->dev);
 159         const struct drm_framebuffer *fb = plane_state->hw.fb;
 160         unsigned int rotation = plane_state->hw.rotation;
 161         u32 dspcntr;
 162
 163         dspcntr = DISP_ENABLE;
 164
 165         if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
 166             IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
 167                 dspcntr |= DISP_TRICKLE_FEED_DISABLE;
 168
 169         switch (fb->format->format) {
 170         case DRM_FORMAT_C8:
 171                 dspcntr |= DISP_FORMAT_8BPP;
 172                 break;
 173         case DRM_FORMAT_XRGB1555:
 174                 dspcntr |= DISP_FORMAT_BGRX555;
 175                 break;
 176         case DRM_FORMAT_ARGB1555:
 177                 dspcntr |= DISP_FORMAT_BGRA555;
 178                 break;
 179         case DRM_FORMAT_RGB565:
 180                 dspcntr |= DISP_FORMAT_BGRX565;
 181                 break;
 182         case DRM_FORMAT_XRGB8888:
 183                 dspcntr |= DISP_FORMAT_BGRX888;
 184                 break;
 185         case DRM_FORMAT_XBGR8888:
 186                 dspcntr |= DISP_FORMAT_RGBX888;
 187                 break;
 188         case DRM_FORMAT_ARGB8888:
 189                 dspcntr |= DISP_FORMAT_BGRA888;
 190                 break;
 191         case DRM_FORMAT_ABGR8888:
 192                 dspcntr |= DISP_FORMAT_RGBA888;
 193                 break;
 194         case DRM_FORMAT_XRGB2101010:
 195                 dspcntr |= DISP_FORMAT_BGRX101010;
 196                 break;
 197         case DRM_FORMAT_XBGR2101010:
 198                 dspcntr |= DISP_FORMAT_RGBX101010;
 199                 break;
 200         case DRM_FORMAT_ARGB2101010:
 201                 dspcntr |= DISP_FORMAT_BGRA101010;
 202                 break;
 203         case DRM_FORMAT_ABGR2101010:
 204                 dspcntr |= DISP_FORMAT_RGBA101010;
 205                 break;
 206         case DRM_FORMAT_XBGR16161616F:
 207                 dspcntr |= DISP_FORMAT_RGBX161616;
 208                 break;
 209         default:
 210                 MISSING_CASE(fb->format->format);
 211                 return 0;
 212         }
 213
 214         if (DISPLAY_VER(dev_priv) >= 4 &&
 215             fb->modifier == I915_FORMAT_MOD_X_TILED)
 216                 dspcntr |= DISP_TILED;
 217
 218         if (rotation & DRM_MODE_ROTATE_180)
 219                 dspcntr |= DISP_ROTATE_180;
 220
 221         if (rotation & DRM_MODE_REFLECT_X)
 222                 dspcntr |= DISP_MIRROR;
 223
 224         return dspcntr;
 225 }
 226
 227 int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
 228 {
 229         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 230         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 231         const struct drm_framebuffer *fb = plane_state->hw.fb;
 232         int src_x, src_y, src_w;
 233         u32 offset;
 234         int ret;
 235
 236         ret = intel_plane_compute_gtt(plane_state);
 237         if (ret)
 238                 return ret;
 239
 240         if (!plane_state->uapi.visible)
 241                 return 0;
 242
 243         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 244         src_x = plane_state->uapi.src.x1 >> 16;
 245         src_y = plane_state->uapi.src.y1 >> 16;
 246
 247         /* Undocumented hardware limit on i965/g4x/vlv/chv */
 248         if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
 249                 return -EINVAL;
 250
 251         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
 252
 253         if (DISPLAY_VER(dev_priv) >= 4)
 254                 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
 255                                                             plane_state, 0);
 256         else
 257                 offset = 0;
 258
 259         /*
 260          * When using an X-tiled surface the plane starts to
 261          * misbehave if the x offset + width exceeds the stride.
 262          * hsw/bdw: underrun galore
 263          * ilk/snb/ivb: wrap to the next tile row mid scanout
 264          * i965/g4x: so far appear immune to this
 265          * vlv/chv: TODO check
 266          *
 267          * Linear surfaces seem to work just fine, even on hsw/bdw
 268          * despite them not using the linear offset anymore.
 269          */
 270         if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) {
 271                 unsigned int alignment = plane->min_alignment(plane, fb, 0);
 272                 int cpp = fb->format->cpp[0];
 273
 274                 while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) {
 275                         if (offset == 0) {
 276                                 drm_dbg_kms(&dev_priv->drm,
 277                                             "Unable to find suitable display surface offset due to X-tiling\n");
 278                                 return -EINVAL;
 279                         }
 280
 281                         offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0,
 282                                                                    offset, offset - alignment);
 283                 }
 284         }
 285
 286         /*
 287          * Put the final coordinates back so that the src
 288          * coordinate checks will see the right values.
 289          */
 290         drm_rect_translate_to(&plane_state->uapi.src,
 291                               src_x << 16, src_y << 16);
 292
 293         /* HSW/BDW do this automagically in hardware */
 294         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
 295                 unsigned int rotation = plane_state->hw.rotation;
 296                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 297                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 298
 299                 if (rotation & DRM_MODE_ROTATE_180) {
 300                         src_x += src_w - 1;
 301                         src_y += src_h - 1;
 302                 } else if (rotation & DRM_MODE_REFLECT_X) {
 303                         src_x += src_w - 1;
 304                 }
 305         }
 306
 307         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 308                 drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095);
 309         } else if (DISPLAY_VER(dev_priv) >= 4 &&
 310                    fb->modifier == I915_FORMAT_MOD_X_TILED) {
 311                 drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095);
 312         }
 313
 314         plane_state->view.color_plane[0].offset = offset;
 315         plane_state->view.color_plane[0].x = src_x;
 316         plane_state->view.color_plane[0].y = src_y;
 317
 318         return 0;
 319 }
 320
 321 static int
 322 i9xx_plane_check(struct intel_crtc_state *crtc_state,
 323                  struct intel_plane_state *plane_state)
 324 {
 325         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 326         int ret;
 327
 328         ret = chv_plane_check_rotation(plane_state);
 329         if (ret)
 330                 return ret;
 331
 332         ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
 333                                                 DRM_PLANE_NO_SCALING,
 334                                                 DRM_PLANE_NO_SCALING,
 335                                                 i9xx_plane_has_windowing(plane));
 336         if (ret)
 337                 return ret;
 338
 339         ret = i9xx_check_plane_surface(plane_state);
 340         if (ret)
 341                 return ret;
 342
 343         if (!plane_state->uapi.visible)
 344                 return 0;
 345
 346         ret = intel_plane_check_src_coordinates(plane_state);
 347         if (ret)
 348                 return ret;
 349
 350         plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
 351
 352         return 0;
 353 }
 354
 355 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 356 {
 357         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 358         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 359         u32 dspcntr = 0;
 360
 361         if (crtc_state->gamma_enable)
 362                 dspcntr |= DISP_PIPE_GAMMA_ENABLE;
 363
 364         if (crtc_state->csc_enable)
 365                 dspcntr |= DISP_PIPE_CSC_ENABLE;
 366
 367         if (DISPLAY_VER(dev_priv) < 5)
 368                 dspcntr |= DISP_PIPE_SEL(crtc->pipe);
 369
 370         return dspcntr;
 371 }
 372
 373 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
 374                              const struct intel_plane_state *plane_state,
 375                              unsigned int *num, unsigned int *den)
 376 {
 377         const struct drm_framebuffer *fb = plane_state->hw.fb;
 378         unsigned int cpp = fb->format->cpp[0];
 379
 380         /*
 381          * g4x bspec says 64bpp pixel rate can't exceed 80%
 382          * of cdclk when the sprite plane is enabled on the
 383          * same pipe. ilk/snb bspec says 64bpp pixel rate is
 384          * never allowed to exceed 80% of cdclk. Let's just go
 385          * with the ilk/snb limit always.
 386          */
 387         if (cpp == 8) {
 388                 *num = 10;
 389                 *den = 8;
 390         } else {
 391                 *num = 1;
 392                 *den = 1;
 393         }
 394 }
 395
 396 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 397                                 const struct intel_plane_state *plane_state)
 398 {
 399         unsigned int pixel_rate;
 400         unsigned int num, den;
 401
 402         /*
 403          * Note that crtc_state->pixel_rate accounts for both
 404          * horizontal and vertical panel fitter downscaling factors.
 405          * Pre-HSW bspec tells us to only consider the horizontal
 406          * downscaling factor here. We ignore that and just consider
 407          * both for simplicity.
 408          */
 409         pixel_rate = crtc_state->pixel_rate;
 410
 411         i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
 412
 413         /* two pixels per clock with double wide pipe */
 414         if (crtc_state->double_wide)
 415                 den *= 2;
 416
 417         return DIV_ROUND_UP(pixel_rate * num, den);
 418 }
 419
 420 static void i9xx_plane_update_noarm(struct intel_dsb *dsb,
 421                                     struct intel_plane *plane,
 422                                     const struct intel_crtc_state *crtc_state,
 423                                     const struct intel_plane_state *plane_state)
 424 {
 425         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 426         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
 427
 428         intel_de_write_fw(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane),
 429                           plane_state->view.color_plane[0].mapping_stride);
 430
 431         if (DISPLAY_VER(dev_priv) < 4) {
 432                 int crtc_x = plane_state->uapi.dst.x1;
 433                 int crtc_y = plane_state->uapi.dst.y1;
 434                 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
 435                 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
 436
 437                 /*
 438                  * PLANE_A doesn't actually have a full window
 439                  * generator but let's assume we still need to
 440                  * program whatever is there.
 441                  */
 442                 intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane),
 443                                   DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x));
 444                 intel_de_write_fw(dev_priv, DSPSIZE(dev_priv, i9xx_plane),
 445                                   DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1));
 446         }
 447 }
 448
 449 static void i9xx_plane_update_arm(struct intel_dsb *dsb,
 450                                   struct intel_plane *plane,
 451                                   const struct intel_crtc_state *crtc_state,
 452                                   const struct intel_plane_state *plane_state)
 453 {
 454         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 455         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
 456         int x = plane_state->view.color_plane[0].x;
 457         int y = plane_state->view.color_plane[0].y;
 458         u32 dspcntr, dspaddr_offset, linear_offset;
 459
 460         dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
 461
 462         /* see intel_plane_atomic_calc_changes() */
 463         if (plane->need_async_flip_toggle_wa &&
 464             crtc_state->async_flip_planes & BIT(plane->id))
 465                 dspcntr |= DISP_ASYNC_FLIP;
 466
 467         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 468
 469         if (DISPLAY_VER(dev_priv) >= 4)
 470                 dspaddr_offset = plane_state->view.color_plane[0].offset;
 471         else
 472                 dspaddr_offset = linear_offset;
 473
 474         if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
 475                 int crtc_x = plane_state->uapi.dst.x1;
 476                 int crtc_y = plane_state->uapi.dst.y1;
 477                 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
 478                 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
 479
 480                 intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane),
 481                                   PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
 482                 intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane),
 483                                   PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
 484                 intel_de_write_fw(dev_priv,
 485                                   PRIMCNSTALPHA(dev_priv, i9xx_plane), 0);
 486         }
 487
 488         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 489                 intel_de_write_fw(dev_priv, DSPOFFSET(dev_priv, i9xx_plane),
 490                                   DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
 491         } else if (DISPLAY_VER(dev_priv) >= 4) {
 492                 intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane),
 493                                   linear_offset);
 494                 intel_de_write_fw(dev_priv, DSPTILEOFF(dev_priv, i9xx_plane),
 495                                   DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
 496         }
 497
 498         /*
 499          * The control register self-arms if the plane was previously
 500          * disabled. Try to make the plane enable atomic by writing
 501          * the control register just before the surface register.
 502          */
 503         intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
 504
 505         if (DISPLAY_VER(dev_priv) >= 4)
 506                 intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),
 507                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
 508         else
 509                 intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
 510                                   intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
 511 }
 512
 513 static void i830_plane_update_arm(struct intel_dsb *dsb,
 514                                   struct intel_plane *plane,
 515                                   const struct intel_crtc_state *crtc_state,
 516                                   const struct intel_plane_state *plane_state)
 517 {
 518         /*
 519          * On i830/i845 all registers are self-arming [ALM040].
 520          *
 521          * Additional breakage on i830 causes register reads to return
 522          * the last latched value instead of the last written value [ALM026].
 523          */
 524         i9xx_plane_update_noarm(dsb, plane, crtc_state, plane_state);
 525         i9xx_plane_update_arm(dsb, plane, crtc_state, plane_state);
 526 }
 527
 528 static void i9xx_plane_disable_arm(struct intel_dsb *dsb,
 529                                    struct intel_plane *plane,
 530                                    const struct intel_crtc_state *crtc_state)
 531 {
 532         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 533         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
 534         u32 dspcntr;
 535
 536         /*
 537          * DSPCNTR pipe gamma enable on g4x+ and pipe csc
 538          * enable on ilk+ affect the pipe bottom color as
 539          * well, so we must configure them even if the plane
 540          * is disabled.
 541          *
 542          * On pre-g4x there is no way to gamma correct the
 543          * pipe bottom color but we'll keep on doing this
 544          * anyway so that the crtc state readout works correctly.
 545          */
 546         dspcntr = i9xx_plane_ctl_crtc(crtc_state);
 547
 548         intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
 549
 550         if (DISPLAY_VER(dev_priv) >= 4)
 551                 intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 0);
 552         else
 553                 intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0);
 554 }
 555
 556 static void
 557 g4x_primary_async_flip(struct intel_dsb *dsb,
 558                        struct intel_plane *plane,
 559                        const struct intel_crtc_state *crtc_state,
 560                        const struct intel_plane_state *plane_state,
 561                        bool async_flip)
 562 {
 563         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 564         u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
 565         u32 dspaddr_offset = plane_state->view.color_plane[0].offset;
 566         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
 567
 568         if (async_flip)
 569                 dspcntr |= DISP_ASYNC_FLIP;
 570
 571         intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);
 572
 573         intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),
 574                           intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
 575 }
 576
 577 static void
 578 vlv_primary_async_flip(struct intel_dsb *dsb,
 579                        struct intel_plane *plane,
 580                        const struct intel_crtc_state *crtc_state,
 581                        const struct intel_plane_state *plane_state,
 582                        bool async_flip)
 583 {
 584         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 585         u32 dspaddr_offset = plane_state->view.color_plane[0].offset;
 586         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
 587
 588         intel_de_write_fw(dev_priv, DSPADDR_VLV(dev_priv, i9xx_plane),
 589                           intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
 590 }
 591
 592 static void
 593 bdw_primary_enable_flip_done(struct intel_plane *plane)
 594 {
 595         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 596         enum pipe pipe = plane->pipe;
 597
 598         spin_lock_irq(&i915->irq_lock);
 599         bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
 600         spin_unlock_irq(&i915->irq_lock);
 601 }
 602
 603 static void
 604 bdw_primary_disable_flip_done(struct intel_plane *plane)
 605 {
 606         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 607         enum pipe pipe = plane->pipe;
 608
 609         spin_lock_irq(&i915->irq_lock);
 610         bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE);
 611         spin_unlock_irq(&i915->irq_lock);
 612 }
 613
 614 static void
 615 ivb_primary_enable_flip_done(struct intel_plane *plane)
 616 {
 617         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 618
 619         spin_lock_irq(&i915->irq_lock);
 620         ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
 621         spin_unlock_irq(&i915->irq_lock);
 622 }
 623
 624 static void
 625 ivb_primary_disable_flip_done(struct intel_plane *plane)
 626 {
 627         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 628
 629         spin_lock_irq(&i915->irq_lock);
 630         ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane));
 631         spin_unlock_irq(&i915->irq_lock);
 632 }
 633
 634 static void
 635 ilk_primary_enable_flip_done(struct intel_plane *plane)
 636 {
 637         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 638
 639         spin_lock_irq(&i915->irq_lock);
 640         ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
 641         spin_unlock_irq(&i915->irq_lock);
 642 }
 643
 644 static void
 645 ilk_primary_disable_flip_done(struct intel_plane *plane)
 646 {
 647         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 648
 649         spin_lock_irq(&i915->irq_lock);
 650         ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
 651         spin_unlock_irq(&i915->irq_lock);
 652 }
 653
 654 static void
 655 vlv_primary_enable_flip_done(struct intel_plane *plane)
 656 {
 657         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 658         enum pipe pipe = plane->pipe;
 659
 660         spin_lock_irq(&i915->irq_lock);
 661         i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
 662         spin_unlock_irq(&i915->irq_lock);
 663 }
 664
 665 static void
 666 vlv_primary_disable_flip_done(struct intel_plane *plane)
 667 {
 668         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 669         enum pipe pipe = plane->pipe;
 670
 671         spin_lock_irq(&i915->irq_lock);
 672         i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV);
 673         spin_unlock_irq(&i915->irq_lock);
 674 }
 675
 676 static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
 677                                     enum pipe *pipe)
 678 {
 679         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 680         enum intel_display_power_domain power_domain;
 681         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
 682         intel_wakeref_t wakeref;
 683         bool ret;
 684         u32 val;
 685
 686         /*
 687          * Not 100% correct for planes that can move between pipes,
 688          * but that's only the case for gen2-4 which don't have any
 689          * display power wells.
 690          */
 691         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 692         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 693         if (!wakeref)
 694                 return false;
 695
 696         val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));
 697
 698         ret = val & DISP_ENABLE;
 699
 700         if (DISPLAY_VER(dev_priv) >= 5)
 701                 *pipe = plane->pipe;
 702         else
 703                 *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val);
 704
 705         intel_display_power_put(dev_priv, power_domain, wakeref);
 706
 707         return ret;
 708 }
 709
 710 static unsigned int
 711 hsw_primary_max_stride(struct intel_plane *plane,
 712                        u32 pixel_format, u64 modifier,
 713                        unsigned int rotation)
 714 {
 715         const struct drm_format_info *info = drm_format_info(pixel_format);
 716         int cpp = info->cpp[0];
 717
 718         /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */
 719         return min(8192 * cpp, 32 * 1024);
 720 }
 721
 722 static unsigned int
 723 ilk_primary_max_stride(struct intel_plane *plane,
 724                        u32 pixel_format, u64 modifier,
 725                        unsigned int rotation)
 726 {
 727         const struct drm_format_info *info = drm_format_info(pixel_format);
 728         int cpp = info->cpp[0];
 729
 730         /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
 731         if (modifier == I915_FORMAT_MOD_X_TILED)
 732                 return min(4096 * cpp, 32 * 1024);
 733         else
 734                 return 32 * 1024;
 735 }
 736
 737 unsigned int
 738 i965_plane_max_stride(struct intel_plane *plane,
 739                       u32 pixel_format, u64 modifier,
 740                       unsigned int rotation)
 741 {
 742         const struct drm_format_info *info = drm_format_info(pixel_format);
 743         int cpp = info->cpp[0];
 744
 745         /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
 746         if (modifier == I915_FORMAT_MOD_X_TILED)
 747                 return min(4096 * cpp, 16 * 1024);
 748         else
 749                 return 32 * 1024;
 750 }
 751
 752 static unsigned int
 753 i915_plane_max_stride(struct intel_plane *plane,
 754                       u32 pixel_format, u64 modifier,
 755                       unsigned int rotation)
 756 {
 757         if (modifier == I915_FORMAT_MOD_X_TILED)
 758                 return 8 * 1024;
 759         else
 760                 return 16 * 1024;
 761 }
 762
 763 static unsigned int
 764 i8xx_plane_max_stride(struct intel_plane *plane,
 765                       u32 pixel_format, u64 modifier,
 766                       unsigned int rotation)
 767 {
 768         if (plane->i9xx_plane == PLANE_C)
 769                 return 4 * 1024;
 770         else
 771                 return 8 * 1024;
 772 }
 773
 774 static unsigned int vlv_primary_min_alignment(struct intel_plane *plane,
 775                                               const struct drm_framebuffer *fb,
 776                                               int color_plane)
 777 {
 778         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 779
 780         switch (fb->modifier) {
 781         case I915_FORMAT_MOD_X_TILED:
 782                 if (HAS_ASYNC_FLIPS(i915))
 783                         return 256 * 1024;
 784                 return 4 * 1024;
 785         case DRM_FORMAT_MOD_LINEAR:
 786                 return 128 * 1024;
 787         default:
 788                 MISSING_CASE(fb->modifier);
 789                 return 0;
 790         }
 791 }
 792
 793 static unsigned int g4x_primary_min_alignment(struct intel_plane *plane,
 794                                               const struct drm_framebuffer *fb,
 795                                               int color_plane)
 796 {
 797         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 798
 799         switch (fb->modifier) {
 800         case I915_FORMAT_MOD_X_TILED:
 801                 if (HAS_ASYNC_FLIPS(i915))
 802                         return 256 * 1024;
 803                 return 4 * 1024;
 804         case DRM_FORMAT_MOD_LINEAR:
 805                 return 4 * 1024;
 806         default:
 807                 MISSING_CASE(fb->modifier);
 808                 return 0;
 809         }
 810 }
 811
 812 static unsigned int i965_plane_min_alignment(struct intel_plane *plane,
 813                                              const struct drm_framebuffer *fb,
 814                                              int color_plane)
 815 {
 816         switch (fb->modifier) {
 817         case I915_FORMAT_MOD_X_TILED:
 818                 return 4 * 1024;
 819         case DRM_FORMAT_MOD_LINEAR:
 820                 return 128 * 1024;
 821         default:
 822                 MISSING_CASE(fb->modifier);
 823                 return 0;
 824         }
 825 }
 826
 827 static unsigned int i9xx_plane_min_alignment(struct intel_plane *plane,
 828                                              const struct drm_framebuffer *fb,
 829                                              int color_plane)
 830 {
 831         return 0;
 832 }
 833
 834 static const struct drm_plane_funcs i965_plane_funcs = {
 835         .update_plane = drm_atomic_helper_update_plane,
 836         .disable_plane = drm_atomic_helper_disable_plane,
 837         .destroy = intel_plane_destroy,
 838         .atomic_duplicate_state = intel_plane_duplicate_state,
 839         .atomic_destroy_state = intel_plane_destroy_state,
 840         .format_mod_supported = i965_plane_format_mod_supported,
 841 };
 842
 843 static const struct drm_plane_funcs i8xx_plane_funcs = {
 844         .update_plane = drm_atomic_helper_update_plane,
 845         .disable_plane = drm_atomic_helper_disable_plane,
 846         .destroy = intel_plane_destroy,
 847         .atomic_duplicate_state = intel_plane_duplicate_state,
 848         .atomic_destroy_state = intel_plane_destroy_state,
 849         .format_mod_supported = i8xx_plane_format_mod_supported,
 850 };
 851
 852 struct intel_plane *
 853 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 854 {
 855         struct intel_plane *plane;
 856         const struct drm_plane_funcs *plane_funcs;
 857         unsigned int supported_rotations;
 858         const u64 *modifiers;
 859         const u32 *formats;
 860         int num_formats;
 861         int ret, zpos;
 862
 863         plane = intel_plane_alloc();
 864         if (IS_ERR(plane))
 865                 return plane;
 866
 867         plane->pipe = pipe;
 868         /*
 869          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
 870          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
 871          */
 872         if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 &&
 873             INTEL_NUM_PIPES(dev_priv) == 2)
 874                 plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
 875         else
 876                 plane->i9xx_plane = (enum i9xx_plane_id) pipe;
 877         plane->id = PLANE_PRIMARY;
 878         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
 879
 880         intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane);
 881
 882         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 883                 formats = vlv_primary_formats;
 884                 num_formats = ARRAY_SIZE(vlv_primary_formats);
 885         } else if (DISPLAY_VER(dev_priv) >= 4) {
 886                 /*
 887                  * WaFP16GammaEnabling:ivb
 888                  * "Workaround : When using the 64-bit format, the plane
 889                  *  output on each color channel has one quarter amplitude.
 890                  *  It can be brought up to full amplitude by using pipe
 891                  *  gamma correction or pipe color space conversion to
 892                  *  multiply the plane output by four."
 893                  *
 894                  * There is no dedicated plane gamma for the primary plane,
 895                  * and using the pipe gamma/csc could conflict with other
 896                  * planes, so we choose not to expose fp16 on IVB primary
 897                  * planes. HSW primary planes no longer have this problem.
 898                  */
 899                 if (IS_IVYBRIDGE(dev_priv)) {
 900                         formats = ivb_primary_formats;
 901                         num_formats = ARRAY_SIZE(ivb_primary_formats);
 902                 } else {
 903                         formats = i965_primary_formats;
 904                         num_formats = ARRAY_SIZE(i965_primary_formats);
 905                 }
 906         } else {
 907                 formats = i8xx_primary_formats;
 908                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
 909         }
 910
 911         if (DISPLAY_VER(dev_priv) >= 4)
 912                 plane_funcs = &i965_plane_funcs;
 913         else
 914                 plane_funcs = &i8xx_plane_funcs;
 915
 916         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 917                 plane->min_cdclk = vlv_plane_min_cdclk;
 918         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
 919                 plane->min_cdclk = hsw_plane_min_cdclk;
 920         else if (IS_IVYBRIDGE(dev_priv))
 921                 plane->min_cdclk = ivb_plane_min_cdclk;
 922         else
 923                 plane->min_cdclk = i9xx_plane_min_cdclk;
 924
 925         if (HAS_GMCH(dev_priv)) {
 926                 if (DISPLAY_VER(dev_priv) >= 4)
 927                         plane->max_stride = i965_plane_max_stride;
 928                 else if (DISPLAY_VER(dev_priv) == 3)
 929                         plane->max_stride = i915_plane_max_stride;
 930                 else
 931                         plane->max_stride = i8xx_plane_max_stride;
 932         } else {
 933                 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
 934                         plane->max_stride = hsw_primary_max_stride;
 935                 else
 936                         plane->max_stride = ilk_primary_max_stride;
 937         }
 938
 939         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 940                 plane->min_alignment = vlv_primary_min_alignment;
 941         else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
 942                 plane->min_alignment = g4x_primary_min_alignment;
 943         else if (DISPLAY_VER(dev_priv) == 4)
 944                 plane->min_alignment = i965_plane_min_alignment;
 945         else
 946                 plane->min_alignment = i9xx_plane_min_alignment;
 947
 948         if (IS_I830(dev_priv) || IS_I845G(dev_priv)) {
 949                 plane->update_arm = i830_plane_update_arm;
 950         } else {
 951                 plane->update_noarm = i9xx_plane_update_noarm;
 952                 plane->update_arm = i9xx_plane_update_arm;
 953         }
 954         plane->disable_arm = i9xx_plane_disable_arm;
 955         plane->get_hw_state = i9xx_plane_get_hw_state;
 956         plane->check_plane = i9xx_plane_check;
 957
 958         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 959                 plane->async_flip = vlv_primary_async_flip;
 960                 plane->enable_flip_done = vlv_primary_enable_flip_done;
 961                 plane->disable_flip_done = vlv_primary_disable_flip_done;
 962         } else if (IS_BROADWELL(dev_priv)) {
 963                 plane->need_async_flip_toggle_wa = true;
 964                 plane->async_flip = g4x_primary_async_flip;
 965                 plane->enable_flip_done = bdw_primary_enable_flip_done;
 966                 plane->disable_flip_done = bdw_primary_disable_flip_done;
 967         } else if (DISPLAY_VER(dev_priv) >= 7) {
 968                 plane->async_flip = g4x_primary_async_flip;
 969                 plane->enable_flip_done = ivb_primary_enable_flip_done;
 970                 plane->disable_flip_done = ivb_primary_disable_flip_done;
 971         } else if (DISPLAY_VER(dev_priv) >= 5) {
 972                 plane->async_flip = g4x_primary_async_flip;
 973                 plane->enable_flip_done = ilk_primary_enable_flip_done;
 974                 plane->disable_flip_done = ilk_primary_disable_flip_done;
 975         }
 976
 977         modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X);
 978
 979         if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
 980                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
 981                                                0, plane_funcs,
 982                                                formats, num_formats,
 983                                                modifiers,
 984                                                DRM_PLANE_TYPE_PRIMARY,
 985                                                "primary %c", pipe_name(pipe));
 986         else
 987                 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
 988                                                0, plane_funcs,
 989                                                formats, num_formats,
 990                                                modifiers,
 991                                                DRM_PLANE_TYPE_PRIMARY,
 992                                                "plane %c",
 993                                                plane_name(plane->i9xx_plane));
 994
 995         kfree(modifiers);
 996
 997         if (ret)
 998                 goto fail;
 999
1000         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1001                 supported_rotations =
1002                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1003                         DRM_MODE_REFLECT_X;
1004         } else if (DISPLAY_VER(dev_priv) >= 4) {
1005                 supported_rotations =
1006                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1007         } else {
1008                 supported_rotations = DRM_MODE_ROTATE_0;
1009         }
1010
1011         if (DISPLAY_VER(dev_priv) >= 4)
1012                 drm_plane_create_rotation_property(&plane->base,
1013                                                    DRM_MODE_ROTATE_0,
1014                                                    supported_rotations);
1015
1016         zpos = 0;
1017         drm_plane_create_zpos_immutable_property(&plane->base, zpos);
1018
1019         intel_plane_helper_add(plane);
1020
1021         return plane;
1022
1023 fail:
1024         intel_plane_free(plane);
1025
1026         return ERR_PTR(ret);
1027 }
1028
1029 static int i9xx_format_to_fourcc(int format)
1030 {
1031         switch (format) {
1032         case DISP_FORMAT_8BPP:
1033                 return DRM_FORMAT_C8;
1034         case DISP_FORMAT_BGRA555:
1035                 return DRM_FORMAT_ARGB1555;
1036         case DISP_FORMAT_BGRX555:
1037                 return DRM_FORMAT_XRGB1555;
1038         case DISP_FORMAT_BGRX565:
1039                 return DRM_FORMAT_RGB565;
1040         default:
1041         case DISP_FORMAT_BGRX888:
1042                 return DRM_FORMAT_XRGB8888;
1043         case DISP_FORMAT_RGBX888:
1044                 return DRM_FORMAT_XBGR8888;
1045         case DISP_FORMAT_BGRA888:
1046                 return DRM_FORMAT_ARGB8888;
1047         case DISP_FORMAT_RGBA888:
1048                 return DRM_FORMAT_ABGR8888;
1049         case DISP_FORMAT_BGRX101010:
1050                 return DRM_FORMAT_XRGB2101010;
1051         case DISP_FORMAT_RGBX101010:
1052                 return DRM_FORMAT_XBGR2101010;
1053         case DISP_FORMAT_BGRA101010:
1054                 return DRM_FORMAT_ARGB2101010;
1055         case DISP_FORMAT_RGBA101010:
1056                 return DRM_FORMAT_ABGR2101010;
1057         case DISP_FORMAT_RGBX161616:
1058                 return DRM_FORMAT_XBGR16161616F;
1059         }
1060 }
1061
1062 void
1063 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
1064                               struct intel_initial_plane_config *plane_config)
1065 {
1066         struct drm_device *dev = crtc->base.dev;
1067         struct drm_i915_private *dev_priv = to_i915(dev);
1068         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1069         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
1070         enum pipe pipe;
1071         u32 val, base, offset;
1072         int fourcc, pixel_format;
1073         unsigned int aligned_height;
1074         struct drm_framebuffer *fb;
1075         struct intel_framebuffer *intel_fb;
1076
1077         if (!plane->get_hw_state(plane, &pipe))
1078                 return;
1079
1080         drm_WARN_ON(dev, pipe != crtc->pipe);
1081
1082         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1083         if (!intel_fb) {
1084                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
1085                 return;
1086         }
1087
1088         fb = &intel_fb->base;
1089
1090         fb->dev = dev;
1091
1092         val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));
1093
1094         if (DISPLAY_VER(dev_priv) >= 4) {
1095                 if (val & DISP_TILED) {
1096                         plane_config->tiling = I915_TILING_X;
1097                         fb->modifier = I915_FORMAT_MOD_X_TILED;
1098                 }
1099
1100                 if (val & DISP_ROTATE_180)
1101                         plane_config->rotation = DRM_MODE_ROTATE_180;
1102         }
1103
1104         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
1105             val & DISP_MIRROR)
1106                 plane_config->rotation |= DRM_MODE_REFLECT_X;
1107
1108         pixel_format = val & DISP_FORMAT_MASK;
1109         fourcc = i9xx_format_to_fourcc(pixel_format);
1110         fb->format = drm_format_info(fourcc);
1111
1112         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1113                 offset = intel_de_read(dev_priv,
1114                                        DSPOFFSET(dev_priv, i9xx_plane));
1115                 base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK;
1116         } else if (DISPLAY_VER(dev_priv) >= 4) {
1117                 if (plane_config->tiling)
1118                         offset = intel_de_read(dev_priv,
1119                                                DSPTILEOFF(dev_priv, i9xx_plane));
1120                 else
1121                         offset = intel_de_read(dev_priv,
1122                                                DSPLINOFF(dev_priv, i9xx_plane));
1123                 base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK;
1124         } else {
1125                 offset = 0;
1126                 base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane));
1127         }
1128         plane_config->base = base;
1129
1130         drm_WARN_ON(&dev_priv->drm, offset != 0);
1131
1132         val = intel_de_read(dev_priv, PIPESRC(dev_priv, pipe));
1133         fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
1134         fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
1135
1136         val = intel_de_read(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane));
1137         fb->pitches[0] = val & 0xffffffc0;
1138
1139         aligned_height = intel_fb_align_height(fb, 0, fb->height);
1140
1141         plane_config->size = fb->pitches[0] * aligned_height;
1142
1143         drm_dbg_kms(&dev_priv->drm,
1144                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
1145                     crtc->base.name, plane->base.name, fb->width, fb->height,
1146                     fb->format->cpp[0] * 8, base, fb->pitches[0],
1147                     plane_config->size);
1148
1149         plane_config->fb = intel_fb;
1150 }
1151
1152 bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
1153                                      const struct intel_initial_plane_config *plane_config)
1154 {
1155         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1156         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1157         const struct intel_plane_state *plane_state =
1158                 to_intel_plane_state(plane->base.state);
1159         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
1160         u32 base;
1161
1162         if (!plane_state->uapi.visible)
1163                 return false;
1164
1165         base = intel_plane_ggtt_offset(plane_state);
1166
1167         /*
1168          * We may have moved the surface to a different
1169          * part of ggtt, make the plane aware of that.
1170          */
1171         if (plane_config->base == base)
1172                 return false;
1173
1174         if (DISPLAY_VER(dev_priv) >= 4)
1175                 intel_de_write(dev_priv, DSPSURF(dev_priv, i9xx_plane), base);
1176         else
1177                 intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base);
1178
1179         return true;
1180 }