]> Git Repo - linux.git/blob - drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.c
Linux 6.14-rc3
[linux.git] / drivers / gpu / drm / amd / display / dc / link / protocols / link_dpcd.c
1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25
26 /* FILE POLICY AND INTENDED USAGE:
27  *
28  * This file implements basic dpcd read/write functionality. It also does basic
29  * dpcd range check to ensure that every dpcd request is compliant with specs
30  * range requirements.
31  */
32
33 #include "link_dpcd.h"
34 #include <drm/display/drm_dp_helper.h>
35 #include "dm_helpers.h"
36
37 #define END_ADDRESS(start, size) (start + size - 1)
38 #define ADDRESS_RANGE_SIZE(start, end) (end - start + 1)
39 struct dpcd_address_range {
40         uint32_t start;
41         uint32_t end;
42 };
43
44 static enum dc_status internal_link_read_dpcd(
45         struct dc_link *link,
46         uint32_t address,
47         uint8_t *data,
48         uint32_t size)
49 {
50         if (!link->aux_access_disabled &&
51                         !dm_helpers_dp_read_dpcd(link->ctx,
52                         link, address, data, size)) {
53                 return DC_ERROR_UNEXPECTED;
54         }
55
56         return DC_OK;
57 }
58
59 static enum dc_status internal_link_write_dpcd(
60         struct dc_link *link,
61         uint32_t address,
62         const uint8_t *data,
63         uint32_t size)
64 {
65         if (!link->aux_access_disabled &&
66                         !dm_helpers_dp_write_dpcd(link->ctx,
67                         link, address, data, size)) {
68                 return DC_ERROR_UNEXPECTED;
69         }
70
71         return DC_OK;
72 }
73
74 /*
75  * Partition the entire DPCD address space
76  * XXX: This partitioning must cover the entire DPCD address space,
77  * and must contain no gaps or overlapping address ranges.
78  */
79 static const struct dpcd_address_range mandatory_dpcd_partitions[] = {
80         { 0, DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1) - 1},
81         { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },
82         { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3) - 1 },
83         { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4) - 1 },
84         { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5) - 1 },
85         { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6) - 1 },
86         { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7) - 1 },
87         { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8) - 1 },
88         { DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },
89         /*
90          * The FEC registers are contiguous
91          */
92         { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },
93         { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },
94         { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3) - 1 },
95         { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4) - 1 },
96         { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5) - 1 },
97         { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6) - 1 },
98         { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7) - 1 },
99         { DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR8), DP_LTTPR_MAX_ADD },
100         /* all remaining DPCD addresses */
101         { DP_LTTPR_MAX_ADD + 1, DP_DPCD_MAX_ADD } };
102
103 static inline bool do_addresses_intersect_with_range(
104                 const struct dpcd_address_range *range,
105                 const uint32_t start_address,
106                 const uint32_t end_address)
107 {
108         return start_address <= range->end && end_address >= range->start;
109 }
110
111 static uint32_t dpcd_get_next_partition_size(const uint32_t address, const uint32_t size)
112 {
113         const uint32_t end_address = END_ADDRESS(address, size);
114         uint32_t partition_iterator = 0;
115
116         /*
117          * find current partition
118          * this loop spins forever if partition map above is not surjective
119          */
120         while (!do_addresses_intersect_with_range(&mandatory_dpcd_partitions[partition_iterator],
121                                 address, end_address))
122                 partition_iterator++;
123         if (end_address < mandatory_dpcd_partitions[partition_iterator].end)
124                 return size;
125         return ADDRESS_RANGE_SIZE(address, mandatory_dpcd_partitions[partition_iterator].end);
126 }
127
128 /*
129  * Ranges of DPCD addresses that must be read in a single transaction
130  * XXX: Do not allow any two address ranges in this array to overlap
131  */
132 static const struct dpcd_address_range mandatory_dpcd_blocks[] = {
133         { DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, DP_PHY_REPEATER_128B132B_RATES }};
134
135 /*
136  * extend addresses to read all mandatory blocks together
137  */
138 static void dpcd_extend_address_range(
139                 const uint32_t in_address,
140                 uint8_t * const in_data,
141                 const uint32_t in_size,
142                 uint32_t *out_address,
143                 uint8_t **out_data,
144                 uint32_t *out_size)
145 {
146         const uint32_t end_address = END_ADDRESS(in_address, in_size);
147         const struct dpcd_address_range *addr_range;
148         struct dpcd_address_range new_addr_range;
149         uint32_t i;
150
151         new_addr_range.start = in_address;
152         new_addr_range.end = end_address;
153         for (i = 0; i < ARRAY_SIZE(mandatory_dpcd_blocks); i++) {
154                 addr_range = &mandatory_dpcd_blocks[i];
155                 if (addr_range->start <= in_address && addr_range->end >= in_address)
156                         new_addr_range.start = addr_range->start;
157
158                 if (addr_range->start <= end_address && addr_range->end >= end_address)
159                         new_addr_range.end = addr_range->end;
160         }
161         *out_address = in_address;
162         *out_size = in_size;
163         *out_data = in_data;
164         if (new_addr_range.start != in_address || new_addr_range.end != end_address) {
165                 *out_address = new_addr_range.start;
166                 *out_size = ADDRESS_RANGE_SIZE(new_addr_range.start, new_addr_range.end);
167                 *out_data = kcalloc(*out_size, sizeof(**out_data), GFP_KERNEL);
168                 ASSERT(*out_data);
169         }
170 }
171
172 /*
173  * Reduce the AUX reply down to the values the caller requested
174  */
175 static void dpcd_reduce_address_range(
176                 const uint32_t extended_address,
177                 uint8_t * const extended_data,
178                 const uint32_t extended_size,
179                 const uint32_t reduced_address,
180                 uint8_t * const reduced_data,
181                 const uint32_t reduced_size)
182 {
183         const uint32_t offset = reduced_address - extended_address;
184
185         /*
186          * If the address is same, address was not extended.
187          * So we do not need to free any memory.
188          * The data is in original buffer(reduced_data).
189          */
190         if (extended_data == reduced_data)
191                 return;
192
193         memcpy(&extended_data[offset], reduced_data, reduced_size);
194         kfree(extended_data);
195 }
196
197 enum dc_status core_link_read_dpcd(
198         struct dc_link *link,
199         uint32_t address,
200         uint8_t *data,
201         uint32_t size)
202 {
203         uint32_t extended_address;
204         uint32_t partitioned_address;
205         uint8_t *extended_data;
206         uint32_t extended_size;
207         /* size of the remaining partitioned address space */
208         uint32_t size_left_to_read;
209         enum dc_status status = DC_ERROR_UNEXPECTED;
210         /* size of the next partition to be read from */
211         uint32_t partition_size;
212         uint32_t data_index = 0;
213
214         dpcd_extend_address_range(address, data, size, &extended_address, &extended_data, &extended_size);
215         partitioned_address = extended_address;
216         size_left_to_read = extended_size;
217         while (size_left_to_read) {
218                 partition_size = dpcd_get_next_partition_size(partitioned_address, size_left_to_read);
219                 status = internal_link_read_dpcd(link, partitioned_address, &extended_data[data_index], partition_size);
220                 if (status != DC_OK)
221                         break;
222                 partitioned_address += partition_size;
223                 data_index += partition_size;
224                 size_left_to_read -= partition_size;
225         }
226         dpcd_reduce_address_range(extended_address, extended_data, extended_size, address, data, size);
227         return status;
228 }
229
230 enum dc_status core_link_write_dpcd(
231         struct dc_link *link,
232         uint32_t address,
233         const uint8_t *data,
234         uint32_t size)
235 {
236         uint32_t partition_size;
237         uint32_t data_index = 0;
238         enum dc_status status = DC_ERROR_UNEXPECTED;
239
240         while (size) {
241                 partition_size = dpcd_get_next_partition_size(address, size);
242                 status = internal_link_write_dpcd(link, address, &data[data_index], partition_size);
243                 if (status != DC_OK)
244                         break;
245                 address += partition_size;
246                 data_index += partition_size;
247                 size -= partition_size;
248         }
249         return status;
250 }
This page took 0.046941 seconds and 4 git commands to generate.