drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__
  27 #define __DAL_TIMING_GENERATOR_TYPES_H__
  28
  29 #include "hw_shared.h"
  30
  31 struct dc_bios;
  32
  33 /* Contains CRTC vertical/horizontal pixel counters */
  34 struct crtc_position {
  35         int32_t vertical_count;
  36         int32_t horizontal_count;
  37         int32_t nominal_vcount;
  38 };
  39
  40 struct dcp_gsl_params {
  41         int gsl_group;
  42         int gsl_master;
  43 };
  44
  45 struct gsl_params {
  46         int gsl0_en;
  47         int gsl1_en;
  48         int gsl2_en;
  49         int gsl_master_en;
  50         int gsl_master_mode;
  51         int master_update_lock_gsl_en;
  52         int gsl_window_start_x;
  53         int gsl_window_end_x;
  54         int gsl_window_start_y;
  55         int gsl_window_end_y;
  56 };
  57
  58 /* define the structure of Dynamic Refresh Mode */
  59 struct drr_params {
  60         uint32_t vertical_total_min;
  61         uint32_t vertical_total_max;
  62         uint32_t vertical_total_mid;
  63         uint32_t vertical_total_mid_frame_num;
  64         bool immediate_flip;
  65 };
  66
  67 struct long_vtotal_params {
  68         uint32_t vertical_total_min;
  69         uint32_t vertical_total_max;
  70         uint32_t vertical_blank_start;
  71 };
  72
  73 #define LEFT_EYE_3D_PRIMARY_SURFACE 1
  74 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0
  75
  76 enum crtc_state {
  77         CRTC_STATE_VBLANK = 0,
  78         CRTC_STATE_VACTIVE
  79 };
  80
  81 struct vupdate_keepout_params {
  82         int start_offset;
  83         int end_offset;
  84         int enable;
  85 };
  86
  87 struct crtc_stereo_flags {
  88         uint8_t PROGRAM_STEREO         : 1;
  89         uint8_t PROGRAM_POLARITY       : 1;
  90         uint8_t RIGHT_EYE_POLARITY     : 1;
  91         uint8_t FRAME_PACKED           : 1;
  92         uint8_t DISABLE_STEREO_DP_SYNC : 1;
  93 };
  94
  95 enum crc_selection {
  96         /* Order must match values expected by hardware */
  97         UNION_WINDOW_A_B = 0,
  98         UNION_WINDOW_A_NOT_B,
  99         UNION_WINDOW_NOT_A_B,
 100         UNION_WINDOW_NOT_A_NOT_B,
 101         INTERSECT_WINDOW_A_B,
 102         INTERSECT_WINDOW_A_NOT_B,
 103         INTERSECT_WINDOW_NOT_A_B,
 104         INTERSECT_WINDOW_NOT_A_NOT_B,
 105 };
 106
 107 enum otg_out_mux_dest {
 108         OUT_MUX_DIO = 0,
 109         OUT_MUX_HPO_DP = 2,
 110 };
 111
 112 enum h_timing_div_mode {
 113         H_TIMING_NO_DIV,
 114         H_TIMING_DIV_BY2,
 115         H_TIMING_RESERVED,
 116         H_TIMING_DIV_BY4,
 117 };
 118
 119 enum timing_synchronization_type {
 120         NOT_SYNCHRONIZABLE,
 121         TIMING_SYNCHRONIZABLE,
 122         VBLANK_SYNCHRONIZABLE
 123 };
 124
 125 struct crc_params {
 126         /* Regions used to calculate CRC*/
 127         uint16_t windowa_x_start;
 128         uint16_t windowa_x_end;
 129         uint16_t windowa_y_start;
 130         uint16_t windowa_y_end;
 131
 132         uint16_t windowb_x_start;
 133         uint16_t windowb_x_end;
 134         uint16_t windowb_y_start;
 135         uint16_t windowb_y_end;
 136
 137         enum crc_selection selection;
 138
 139         uint8_t dsc_mode;
 140         uint8_t odm_mode;
 141
 142         bool continuous_mode;
 143         bool enable;
 144
 145         uint8_t crc_eng_inst;
 146         bool reset;
 147 };
 148
 149 /**
 150  * struct timing_generator - Entry point to Output Timing Generator feature.
 151  */
 152 struct timing_generator {
 153         /**
 154          * @funcs: Timing generator control functions
 155          */
 156         const struct timing_generator_funcs *funcs;
 157         struct dc_bios *bp;
 158         struct dc_context *ctx;
 159         int inst;
 160 };
 161
 162 struct dc_crtc_timing;
 163
 164 struct drr_params;
 165
 166 /**
 167  * struct timing_generator_funcs - Control timing generator on a given device.
 168  */
 169 struct timing_generator_funcs {
 170         bool (*validate_timing)(struct timing_generator *tg,
 171                                                         const struct dc_crtc_timing *timing);
 172         void (*program_timing)(struct timing_generator *tg,
 173                                                         const struct dc_crtc_timing *timing,
 174                                                         int vready_offset,
 175                                                         int vstartup_start,
 176                                                         int vupdate_offset,
 177                                                         int vupdate_width,
 178                                                         int pstate_keepout,
 179                                                         const enum signal_type signal,
 180                                                         bool use_vbios
 181         );
 182         void (*setup_vertical_interrupt0)(
 183                         struct timing_generator *optc,
 184                         uint32_t start_line,
 185                         uint32_t end_line);
 186         void (*setup_vertical_interrupt1)(
 187                         struct timing_generator *optc,
 188                         uint32_t start_line);
 189         void (*setup_vertical_interrupt2)(
 190                         struct timing_generator *optc,
 191                         uint32_t start_line);
 192
 193         bool (*enable_crtc)(struct timing_generator *tg);
 194         bool (*disable_crtc)(struct timing_generator *tg);
 195         void (*phantom_crtc_post_enable)(struct timing_generator *tg);
 196         void (*disable_phantom_crtc)(struct timing_generator *tg);
 197         bool (*immediate_disable_crtc)(struct timing_generator *tg);
 198         bool (*is_counter_moving)(struct timing_generator *tg);
 199         void (*get_position)(struct timing_generator *tg,
 200                                 struct crtc_position *position);
 201
 202         uint32_t (*get_frame_count)(struct timing_generator *tg);
 203         void (*get_scanoutpos)(
 204                 struct timing_generator *tg,
 205                 uint32_t *v_blank_start,
 206                 uint32_t *v_blank_end,
 207                 uint32_t *h_position,
 208                 uint32_t *v_position);
 209         bool (*get_otg_active_size)(struct timing_generator *optc,
 210                         uint32_t *otg_active_width,
 211                         uint32_t *otg_active_height);
 212         bool (*is_matching_timing)(struct timing_generator *tg,
 213                         const struct dc_crtc_timing *otg_timing);
 214         void (*set_early_control)(struct timing_generator *tg,
 215                                                            uint32_t early_cntl);
 216         void (*wait_for_state)(struct timing_generator *tg,
 217                                                         enum crtc_state state);
 218         void (*set_blank)(struct timing_generator *tg,
 219                                         bool enable_blanking);
 220         bool (*is_blanked)(struct timing_generator *tg);
 221         void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
 222         void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
 223         void (*set_colors)(struct timing_generator *tg,
 224                                                 const struct tg_color *blank_color,
 225                                                 const struct tg_color *overscan_color);
 226
 227         void (*disable_vga)(struct timing_generator *tg);
 228         bool (*did_triggered_reset_occur)(struct timing_generator *tg);
 229         void (*setup_global_swap_lock)(struct timing_generator *tg,
 230                                                         const struct dcp_gsl_params *gsl_params);
 231         void (*unlock)(struct timing_generator *tg);
 232         void (*lock)(struct timing_generator *tg);
 233         void (*lock_doublebuffer_disable)(struct timing_generator *tg);
 234         void (*lock_doublebuffer_enable)(struct timing_generator *tg);
 235         void(*triplebuffer_unlock)(struct timing_generator *tg);
 236         void(*triplebuffer_lock)(struct timing_generator *tg);
 237         void (*enable_reset_trigger)(struct timing_generator *tg,
 238                                      int source_tg_inst);
 239         void (*enable_crtc_reset)(struct timing_generator *tg,
 240                                   int source_tg_inst,
 241                                   struct crtc_trigger_info *crtc_tp);
 242         void (*disable_reset_trigger)(struct timing_generator *tg);
 243         void (*tear_down_global_swap_lock)(struct timing_generator *tg);
 244         void (*enable_advanced_request)(struct timing_generator *tg,
 245                                         bool enable, const struct dc_crtc_timing *timing);
 246         void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
 247         void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max);
 248         void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate);
 249         void (*set_static_screen_control)(struct timing_generator *tg,
 250                                                 uint32_t event_triggers,
 251                                                 uint32_t num_frames);
 252         void (*set_test_pattern)(
 253                 struct timing_generator *tg,
 254                 enum controller_dp_test_pattern test_pattern,
 255                 enum dc_color_depth color_depth);
 256
 257         bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
 258
 259         void (*program_global_sync)(struct timing_generator *tg,
 260                         int vready_offset,
 261                         int vstartup_start,
 262                         int vupdate_offset,
 263                         int vupdate_width,
 264                         int pstate_keepout);
 265         void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
 266         void (*program_stereo)(struct timing_generator *tg,
 267                 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
 268         bool (*is_stereo_left_eye)(struct timing_generator *tg);
 269
 270         void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
 271
 272         void (*tg_init)(struct timing_generator *tg);
 273         bool (*is_tg_enabled)(struct timing_generator *tg);
 274         bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
 275         void (*clear_optc_underflow)(struct timing_generator *tg);
 276
 277         void (*set_dwb_source)(struct timing_generator *optc,
 278                 uint32_t dwb_pipe_inst);
 279
 280         void (*get_optc_source)(struct timing_generator *optc,
 281                         uint32_t *num_of_input_segments,
 282                         uint32_t *seg0_src_sel,
 283                         uint32_t *seg1_src_sel);
 284         bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing);
 285
 286         /**
 287          * Configure CRCs for the given timing generator. Return false if TG is
 288          * not on.
 289          */
 290         bool (*configure_crc)(struct timing_generator *tg,
 291                                const struct crc_params *params);
 292
 293         /**
 294          * @get_crc: Get CRCs for the given timing generator. Return false if
 295          * CRCs are not enabled (via configure_crc).
 296          */
 297         bool (*get_crc)(struct timing_generator *tg, uint8_t idx,
 298                         uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
 299
 300         void (*program_manual_trigger)(struct timing_generator *optc);
 301         void (*setup_manual_trigger)(struct timing_generator *optc);
 302         bool (*get_hw_timing)(struct timing_generator *optc,
 303                         struct dc_crtc_timing *hw_crtc_timing);
 304
 305         void (*set_vtg_params)(struct timing_generator *optc,
 306                         const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
 307
 308         void (*set_dsc_config)(struct timing_generator *optc,
 309                                enum optc_dsc_mode dsc_mode,
 310                                uint32_t dsc_bytes_per_pixel,
 311                                uint32_t dsc_slice_width);
 312         void (*get_dsc_status)(struct timing_generator *optc,
 313                                         uint32_t *dsc_mode);
 314         void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
 315
 316         /**
 317          * @set_odm_combine: Set up the ODM block to read from the correct
 318          * OPP(s) and turn on/off ODM memory.
 319          */
 320         void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
 321                         int segment_width, int last_segment_width);
 322         void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments);
 323         void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);
 324         void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
 325         void (*set_gsl_source_select)(struct timing_generator *optc,
 326                         int group_idx,
 327                         uint32_t gsl_ready_signal);
 328         void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
 329         void (*set_drr_trigger_window)(struct timing_generator *optc,
 330                         uint32_t window_start, uint32_t window_end);
 331         void (*set_vtotal_change_limit)(struct timing_generator *optc,
 332                         uint32_t limit);
 333         void (*align_vblanks)(struct timing_generator *master_optc,
 334                         struct timing_generator *slave_optc,
 335                         uint32_t master_pixel_clock_100Hz,
 336                         uint32_t slave_pixel_clock_100Hz,
 337                         uint8_t master_clock_divider,
 338                         uint8_t slave_clock_divider);
 339         bool (*validate_vmin_vmax)(struct timing_generator *optc,
 340                         int vmin, int vmax);
 341         bool (*validate_vtotal_change_limit)(struct timing_generator *optc,
 342                         uint32_t vtotal_change_limit);
 343
 344         void (*init_odm)(struct timing_generator *tg);
 345         void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg);
 346         void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params);
 347         void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg);
 348         bool (*get_optc_double_buffer_pending)(struct timing_generator *tg);
 349         bool (*get_otg_double_buffer_pending)(struct timing_generator *tg);
 350         bool (*get_pipe_update_pending)(struct timing_generator *tg);
 351         void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable);
 352         bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked);
 353 };
 354
 355 #endif