drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27
  28 #include "dm_services.h"
  29 #include "dm_helpers.h"
  30 #include "core_types.h"
  31 #include "resource.h"
  32 #include "dccg.h"
  33 #include "dce/dce_hwseq.h"
  34 #include "clk_mgr.h"
  35 #include "reg_helper.h"
  36 #include "abm.h"
  37 #include "hubp.h"
  38 #include "dchubbub.h"
  39 #include "timing_generator.h"
  40 #include "opp.h"
  41 #include "ipp.h"
  42 #include "mpc.h"
  43 #include "mcif_wb.h"
  44 #include "dc_dmub_srv.h"
  45 #include "dcn314_hwseq.h"
  46 #include "link_hwss.h"
  47 #include "dpcd_defs.h"
  48 #include "dce/dmub_outbox.h"
  49 #include "link.h"
  50 #include "dcn10/dcn10_hwseq.h"
  51 #include "inc/link_enc_cfg.h"
  52 #include "dcn30/dcn30_vpg.h"
  53 #include "dce/dce_i2c_hw.h"
  54 #include "dsc.h"
  55 #include "dcn20/dcn20_optc.h"
  56 #include "dcn30/dcn30_cm_common.h"
  57
  58 #define DC_LOGGER_INIT(logger)
  59
  60 #define CTX \
  61         hws->ctx
  62 #define REG(reg)\
  63         hws->regs->reg
  64 #define DC_LOGGER \
  65         stream->ctx->logger
  66
  67
  68 #undef FN
  69 #define FN(reg_name, field_name) \
  70         hws->shifts->field_name, hws->masks->field_name
  71
  72 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
  73 {
  74         struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
  75         struct dc_stream_state *stream = pipe_ctx->stream;
  76         struct pipe_ctx *odm_pipe;
  77         int opp_cnt = 1;
  78
  79         ASSERT(dsc);
  80         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
  81                 opp_cnt++;
  82
  83         if (enable) {
  84                 struct dsc_config dsc_cfg;
  85                 struct dsc_optc_config dsc_optc_cfg = {0};
  86                 enum optc_dsc_mode optc_dsc_mode;
  87
  88                 /* Enable DSC hw block */
  89                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
  90                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
  91                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
  92                 dsc_cfg.color_depth = stream->timing.display_color_depth;
  93                 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
  94                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
  95                 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
  96                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
  97
  98                 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
  99                 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
 100                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 101                         struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
 102
 103                         ASSERT(odm_dsc);
 104                         odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
 105                         odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
 106                 }
 107                 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
 108                 dsc_cfg.pic_width *= opp_cnt;
 109
 110                 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
 111
 112                 /* Enable DSC in OPTC */
 113                 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
 114                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
 115                                                         optc_dsc_mode,
 116                                                         dsc_optc_cfg.bytes_per_pixel,
 117                                                         dsc_optc_cfg.slice_width);
 118         } else {
 119                 /* disable DSC in OPTC */
 120                 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
 121                                 pipe_ctx->stream_res.tg,
 122                                 OPTC_DSC_DISABLED, 0, 0);
 123
 124                 /* disable DSC block */
 125                 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
 126                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 127                         ASSERT(odm_pipe->stream_res.dsc);
 128                         odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
 129                 }
 130         }
 131 }
 132
 133 // Given any pipe_ctx, return the total ODM combine factor, and optionally return
 134 // the OPPids which are used
 135 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
 136 {
 137         unsigned int opp_count = 1;
 138         struct pipe_ctx *odm_pipe;
 139
 140         // First get to the top pipe
 141         for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
 142                 ;
 143
 144         // First pipe is always used
 145         if (opp_instances)
 146                 opp_instances[0] = odm_pipe->stream_res.opp->inst;
 147
 148         // Find and count odm pipes, if any
 149         for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 150                 if (opp_instances)
 151                         opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
 152                 opp_count++;
 153         }
 154
 155         return opp_count;
 156 }
 157
 158 void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
 159 {
 160         struct pipe_ctx *odm_pipe;
 161         int opp_cnt = 0;
 162         int opp_inst[MAX_PIPES] = {0};
 163         int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
 164         int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);
 165         struct mpc *mpc = dc->res_pool->mpc;
 166         int i;
 167
 168         opp_cnt = get_odm_config(pipe_ctx, opp_inst);
 169
 170         if (opp_cnt > 1)
 171                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 172                                 pipe_ctx->stream_res.tg,
 173                                 opp_inst, opp_cnt,
 174                                 odm_slice_width, last_odm_slice_width);
 175         else
 176                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
 177                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
 178
 179         if (mpc->funcs->set_out_rate_control) {
 180                 for (i = 0; i < opp_cnt; ++i) {
 181                         mpc->funcs->set_out_rate_control(
 182                                         mpc, opp_inst[i],
 183                                         false,
 184                                         0,
 185                                         NULL);
 186                 }
 187         }
 188
 189         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 190                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 191                                 odm_pipe->stream_res.opp,
 192                                 true);
 193         }
 194
 195         if (pipe_ctx->stream_res.dsc) {
 196                 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
 197
 198                 update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
 199
 200                 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
 201                 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
 202                                 current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
 203                         struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
 204                         /* disconnect DSC block from stream */
 205                         dsc->funcs->dsc_disconnect(dsc);
 206                 }
 207         }
 208 }
 209
 210 void dcn314_dsc_pg_control(
 211                 struct dce_hwseq *hws,
 212                 unsigned int dsc_inst,
 213                 bool power_on)
 214 {
 215         uint32_t power_gate = power_on ? 0 : 1;
 216         uint32_t pwr_status = power_on ? 0 : 2;
 217         uint32_t org_ip_request_cntl = 0;
 218
 219         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 220                 return;
 221
 222         if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
 223                 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
 224                 power_on)
 225                 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
 226                         hws->ctx->dc->res_pool->dccg, dsc_inst);
 227
 228         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 229         if (org_ip_request_cntl == 0)
 230                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 231
 232         switch (dsc_inst) {
 233         case 0: /* DSC0 */
 234                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 235                                 DOMAIN_POWER_GATE, power_gate);
 236
 237                 REG_WAIT(DOMAIN16_PG_STATUS,
 238                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 239                                 1, 1000);
 240                 break;
 241         case 1: /* DSC1 */
 242                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 243                                 DOMAIN_POWER_GATE, power_gate);
 244
 245                 REG_WAIT(DOMAIN17_PG_STATUS,
 246                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 247                                 1, 1000);
 248                 break;
 249         case 2: /* DSC2 */
 250                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 251                                 DOMAIN_POWER_GATE, power_gate);
 252
 253                 REG_WAIT(DOMAIN18_PG_STATUS,
 254                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 255                                 1, 1000);
 256                 break;
 257         case 3: /* DSC3 */
 258                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 259                                 DOMAIN_POWER_GATE, power_gate);
 260
 261                 REG_WAIT(DOMAIN19_PG_STATUS,
 262                                 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
 263                                 1, 1000);
 264                 break;
 265         default:
 266                 BREAK_TO_DEBUGGER();
 267                 break;
 268         }
 269
 270         if (org_ip_request_cntl == 0)
 271                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 272
 273         if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
 274                 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
 275                         hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
 276                                 hws->ctx->dc->res_pool->dccg, dsc_inst);
 277         }
 278
 279 }
 280
 281 void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
 282 {
 283         bool force_on = true; /* disable power gating */
 284         uint32_t org_ip_request_cntl = 0;
 285
 286         if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
 287                 force_on = false;
 288
 289         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 290         if (org_ip_request_cntl == 0)
 291                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 292         /* DCHUBP0/1/2/3/4/5 */
 293         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 294         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 295         /* DPP0/1/2/3/4/5 */
 296         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 297         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 298
 299         force_on = true; /* disable power gating */
 300         if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
 301                 force_on = false;
 302
 303         /* DCS0/1/2/3/4 */
 304         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 305         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 306         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 307         REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
 308
 309         if (org_ip_request_cntl == 0)
 310                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 311 }
 312
 313 unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
 314 {
 315         struct dc_stream_state *stream = pipe_ctx->stream;
 316         unsigned int odm_combine_factor = 0;
 317         bool two_pix_per_container = false;
 318
 319         two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
 320         odm_combine_factor = get_odm_config(pipe_ctx, NULL);
 321
 322         if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
 323                 *k1_div = PIXEL_RATE_DIV_BY_1;
 324                 *k2_div = PIXEL_RATE_DIV_BY_1;
 325         } else if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) {
 326                 *k1_div = PIXEL_RATE_DIV_BY_1;
 327                 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
 328                         *k2_div = PIXEL_RATE_DIV_BY_2;
 329                 else
 330                         *k2_div = PIXEL_RATE_DIV_BY_4;
 331         } else if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {
 332                 if (two_pix_per_container) {
 333                         *k1_div = PIXEL_RATE_DIV_BY_1;
 334                         *k2_div = PIXEL_RATE_DIV_BY_2;
 335                 } else {
 336                         *k1_div = PIXEL_RATE_DIV_BY_1;
 337                         *k2_div = PIXEL_RATE_DIV_BY_4;
 338                         if (odm_combine_factor == 2)
 339                                 *k2_div = PIXEL_RATE_DIV_BY_2;
 340                 }
 341         }
 342
 343         if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
 344                 ASSERT(false);
 345
 346         return odm_combine_factor;
 347 }
 348
 349 void dcn314_calculate_pix_rate_divider(
 350                 struct dc *dc,
 351                 struct dc_state *context,
 352                 const struct dc_stream_state *stream)
 353 {
 354         struct dce_hwseq *hws = dc->hwseq;
 355         struct pipe_ctx *pipe_ctx = NULL;
 356         unsigned int k1_div = PIXEL_RATE_DIV_NA;
 357         unsigned int k2_div = PIXEL_RATE_DIV_NA;
 358
 359         pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
 360
 361         if (pipe_ctx) {
 362                 if (hws->funcs.calculate_dccg_k1_k2_values)
 363                         hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
 364
 365                 pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;
 366                 pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;
 367         }
 368 }
 369
 370 static bool dcn314_is_pipe_dig_fifo_on(struct pipe_ctx *pipe)
 371 {
 372         return pipe && pipe->stream
 373                 // Check dig's otg instance.
 374                 && pipe->stream_res.stream_enc
 375                 && pipe->stream_res.stream_enc->funcs->dig_source_otg
 376                 && pipe->stream_res.tg->inst == pipe->stream_res.stream_enc->funcs->dig_source_otg(pipe->stream_res.stream_enc)
 377                 && pipe->stream->link && pipe->stream->link->link_enc
 378                 && pipe->stream->link->link_enc->funcs->is_dig_enabled
 379                 && pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc)
 380                 && pipe->stream_res.stream_enc->funcs->is_fifo_enabled
 381                 && pipe->stream_res.stream_enc->funcs->is_fifo_enabled(pipe->stream_res.stream_enc);
 382 }
 383
 384 void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)
 385 {
 386         unsigned int i;
 387         struct pipe_ctx *pipe = NULL;
 388         bool otg_disabled[MAX_PIPES] = {false};
 389
 390         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 391                 if (i <= current_pipe_idx) {
 392                         pipe = &context->res_ctx.pipe_ctx[i];
 393                 } else {
 394                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 395                 }
 396
 397                 if (pipe->top_pipe || pipe->prev_odm_pipe)
 398                         continue;
 399
 400                 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal)) &&
 401                         !pipe->stream->apply_seamless_boot_optimization &&
 402                         !pipe->stream->apply_edp_fast_boot_optimization) {
 403                         if (dcn314_is_pipe_dig_fifo_on(pipe))
 404                                 continue;
 405                         pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
 406                         reset_sync_context_for_pipe(dc, context, i);
 407                         otg_disabled[i] = true;
 408                 }
 409         }
 410
 411         hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
 412
 413         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 414                 if (i <= current_pipe_idx)
 415                         pipe = &context->res_ctx.pipe_ctx[i];
 416                 else
 417                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 418
 419                 if (otg_disabled[i]) {
 420                         int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
 421                         int opp_cnt = 1;
 422                         int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);
 423                         int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);
 424                         struct pipe_ctx *odm_pipe;
 425
 426                         for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 427                                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 428                                 opp_cnt++;
 429                         }
 430                         if (opp_cnt > 1)
 431                                 pipe->stream_res.tg->funcs->set_odm_combine(
 432                                                 pipe->stream_res.tg,
 433                                                 opp_inst, opp_cnt,
 434                                                 odm_slice_width,
 435                                                 last_odm_slice_width);
 436                         pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
 437                 }
 438         }
 439 }
 440
 441 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)
 442 {
 443         if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)
 444                 return;
 445
 446         if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)
 447                 hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(
 448                         hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
 449 }
 450
 451 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
 452 {
 453         /* There are use cases where SYMCLK is referenced by OTG. For instance
 454          * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
 455          * However current link interface will power off PHY when disabling link
 456          * output. This will turn off SYMCLK generated by PHY. The workaround is
 457          * to identify such case where SYMCLK is still in use by OTG when we
 458          * power off PHY. When this is detected, we will temporarily power PHY
 459          * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
 460          * program_pix_clk interface. When OTG is disabled, we will then power
 461          * off PHY by calling disable link output again.
 462          *
 463          * In future dcn generations, we plan to rework transmitter control
 464          * interface so that we could have an option to set SYMCLK ON TX OFF
 465          * state in one step without this workaround
 466          */
 467
 468         struct dc *dc = link->ctx->dc;
 469         struct pipe_ctx *pipe_ctx = NULL;
 470         uint8_t i;
 471
 472         if (link->phy_state.symclk_ref_cnts.otg > 0) {
 473                 for (i = 0; i < MAX_PIPES; i++) {
 474                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 475                         if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
 476                                 pipe_ctx->clock_source->funcs->program_pix_clk(
 477                                                 pipe_ctx->clock_source,
 478                                                 &pipe_ctx->stream_res.pix_clk_params,
 479                                                 dc->link_srv->dp_get_encoding_format(
 480                                                                 &pipe_ctx->link_config.dp_link_settings),
 481                                                 &pipe_ctx->pll_settings);
 482                                 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
 483                                 break;
 484                         }
 485                 }
 486         }
 487 }
 488
 489 void dcn314_disable_link_output(struct dc_link *link,
 490                 const struct link_resource *link_res,
 491                 enum signal_type signal)
 492 {
 493         struct dc *dc = link->ctx->dc;
 494         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
 495         struct dmcu *dmcu = dc->res_pool->dmcu;
 496
 497         if (signal == SIGNAL_TYPE_EDP &&
 498                         link->dc->hwss.edp_backlight_control &&
 499                         !link->skip_implict_edp_power_control)
 500                 link->dc->hwss.edp_backlight_control(link, false);
 501         else if (dmcu != NULL && dmcu->funcs->lock_phy)
 502                 dmcu->funcs->lock_phy(dmcu);
 503
 504         link_hwss->disable_link_output(link, link_res, signal);
 505         link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
 506         /*
 507          * Add the logic to extract BOTH power up and power down sequences
 508          * from enable/disable link output and only call edp panel control
 509          * in enable_link_dp and disable_link_dp once.
 510          */
 511         if (dmcu != NULL && dmcu->funcs->unlock_phy)
 512                 dmcu->funcs->unlock_phy(dmcu);
 513         dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
 514
 515         apply_symclk_on_tx_off_wa(link);
 516 }