drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dc_bios_types.h"
  27 #include "dce_stream_encoder.h"
  28 #include "reg_helper.h"
  29 #include "hw_shared.h"
  30
  31 #define DC_LOGGER \
  32                 enc110->base.ctx->logger
  33
  34 #define REG(reg)\
  35         (enc110->regs->reg)
  36
  37 #undef FN
  38 #define FN(reg_name, field_name) \
  39         enc110->se_shift->field_name, enc110->se_mask->field_name
  40
  41 #define VBI_LINE_0 0
  42 #define DP_BLANK_MAX_RETRY 20
  43 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
  44
  45 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
  46         #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
  47         #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
  48         #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT     0x00000004
  49         #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT       0x00000008
  50 #endif
  51
  52 enum {
  53         DP_MST_UPDATE_MAX_RETRY = 50
  54 };
  55
  56 #define DCE110_SE(audio)\
  57         container_of(audio, struct dce110_stream_encoder, base)
  58
  59 #define CTX \
  60         enc110->base.ctx
  61
  62 static void dce110_update_generic_info_packet(
  63         struct dce110_stream_encoder *enc110,
  64         uint32_t packet_index,
  65         const struct dc_info_packet *info_packet)
  66 {
  67         /* TODOFPGA Figure out a proper number for max_retries polling for lock
  68          * use 50 for now.
  69          */
  70         uint32_t max_retries = 50;
  71
  72         /*we need turn on clock before programming AFMT block*/
  73         if (REG(AFMT_CNTL))
  74                 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
  75
  76         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
  77                 if (packet_index >= 8)
  78                         ASSERT(0);
  79
  80                 /* poll dig_update_lock is not locked -> asic internal signal
  81                  * assume otg master lock will unlock it
  82                  */
  83 /*              REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
  84                                 0, 10, max_retries);*/
  85
  86                 /* check if HW reading GSP memory */
  87                 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
  88                                 0, 10, max_retries);
  89
  90                 /* HW does is not reading GSP memory not reading too long ->
  91                  * something wrong. clear GPS memory access and notify?
  92                  * hw SW is writing to GSP memory
  93                  */
  94                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
  95         }
  96         /* choose which generic packet to use */
  97         {
  98                 REG_READ(AFMT_VBI_PACKET_CONTROL);
  99                 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
 100                                 AFMT_GENERIC_INDEX, packet_index);
 101         }
 102
 103         /* write generic packet header
 104          * (4th byte is for GENERIC0 only) */
 105         {
 106                 REG_SET_4(AFMT_GENERIC_HDR, 0,
 107                                 AFMT_GENERIC_HB0, info_packet->hb0,
 108                                 AFMT_GENERIC_HB1, info_packet->hb1,
 109                                 AFMT_GENERIC_HB2, info_packet->hb2,
 110                                 AFMT_GENERIC_HB3, info_packet->hb3);
 111         }
 112
 113         /* write generic packet contents
 114          * (we never use last 4 bytes)
 115          * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
 116         {
 117                 const uint32_t *content =
 118                         (const uint32_t *) &info_packet->sb[0];
 119
 120                 REG_WRITE(AFMT_GENERIC_0, *content++);
 121                 REG_WRITE(AFMT_GENERIC_1, *content++);
 122                 REG_WRITE(AFMT_GENERIC_2, *content++);
 123                 REG_WRITE(AFMT_GENERIC_3, *content++);
 124                 REG_WRITE(AFMT_GENERIC_4, *content++);
 125                 REG_WRITE(AFMT_GENERIC_5, *content++);
 126                 REG_WRITE(AFMT_GENERIC_6, *content++);
 127                 REG_WRITE(AFMT_GENERIC_7, *content);
 128         }
 129
 130         if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
 131                 /* force double-buffered packet update */
 132                 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
 133                         AFMT_GENERIC0_UPDATE, (packet_index == 0),
 134                         AFMT_GENERIC2_UPDATE, (packet_index == 2));
 135         }
 136
 137         if (REG(AFMT_VBI_PACKET_CONTROL1)) {
 138                 switch (packet_index) {
 139                 case 0:
 140                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 141                                         AFMT_GENERIC0_FRAME_UPDATE, 1);
 142                         break;
 143                 case 1:
 144                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 145                                         AFMT_GENERIC1_FRAME_UPDATE, 1);
 146                         break;
 147                 case 2:
 148                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 149                                         AFMT_GENERIC2_FRAME_UPDATE, 1);
 150                         break;
 151                 case 3:
 152                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 153                                         AFMT_GENERIC3_FRAME_UPDATE, 1);
 154                         break;
 155                 case 4:
 156                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 157                                         AFMT_GENERIC4_FRAME_UPDATE, 1);
 158                         break;
 159                 case 5:
 160                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 161                                         AFMT_GENERIC5_FRAME_UPDATE, 1);
 162                         break;
 163                 case 6:
 164                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 165                                         AFMT_GENERIC6_FRAME_UPDATE, 1);
 166                         break;
 167                 case 7:
 168                         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
 169                                         AFMT_GENERIC7_FRAME_UPDATE, 1);
 170                         break;
 171                 default:
 172                         break;
 173                 }
 174         }
 175 }
 176
 177 static void dce110_update_hdmi_info_packet(
 178         struct dce110_stream_encoder *enc110,
 179         uint32_t packet_index,
 180         const struct dc_info_packet *info_packet)
 181 {
 182         uint32_t cont, send, line;
 183
 184         if (info_packet->valid) {
 185                 dce110_update_generic_info_packet(
 186                         enc110,
 187                         packet_index,
 188                         info_packet);
 189
 190                 /* enable transmission of packet(s) -
 191                  * packet transmission begins on the next frame */
 192                 cont = 1;
 193                 /* send packet(s) every frame */
 194                 send = 1;
 195                 /* select line number to send packets on */
 196                 line = 2;
 197         } else {
 198                 cont = 0;
 199                 send = 0;
 200                 line = 0;
 201         }
 202
 203         /* choose which generic packet control to use */
 204         switch (packet_index) {
 205         case 0:
 206                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 207                                 HDMI_GENERIC0_CONT, cont,
 208                                 HDMI_GENERIC0_SEND, send,
 209                                 HDMI_GENERIC0_LINE, line);
 210                 break;
 211         case 1:
 212                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
 213                                 HDMI_GENERIC1_CONT, cont,
 214                                 HDMI_GENERIC1_SEND, send,
 215                                 HDMI_GENERIC1_LINE, line);
 216                 break;
 217         case 2:
 218                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 219                                 HDMI_GENERIC0_CONT, cont,
 220                                 HDMI_GENERIC0_SEND, send,
 221                                 HDMI_GENERIC0_LINE, line);
 222                 break;
 223         case 3:
 224                 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
 225                                 HDMI_GENERIC1_CONT, cont,
 226                                 HDMI_GENERIC1_SEND, send,
 227                                 HDMI_GENERIC1_LINE, line);
 228                 break;
 229         case 4:
 230                 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 231                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 232                                         HDMI_GENERIC0_CONT, cont,
 233                                         HDMI_GENERIC0_SEND, send,
 234                                         HDMI_GENERIC0_LINE, line);
 235                 break;
 236         case 5:
 237                 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 238                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
 239                                         HDMI_GENERIC1_CONT, cont,
 240                                         HDMI_GENERIC1_SEND, send,
 241                                         HDMI_GENERIC1_LINE, line);
 242                 break;
 243         case 6:
 244                 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 245                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 246                                         HDMI_GENERIC0_CONT, cont,
 247                                         HDMI_GENERIC0_SEND, send,
 248                                         HDMI_GENERIC0_LINE, line);
 249                 break;
 250         case 7:
 251                 if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 252                         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
 253                                         HDMI_GENERIC1_CONT, cont,
 254                                         HDMI_GENERIC1_SEND, send,
 255                                         HDMI_GENERIC1_LINE, line);
 256                 break;
 257         default:
 258                 /* invalid HW packet index */
 259                 DC_LOG_WARNING(
 260                         "Invalid HW packet index: %s()\n",
 261                         __func__);
 262                 return;
 263         }
 264 }
 265
 266 /* setup stream encoder in dp mode */
 267 static void dce110_stream_encoder_dp_set_stream_attribute(
 268         struct stream_encoder *enc,
 269         struct dc_crtc_timing *crtc_timing,
 270         enum dc_color_space output_color_space,
 271         bool use_vsc_sdp_for_colorimetry,
 272         uint32_t enable_sdp_splitting)
 273 {
 274         uint32_t h_active_start;
 275         uint32_t v_active_start;
 276         uint32_t misc0 = 0;
 277         uint32_t misc1 = 0;
 278         uint32_t h_blank;
 279         uint32_t h_back_porch;
 280         uint8_t colorimetry_bpc;
 281         uint8_t dynamic_range_rgb = 0; /*full range*/
 282         uint8_t dynamic_range_ycbcr = 1; /*bt709*/
 283
 284         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 285         struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
 286         if (hw_crtc_timing.flags.INTERLACE) {
 287                 /*the input timing is in VESA spec format with Interlace flag =1*/
 288                 hw_crtc_timing.v_total /= 2;
 289                 hw_crtc_timing.v_border_top /= 2;
 290                 hw_crtc_timing.v_addressable /= 2;
 291                 hw_crtc_timing.v_border_bottom /= 2;
 292                 hw_crtc_timing.v_front_porch /= 2;
 293                 hw_crtc_timing.v_sync_width /= 2;
 294         }
 295         /* set pixel encoding */
 296         switch (hw_crtc_timing.pixel_encoding) {
 297         case PIXEL_ENCODING_YCBCR422:
 298                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 299                                 DP_PIXEL_ENCODING_TYPE_YCBCR422);
 300                 break;
 301         case PIXEL_ENCODING_YCBCR444:
 302                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 303                                 DP_PIXEL_ENCODING_TYPE_YCBCR444);
 304
 305                 if (hw_crtc_timing.flags.Y_ONLY)
 306                         if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
 307                                 /* HW testing only, no use case yet.
 308                                  * Color depth of Y-only could be
 309                                  * 8, 10, 12, 16 bits */
 310                                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 311                                                 DP_PIXEL_ENCODING_TYPE_Y_ONLY);
 312                 /* Note: DP_MSA_MISC1 bit 7 is the indicator
 313                  * of Y-only mode.
 314                  * This bit is set in HW if register
 315                  * DP_PIXEL_ENCODING is programmed to 0x4 */
 316                 break;
 317         case PIXEL_ENCODING_YCBCR420:
 318                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 319                                 DP_PIXEL_ENCODING_TYPE_YCBCR420);
 320                 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
 321                         REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
 322
 323                 if (enc110->se_mask->DP_VID_N_MUL)
 324                         REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
 325                 break;
 326         default:
 327                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 328                                 DP_PIXEL_ENCODING_TYPE_RGB444);
 329                 break;
 330         }
 331
 332         if (REG(DP_MSA_MISC))
 333                 misc1 = REG_READ(DP_MSA_MISC);
 334
 335         /* set color depth */
 336
 337         switch (hw_crtc_timing.display_color_depth) {
 338         case COLOR_DEPTH_666:
 339                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 340                                 0);
 341                 break;
 342         case COLOR_DEPTH_888:
 343                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 344                                 DP_COMPONENT_PIXEL_DEPTH_8BPC);
 345                 break;
 346         case COLOR_DEPTH_101010:
 347                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 348                                 DP_COMPONENT_PIXEL_DEPTH_10BPC);
 349
 350                 break;
 351         case COLOR_DEPTH_121212:
 352                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 353                                 DP_COMPONENT_PIXEL_DEPTH_12BPC);
 354                 break;
 355         default:
 356                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
 357                                 DP_COMPONENT_PIXEL_DEPTH_6BPC);
 358                 break;
 359         }
 360
 361         /* set dynamic range and YCbCr range */
 362
 363
 364         switch (hw_crtc_timing.display_color_depth) {
 365         case COLOR_DEPTH_666:
 366                 colorimetry_bpc = 0;
 367                 break;
 368         case COLOR_DEPTH_888:
 369                 colorimetry_bpc = 1;
 370                 break;
 371         case COLOR_DEPTH_101010:
 372                 colorimetry_bpc = 2;
 373                 break;
 374         case COLOR_DEPTH_121212:
 375                 colorimetry_bpc = 3;
 376                 break;
 377         default:
 378                 colorimetry_bpc = 0;
 379                 break;
 380         }
 381
 382         misc0 = colorimetry_bpc << 5;
 383
 384         if (REG(DP_MSA_TIMING_PARAM1)) {
 385                 switch (output_color_space) {
 386                 case COLOR_SPACE_SRGB:
 387                         misc0 = misc0 | 0x0;
 388                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 389                         dynamic_range_rgb = 0; /*full range*/
 390                         break;
 391                 case COLOR_SPACE_SRGB_LIMITED:
 392                         misc0 = misc0 | 0x8; /* bit3=1 */
 393                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 394                         dynamic_range_rgb = 1; /*limited range*/
 395                         break;
 396                 case COLOR_SPACE_YCBCR601:
 397                 case COLOR_SPACE_YCBCR601_LIMITED:
 398                         misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
 399                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 400                         dynamic_range_ycbcr = 0; /*bt601*/
 401                         if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 402                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 403                         else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 404                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 405                         break;
 406                 case COLOR_SPACE_YCBCR709:
 407                 case COLOR_SPACE_YCBCR709_LIMITED:
 408                 case COLOR_SPACE_YCBCR709_BLACK:
 409                         misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
 410                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
 411                         dynamic_range_ycbcr = 1; /*bt709*/
 412                         if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 413                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
 414                         else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
 415                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
 416                         break;
 417                 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 418                         dynamic_range_rgb = 1; /*limited range*/
 419                         break;
 420                 case COLOR_SPACE_2020_RGB_FULLRANGE:
 421                 case COLOR_SPACE_2020_YCBCR:
 422                 case COLOR_SPACE_XR_RGB:
 423                 case COLOR_SPACE_MSREF_SCRGB:
 424                 case COLOR_SPACE_ADOBERGB:
 425                 case COLOR_SPACE_DCIP3:
 426                 case COLOR_SPACE_XV_YCC_709:
 427                 case COLOR_SPACE_XV_YCC_601:
 428                 case COLOR_SPACE_DISPLAYNATIVE:
 429                 case COLOR_SPACE_DOLBYVISION:
 430                 case COLOR_SPACE_APPCTRL:
 431                 case COLOR_SPACE_CUSTOMPOINTS:
 432                 case COLOR_SPACE_UNKNOWN:
 433                         /* do nothing */
 434                         break;
 435                 }
 436                 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
 437                         REG_UPDATE_2(
 438                                 DP_PIXEL_FORMAT,
 439                                 DP_DYN_RANGE, dynamic_range_rgb,
 440                                 DP_YCBCR_RANGE, dynamic_range_ycbcr);
 441
 442                 if (REG(DP_MSA_COLORIMETRY))
 443                         REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
 444
 445                 if (REG(DP_MSA_MISC))
 446                         REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
 447
 448         /* dcn new register
 449          * dc_crtc_timing is vesa dmt struct. data from edid
 450          */
 451                 if (REG(DP_MSA_TIMING_PARAM1))
 452                         REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
 453                                         DP_MSA_HTOTAL, hw_crtc_timing.h_total,
 454                                         DP_MSA_VTOTAL, hw_crtc_timing.v_total);
 455
 456                 /* calcuate from vesa timing parameters
 457                  * h_active_start related to leading edge of sync
 458                  */
 459
 460                 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
 461                                 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
 462
 463                 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
 464                                 hw_crtc_timing.h_sync_width;
 465
 466                 /* start at begining of left border */
 467                 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
 468
 469
 470                 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
 471                                 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
 472                                 hw_crtc_timing.v_front_porch;
 473
 474
 475                 /* start at begining of left border */
 476                 if (REG(DP_MSA_TIMING_PARAM2))
 477                         REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
 478                                 DP_MSA_HSTART, h_active_start,
 479                                 DP_MSA_VSTART, v_active_start);
 480
 481                 if (REG(DP_MSA_TIMING_PARAM3))
 482                         REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
 483                                         DP_MSA_HSYNCWIDTH,
 484                                         hw_crtc_timing.h_sync_width,
 485                                         DP_MSA_HSYNCPOLARITY,
 486                                         !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
 487                                         DP_MSA_VSYNCWIDTH,
 488                                         hw_crtc_timing.v_sync_width,
 489                                         DP_MSA_VSYNCPOLARITY,
 490                                         !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
 491
 492                 /* HWDITH include border or overscan */
 493                 if (REG(DP_MSA_TIMING_PARAM4))
 494                         REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
 495                                 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
 496                                 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
 497                                 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
 498                                 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
 499         }
 500 }
 501
 502 static void dce110_stream_encoder_set_stream_attribute_helper(
 503                 struct dce110_stream_encoder *enc110,
 504                 struct dc_crtc_timing *crtc_timing)
 505 {
 506         if (enc110->regs->TMDS_CNTL) {
 507                 switch (crtc_timing->pixel_encoding) {
 508                 case PIXEL_ENCODING_YCBCR422:
 509                         REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
 510                         break;
 511                 default:
 512                         REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
 513                         break;
 514                 }
 515                 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
 516         } else if (enc110->regs->DIG_FE_CNTL) {
 517                 switch (crtc_timing->pixel_encoding) {
 518                 case PIXEL_ENCODING_YCBCR422:
 519                         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
 520                         break;
 521                 default:
 522                         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
 523                         break;
 524                 }
 525                 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
 526         }
 527
 528 }
 529
 530 /* setup stream encoder in hdmi mode */
 531 static void dce110_stream_encoder_hdmi_set_stream_attribute(
 532         struct stream_encoder *enc,
 533         struct dc_crtc_timing *crtc_timing,
 534         int actual_pix_clk_khz,
 535         bool enable_audio)
 536 {
 537         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 538         struct bp_encoder_control cntl = {0};
 539
 540         cntl.action = ENCODER_CONTROL_SETUP;
 541         cntl.engine_id = enc110->base.id;
 542         cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 543         cntl.enable_dp_audio = enable_audio;
 544         cntl.pixel_clock = actual_pix_clk_khz;
 545         cntl.lanes_number = LANE_COUNT_FOUR;
 546         cntl.color_depth = crtc_timing->display_color_depth;
 547
 548         if (enc110->base.bp->funcs->encoder_control(
 549                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 550                 return;
 551
 552         dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 553
 554         /* setup HDMI engine */
 555         if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 556                 REG_UPDATE_3(HDMI_CONTROL,
 557                         HDMI_PACKET_GEN_VERSION, 1,
 558                         HDMI_KEEPOUT_MODE, 1,
 559                         HDMI_DEEP_COLOR_ENABLE, 0);
 560         } else if (enc110->regs->DIG_FE_CNTL) {
 561                 REG_UPDATE_5(HDMI_CONTROL,
 562                         HDMI_PACKET_GEN_VERSION, 1,
 563                         HDMI_KEEPOUT_MODE, 1,
 564                         HDMI_DEEP_COLOR_ENABLE, 0,
 565                         HDMI_DATA_SCRAMBLE_EN, 0,
 566                         HDMI_CLOCK_CHANNEL_RATE, 0);
 567         }
 568
 569         switch (crtc_timing->display_color_depth) {
 570         case COLOR_DEPTH_888:
 571                 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
 572                 break;
 573         case COLOR_DEPTH_101010:
 574                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 575                         REG_UPDATE_2(HDMI_CONTROL,
 576                                         HDMI_DEEP_COLOR_DEPTH, 1,
 577                                         HDMI_DEEP_COLOR_ENABLE, 0);
 578                 } else {
 579                         REG_UPDATE_2(HDMI_CONTROL,
 580                                         HDMI_DEEP_COLOR_DEPTH, 1,
 581                                         HDMI_DEEP_COLOR_ENABLE, 1);
 582                         }
 583                 break;
 584         case COLOR_DEPTH_121212:
 585                 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 586                         REG_UPDATE_2(HDMI_CONTROL,
 587                                         HDMI_DEEP_COLOR_DEPTH, 2,
 588                                         HDMI_DEEP_COLOR_ENABLE, 0);
 589                 } else {
 590                         REG_UPDATE_2(HDMI_CONTROL,
 591                                         HDMI_DEEP_COLOR_DEPTH, 2,
 592                                         HDMI_DEEP_COLOR_ENABLE, 1);
 593                         }
 594                 break;
 595         case COLOR_DEPTH_161616:
 596                 REG_UPDATE_2(HDMI_CONTROL,
 597                                 HDMI_DEEP_COLOR_DEPTH, 3,
 598                                 HDMI_DEEP_COLOR_ENABLE, 1);
 599                 break;
 600         default:
 601                 break;
 602         }
 603
 604         if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 605                 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
 606                         /* enable HDMI data scrambler
 607                          * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
 608                          * Clock channel frequency is 1/4 of character rate.
 609                          */
 610                         REG_UPDATE_2(HDMI_CONTROL,
 611                                 HDMI_DATA_SCRAMBLE_EN, 1,
 612                                 HDMI_CLOCK_CHANNEL_RATE, 1);
 613                 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
 614
 615                         /* TODO: New feature for DCE11, still need to implement */
 616
 617                         /* enable HDMI data scrambler
 618                          * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
 619                          * Clock channel frequency is the same
 620                          * as character rate
 621                          */
 622                         REG_UPDATE_2(HDMI_CONTROL,
 623                                 HDMI_DATA_SCRAMBLE_EN, 1,
 624                                 HDMI_CLOCK_CHANNEL_RATE, 0);
 625                 }
 626         }
 627
 628         REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
 629                 HDMI_GC_CONT, 1,
 630                 HDMI_GC_SEND, 1,
 631                 HDMI_NULL_SEND, 1);
 632
 633         REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
 634
 635         /* following belongs to audio */
 636         REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
 637
 638         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
 639
 640         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
 641                                 VBI_LINE_0 + 2);
 642
 643         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
 644
 645 }
 646
 647 /* setup stream encoder in dvi mode */
 648 static void dce110_stream_encoder_dvi_set_stream_attribute(
 649         struct stream_encoder *enc,
 650         struct dc_crtc_timing *crtc_timing,
 651         bool is_dual_link)
 652 {
 653         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 654         struct bp_encoder_control cntl = {0};
 655
 656         cntl.action = ENCODER_CONTROL_SETUP;
 657         cntl.engine_id = enc110->base.id;
 658         cntl.signal = is_dual_link ?
 659                         SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
 660         cntl.enable_dp_audio = false;
 661         cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 662         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 663
 664         if (enc110->base.bp->funcs->encoder_control(
 665                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 666                 return;
 667
 668         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 669         ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
 670         dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 671 }
 672
 673 /* setup stream encoder in LVDS mode */
 674 static void dce110_stream_encoder_lvds_set_stream_attribute(
 675         struct stream_encoder *enc,
 676         struct dc_crtc_timing *crtc_timing)
 677 {
 678         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 679         struct bp_encoder_control cntl = {0};
 680
 681         cntl.action = ENCODER_CONTROL_SETUP;
 682         cntl.engine_id = enc110->base.id;
 683         cntl.signal = SIGNAL_TYPE_LVDS;
 684         cntl.enable_dp_audio = false;
 685         cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
 686         cntl.lanes_number = LANE_COUNT_FOUR;
 687
 688         if (enc110->base.bp->funcs->encoder_control(
 689                         enc110->base.bp, &cntl) != BP_RESULT_OK)
 690                 return;
 691
 692         ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
 693 }
 694
 695 static void dce110_stream_encoder_set_throttled_vcp_size(
 696         struct stream_encoder *enc,
 697         struct fixed31_32 avg_time_slots_per_mtp)
 698 {
 699         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 700         uint32_t x = dc_fixpt_floor(
 701                 avg_time_slots_per_mtp);
 702         uint32_t y = dc_fixpt_ceil(
 703                 dc_fixpt_shl(
 704                         dc_fixpt_sub_int(
 705                                 avg_time_slots_per_mtp,
 706                                 x),
 707                         26));
 708
 709         {
 710                 REG_SET_2(DP_MSE_RATE_CNTL, 0,
 711                         DP_MSE_RATE_X, x,
 712                         DP_MSE_RATE_Y, y);
 713         }
 714
 715         /* wait for update to be completed on the link */
 716         /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
 717         /* is reset to 0 (not pending) */
 718         REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
 719                         0,
 720                         10, DP_MST_UPDATE_MAX_RETRY);
 721 }
 722
 723 static void dce110_stream_encoder_update_hdmi_info_packets(
 724         struct stream_encoder *enc,
 725         const struct encoder_info_frame *info_frame)
 726 {
 727         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 728
 729         if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 730                         enc110->se_mask->HDMI_AVI_INFO_SEND) {
 731
 732                 if (info_frame->avi.valid) {
 733                         const uint32_t *content =
 734                                 (const uint32_t *) &info_frame->avi.sb[0];
 735                         /*we need turn on clock before programming AFMT block*/
 736                         if (REG(AFMT_CNTL))
 737                                 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
 738
 739                         REG_WRITE(AFMT_AVI_INFO0, content[0]);
 740
 741                         REG_WRITE(AFMT_AVI_INFO1, content[1]);
 742
 743                         REG_WRITE(AFMT_AVI_INFO2, content[2]);
 744
 745                         REG_WRITE(AFMT_AVI_INFO3, content[3]);
 746
 747                         REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
 748                                                 info_frame->avi.hb1);
 749
 750                         REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 751                                         HDMI_AVI_INFO_SEND, 1,
 752                                         HDMI_AVI_INFO_CONT, 1);
 753
 754                         REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
 755                                                         VBI_LINE_0 + 2);
 756
 757                 } else {
 758                         REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
 759                                 HDMI_AVI_INFO_SEND, 0,
 760                                 HDMI_AVI_INFO_CONT, 0);
 761                 }
 762         }
 763
 764         if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
 765                         enc110->se_mask->HDMI_AVI_INFO_SEND) {
 766                 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
 767                 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
 768                 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
 769                 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
 770         }
 771
 772         if (enc110->se_mask->HDMI_DB_DISABLE) {
 773                 /* for bring up, disable dp double  TODO */
 774                 if (REG(HDMI_DB_CONTROL))
 775                         REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
 776
 777                 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
 778                 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
 779                 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
 780                 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
 781                 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
 782         }
 783 }
 784
 785 static void dce110_stream_encoder_stop_hdmi_info_packets(
 786         struct stream_encoder *enc)
 787 {
 788         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 789
 790         /* stop generic packets 0 & 1 on HDMI */
 791         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
 792                 HDMI_GENERIC1_CONT, 0,
 793                 HDMI_GENERIC1_LINE, 0,
 794                 HDMI_GENERIC1_SEND, 0,
 795                 HDMI_GENERIC0_CONT, 0,
 796                 HDMI_GENERIC0_LINE, 0,
 797                 HDMI_GENERIC0_SEND, 0);
 798
 799         /* stop generic packets 2 & 3 on HDMI */
 800         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
 801                 HDMI_GENERIC0_CONT, 0,
 802                 HDMI_GENERIC0_LINE, 0,
 803                 HDMI_GENERIC0_SEND, 0,
 804                 HDMI_GENERIC1_CONT, 0,
 805                 HDMI_GENERIC1_LINE, 0,
 806                 HDMI_GENERIC1_SEND, 0);
 807
 808         /* stop generic packets 2 & 3 on HDMI */
 809         if (REG(HDMI_GENERIC_PACKET_CONTROL2))
 810                 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
 811                         HDMI_GENERIC0_CONT, 0,
 812                         HDMI_GENERIC0_LINE, 0,
 813                         HDMI_GENERIC0_SEND, 0,
 814                         HDMI_GENERIC1_CONT, 0,
 815                         HDMI_GENERIC1_LINE, 0,
 816                         HDMI_GENERIC1_SEND, 0);
 817
 818         if (REG(HDMI_GENERIC_PACKET_CONTROL3))
 819                 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
 820                         HDMI_GENERIC0_CONT, 0,
 821                         HDMI_GENERIC0_LINE, 0,
 822                         HDMI_GENERIC0_SEND, 0,
 823                         HDMI_GENERIC1_CONT, 0,
 824                         HDMI_GENERIC1_LINE, 0,
 825                         HDMI_GENERIC1_SEND, 0);
 826 }
 827
 828 static void dce110_stream_encoder_update_dp_info_packets(
 829         struct stream_encoder *enc,
 830         const struct encoder_info_frame *info_frame)
 831 {
 832         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 833         uint32_t value = 0;
 834
 835         if (info_frame->vsc.valid)
 836                 dce110_update_generic_info_packet(
 837                                         enc110,
 838                                         0,  /* packetIndex */
 839                                         &info_frame->vsc);
 840
 841         if (info_frame->spd.valid)
 842                 dce110_update_generic_info_packet(
 843                                 enc110,
 844                                 2,  /* packetIndex */
 845                                 &info_frame->spd);
 846
 847         if (info_frame->hdrsmd.valid)
 848                 dce110_update_generic_info_packet(
 849                                 enc110,
 850                                 3,  /* packetIndex */
 851                                 &info_frame->hdrsmd);
 852
 853         /* enable/disable transmission of packet(s).
 854         *  If enabled, packet transmission begins on the next frame
 855         */
 856         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
 857         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
 858         REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
 859
 860         /* This bit is the master enable bit.
 861         * When enabling secondary stream engine,
 862         * this master bit must also be set.
 863         * This register shared with audio info frame.
 864         * Therefore we need to enable master bit
 865         * if at least on of the fields is not 0
 866         */
 867         value = REG_READ(DP_SEC_CNTL);
 868         if (value)
 869                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 870 }
 871
 872 static void dce110_stream_encoder_stop_dp_info_packets(
 873         struct stream_encoder *enc)
 874 {
 875         /* stop generic packets on DP */
 876         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 877         uint32_t value = 0;
 878
 879         if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
 880                 REG_SET_7(DP_SEC_CNTL, 0,
 881                         DP_SEC_GSP0_ENABLE, 0,
 882                         DP_SEC_GSP1_ENABLE, 0,
 883                         DP_SEC_GSP2_ENABLE, 0,
 884                         DP_SEC_GSP3_ENABLE, 0,
 885                         DP_SEC_AVI_ENABLE, 0,
 886                         DP_SEC_MPG_ENABLE, 0,
 887                         DP_SEC_STREAM_ENABLE, 0);
 888         }
 889
 890         /* this register shared with audio info frame.
 891          * therefore we need to keep master enabled
 892          * if at least one of the fields is not 0 */
 893         value = REG_READ(DP_SEC_CNTL);
 894         if (value)
 895                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
 896
 897 }
 898
 899 static void dce110_stream_encoder_dp_blank(
 900         struct dc_link *link,
 901         struct stream_encoder *enc)
 902 {
 903         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 904         uint32_t  reg1 = 0;
 905         uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
 906
 907         /* Note: For CZ, we are changing driver default to disable
 908          * stream deferred to next VBLANK. If results are positive, we
 909          * will make the same change to all DCE versions. There are a
 910          * handful of panels that cannot handle disable stream at
 911          * HBLANK and will result in a white line flash across the
 912          * screen on stream disable. */
 913         REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
 914         if ((reg1 & 0x1) == 0)
 915                 /*stream not enabled*/
 916                 return;
 917         /* Specify the video stream disable point
 918          * (2 = start of the next vertical blank) */
 919         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
 920         /* Larger delay to wait until VBLANK - use max retry of
 921          * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
 922          * a little more because we may not trust delay accuracy.
 923          */
 924         max_retries = DP_BLANK_MAX_RETRY * 150;
 925
 926         /* disable DP stream */
 927         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
 928
 929         /* the encoder stops sending the video stream
 930          * at the start of the vertical blanking.
 931          * Poll for DP_VID_STREAM_STATUS == 0
 932          */
 933
 934         REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
 935                         0,
 936                         10, max_retries);
 937
 938         /* Tell the DP encoder to ignore timing from CRTC, must be done after
 939          * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
 940          * complete, stream status will be stuck in video stream enabled state,
 941          * i.e. DP_VID_STREAM_STATUS stuck at 1.
 942          */
 943
 944         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
 945 }
 946
 947 /* output video stream to link encoder */
 948 static void dce110_stream_encoder_dp_unblank(
 949         struct dc_link *link,
 950         struct stream_encoder *enc,
 951         const struct encoder_unblank_param *param)
 952 {
 953         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 954
 955         if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
 956                 uint32_t n_vid = 0x8000;
 957                 uint32_t m_vid;
 958
 959                 /* M / N = Fstream / Flink
 960                 * m_vid / n_vid = pixel rate / link rate
 961                 */
 962
 963                 uint64_t m_vid_l = n_vid;
 964
 965                 m_vid_l *= param->timing.pix_clk_100hz / 10;
 966                 m_vid_l = div_u64(m_vid_l,
 967                         param->link_settings.link_rate
 968                                 * LINK_RATE_REF_FREQ_IN_KHZ);
 969
 970                 m_vid = (uint32_t) m_vid_l;
 971
 972                 /* enable auto measurement */
 973
 974                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
 975
 976                 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
 977                  * therefore program initial value for Mvid and Nvid
 978                  */
 979
 980                 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
 981
 982                 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
 983
 984                 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
 985         }
 986
 987         /* set DIG_START to 0x1 to resync FIFO */
 988
 989         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
 990
 991         /* switch DP encoder to CRTC data */
 992
 993         REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
 994
 995         /* wait 100us for DIG/DP logic to prime
 996         * (i.e. a few video lines)
 997         */
 998         udelay(100);
 999
1000         /* the hardware would start sending video at the start of the next DP
1001         * frame (i.e. rising edge of the vblank).
1002         * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1003         * register has no effect on enable transition! HW always guarantees
1004         * VID_STREAM enable at start of next frame, and this is not
1005         * programmable
1006         */
1007
1008         REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1009 }
1010
1011 static void dce110_stream_encoder_set_avmute(
1012         struct stream_encoder *enc,
1013         bool enable)
1014 {
1015         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1016         unsigned int value = enable ? 1 : 0;
1017
1018         REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1019 }
1020
1021
1022 static void dce110_reset_hdmi_stream_attribute(
1023         struct stream_encoder *enc)
1024 {
1025         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1026
1027         if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
1028                 REG_UPDATE_5(HDMI_CONTROL,
1029                         HDMI_PACKET_GEN_VERSION, 1,
1030                         HDMI_KEEPOUT_MODE, 1,
1031                         HDMI_DEEP_COLOR_ENABLE, 0,
1032                         HDMI_DATA_SCRAMBLE_EN, 0,
1033                         HDMI_CLOCK_CHANNEL_RATE, 0);
1034         else
1035                 REG_UPDATE_3(HDMI_CONTROL,
1036                         HDMI_PACKET_GEN_VERSION, 1,
1037                         HDMI_KEEPOUT_MODE, 1,
1038                         HDMI_DEEP_COLOR_ENABLE, 0);
1039 }
1040
1041 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1042 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1043
1044 #include "include/audio_types.h"
1045
1046
1047 /* 25.2MHz/1.001*/
1048 /* 25.2MHz/1.001*/
1049 /* 25.2MHz*/
1050 /* 27MHz */
1051 /* 27MHz*1.001*/
1052 /* 27MHz*1.001*/
1053 /* 54MHz*/
1054 /* 54MHz*1.001*/
1055 /* 74.25MHz/1.001*/
1056 /* 74.25MHz*/
1057 /* 148.5MHz/1.001*/
1058 /* 148.5MHz*/
1059
1060 static const struct audio_clock_info audio_clock_info_table[16] = {
1061         {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1062         {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1063         {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1064         {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1065         {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1066         {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1067         {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1068         {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1069         {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1070         {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1071         {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1072         {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1073         {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1074         {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1075         {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1076         {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1077 };
1078
1079 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1080         {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1081         {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1082         {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1083         {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1084         {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1085         {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1086         {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1087         {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1088         {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1089         {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1090         {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1091         {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1092         {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1093         {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1094 };
1095
1096 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1097         {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1098         {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1099         {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1100         {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1101         {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1102         {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1103         {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1104         {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1105         {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1106         {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1107         {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1108         {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1109         {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1110         {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1111
1112
1113 };
1114
1115 static union audio_cea_channels speakers_to_channels(
1116         struct audio_speaker_flags speaker_flags)
1117 {
1118         union audio_cea_channels cea_channels = {0};
1119
1120         /* these are one to one */
1121         cea_channels.channels.FL = speaker_flags.FL_FR;
1122         cea_channels.channels.FR = speaker_flags.FL_FR;
1123         cea_channels.channels.LFE = speaker_flags.LFE;
1124         cea_channels.channels.FC = speaker_flags.FC;
1125
1126         /* if Rear Left and Right exist move RC speaker to channel 7
1127          * otherwise to channel 5
1128          */
1129         if (speaker_flags.RL_RR) {
1130                 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1131                 cea_channels.channels.RR = speaker_flags.RL_RR;
1132                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1133         } else {
1134                 cea_channels.channels.RL_RC = speaker_flags.RC;
1135         }
1136
1137         /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1138         if (speaker_flags.FLC_FRC) {
1139                 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1140                 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1141         } else {
1142                 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1143                 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1144         }
1145
1146         return cea_channels;
1147 }
1148
1149 static uint32_t calc_max_audio_packets_per_line(
1150         const struct audio_crtc_info *crtc_info)
1151 {
1152         uint32_t max_packets_per_line;
1153
1154         max_packets_per_line =
1155                 crtc_info->h_total - crtc_info->h_active;
1156
1157         if (crtc_info->pixel_repetition)
1158                 max_packets_per_line *= crtc_info->pixel_repetition;
1159
1160         /* for other hdmi features */
1161         max_packets_per_line -= 58;
1162         /* for Control Period */
1163         max_packets_per_line -= 16;
1164         /* Number of Audio Packets per Line */
1165         max_packets_per_line /= 32;
1166
1167         return max_packets_per_line;
1168 }
1169
1170 static void get_audio_clock_info(
1171         enum dc_color_depth color_depth,
1172         uint32_t crtc_pixel_clock_100Hz,
1173         uint32_t actual_pixel_clock_100Hz,
1174         struct audio_clock_info *audio_clock_info)
1175 {
1176         const struct audio_clock_info *clock_info;
1177         uint32_t index;
1178         uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1179         uint32_t audio_array_size;
1180
1181         switch (color_depth) {
1182         case COLOR_DEPTH_161616:
1183                 clock_info = audio_clock_info_table_48bpc;
1184                 audio_array_size = ARRAY_SIZE(
1185                                 audio_clock_info_table_48bpc);
1186                 break;
1187         case COLOR_DEPTH_121212:
1188                 clock_info = audio_clock_info_table_36bpc;
1189                 audio_array_size = ARRAY_SIZE(
1190                                 audio_clock_info_table_36bpc);
1191                 break;
1192         default:
1193                 clock_info = audio_clock_info_table;
1194                 audio_array_size = ARRAY_SIZE(
1195                                 audio_clock_info_table);
1196                 break;
1197         }
1198
1199         if (clock_info != NULL) {
1200                 /* search for exact pixel clock in table */
1201                 for (index = 0; index < audio_array_size; index++) {
1202                         if (clock_info[index].pixel_clock_in_10khz >
1203                                 crtc_pixel_clock_in_10khz)
1204                                 break;  /* not match */
1205                         else if (clock_info[index].pixel_clock_in_10khz ==
1206                                         crtc_pixel_clock_in_10khz) {
1207                                 /* match found */
1208                                 *audio_clock_info = clock_info[index];
1209                                 return;
1210                         }
1211                 }
1212         }
1213
1214         /* not found */
1215         if (actual_pixel_clock_100Hz == 0)
1216                 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1217
1218         /* See HDMI spec  the table entry under
1219          *  pixel clock of "Other". */
1220         audio_clock_info->pixel_clock_in_10khz =
1221                         actual_pixel_clock_100Hz / 100;
1222         audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1223         audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1224         audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1225
1226         audio_clock_info->n_32khz = 4096;
1227         audio_clock_info->n_44khz = 6272;
1228         audio_clock_info->n_48khz = 6144;
1229 }
1230
1231 static void dce110_se_audio_setup(
1232         struct stream_encoder *enc,
1233         unsigned int az_inst,
1234         struct audio_info *audio_info)
1235 {
1236         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1237
1238         uint32_t channels = 0;
1239
1240         ASSERT(audio_info);
1241         if (audio_info == NULL)
1242                 /* This should not happen.it does so we don't get BSOD*/
1243                 return;
1244
1245         channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1246
1247         /* setup the audio stream source select (audio -> dig mapping) */
1248         REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1249
1250         /* Channel allocation */
1251         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1252 }
1253
1254 static void dce110_se_setup_hdmi_audio(
1255         struct stream_encoder *enc,
1256         const struct audio_crtc_info *crtc_info)
1257 {
1258         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1259
1260         struct audio_clock_info audio_clock_info = {0};
1261         uint32_t max_packets_per_line;
1262
1263         /* For now still do calculation, although this field is ignored when
1264         above HDMI_PACKET_GEN_VERSION set to 1 */
1265         max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1266
1267         /* HDMI_AUDIO_PACKET_CONTROL */
1268         REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1269                         HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1270                         HDMI_AUDIO_DELAY_EN, 1);
1271
1272         /* AFMT_AUDIO_PACKET_CONTROL */
1273         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1274
1275         /* AFMT_AUDIO_PACKET_CONTROL2 */
1276         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1277                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1278                         AFMT_60958_OSF_OVRD, 0);
1279
1280         /* HDMI_ACR_PACKET_CONTROL */
1281         REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1282                         HDMI_ACR_AUTO_SEND, 1,
1283                         HDMI_ACR_SOURCE, 0,
1284                         HDMI_ACR_AUDIO_PRIORITY, 0);
1285
1286         /* Program audio clock sample/regeneration parameters */
1287         get_audio_clock_info(crtc_info->color_depth,
1288                              crtc_info->requested_pixel_clock_100Hz,
1289                              crtc_info->calculated_pixel_clock_100Hz,
1290                              &audio_clock_info);
1291         DC_LOG_HW_AUDIO(
1292                         "\n%s:Input::requested_pixel_clock_100Hz = %d"  \
1293                         "calculated_pixel_clock_100Hz = %d \n", __func__,       \
1294                         crtc_info->requested_pixel_clock_100Hz,         \
1295                         crtc_info->calculated_pixel_clock_100Hz);
1296
1297         /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1298         REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1299
1300         /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1301         REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1302
1303         /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1304         REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1305
1306         /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1307         REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1308
1309         /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1310         REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1311
1312         /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1313         REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1314
1315         /* Video driver cannot know in advance which sample rate will
1316            be used by HD Audio driver
1317            HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1318            programmed below in interruppt callback */
1319
1320         /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1321         AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1322         REG_UPDATE_2(AFMT_60958_0,
1323                         AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1324                         AFMT_60958_CS_CLOCK_ACCURACY, 0);
1325
1326         /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1327         REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1328
1329         /*AFMT_60958_2 now keep this settings until
1330          *  Programming guide comes out*/
1331         REG_UPDATE_6(AFMT_60958_2,
1332                         AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1333                         AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1334                         AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1335                         AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1336                         AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1337                         AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1338 }
1339
1340 static void dce110_se_setup_dp_audio(
1341         struct stream_encoder *enc)
1342 {
1343         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1344
1345         /* --- DP Audio packet configurations --- */
1346
1347         /* ATP Configuration */
1348         REG_SET(DP_SEC_AUD_N, 0,
1349                         DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1350
1351         /* Async/auto-calc timestamp mode */
1352         REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1353                         DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1354
1355         /* --- The following are the registers
1356          *  copied from the SetupHDMI --- */
1357
1358         /* AFMT_AUDIO_PACKET_CONTROL */
1359         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1360
1361         /* AFMT_AUDIO_PACKET_CONTROL2 */
1362         /* Program the ATP and AIP next */
1363         REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1364                         AFMT_AUDIO_LAYOUT_OVRD, 0,
1365                         AFMT_60958_OSF_OVRD, 0);
1366
1367         /* AFMT_INFOFRAME_CONTROL0 */
1368         REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1369
1370         /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1371         REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1372 }
1373
1374 static void dce110_se_enable_audio_clock(
1375         struct stream_encoder *enc,
1376         bool enable)
1377 {
1378         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1379
1380         if (REG(AFMT_CNTL) == 0)
1381                 return;   /* DCE8/10 does not have this register */
1382
1383         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1384
1385         /* wait for AFMT clock to turn on,
1386          * expectation: this should complete in 1-2 reads
1387          *
1388          * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1389          *
1390          * TODO: wait for clock_on does not work well. May need HW
1391          * program sequence. But audio seems work normally even without wait
1392          * for clock_on status change
1393          */
1394 }
1395
1396 static void dce110_se_enable_dp_audio(
1397         struct stream_encoder *enc)
1398 {
1399         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1400
1401         /* Enable Audio packets */
1402         REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1403
1404         /* Program the ATP and AIP next */
1405         REG_UPDATE_2(DP_SEC_CNTL,
1406                         DP_SEC_ATP_ENABLE, 1,
1407                         DP_SEC_AIP_ENABLE, 1);
1408
1409         /* Program STREAM_ENABLE after all the other enables. */
1410         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1411 }
1412
1413 static void dce110_se_disable_dp_audio(
1414         struct stream_encoder *enc)
1415 {
1416         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1417         uint32_t value = 0;
1418
1419         /* Disable Audio packets */
1420         REG_UPDATE_5(DP_SEC_CNTL,
1421                         DP_SEC_ASP_ENABLE, 0,
1422                         DP_SEC_ATP_ENABLE, 0,
1423                         DP_SEC_AIP_ENABLE, 0,
1424                         DP_SEC_ACM_ENABLE, 0,
1425                         DP_SEC_STREAM_ENABLE, 0);
1426
1427         /* This register shared with encoder info frame. Therefore we need to
1428         keep master enabled if at least on of the fields is not 0 */
1429         value = REG_READ(DP_SEC_CNTL);
1430         if (value != 0)
1431                 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1432
1433 }
1434
1435 void dce110_se_audio_mute_control(
1436         struct stream_encoder *enc,
1437         bool mute)
1438 {
1439         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1440
1441         REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1442 }
1443
1444 void dce110_se_dp_audio_setup(
1445         struct stream_encoder *enc,
1446         unsigned int az_inst,
1447         struct audio_info *info)
1448 {
1449         dce110_se_audio_setup(enc, az_inst, info);
1450 }
1451
1452 void dce110_se_dp_audio_enable(
1453         struct stream_encoder *enc)
1454 {
1455         dce110_se_enable_audio_clock(enc, true);
1456         dce110_se_setup_dp_audio(enc);
1457         dce110_se_enable_dp_audio(enc);
1458 }
1459
1460 void dce110_se_dp_audio_disable(
1461         struct stream_encoder *enc)
1462 {
1463         dce110_se_disable_dp_audio(enc);
1464         dce110_se_enable_audio_clock(enc, false);
1465 }
1466
1467 void dce110_se_hdmi_audio_setup(
1468         struct stream_encoder *enc,
1469         unsigned int az_inst,
1470         struct audio_info *info,
1471         struct audio_crtc_info *audio_crtc_info)
1472 {
1473         dce110_se_enable_audio_clock(enc, true);
1474         dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1475         dce110_se_audio_setup(enc, az_inst, info);
1476 }
1477
1478 void dce110_se_hdmi_audio_disable(
1479         struct stream_encoder *enc)
1480 {
1481         dce110_se_enable_audio_clock(enc, false);
1482 }
1483
1484
1485 static void setup_stereo_sync(
1486         struct stream_encoder *enc,
1487         int tg_inst, bool enable)
1488 {
1489         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1490         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1491         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1492 }
1493
1494 static void dig_connect_to_otg(
1495         struct stream_encoder *enc,
1496         int tg_inst)
1497 {
1498         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1499
1500         REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1501 }
1502
1503 static unsigned int dig_source_otg(
1504         struct stream_encoder *enc)
1505 {
1506         uint32_t tg_inst = 0;
1507         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1508
1509         REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1510
1511         return tg_inst;
1512 }
1513
1514 static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1515         .dp_set_stream_attribute =
1516                 dce110_stream_encoder_dp_set_stream_attribute,
1517         .hdmi_set_stream_attribute =
1518                 dce110_stream_encoder_hdmi_set_stream_attribute,
1519         .dvi_set_stream_attribute =
1520                 dce110_stream_encoder_dvi_set_stream_attribute,
1521         .lvds_set_stream_attribute =
1522                 dce110_stream_encoder_lvds_set_stream_attribute,
1523         .set_throttled_vcp_size =
1524                 dce110_stream_encoder_set_throttled_vcp_size,
1525         .update_hdmi_info_packets =
1526                 dce110_stream_encoder_update_hdmi_info_packets,
1527         .stop_hdmi_info_packets =
1528                 dce110_stream_encoder_stop_hdmi_info_packets,
1529         .update_dp_info_packets =
1530                 dce110_stream_encoder_update_dp_info_packets,
1531         .stop_dp_info_packets =
1532                 dce110_stream_encoder_stop_dp_info_packets,
1533         .dp_blank =
1534                 dce110_stream_encoder_dp_blank,
1535         .dp_unblank =
1536                 dce110_stream_encoder_dp_unblank,
1537         .audio_mute_control = dce110_se_audio_mute_control,
1538
1539         .dp_audio_setup = dce110_se_dp_audio_setup,
1540         .dp_audio_enable = dce110_se_dp_audio_enable,
1541         .dp_audio_disable = dce110_se_dp_audio_disable,
1542
1543         .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1544         .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1545         .setup_stereo_sync  = setup_stereo_sync,
1546         .set_avmute = dce110_stream_encoder_set_avmute,
1547         .dig_connect_to_otg  = dig_connect_to_otg,
1548         .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
1549         .dig_source_otg = dig_source_otg,
1550 };
1551
1552 void dce110_stream_encoder_construct(
1553         struct dce110_stream_encoder *enc110,
1554         struct dc_context *ctx,
1555         struct dc_bios *bp,
1556         enum engine_id eng_id,
1557         const struct dce110_stream_enc_registers *regs,
1558         const struct dce_stream_encoder_shift *se_shift,
1559         const struct dce_stream_encoder_mask *se_mask)
1560 {
1561         enc110->base.funcs = &dce110_str_enc_funcs;
1562         enc110->base.ctx = ctx;
1563         enc110->base.id = eng_id;
1564         enc110->base.bp = bp;
1565         enc110->regs = regs;
1566         enc110->se_shift = se_shift;
1567         enc110->se_mask = se_mask;
1568 }