drivers/gpu/drm/amd/amdgpu/vega20_ih.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/pci.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_ih.h"
  28 #include "soc15.h"
  29
  30 #include "oss/osssys_4_2_0_offset.h"
  31 #include "oss/osssys_4_2_0_sh_mask.h"
  32
  33 #include "soc15_common.h"
  34 #include "vega20_ih.h"
  35
  36 #define MAX_REARM_RETRY 10
  37
  38 #define mmIH_CHICKEN_ALDEBARAN                  0x18d
  39 #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX         0
  40
  41 #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN               0x00ea
  42 #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX      0
  43 #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT  0x10
  44 #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK    0x00010000L
  45
  46 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
  47
  48 /**
  49  * vega20_ih_init_register_offset - Initialize register offset for ih rings
  50  *
  51  * @adev: amdgpu_device pointer
  52  *
  53  * Initialize register offset ih rings (VEGA20).
  54  */
  55 static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
  56 {
  57         struct amdgpu_ih_regs *ih_regs;
  58
  59         if (adev->irq.ih.ring_size) {
  60                 ih_regs = &adev->irq.ih.ih_regs;
  61                 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
  62                 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
  63                 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
  64                 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
  65                 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
  66                 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
  67                 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
  68                 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
  69                 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
  70         }
  71
  72         if (adev->irq.ih1.ring_size) {
  73                 ih_regs = &adev->irq.ih1.ih_regs;
  74                 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
  75                 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
  76                 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
  77                 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
  78                 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
  79                 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
  80                 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
  81         }
  82
  83         if (adev->irq.ih2.ring_size) {
  84                 ih_regs = &adev->irq.ih2.ih_regs;
  85                 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
  86                 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
  87                 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
  88                 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
  89                 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
  90                 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
  91                 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
  92         }
  93 }
  94
  95 /**
  96  * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
  97  *
  98  * @adev: amdgpu_device pointer
  99  * @ih: amdgpu_ih_ring pointer
 100  * @enable: true - enable the interrupts, false - disable the interrupts
 101  *
 102  * Toggle the interrupt ring buffer (VEGA20)
 103  */
 104 static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
 105                                             struct amdgpu_ih_ring *ih,
 106                                             bool enable)
 107 {
 108         struct amdgpu_ih_regs *ih_regs;
 109         uint32_t tmp;
 110
 111         ih_regs = &ih->ih_regs;
 112
 113         tmp = RREG32(ih_regs->ih_rb_cntl);
 114         tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
 115         tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
 116
 117         if (enable) {
 118                 /* Unset the CLEAR_OVERFLOW bit to make sure the next step
 119                  * is switching the bit from 0 to 1
 120                  */
 121                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
 122                 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
 123                         if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
 124                                 return -ETIMEDOUT;
 125                 } else {
 126                         WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
 127                 }
 128
 129                 /* Clear RB_OVERFLOW bit */
 130                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
 131                 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
 132                         if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
 133                                 return -ETIMEDOUT;
 134                 } else {
 135                         WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
 136                 }
 137
 138                 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
 139                  * can be detected.
 140                  */
 141                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
 142         }
 143
 144         /* enable_intr field is only valid in ring0 */
 145         if (ih == &adev->irq.ih)
 146                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
 147         if (amdgpu_sriov_vf(adev)) {
 148                 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
 149                         dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
 150                         return -ETIMEDOUT;
 151                 }
 152         } else {
 153                 WREG32(ih_regs->ih_rb_cntl, tmp);
 154         }
 155
 156         if (enable) {
 157                 ih->enabled = true;
 158         } else {
 159                 /* set rptr, wptr to 0 */
 160                 WREG32(ih_regs->ih_rb_rptr, 0);
 161                 WREG32(ih_regs->ih_rb_wptr, 0);
 162                 ih->enabled = false;
 163                 ih->rptr = 0;
 164         }
 165
 166         return 0;
 167 }
 168
 169 /**
 170  * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
 171  *
 172  * @adev: amdgpu_device pointer
 173  * @enable: enable or disable interrupt ring buffers
 174  *
 175  * Toggle all the available interrupt ring buffers (VEGA20).
 176  */
 177 static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
 178 {
 179         struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
 180         int i;
 181         int r;
 182
 183         for (i = 0; i < ARRAY_SIZE(ih); i++) {
 184                 if (ih[i]->ring_size) {
 185                         r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
 186                         if (r)
 187                                 return r;
 188                 }
 189         }
 190
 191         return 0;
 192 }
 193
 194 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
 195 {
 196         int rb_bufsz = order_base_2(ih->ring_size / 4);
 197
 198         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
 199                                    MC_SPACE, ih->use_bus_addr ? 1 : 4);
 200         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
 201                                    WPTR_OVERFLOW_CLEAR, 1);
 202         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
 203                                    WPTR_OVERFLOW_ENABLE, 1);
 204         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
 205         /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
 206          * value is written to memory
 207          */
 208         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
 209                                    WPTR_WRITEBACK_ENABLE, 1);
 210         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
 211         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
 212         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
 213
 214         return ih_rb_cntl;
 215 }
 216
 217 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
 218 {
 219         u32 ih_doorbell_rtpr = 0;
 220
 221         if (ih->use_doorbell) {
 222                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
 223                                                  IH_DOORBELL_RPTR, OFFSET,
 224                                                  ih->doorbell_index);
 225                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
 226                                                  IH_DOORBELL_RPTR,
 227                                                  ENABLE, 1);
 228         } else {
 229                 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
 230                                                  IH_DOORBELL_RPTR,
 231                                                  ENABLE, 0);
 232         }
 233         return ih_doorbell_rtpr;
 234 }
 235
 236 /**
 237  * vega20_ih_enable_ring - enable an ih ring buffer
 238  *
 239  * @adev: amdgpu_device pointer
 240  * @ih: amdgpu_ih_ring pointer
 241  *
 242  * Enable an ih ring buffer (VEGA20)
 243  */
 244 static int vega20_ih_enable_ring(struct amdgpu_device *adev,
 245                                  struct amdgpu_ih_ring *ih)
 246 {
 247         struct amdgpu_ih_regs *ih_regs;
 248         uint32_t tmp;
 249
 250         ih_regs = &ih->ih_regs;
 251
 252         /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
 253         WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
 254         WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
 255
 256         tmp = RREG32(ih_regs->ih_rb_cntl);
 257         tmp = vega20_ih_rb_cntl(ih, tmp);
 258         if (ih == &adev->irq.ih)
 259                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
 260         if (ih == &adev->irq.ih1)
 261                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
 262         if (amdgpu_sriov_vf(adev)) {
 263                 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
 264                         dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
 265                         return -ETIMEDOUT;
 266                 }
 267         } else {
 268                 WREG32(ih_regs->ih_rb_cntl, tmp);
 269         }
 270
 271         if (ih == &adev->irq.ih) {
 272                 /* set the ih ring 0 writeback address whether it's enabled or not */
 273                 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
 274                 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
 275         }
 276
 277         /* set rptr, wptr to 0 */
 278         WREG32(ih_regs->ih_rb_wptr, 0);
 279         WREG32(ih_regs->ih_rb_rptr, 0);
 280
 281         WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
 282
 283         return 0;
 284 }
 285
 286 static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)
 287 {
 288         u32 val = 0;
 289
 290         val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);
 291         val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);
 292
 293         return val;
 294 }
 295
 296 /**
 297  * vega20_ih_irq_init - init and enable the interrupt ring
 298  *
 299  * @adev: amdgpu_device pointer
 300  *
 301  * Allocate a ring buffer for the interrupt controller,
 302  * enable the RLC, disable interrupts, enable the IH
 303  * ring buffer and enable it (VI).
 304  * Called at device load and reume.
 305  * Returns 0 for success, errors for failure.
 306  */
 307 static int vega20_ih_irq_init(struct amdgpu_device *adev)
 308 {
 309         struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
 310         u32 ih_chicken;
 311         int ret;
 312         int i;
 313
 314         /* disable irqs */
 315         ret = vega20_ih_toggle_interrupts(adev, false);
 316         if (ret)
 317                 return ret;
 318
 319         adev->nbio.funcs->ih_control(adev);
 320
 321         if (!amdgpu_sriov_vf(adev)) {
 322                 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 2, 1)) &&
 323                     adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 324                         ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
 325                         if (adev->irq.ih.use_bus_addr) {
 326                                 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
 327                                                            MC_SPACE_GPA_ENABLE, 1);
 328                         }
 329                         WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
 330                 }
 331
 332                 /* psp firmware won't program IH_CHICKEN for aldebaran
 333                  * driver needs to program it properly according to
 334                  * MC_SPACE type in IH_RB_CNTL */
 335                 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0)) ||
 336                     (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)) ||
 337                     (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))) {
 338                         ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
 339                         if (adev->irq.ih.use_bus_addr) {
 340                                 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
 341                                                            MC_SPACE_GPA_ENABLE, 1);
 342                         }
 343                         WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken);
 344                 }
 345         }
 346
 347         for (i = 0; i < ARRAY_SIZE(ih); i++) {
 348                 if (ih[i]->ring_size) {
 349                         ret = vega20_ih_enable_ring(adev, ih[i]);
 350                         if (ret)
 351                                 return ret;
 352                 }
 353         }
 354
 355         if (!amdgpu_sriov_vf(adev))
 356                 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
 357                                                     adev->irq.ih.doorbell_index);
 358
 359         pci_set_master(adev->pdev);
 360
 361         /* Allocate the doorbell for IH Retry CAM */
 362         adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;
 363         WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM,
 364                 vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index));
 365
 366         /* Enable IH Retry CAM */
 367         if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0) ||
 368             amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2) ||
 369             amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 4) ||
 370             amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))
 371                 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,
 372                                ENABLE, 1);
 373         else
 374                 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);
 375
 376         adev->irq.retry_cam_enabled = true;
 377
 378         /* enable interrupts */
 379         ret = vega20_ih_toggle_interrupts(adev, true);
 380         if (ret)
 381                 return ret;
 382
 383         if (adev->irq.ih_soft.ring_size)
 384                 adev->irq.ih_soft.enabled = true;
 385
 386         return 0;
 387 }
 388
 389 /**
 390  * vega20_ih_irq_disable - disable interrupts
 391  *
 392  * @adev: amdgpu_device pointer
 393  *
 394  * Disable interrupts on the hw (VEGA20).
 395  */
 396 static void vega20_ih_irq_disable(struct amdgpu_device *adev)
 397 {
 398         vega20_ih_toggle_interrupts(adev, false);
 399
 400         /* Wait and acknowledge irq */
 401         mdelay(1);
 402 }
 403
 404 /**
 405  * vega20_ih_get_wptr - get the IH ring buffer wptr
 406  *
 407  * @adev: amdgpu_device pointer
 408  * @ih: amdgpu_ih_ring pointer
 409  *
 410  * Get the IH ring buffer wptr from either the register
 411  * or the writeback memory buffer (VEGA20).  Also check for
 412  * ring buffer overflow and deal with it.
 413  * Returns the value of the wptr.
 414  */
 415 static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
 416                               struct amdgpu_ih_ring *ih)
 417 {
 418         u32 wptr, tmp;
 419         struct amdgpu_ih_regs *ih_regs;
 420
 421         if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
 422                 /* Only ring0 supports writeback. On other rings fall back
 423                  * to register-based code with overflow checking below.
 424                  * ih_soft ring doesn't have any backing hardware registers,
 425                  * update wptr and return.
 426                  */
 427                 wptr = le32_to_cpu(*ih->wptr_cpu);
 428
 429                 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
 430                         goto out;
 431         }
 432
 433         ih_regs = &ih->ih_regs;
 434
 435         /* Double check that the overflow wasn't already cleared. */
 436         wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
 437         if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
 438                 goto out;
 439
 440         wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
 441
 442         /* When a ring buffer overflow happen start parsing interrupt
 443          * from the last not overwritten vector (wptr + 32). Hopefully
 444          * this should allow us to catchup.
 445          */
 446         tmp = (wptr + 32) & ih->ptr_mask;
 447         dev_warn_ratelimited(adev->dev, "%s ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
 448                              amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp);
 449         ih->rptr = tmp;
 450
 451         tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
 452         tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
 453         WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
 454
 455         /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
 456          * can be detected.
 457          */
 458         tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
 459         WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
 460
 461 out:
 462         return (wptr & ih->ptr_mask);
 463 }
 464
 465 /**
 466  * vega20_ih_irq_rearm - rearm IRQ if lost
 467  *
 468  * @adev: amdgpu_device pointer
 469  * @ih: amdgpu_ih_ring pointer
 470  *
 471  */
 472 static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
 473                                struct amdgpu_ih_ring *ih)
 474 {
 475         uint32_t v = 0;
 476         uint32_t i = 0;
 477         struct amdgpu_ih_regs *ih_regs;
 478
 479         ih_regs = &ih->ih_regs;
 480
 481         /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
 482         for (i = 0; i < MAX_REARM_RETRY; i++) {
 483                 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
 484                 if ((v < ih->ring_size) && (v != ih->rptr))
 485                         WDOORBELL32(ih->doorbell_index, ih->rptr);
 486                 else
 487                         break;
 488         }
 489 }
 490
 491 /**
 492  * vega20_ih_set_rptr - set the IH ring buffer rptr
 493  *
 494  * @adev: amdgpu_device pointer
 495  * @ih: amdgpu_ih_ring pointer
 496  *
 497  * Set the IH ring buffer rptr.
 498  */
 499 static void vega20_ih_set_rptr(struct amdgpu_device *adev,
 500                                struct amdgpu_ih_ring *ih)
 501 {
 502         struct amdgpu_ih_regs *ih_regs;
 503
 504         if (ih == &adev->irq.ih_soft)
 505                 return;
 506
 507         if (ih->use_doorbell) {
 508                 /* XXX check if swapping is necessary on BE */
 509                 *ih->rptr_cpu = ih->rptr;
 510                 WDOORBELL32(ih->doorbell_index, ih->rptr);
 511
 512                 if (amdgpu_sriov_vf(adev))
 513                         vega20_ih_irq_rearm(adev, ih);
 514         } else {
 515                 ih_regs = &ih->ih_regs;
 516                 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
 517         }
 518 }
 519
 520 /**
 521  * vega20_ih_self_irq - dispatch work for ring 1 and 2
 522  *
 523  * @adev: amdgpu_device pointer
 524  * @source: irq source
 525  * @entry: IV with WPTR update
 526  *
 527  * Update the WPTR from the IV and schedule work to handle the entries.
 528  */
 529 static int vega20_ih_self_irq(struct amdgpu_device *adev,
 530                               struct amdgpu_irq_src *source,
 531                               struct amdgpu_iv_entry *entry)
 532 {
 533         switch (entry->ring_id) {
 534         case 1:
 535                 schedule_work(&adev->irq.ih1_work);
 536                 break;
 537         case 2:
 538                 schedule_work(&adev->irq.ih2_work);
 539                 break;
 540         default:
 541                 break;
 542         }
 543         return 0;
 544 }
 545
 546 static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
 547         .process = vega20_ih_self_irq,
 548 };
 549
 550 static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
 551 {
 552         adev->irq.self_irq.num_types = 0;
 553         adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
 554 }
 555
 556 static int vega20_ih_early_init(struct amdgpu_ip_block *ip_block)
 557 {
 558         struct amdgpu_device *adev = ip_block->adev;
 559
 560         vega20_ih_set_interrupt_funcs(adev);
 561         vega20_ih_set_self_irq_funcs(adev);
 562         return 0;
 563 }
 564
 565 static int vega20_ih_sw_init(struct amdgpu_ip_block *ip_block)
 566 {
 567         struct amdgpu_device *adev = ip_block->adev;
 568         bool use_bus_addr = true;
 569         int r;
 570
 571         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
 572                               &adev->irq.self_irq);
 573         if (r)
 574                 return r;
 575
 576         if ((adev->flags & AMD_IS_APU) &&
 577             (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)))
 578                 use_bus_addr = false;
 579
 580         r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
 581         if (r)
 582                 return r;
 583
 584         adev->irq.ih.use_doorbell = true;
 585         adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 586
 587         r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr);
 588         if (r)
 589                 return r;
 590
 591         adev->irq.ih1.use_doorbell = true;
 592         adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
 593
 594         if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2) &&
 595             amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 5)) {
 596                 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
 597                 if (r)
 598                         return r;
 599
 600                 adev->irq.ih2.use_doorbell = true;
 601                 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
 602         }
 603
 604         /* initialize ih control registers offset */
 605         vega20_ih_init_register_offset(adev);
 606
 607         r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);
 608         if (r)
 609                 return r;
 610
 611         r = amdgpu_irq_init(adev);
 612
 613         return r;
 614 }
 615
 616 static int vega20_ih_sw_fini(struct amdgpu_ip_block *ip_block)
 617 {
 618         struct amdgpu_device *adev = ip_block->adev;
 619
 620         amdgpu_irq_fini_sw(adev);
 621
 622         return 0;
 623 }
 624
 625 static int vega20_ih_hw_init(struct amdgpu_ip_block *ip_block)
 626 {
 627         int r;
 628         struct amdgpu_device *adev = ip_block->adev;
 629
 630         r = vega20_ih_irq_init(adev);
 631         if (r)
 632                 return r;
 633
 634         return 0;
 635 }
 636
 637 static int vega20_ih_hw_fini(struct amdgpu_ip_block *ip_block)
 638 {
 639         vega20_ih_irq_disable(ip_block->adev);
 640
 641         return 0;
 642 }
 643
 644 static int vega20_ih_suspend(struct amdgpu_ip_block *ip_block)
 645 {
 646         return vega20_ih_hw_fini(ip_block);
 647 }
 648
 649 static int vega20_ih_resume(struct amdgpu_ip_block *ip_block)
 650 {
 651         return vega20_ih_hw_init(ip_block);
 652 }
 653
 654 static bool vega20_ih_is_idle(void *handle)
 655 {
 656         /* todo */
 657         return true;
 658 }
 659
 660 static int vega20_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
 661 {
 662         /* todo */
 663         return -ETIMEDOUT;
 664 }
 665
 666 static int vega20_ih_soft_reset(struct amdgpu_ip_block *ip_block)
 667 {
 668         /* todo */
 669
 670         return 0;
 671 }
 672
 673 static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
 674                                                bool enable)
 675 {
 676         uint32_t data, def, field_val;
 677
 678         if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
 679                 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
 680                 field_val = enable ? 0 : 1;
 681                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 682                                      IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
 683                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 684                                      IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
 685                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 686                                      DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
 687                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 688                                      OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
 689                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 690                                      LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
 691                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 692                                      DYN_CLK_SOFT_OVERRIDE, field_val);
 693                 data = REG_SET_FIELD(data, IH_CLK_CTRL,
 694                                      REG_CLK_SOFT_OVERRIDE, field_val);
 695                 if (def != data)
 696                         WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
 697         }
 698 }
 699
 700 static int vega20_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
 701                                           enum amd_clockgating_state state)
 702 {
 703         struct amdgpu_device *adev = ip_block->adev;
 704
 705         vega20_ih_update_clockgating_state(adev,
 706                                 state == AMD_CG_STATE_GATE);
 707         return 0;
 708
 709 }
 710
 711 static int vega20_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
 712                                           enum amd_powergating_state state)
 713 {
 714         return 0;
 715 }
 716
 717 const struct amd_ip_funcs vega20_ih_ip_funcs = {
 718         .name = "vega20_ih",
 719         .early_init = vega20_ih_early_init,
 720         .sw_init = vega20_ih_sw_init,
 721         .sw_fini = vega20_ih_sw_fini,
 722         .hw_init = vega20_ih_hw_init,
 723         .hw_fini = vega20_ih_hw_fini,
 724         .suspend = vega20_ih_suspend,
 725         .resume = vega20_ih_resume,
 726         .is_idle = vega20_ih_is_idle,
 727         .wait_for_idle = vega20_ih_wait_for_idle,
 728         .soft_reset = vega20_ih_soft_reset,
 729         .set_clockgating_state = vega20_ih_set_clockgating_state,
 730         .set_powergating_state = vega20_ih_set_powergating_state,
 731 };
 732
 733 static const struct amdgpu_ih_funcs vega20_ih_funcs = {
 734         .get_wptr = vega20_ih_get_wptr,
 735         .decode_iv = amdgpu_ih_decode_iv_helper,
 736         .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
 737         .set_rptr = vega20_ih_set_rptr
 738 };
 739
 740 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
 741 {
 742         adev->irq.ih_funcs = &vega20_ih_funcs;
 743 }
 744
 745 const struct amdgpu_ip_block_version vega20_ih_ip_block = {
 746         .type = AMD_IP_BLOCK_TYPE_IH,
 747         .major = 4,
 748         .minor = 2,
 749         .rev = 0,
 750         .funcs = &vega20_ih_ip_funcs,
 751 };