drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/sort.h>
  25 #include "amdgpu.h"
  26 #include "umc_v6_7.h"
  27 #define MAX_UMC_POISON_POLLING_TIME_SYNC   20  //ms
  28
  29 #define MAX_UMC_HASH_STRING_SIZE  256
  30
  31 static int amdgpu_umc_convert_error_address(struct amdgpu_device *adev,
  32                                     struct ras_err_data *err_data, uint64_t err_addr,
  33                                     uint32_t ch_inst, uint32_t umc_inst)
  34 {
  35         switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
  36         case IP_VERSION(6, 7, 0):
  37                 umc_v6_7_convert_error_address(adev,
  38                                 err_data, err_addr, ch_inst, umc_inst);
  39                 break;
  40         default:
  41                 dev_warn(adev->dev,
  42                          "UMC address to Physical address translation is not supported\n");
  43                 return AMDGPU_RAS_FAIL;
  44         }
  45
  46         return AMDGPU_RAS_SUCCESS;
  47 }
  48
  49 int amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev,
  50                         uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst)
  51 {
  52         struct ras_err_data err_data;
  53         int ret;
  54
  55         ret = amdgpu_ras_error_data_init(&err_data);
  56         if (ret)
  57                 return ret;
  58
  59         err_data.err_addr =
  60                 kcalloc(adev->umc.max_ras_err_cnt_per_query,
  61                         sizeof(struct eeprom_table_record), GFP_KERNEL);
  62         if (!err_data.err_addr) {
  63                 dev_warn(adev->dev,
  64                         "Failed to alloc memory for umc error record in MCA notifier!\n");
  65                 ret = AMDGPU_RAS_FAIL;
  66                 goto out_fini_err_data;
  67         }
  68
  69         err_data.err_addr_len = adev->umc.max_ras_err_cnt_per_query;
  70
  71         /*
  72          * Translate UMC channel address to Physical address
  73          */
  74         ret = amdgpu_umc_convert_error_address(adev, &err_data, err_addr,
  75                                         ch_inst, umc_inst);
  76         if (ret)
  77                 goto out_free_err_addr;
  78
  79         if (amdgpu_bad_page_threshold != 0) {
  80                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
  81                                                 err_data.err_addr_cnt, false);
  82                 amdgpu_ras_save_bad_pages(adev, NULL);
  83         }
  84
  85 out_free_err_addr:
  86         kfree(err_data.err_addr);
  87
  88 out_fini_err_data:
  89         amdgpu_ras_error_data_fini(&err_data);
  90
  91         return ret;
  92 }
  93
  94 void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,
  95                         void *ras_error_status)
  96 {
  97         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
  98         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
  99         unsigned int error_query_mode;
 100         int ret = 0;
 101         unsigned long err_count;
 102
 103         amdgpu_ras_get_error_query_mode(adev, &error_query_mode);
 104
 105         mutex_lock(&con->page_retirement_lock);
 106         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc));
 107         if (ret == -EOPNOTSUPP &&
 108             error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {
 109                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
 110                     adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
 111                     adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status);
 112
 113                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
 114                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address &&
 115                     adev->umc.max_ras_err_cnt_per_query) {
 116                         err_data->err_addr =
 117                                 kcalloc(adev->umc.max_ras_err_cnt_per_query,
 118                                         sizeof(struct eeprom_table_record), GFP_KERNEL);
 119
 120                         /* still call query_ras_error_address to clear error status
 121                          * even NOMEM error is encountered
 122                          */
 123                         if(!err_data->err_addr)
 124                                 dev_warn(adev->dev, "Failed to alloc memory for "
 125                                                 "umc error address record!\n");
 126                         else
 127                                 err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query;
 128
 129                         /* umc query_ras_error_address is also responsible for clearing
 130                          * error status
 131                          */
 132                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status);
 133                 }
 134         } else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY ||
 135             (!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) {
 136                 if (adev->umc.ras &&
 137                     adev->umc.ras->ecc_info_query_ras_error_count)
 138                     adev->umc.ras->ecc_info_query_ras_error_count(adev, ras_error_status);
 139
 140                 if (adev->umc.ras &&
 141                     adev->umc.ras->ecc_info_query_ras_error_address &&
 142                     adev->umc.max_ras_err_cnt_per_query) {
 143                         err_data->err_addr =
 144                                 kcalloc(adev->umc.max_ras_err_cnt_per_query,
 145                                         sizeof(struct eeprom_table_record), GFP_KERNEL);
 146
 147                         /* still call query_ras_error_address to clear error status
 148                          * even NOMEM error is encountered
 149                          */
 150                         if(!err_data->err_addr)
 151                                 dev_warn(adev->dev, "Failed to alloc memory for "
 152                                                 "umc error address record!\n");
 153                         else
 154                                 err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query;
 155
 156                         /* umc query_ras_error_address is also responsible for clearing
 157                          * error status
 158                          */
 159                         adev->umc.ras->ecc_info_query_ras_error_address(adev, ras_error_status);
 160                 }
 161         }
 162
 163         /* only uncorrectable error needs gpu reset */
 164         if (err_data->ue_count || err_data->de_count) {
 165                 err_count = err_data->ue_count + err_data->de_count;
 166                 if ((amdgpu_bad_page_threshold != 0) &&
 167                         err_data->err_addr_cnt) {
 168                         amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
 169                                                 err_data->err_addr_cnt, false);
 170                         amdgpu_ras_save_bad_pages(adev, &err_count);
 171
 172                         amdgpu_dpm_send_hbm_bad_pages_num(adev,
 173                                         con->eeprom_control.ras_num_bad_pages);
 174
 175                         if (con->update_channel_flag == true) {
 176                                 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
 177                                 con->update_channel_flag = false;
 178                         }
 179                 }
 180         }
 181
 182         kfree(err_data->err_addr);
 183         err_data->err_addr = NULL;
 184
 185         mutex_unlock(&con->page_retirement_lock);
 186 }
 187
 188 static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
 189                 void *ras_error_status,
 190                 struct amdgpu_iv_entry *entry,
 191                 uint32_t reset)
 192 {
 193         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 194         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 195
 196         kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 197         amdgpu_umc_handle_bad_pages(adev, ras_error_status);
 198
 199         if ((err_data->ue_count || err_data->de_count) &&
 200             (reset || amdgpu_ras_is_rma(adev))) {
 201                 con->gpu_reset_flags |= reset;
 202                 amdgpu_ras_reset_gpu(adev);
 203         }
 204
 205         return AMDGPU_RAS_SUCCESS;
 206 }
 207
 208 int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev,
 209                         enum amdgpu_ras_block block, uint16_t pasid,
 210                         pasid_notify pasid_fn, void *data, uint32_t reset)
 211 {
 212         int ret = AMDGPU_RAS_SUCCESS;
 213
 214         if (adev->gmc.xgmi.connected_to_cpu ||
 215                 adev->gmc.is_app_apu) {
 216                 if (reset) {
 217                         /* MCA poison handler is only responsible for GPU reset,
 218                          * let MCA notifier do page retirement.
 219                          */
 220                         kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 221                         amdgpu_ras_reset_gpu(adev);
 222                 }
 223                 return ret;
 224         }
 225
 226         if (!amdgpu_sriov_vf(adev)) {
 227                 if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) {
 228                         struct ras_err_data err_data;
 229                         struct ras_common_if head = {
 230                                 .block = AMDGPU_RAS_BLOCK__UMC,
 231                         };
 232                         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head);
 233
 234                         ret = amdgpu_ras_error_data_init(&err_data);
 235                         if (ret)
 236                                 return ret;
 237
 238                         ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset);
 239
 240                         if (ret == AMDGPU_RAS_SUCCESS && obj) {
 241                                 obj->err_data.ue_count += err_data.ue_count;
 242                                 obj->err_data.ce_count += err_data.ce_count;
 243                                 obj->err_data.de_count += err_data.de_count;
 244                         }
 245
 246                         amdgpu_ras_error_data_fini(&err_data);
 247                 } else {
 248                         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 249                         int ret;
 250
 251                         ret = amdgpu_ras_put_poison_req(adev,
 252                                 block, pasid, pasid_fn, data, reset);
 253                         if (!ret) {
 254                                 atomic_inc(&con->page_retirement_req_cnt);
 255                                 wake_up(&con->page_retirement_wq);
 256                         }
 257                 }
 258         } else {
 259                 if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
 260                         adev->virt.ops->ras_poison_handler(adev, block);
 261                 else
 262                         dev_warn(adev->dev,
 263                                 "No ras_poison_handler interface in SRIOV!\n");
 264         }
 265
 266         return ret;
 267 }
 268
 269 int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
 270                         enum amdgpu_ras_block block, uint32_t reset)
 271 {
 272         return amdgpu_umc_pasid_poison_handler(adev,
 273                                 block, 0, NULL, NULL, reset);
 274 }
 275
 276 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
 277                 void *ras_error_status,
 278                 struct amdgpu_iv_entry *entry)
 279 {
 280         return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry,
 281                                 AMDGPU_RAS_GPU_RESET_MODE1_RESET);
 282 }
 283
 284 int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev)
 285 {
 286         int err;
 287         struct amdgpu_umc_ras *ras;
 288
 289         if (!adev->umc.ras)
 290                 return 0;
 291
 292         ras = adev->umc.ras;
 293
 294         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 295         if (err) {
 296                 dev_err(adev->dev, "Failed to register umc ras block!\n");
 297                 return err;
 298         }
 299
 300         strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
 301         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
 302         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 303         adev->umc.ras_if = &ras->ras_block.ras_comm;
 304
 305         if (!ras->ras_block.ras_late_init)
 306                 ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
 307
 308         if (!ras->ras_block.ras_cb)
 309                 ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
 310
 311         return 0;
 312 }
 313
 314 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 315 {
 316         int r;
 317
 318         r = amdgpu_ras_block_late_init(adev, ras_block);
 319         if (r)
 320                 return r;
 321
 322         if (amdgpu_sriov_vf(adev))
 323                 return r;
 324
 325         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
 326                 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
 327                 if (r)
 328                         goto late_fini;
 329         }
 330
 331         /* ras init of specific umc version */
 332         if (adev->umc.ras &&
 333             adev->umc.ras->err_cnt_init)
 334                 adev->umc.ras->err_cnt_init(adev);
 335
 336         return 0;
 337
 338 late_fini:
 339         amdgpu_ras_block_late_fini(adev, ras_block);
 340         return r;
 341 }
 342
 343 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
 344                 struct amdgpu_irq_src *source,
 345                 struct amdgpu_iv_entry *entry)
 346 {
 347         struct ras_common_if *ras_if = adev->umc.ras_if;
 348         struct ras_dispatch_if ih_data = {
 349                 .entry = entry,
 350         };
 351
 352         if (!ras_if)
 353                 return 0;
 354
 355         ih_data.head = *ras_if;
 356
 357         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 358         return 0;
 359 }
 360
 361 int amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
 362                 uint64_t err_addr,
 363                 uint64_t retired_page,
 364                 uint32_t channel_index,
 365                 uint32_t umc_inst)
 366 {
 367         struct eeprom_table_record *err_rec;
 368
 369         if (!err_data ||
 370             !err_data->err_addr ||
 371             (err_data->err_addr_cnt >= err_data->err_addr_len))
 372                 return -EINVAL;
 373
 374         err_rec = &err_data->err_addr[err_data->err_addr_cnt];
 375
 376         err_rec->address = err_addr;
 377         /* page frame address is saved */
 378         err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
 379         err_rec->ts = (uint64_t)ktime_get_real_seconds();
 380         err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
 381         err_rec->cu = 0;
 382         err_rec->mem_channel = channel_index;
 383         err_rec->mcumc_id = umc_inst;
 384
 385         err_data->err_addr_cnt++;
 386
 387         return 0;
 388 }
 389
 390 int amdgpu_umc_loop_channels(struct amdgpu_device *adev,
 391                         umc_func func, void *data)
 392 {
 393         uint32_t node_inst       = 0;
 394         uint32_t umc_inst        = 0;
 395         uint32_t ch_inst         = 0;
 396         int ret = 0;
 397
 398         if (adev->umc.node_inst_num) {
 399                 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
 400                         ret = func(adev, node_inst, umc_inst, ch_inst, data);
 401                         if (ret) {
 402                                 dev_err(adev->dev, "Node %d umc %d ch %d func returns %d\n",
 403                                         node_inst, umc_inst, ch_inst, ret);
 404                                 return ret;
 405                         }
 406                 }
 407         } else {
 408                 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
 409                         ret = func(adev, 0, umc_inst, ch_inst, data);
 410                         if (ret) {
 411                                 dev_err(adev->dev, "Umc %d ch %d func returns %d\n",
 412                                         umc_inst, ch_inst, ret);
 413                                 return ret;
 414                         }
 415                 }
 416         }
 417
 418         return 0;
 419 }
 420
 421 int amdgpu_umc_update_ecc_status(struct amdgpu_device *adev,
 422                                 uint64_t status, uint64_t ipid, uint64_t addr)
 423 {
 424         if (adev->umc.ras->update_ecc_status)
 425                 return adev->umc.ras->update_ecc_status(adev,
 426                                         status, ipid, addr);
 427         return 0;
 428 }
 429
 430 int amdgpu_umc_logs_ecc_err(struct amdgpu_device *adev,
 431                 struct radix_tree_root *ecc_tree, struct ras_ecc_err *ecc_err)
 432 {
 433         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 434         struct ras_ecc_log_info *ecc_log;
 435         int ret;
 436
 437         ecc_log = &con->umc_ecc_log;
 438
 439         mutex_lock(&ecc_log->lock);
 440         ret = radix_tree_insert(ecc_tree, ecc_err->pa_pfn, ecc_err);
 441         if (!ret)
 442                 radix_tree_tag_set(ecc_tree,
 443                         ecc_err->pa_pfn, UMC_ECC_NEW_DETECTED_TAG);
 444         mutex_unlock(&ecc_log->lock);
 445
 446         return ret;
 447 }
 448
 449 int amdgpu_umc_pages_in_a_row(struct amdgpu_device *adev,
 450                         struct ras_err_data *err_data, uint64_t pa_addr)
 451 {
 452         struct ta_ras_query_address_output addr_out;
 453
 454         /* reinit err_data */
 455         err_data->err_addr_cnt = 0;
 456         err_data->err_addr_len = adev->umc.retire_unit;
 457
 458         addr_out.pa.pa = pa_addr;
 459         if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr)
 460                 return adev->umc.ras->convert_ras_err_addr(adev, err_data, NULL,
 461                                 &addr_out, false);
 462         else
 463                 return -EINVAL;
 464 }
 465
 466 int amdgpu_umc_lookup_bad_pages_in_a_row(struct amdgpu_device *adev,
 467                         uint64_t pa_addr, uint64_t *pfns, int len)
 468 {
 469         int i, ret;
 470         struct ras_err_data err_data;
 471
 472         err_data.err_addr = kcalloc(adev->umc.retire_unit,
 473                                 sizeof(struct eeprom_table_record), GFP_KERNEL);
 474         if (!err_data.err_addr) {
 475                 dev_warn(adev->dev, "Failed to alloc memory in bad page lookup!\n");
 476                 return 0;
 477         }
 478
 479         ret = amdgpu_umc_pages_in_a_row(adev, &err_data, pa_addr);
 480         if (ret)
 481                 goto out;
 482
 483         for (i = 0; i < adev->umc.retire_unit; i++) {
 484                 if (i >= len)
 485                         goto out;
 486
 487                 pfns[i] = err_data.err_addr[i].retired_page;
 488         }
 489         ret = i;
 490
 491 out:
 492         kfree(err_data.err_addr);
 493         return ret;
 494 }
 495
 496 int amdgpu_umc_mca_to_addr(struct amdgpu_device *adev,
 497                         uint64_t err_addr, uint32_t ch, uint32_t umc,
 498                         uint32_t node, uint32_t socket,
 499                         struct ta_ras_query_address_output *addr_out, bool dump_addr)
 500 {
 501         struct ta_ras_query_address_input addr_in;
 502         int ret;
 503
 504         memset(&addr_in, 0, sizeof(addr_in));
 505         addr_in.ma.err_addr = err_addr;
 506         addr_in.ma.ch_inst = ch;
 507         addr_in.ma.umc_inst = umc;
 508         addr_in.ma.node_inst = node;
 509         addr_in.ma.socket_id = socket;
 510
 511         if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) {
 512                 ret = adev->umc.ras->convert_ras_err_addr(adev, NULL, &addr_in,
 513                                 addr_out, dump_addr);
 514                 if (ret)
 515                         return ret;
 516         } else {
 517                 return 0;
 518         }
 519
 520         return 0;
 521 }